From badcb343d7844e81be92ba9a7a02f22159591650 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 10 Oct 2012 13:12:56 +0000 Subject: x86: coreboot: Move non-board specific files to coreboot arch directory coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit) Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- arch/x86/cpu/coreboot/pci.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 arch/x86/cpu/coreboot/pci.c (limited to 'arch/x86/cpu/coreboot/pci.c') diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c new file mode 100644 index 00000000000..732ca3ceaff --- /dev/null +++ b/arch/x86/cpu/coreboot/pci.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008,2009 + * Graeme Russ, + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +void pci_init_board(void) +{ +} -- cgit v1.2.3 From 452f50f7cff5d77db79ee3b11b4b3e19b166e6b0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 10 Oct 2012 13:12:57 +0000 Subject: x86: coreboot: Tell u-boot about PCI bus 0 when initializing U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black Signed-off-by: Simon Glass Acked-by: Graeme Russ --- arch/x86/cpu/coreboot/pci.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/x86/cpu/coreboot/pci.c') diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 732ca3ceaff..0ddc97501b7 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -25,6 +25,21 @@ * MA 02111-1307 USA */ +#include +#include +#include + +static struct pci_controller coreboot_hose; + void pci_init_board(void) { + coreboot_hose.first_busno = 0; + coreboot_hose.last_busno = 0xff; + coreboot_hose.region_count = 0; + + pci_setup_type1(&coreboot_hose); + + pci_register_hose(&coreboot_hose); + + coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose); } -- cgit v1.2.3 From 82e73f0e3da3ae8b1a6a14dafa8af38d140fb1b2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 10 Oct 2012 13:12:59 +0000 Subject: x86: coreboot: Implement recursively scanning PCI busses A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus. On Coreboot, the PCI bus address space has identity mapping with the physical address space, so declare it as such to ensure that the "pci_map_bar" function used by some PCI drivers is behaving properly. This fixes the EHCI PCI driver initialization on Stumpy. This was tested as follows: Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges reported on bus 0 and the PCI configuration output from coreboot. Signed-off-by: Gabe Black Signed-off-by: Vincent Palatin Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- arch/x86/cpu/coreboot/pci.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'arch/x86/cpu/coreboot/pci.c') diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 0ddc97501b7..8f941674806 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -31,15 +31,35 @@ static struct pci_controller coreboot_hose; +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + hose->last_busno = max(hose->last_busno, secondary); + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_coreboot_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, + {} +}; + void pci_init_board(void) { + coreboot_hose.config_table = pci_coreboot_config_table; coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0xff; - coreboot_hose.region_count = 0; + coreboot_hose.last_busno = 0; + + pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, + PCI_REGION_MEM); + coreboot_hose.region_count = 1; pci_setup_type1(&coreboot_hose); pci_register_hose(&coreboot_hose); - coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose); + pci_hose_scan(&coreboot_hose); } -- cgit v1.2.3