From ef5a5b004997a0759d6f5f3206a419f90d5ffac5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 29 Nov 2011 18:05:07 +0000 Subject: x86: Initial commit for running as a coreboot payload Add a target for running u-boot as a coreboot payload in boards.cfg, a board, CPU and a config. This is a skeleton implementation which always reports the size of memory as 64 MB. Signed-off-by: Gabe Black --- arch/x86/cpu/coreboot/sdram.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 arch/x86/cpu/coreboot/sdram.c (limited to 'arch/x86/cpu/coreboot/sdram.c') diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c new file mode 100644 index 00000000000..b56085a9325 --- /dev/null +++ b/arch/x86/cpu/coreboot/sdram.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 + * Graeme Russ, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init_f(void) +{ + gd->ram_size = 64*1024*1024; + return 0; +} + +int dram_init(void) +{ + return 0; +} -- cgit v1.2.3 From f08fa7a2018495c6f2a5eaba5f6d8fdcbc67e6c6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 5 Dec 2011 12:09:25 +0000 Subject: x86: Add infrastructure to extract an e820 table from the coreboot tables Also approximate the size of RAM using the largest RAM address available in the tables. There may be areas which are marked as reserved which are actually at the end of RAM. Signed-off-by: Gabe Black --- arch/x86/cpu/coreboot/sdram.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) (limited to 'arch/x86/cpu/coreboot/sdram.c') diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index b56085a9325..f8fdac6319e 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -23,13 +23,49 @@ */ #include +#include +#include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + int i; + + unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries); + if (num_entries < lib_sysinfo.n_memranges) { + printf("Warning: Limiting e820 map to %d entries.\n", + num_entries); + } + for (i = 0; i < num_entries; i++) { + struct memrange *memrange = &lib_sysinfo.memrange[i]; + + entries[i].addr = memrange->base; + entries[i].size = memrange->size; + entries[i].type = memrange->type; + } + return num_entries; +} + int dram_init_f(void) { - gd->ram_size = 64*1024*1024; + int i; + phys_size_t ram_size = 0; + + for (i = 0; i < lib_sysinfo.n_memranges; i++) { + struct memrange *memrange = &lib_sysinfo.memrange[i]; + unsigned long long end = memrange->base + memrange->size; + + if (memrange->type == CB_MEM_RAM && end > ram_size) + ram_size = end; + } + gd->ram_size = ram_size; + if (ram_size == 0) + return -1; return 0; } -- cgit v1.2.3