From a65b25d148fb0a9ef7dd5fba4ae2709f5bcae0c6 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 7 May 2015 21:34:08 +0800 Subject: x86: Support QEMU x86 targets This commit introduces the initial U-Boot support for QEMU x86 targets. U-Boot can boot from coreboot as a payload, or directly without coreboot. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig https://patchwork.ozlabs.org/patch/479745/ --- arch/x86/cpu/qemu/pci.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 arch/x86/cpu/qemu/pci.c (limited to 'arch/x86/cpu/qemu/pci.c') diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c new file mode 100644 index 00000000000..d50ab752d39 --- /dev/null +++ b/arch/x86/cpu/qemu/pci.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + pci_set_region(hose->regions + 3, + 0, + 0, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; +} + +int board_pci_post_scan(struct pci_controller *hose) +{ + return 0; +} -- cgit v1.2.3 From 9c4f541237d43439df4cc3021544741f318d378d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 11 May 2015 07:36:30 +0800 Subject: x86: qemu: Add graphics support It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/qemu/pci.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) (limited to 'arch/x86/cpu/qemu/pci.c') diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index d50ab752d39..ac9c056e2be 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -6,6 +6,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -45,5 +46,26 @@ void board_pci_setup_hose(struct pci_controller *hose) int board_pci_post_scan(struct pci_controller *hose) { - return 0; + int ret = 0; + ulong start; + pci_dev_t bdf; + struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } }; + + /* + * QEMU emulated graphic card shows in the PCI configuration space with + * PCI vendor id and device id as an artificial pair 0x1234:0x1111. + * It is on PCI bus 0, function 0, but device number is not consistent + * for the two x86 targets it supports. For i440FX and PIIX chipset + * board, it shows as device 2, while for Q35 and ICH9 chipset board, + * it shows as device 1. Here we locate its bdf at run-time based on + * its vendor id and device id pair so we can support both boards. + */ + bdf = pci_find_devices(graphic_card, 0); + if (bdf != -1) { + start = get_timer(0); + ret = pci_run_vga_bios(bdf, NULL, PCI_ROM_USE_NATIVE); + debug("BIOS ran in %lums\n", get_timer(start)); + } + + return ret; } -- cgit v1.2.3 From cc7debc7199b3c637ceead92bc103aeb6eb10a38 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 24 May 2015 00:12:33 +0800 Subject: x86: qemu: Turn on legacy segments decode By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/qemu/pci.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/x86/cpu/qemu/pci.c') diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index ac9c056e2be..2f4ba1785db 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +52,8 @@ int board_pci_post_scan(struct pci_controller *hose) ulong start; pci_dev_t bdf; struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } }; + u16 device; + int pam, i; /* * QEMU emulated graphic card shows in the PCI configuration space with @@ -67,5 +71,21 @@ int board_pci_post_scan(struct pci_controller *hose) debug("BIOS ran in %lums\n", get_timer(start)); } + /* + * i440FX and Q35 chipset have different PAM register offset, but with + * the same bitfield layout. Here we determine the offset based on its + * PCI device ID. + */ + device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); + pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM; + + /* + * Initialize Programmable Attribute Map (PAM) Registers + * + * Configure legacy segments C/D/E/F to system RAM + */ + for (i = 0; i < PAM_NUM; i++) + x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); + return ret; } -- cgit v1.2.3 From 0fcb7acf6748d2ee0b7abfd75e074840be6b7e0e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 25 May 2015 22:36:26 +0800 Subject: x86: qemu: Enable legacy IDE I/O ports decode QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix driver does sanity check to see whether legacy ports decode is turned on. To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/qemu/pci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/x86/cpu/qemu/pci.c') diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index 2f4ba1785db..467d51dbed8 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -8,6 +8,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -87,5 +88,18 @@ int board_pci_post_scan(struct pci_controller *hose) for (i = 0; i < PAM_NUM; i++) x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); + if (device == PCI_DEVICE_ID_INTEL_82441) { + /* + * Enable legacy IDE I/O ports decode + * + * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. + * However Linux ata_piix driver does sanity check on these two + * registers to see whether legacy ports decode is turned on. + * This is to make Linux ata_piix driver happy. + */ + x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); + x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); + } + return ret; } -- cgit v1.2.3 From 4be2f42bbc8171eae930db37f370f10779c5b02c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 25 May 2015 22:36:27 +0800 Subject: x86: qemu: Adjust VGA initialization As VGA option rom needs to run at C segment, although QEMU PAM emulation seems to only guard E/F segments, for correctness, move VGA initialization after PAM decode C/D/E/F segments. Also since we already tested QEMU targets to differentiate I440FX and Q35 platforms, change to locate the VGA device via hardcoded b.d.f instead of dynamic search for its vendor id & device id pair. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/qemu/pci.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) (limited to 'arch/x86/cpu/qemu/pci.c') diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index 467d51dbed8..1a9140b46e0 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -50,27 +50,10 @@ void board_pci_setup_hose(struct pci_controller *hose) int board_pci_post_scan(struct pci_controller *hose) { int ret = 0; - ulong start; - pci_dev_t bdf; - struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } }; u16 device; int pam, i; - - /* - * QEMU emulated graphic card shows in the PCI configuration space with - * PCI vendor id and device id as an artificial pair 0x1234:0x1111. - * It is on PCI bus 0, function 0, but device number is not consistent - * for the two x86 targets it supports. For i440FX and PIIX chipset - * board, it shows as device 2, while for Q35 and ICH9 chipset board, - * it shows as device 1. Here we locate its bdf at run-time based on - * its vendor id and device id pair so we can support both boards. - */ - bdf = pci_find_devices(graphic_card, 0); - if (bdf != -1) { - start = get_timer(0); - ret = pci_run_vga_bios(bdf, NULL, PCI_ROM_USE_NATIVE); - debug("BIOS ran in %lums\n", get_timer(start)); - } + pci_dev_t vga; + ulong start; /* * i440FX and Q35 chipset have different PAM register offset, but with @@ -101,5 +84,18 @@ int board_pci_post_scan(struct pci_controller *hose) x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); } + /* + * QEMU emulated graphic card shows in the PCI configuration space with + * PCI vendor id and device id as an artificial pair 0x1234:0x1111. + * It is on PCI bus 0, function 0, but device number is not consistent + * for the two x86 targets it supports. For i440FX and PIIX chipset + * board, it shows as device 2, while for Q35 and ICH9 chipset board, + * it shows as device 1. + */ + vga = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_VGA : Q35_VGA; + start = get_timer(0); + ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE); + debug("BIOS ran in %lums\n", get_timer(start)); + return ret; } -- cgit v1.2.3