From 05b98ec3468547057666dd685b2a1615298c24cc Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 25 May 2015 22:35:06 +0800 Subject: x86: quark: Implement PIRQ routing Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/quark/quark.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/x86/cpu/quark/quark.c') diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index e78a271c509..20cc09e113d 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -147,3 +148,33 @@ int cpu_eth_init(bd_t *bis) else return 0; } + +void cpu_irq_init(void) +{ + struct quark_rcba *rcba; + u32 base; + + base = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, LB_RCBA); + base &= ~MEM_BAR_EN; + rcba = (struct quark_rcba *)base; + + /* + * Route Quark PCI device interrupt pin to PIRQ + * + * Route device#23's INTA/B/C/D to PIRQA/B/C/D + * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H + */ + writew(PIRQC, &rcba->rmu_ir); + writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), + &rcba->d23_ir); + writew(PIRQD, &rcba->core_ir); + writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), + &rcba->d20d21_ir); +} + +int arch_misc_init(void) +{ + pirq_init(); + + return 0; +} -- cgit v1.2.3