From 5811830fae92cf0a3bb11ead54ef1267464a1280 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Sep 2012 10:13:35 +0200 Subject: microblaze: Flush caches before enabling them Flushing caches is necessary because of soft reset which doesn't clear caches. Signed-off-by: Michal Simek Reviewed-by: Marek Vasut --- arch/microblaze/cpu/cache.c | 5 ----- arch/microblaze/cpu/start.S | 6 ++++++ arch/microblaze/lib/bootm.c | 5 ----- 3 files changed, 6 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index d258a693822..ce066b96e99 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -61,12 +61,7 @@ void dcache_enable (void) { void dcache_disable(void) { #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif MSRCLR(0x80); } diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8564c4e30ab..3da711d4d50 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -132,6 +132,12 @@ _start: rsubi r8, r10, 0x26 sh r6, r0, r8 + /* Flush cache before enable cache */ + addik r5, r0, 0 + addik r6, r0, XILINX_DCACHE_BYTE_SIZE +flush: bralid r15, flush_cache + nop + /* enable instruction and data cache */ mfs r12, rmsr ori r12, r12, 0xa0 diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 95cee509d25..66d21f4ef66 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -70,12 +70,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima #endif #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif /* * Linux Kernel Parameters (passing device tree): -- cgit v1.2.3