From a259243e9d5895e03348cad98b82524e61cd47e8 Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Tue, 17 Jan 2017 16:27:24 +0100 Subject: net: zynq: Don't overwrite gem_rclk_ctrl with default value The gem[0-1]_rclk_ctrl registers control the source of the rx clock, control and data signals and configure via ps7_init function. Don't overwrite the register with the default value. Signed-off-by: Stefan Herbrechtsmeier Reviewed-by: Joe Hershberger Signed-off-by: Michal Simek --- arch/arm/mach-zynq/slcr.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 2d3bf2acef7..c1129cd370a 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -140,13 +140,6 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) if (ret) goto out; - if (gem_id) { - /* Configure GEM_RCLK_CTRL */ - writel(1, &slcr_base->gem1_rclk_ctrl); - } else { - /* Configure GEM_RCLK_CTRL */ - writel(1, &slcr_base->gem0_rclk_ctrl); - } udelay(100000); out: zynq_slcr_lock(); -- cgit v1.2.3