From f8523cb0815b2d3d2d780b7d49ca614105555f58 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 6 Feb 2009 09:56:35 -0600 Subject: 85xx: Fix how we map DDR memory Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 74 ++++++++++++++++++++----------------------------------- 1 file changed, 27 insertions(+), 47 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 25fa9ee8f8e..c73bf056ec7 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -132,61 +132,41 @@ void init_addr_map(void) unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; - unsigned int ram_tlb_index; - unsigned int ram_tlb_address; + unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START; + unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff; + u64 size, memsize = (u64)memsize_in_meg << 20; - /* - * Determine size of each TLB1 entry. - */ - switch (memsize_in_meg) { - case 16: - case 32: - tlb_size = BOOKE_PAGESZ_16M; - break; - case 64: - case 128: - tlb_size = BOOKE_PAGESZ_64M; - break; - case 256: - case 512: - tlb_size = BOOKE_PAGESZ_256M; - break; - case 1024: - case 2048: - if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) - tlb_size = BOOKE_PAGESZ_1G; - else - tlb_size = BOOKE_PAGESZ_256M; - break; - default: - puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G" - " and 2G are supported.\n"); - - /* - * The memory was not able to be mapped. - * Default to a small size. - */ - tlb_size = BOOKE_PAGESZ_64M; - memsize_in_meg = 64; - break; - } + size = min(memsize, CONFIG_MAX_MEM_MAPPED); + + /* Convert (4^max) kB to (2^max) bytes */ + max_cam = max_cam * 2 + 10; + + for (; size && ram_tlb_index < 16; ram_tlb_index++) { + u32 camsize = __ilog2_u64(size) & ~1U; + u32 align = __ilog2(ram_tlb_address) & ~1U; + + if (align == -2) align = max_cam; + if (camsize > align) + camsize = align; + + if (camsize > max_cam) + camsize = max_cam; + + tlb_size = (camsize - 10) / 2; - /* - * Configure DDR TLB1 entries. - * Starting at TLB1 8, use no more than 8 TLB1 entries. - */ - ram_tlb_index = CONFIG_SYS_DDR_TLB_START; - ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; - while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) - && ram_tlb_index < 16) { set_tlb(1, ram_tlb_address, ram_tlb_address, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1); - ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); - ram_tlb_index++; + size -= 1ULL << camsize; + memsize -= 1ULL << camsize; + ram_tlb_address += 1UL << camsize; } + if (memsize) + printf("%lldM left unmapped\n", memsize >> 20); + /* * Confirm that the requested amount of memory was mapped. */ -- cgit v1.2.3