From 0f347a0096ad0c1e56d1b18b7eb60731d40d49c2 Mon Sep 17 00:00:00 2001 From: Janine Hagemann Date: Tue, 28 Aug 2018 08:25:39 +0200 Subject: net: phy: ti: Add binding for the CLK_OUT pin muxing The DP83867 has a muxing option for the CLK_OUT pin. It is possible to set CLK_OUT for different channels. Create a binding to select a specific clock for CLK_OUT pin. Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for the CLK_OUT pin muxing option") of mainline linux kernel. Signed-off-by: Janine Hagemann Acked-by: Joe Hershberger --- doc/device-tree-bindings/net/ti,dp83867.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'doc') diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt index f31c2da902..034146f5f8 100644 --- a/doc/device-tree-bindings/net/ti,dp83867.txt +++ b/doc/device-tree-bindings/net/ti,dp83867.txt @@ -12,6 +12,8 @@ Required properties: compensate for the board being designed with the lanes swapped. - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the TX/RX lanes. + - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h + for applicable values Default child nodes are standard Ethernet PHY device nodes as described in doc/devicetree/bindings/net/ethernet.txt @@ -24,6 +26,7 @@ Example: ti,tx-internal-delay = ; ti,fifo-depth = ; enet-phy-lane-no-swap; + ti,clk-output-sel = ; }; Datasheet can be found: -- cgit v1.2.3