From b4d00b256e3c784de4a33a40f4cd28a94ee2a80c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 6 Feb 2020 09:54:53 -0700 Subject: x86: Add a clock driver for Intel devices So far we have avoided adding a clock driver for Intel devices. But the Designware I2C driver needs a different clock (133MHz) on Intel devices than on others (166MHz). Add a simple driver that provides this information. This driver can be expanded later as needed. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/clk/intel/clk_intel.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 drivers/clk/intel/clk_intel.c (limited to 'drivers/clk/intel/clk_intel.c') diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c new file mode 100644 index 00000000000..d2e15491a3d --- /dev/null +++ b/drivers/clk/intel/clk_intel.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include + +static ulong intel_clk_get_rate(struct clk *clk) +{ + ulong rate; + + switch (clk->id) { + case CLK_I2C: + /* Hard-coded to 133MHz on current platforms */ + return 133333333; + default: + return -ENODEV; + } + + return rate; +} + +static struct clk_ops intel_clk_ops = { + .get_rate = intel_clk_get_rate, +}; + +static const struct udevice_id intel_clk_ids[] = { + { .compatible = "intel,apl-clk" }, + { } +}; + +U_BOOT_DRIVER(clk_intel) = { + .name = "clk_intel", + .id = UCLASS_CLK, + .of_match = intel_clk_ids, + .ops = &intel_clk_ops, +}; -- cgit v1.2.3