From 444ab3569bae32daed9c05fb10f87d907cc180ff Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 4 May 2022 22:10:28 +0100 Subject: clk: sunxi: add PIO bus gate clocks The introduction of the DM pinctrl driver made its probe function enable all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device. So far we didn't describe those clocks in our clock driver. As we enable them already in the SPL, the devices happen to work, but the clock driver still complains about not finding those clocks: ========= sunxi_set_gate: (CLK#58) unhandled ========= Add the one-liners that are needed to announce the gate bit for those clocks, to silence that message on the console. Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland --- drivers/clk/sunxi/clk_r40.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk/sunxi/clk_r40.c') diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 4d5b69a9765..45633a2a524 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -32,6 +32,8 @@ static struct ccu_clk_gate r40_gates[] = { [CLK_BUS_GMAC] = GATE(0x064, BIT(17)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), -- cgit v1.2.3