From 362c355dd7346166986de280226750fb328b69d3 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Sun, 3 Aug 2025 18:24:38 -0700 Subject: ddr: altera: soc64: Add secure region support for ATF flow Setting up firewall regions based on SDRAM memory banks configuration (up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space. First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region, other address spaces are non-secure regions. The ARM Trusted Firmware (ATF) image is located in this first 1 MiB memory region. So, this can prevent software executing at non-secure state EL0-EL2 and non-secure masters access to secure region. Add common function for firewall setup and reuse for all SoC64 devices. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/sdram_agilex.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) (limited to 'drivers/ddr/altera/sdram_agilex.c') diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index 7f2cccb6af2..8aeb4320702 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2025 Altera Corporation * */ @@ -114,20 +115,6 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: %lld MiB\n", gd->ram_size >> 20); - /* This enables nonsecure access to DDR */ - /* mpuregion0addr_limit */ - FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, - FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); - FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); - - /* nonmpuregion0addr_limit */ - FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, - FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); - - /* Enable mpuregion0enable and nonmpuregion0enable */ - FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, - FW_MPU_DDR_SCR_EN_SET); - u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1); /* Enable or disable the DDR ECC */ @@ -162,6 +149,8 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_size_check(&bd); + sdram_set_firewall(&bd); + priv->info.base = bd.bi_dram[0].start; priv->info.size = gd->ram_size; -- cgit v1.2.3 From 2c0faf07218674fd0fe2abdd6264fcae28080e60 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Sun, 3 Aug 2025 18:24:39 -0700 Subject: ddr: altera: agilex: Remove code redundancy Remove redundant code for MPFE CSR firewall disabled as this was already set in DTreg dts. Signed-off-by: Tien Fong Chee Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/sdram_agilex.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/ddr/altera/sdram_agilex.c') diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index 8aeb4320702..e4655877a78 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -144,9 +144,6 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } - /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */ - writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); - sdram_size_check(&bd); sdram_set_firewall(&bd); -- cgit v1.2.3 From 1e354de7fc36c5cf1f7e77c5dca4713100fbb503 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Sun, 3 Aug 2025 18:24:41 -0700 Subject: ddr: altera: agilex: Get ACF from boot scratch register The DDR data rate must be set correctly in the DDRIOCTRL register according to the Actual Clock Frequency (ACF) value. By enabling the reading of ACF value from bit 18 of the boot scratch register during initialization, the DDR data rate is able to be configured accurately. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/sdram_agilex.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers/ddr/altera/sdram_agilex.c') diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index e4655877a78..b36a765a5de 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -73,12 +73,22 @@ int sdram_mmr_init_full(struct udevice *dev) */ /* Configure DDR IO size x16, x32 and x64 mode */ u32 update_value; + u32 reg; update_value = hmc_readl(plat, NIOSRESERVED0); update_value = (update_value & 0xFF) >> 5; - /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */ - update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4); + /* Read ACF from boot_scratch_cold_8 register bit[18]*/ + reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + reg = ((reg & SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK) + >> SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT); + + /* bit-2 of DDRIOCTRL: Configure DDR data rate 0-Half-rate 1-Quarter-rate */ + clrsetbits_le32(&update_value, + DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK, + reg << DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_SHIFT); + hmc_ecc_writel(plat, update_value, DDRIOCTRL); /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */ -- cgit v1.2.3