From a8571337d78093d2aff25add22df5cdc4e30f8a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 14 May 2021 21:34:20 -0400 Subject: ppc: Remove MPC8541CDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain Signed-off-by: Tom Rini --- drivers/ddr/fsl/ctrl_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/ddr/fsl/ctrl_regs.c') diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index c849ef3a4c7..b80034478e1 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1866,7 +1866,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int clk_adjust; /* Clock adjust */ unsigned int ss_en = 0; /* Source synchronous enable */ -#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) +#if defined(CONFIG_ARCH_MPC8555) /* Per FSL Application Note: AN2805 */ ss_en = 1; #endif -- cgit v1.2.3 From 98898601b46920904e63419fa38dd16a3e3b740e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 14 May 2021 21:34:21 -0400 Subject: ppc: Remove MPC8555CDS boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_MPC8555 platform left, remove that support as well. Cc: Priyanka Jain Signed-off-by: Tom Rini --- drivers/ddr/fsl/ctrl_regs.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) (limited to 'drivers/ddr/fsl/ctrl_regs.c') diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index b80034478e1..b5122d1a1c3 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1863,25 +1863,13 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { - unsigned int clk_adjust; /* Clock adjust */ - unsigned int ss_en = 0; /* Source synchronous enable */ - -#if defined(CONFIG_ARCH_MPC8555) - /* Per FSL Application Note: AN2805 */ - ss_en = 1; -#endif - if (fsl_ddr_get_version(0) >= 0x40701) { + if (fsl_ddr_get_version(0) >= 0x40701) /* clk_adjust in 5-bits on T-series and LS-series */ - clk_adjust = (popts->clk_adjust & 0x1F) << 22; - } else { + ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22; + else /* clk_adjust in 4-bits on earlier MPC85xx and P-series */ - clk_adjust = (popts->clk_adjust & 0xF) << 23; - } + ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23; - ddr->ddr_sdram_clk_cntl = (0 - | ((ss_en & 0x1) << 31) - | clk_adjust - ); debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); } -- cgit v1.2.3