From b335966958a93e49439bf248adadce89e7e2bee3 Mon Sep 17 00:00:00 2001 From: Oliver Chen Date: Tue, 21 Apr 2020 14:48:09 +0800 Subject: drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by: Ye Li Signed-off-by: Oliver Chen Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/ddr/imx/imx8m/ddr_init.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/ddr/imx/imx8m/ddr_init.c') diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index 664966c41bf..99a67edfb0a 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -190,6 +190,9 @@ int ddr_init(struct dram_timing_info *dram_timing) /* Step15: Set SWCTL.sw_done to 0 */ reg32_write(DDRC_SWCTL(0), 0x00000000); + /* Apply rank-to-rank workaround */ + update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); + /* Step16: Set DFIMISC.dfi_init_start to 1 */ setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); -- cgit v1.2.3