From b335966958a93e49439bf248adadce89e7e2bee3 Mon Sep 17 00:00:00 2001
From: Oliver Chen <Oliver.Chen@nxp.com>
Date: Tue, 21 Apr 2020 14:48:09 +0800
Subject: drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue

Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue

Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/ddr/imx/imx8m/ddrphy_train.c | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'drivers/ddr/imx/imx8m/ddrphy_train.c')

diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c
index f2a997b50a6..08fed6178f3 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_train.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_train.c
@@ -8,6 +8,7 @@
 #include <linux/kernel.h>
 #include <asm/arch/ddr.h>
 #include <asm/arch/lpddr4_define.h>
+#include <asm/arch/sys_proto.h>
 
 int ddr_cfg_phy(struct dram_timing_info *dram_timing)
 {
@@ -71,9 +72,15 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
 
 		/* Read the Message Block results */
 		dwc_ddrphy_apb_wr(0xd0000, 0x0);
+
 		ddrphy_init_read_msg_block(fsp_msg->fw_type);
+
+		if(fsp_msg->fw_type != FW_2D_IMAGE)
+			get_trained_CDD(i);
+
 		dwc_ddrphy_apb_wr(0xd0000, 0x1);
 
+
 		fsp_msg++;
 	}
 
-- 
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