From 662f05fcb6798277c69700c7deadd1c3c6a1b363 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 28 Apr 2023 12:08:39 +0800 Subject: ddr: imx9: Add workaround for DDRPHY rank-to-rank errata According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li Acked-by: Peng Fan --- drivers/ddr/imx/imx9/ddr_init.c | 122 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) (limited to 'drivers/ddr/imx/imx9/ddr_init.c') diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index 8b8ec7f8de3..a1d953026f3 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -12,6 +12,13 @@ #include #include +static unsigned int g_cdd_rr_max[4]; +static unsigned int g_cdd_rw_max[4]; +static unsigned int g_cdd_wr_max[4]; +static unsigned int g_cdd_ww_max[4]; + +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + void ddrphy_coldreset(void) { /* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */ @@ -74,8 +81,121 @@ void ddrc_config(struct dram_cfg_param *ddrc_config, int num) } } +static unsigned int look_for_max(unsigned int data[], unsigned int addr_start, + unsigned int addr_end) +{ + unsigned int i, imax = 0; + + for (i = addr_start; i <= addr_end; i++) { + if (((data[i] >> 7) == 0) && data[i] > imax) + imax = data[i]; + } + + return imax; +} + void get_trained_CDD(u32 fsp) { + unsigned int i, tmp; + unsigned int cdd_cha[12], cdd_chb[12]; + unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max; + unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max; + + for (i = 0; i < 6; i++) { + tmp = dwc_ddrphy_apb_rd(0x54013 + i); + cdd_cha[i * 2] = tmp & 0xff; + cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + for (i = 0; i < 7; i++) { + tmp = dwc_ddrphy_apb_rd(0x5402c + i); + + if (i == 0) { + cdd_chb[0] = (tmp >> 8) & 0xff; + } else if (i == 6) { + cdd_chb[11] = tmp & 0xff; + } else { + cdd_chb[i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2] = (tmp >> 8) & 0xff; + } + } + + cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1); + cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5); + cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9); + cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11); + cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1); + cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5); + cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9); + cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11); + g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; + g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; + g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; + g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; +} + +void update_umctl2_rank_space_setting(unsigned int pstat_num) +{ + u32 tmp, tmp_t; + + int wwt, rrt, wrt, rwt; + int ext_wwt, ext_rrt, ext_wrt, ext_rwt; + int max_wwt, max_rrt, max_wrt, max_rwt; + + /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */ + tmp = readl(REG_DDR_TIMING_CFG_0); + wwt = (tmp >> 24) & 0x3; + rrt = (tmp >> 26) & 0x3; + wrt = (tmp >> 28) & 0x3; + rwt = (tmp >> 30) & 0x3; + + /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */ + tmp_t = readl(REG_DDR_TIMING_CFG_4); + ext_wwt = (tmp >> 8) & 0x1; + ext_rrt = (tmp >> 10) & 0x1; + ext_wrt = (tmp >> 12) & 0x1; + ext_rwt = (tmp >> 14) & 0x3; + + wwt = (ext_wwt << 2) | wwt; + rrt = (ext_rrt << 2) | wwt; + wrt = (ext_wrt << 2) | wrt; + rwt = (ext_rwt << 2) | rwt; + + /* calculate the maximum between controller and cdd values */ + max_wwt = MAX(g_cdd_ww_max[0], wwt); + max_rrt = MAX(g_cdd_rr_max[0], rrt); + max_wrt = MAX(g_cdd_wr_max[0], wrt); + max_rwt = MAX(g_cdd_rw_max[0], rwt); + + /* verify values to see if are bigger then 7 or 15 (3 bits or 4 bits) */ + if (max_wwt > 7) + max_wwt = 7; + if (max_rrt > 7) + max_rrt = 7; + if (max_wrt > 7) + max_wrt = 7; + if (max_rwt > 15) + max_rwt = 15; + + /* recalculate timings for controller registers */ + wwt = max_wwt & 0x3; + rrt = max_rrt & 0x3; + wrt = max_wrt & 0x3; + rwt = max_rwt & 0x3; + + ext_wwt = (max_wwt & 0x4) >> 2; + ext_rrt = (max_rrt & 0x4) >> 2; + ext_wrt = (max_wrt & 0x4) >> 2; + ext_rwt = (max_rwt & 0xC) >> 2; + + /* update timing_cfg_0 and timing_cfg_4 */ + tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) | + (rrt << 26) | (wwt << 24); + writel(tmp, REG_DDR_TIMING_CFG_0); + + tmp_t = (tmp_t & 0xFFFF2AFF) | (ext_rwt << 14) | + (ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8); + writel(tmp_t, REG_DDR_TIMING_CFG_4); } int ddr_init(struct dram_timing_info *dram_timing) @@ -112,6 +232,8 @@ int ddr_init(struct dram_timing_info *dram_timing) ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); debug("DDRINFO: ddrc config done\n"); + update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); + #ifdef CONFIG_IMX9_DRAM_PM_COUNTER writel(0x200000, REG_DDR_DEBUG_19); #endif -- cgit v1.2.3 From 8e81e679db3248f2b3c34aee5302cd15a8283293 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 28 Apr 2023 12:08:43 +0800 Subject: ddr: imx93: update the ddr init to support mult setpoints Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan --- drivers/ddr/imx/imx9/ddr_init.c | 113 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 110 insertions(+), 3 deletions(-) (limited to 'drivers/ddr/imx/imx9/ddr_init.c') diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index a1d953026f3..a2158094b28 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -71,14 +71,25 @@ void check_dfi_init_complete(void) setbits_le32(REG_DDRDSR_2, BIT(2)); } -void ddrc_config(struct dram_cfg_param *ddrc_config, int num) +void ddrc_config(struct dram_timing_info *dram_timing) { + u32 num = dram_timing->ddrc_cfg_num; + struct dram_cfg_param *ddrc_config; int i = 0; + ddrc_config = dram_timing->ddrc_cfg; for (i = 0; i < num; i++) { writel(ddrc_config->val, (ulong)ddrc_config->reg); ddrc_config++; } + + if (dram_timing->fsp_cfg) { + ddrc_config = dram_timing->fsp_cfg[0].ddrc_cfg; + while (ddrc_config->reg != 0) { + writel(ddrc_config->val, (ulong)ddrc_config->reg); + ddrc_config++; + } + } } static unsigned int look_for_max(unsigned int data[], unsigned int addr_start, @@ -198,10 +209,85 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) writel(tmp_t, REG_DDR_TIMING_CFG_4); } +u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val) +{ + u32 temp; + + writel(0x80000000, REG_DDR_SDRAM_MD_CNTL_2); + temp = 0x80000000 | (chip_select << 28) | (mode_reg_num << 0); + writel(temp, REG_DDR_SDRAM_MD_CNTL); + while ((readl(REG_DDR_SDRAM_MD_CNTL) & 0x80000000) == 0x80000000) + ; + while (!(readl(REG_DDR_SDRAM_MPR5))) + ; + *mode_reg_val = (readl(REG_DDR_SDRAM_MPR4) & 0xFF0000) >> 16; + writel(0x0, REG_DDR_SDRAM_MPR5); + while ((readl(REG_DDR_SDRAM_MPR5))) + ; + writel(0x0, REG_DDR_SDRAM_MPR4); + writel(0x0, REG_DDR_SDRAM_MD_CNTL_2); + + return 0; +} + +void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr) +{ + u32 regval; + + regval = (cs_sel << 28) | (opcode << 6) | (mr); + writel(regval, REG_DDR_SDRAM_MD_CNTL); + setbits_le32(REG_DDR_SDRAM_MD_CNTL, BIT(31)); + check_ddrc_idle(); +} + +u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr) +{ + u32 chip_select, regval; + + if (mr_rank == 1) + chip_select = 0; /* CS0 */ + else if (mr_rank == 2) + chip_select = 1; /* CS1 */ + else + chip_select = 4; /* CS0 & CS1 */ + + ddrc_mrr(chip_select, mr_addr, ®val); + + return regval; +} + +void update_mr_fsp_op0(struct dram_cfg_param *cfg, unsigned int num) +{ + int i; + + ddrc_mrs(0x4, 0x88, 13); /* FSP-OP->1, FSP-WR->0, VRCG=1, DMD=0 */ + for (i = 0; i < num; i++) { + if (cfg[i].reg) + ddrc_mrs(0x4, cfg[i].val, cfg[i].reg); + } + ddrc_mrs(0x4, 0xc0, 13); /* FSP-OP->1, FSP-WR->1, VRCG=0, DMD=0 */ +} + +void save_trained_mr12_14(struct dram_cfg_param *cfg, u32 cfg_num, u32 mr12, u32 mr14) +{ + int i; + + for (i = 0; i < cfg_num; i++) { + if (cfg->reg == 12) + cfg->val = mr12; + else if (cfg->reg == 14) + cfg->val = mr14; + cfg++; + } +} + int ddr_init(struct dram_timing_info *dram_timing) { unsigned int initial_drate; + struct dram_timing_info *saved_timing; + void *fsp; int ret; + u32 mr12, mr14; u32 regval; debug("DDRINFO: start DRAM init\n"); @@ -229,7 +315,7 @@ int ddr_init(struct dram_timing_info *dram_timing) /* rogram the ddrc registers */ debug("DDRINFO: ddrc config start\n"); - ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + ddrc_config(dram_timing); debug("DDRINFO: ddrc config done\n"); update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); @@ -245,8 +331,29 @@ int ddr_init(struct dram_timing_info *dram_timing) check_ddrc_idle(); + mr12 = lpddr4_mr_read(1, 12); + mr14 = lpddr4_mr_read(1, 14); + /* save the dram timing config into memory */ - dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); + fsp = dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); + + saved_timing = (struct dram_timing_info *)CONFIG_SAVED_DRAM_TIMING_BASE; + saved_timing->fsp_cfg = fsp; + saved_timing->fsp_cfg_num = dram_timing->fsp_cfg_num; + if (saved_timing->fsp_cfg_num) { + memcpy(saved_timing->fsp_cfg, dram_timing->fsp_cfg, + dram_timing->fsp_cfg_num * sizeof(struct dram_fsp_cfg)); + + save_trained_mr12_14(saved_timing->fsp_cfg[0].mr_cfg, + ARRAY_SIZE(saved_timing->fsp_cfg[0].mr_cfg), mr12, mr14); + /* + * Configure mode registers in fsp1 to mode register 0 because DDRC + * doesn't automatically set. + */ + if (saved_timing->fsp_cfg_num > 1) + update_mr_fsp_op0(saved_timing->fsp_cfg[1].mr_cfg, + ARRAY_SIZE(saved_timing->fsp_cfg[1].mr_cfg)); + } return 0; } -- cgit v1.2.3 From 212a4e19615102277718f6adaa0282b2a69d7320 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 28 Apr 2023 12:08:44 +0800 Subject: ddr: imx9: update the rank setting for multi fsp support The rank setting flow should be updated to support multi fsp config. Signed-off-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan --- drivers/ddr/imx/imx9/ddr_init.c | 178 ++++++++++++++++++++++++++-------------- 1 file changed, 116 insertions(+), 62 deletions(-) (limited to 'drivers/ddr/imx/imx9/ddr_init.c') diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index a2158094b28..7a333880e6b 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -145,68 +145,122 @@ void get_trained_CDD(u32 fsp) g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; } -void update_umctl2_rank_space_setting(unsigned int pstat_num) +static u32 ddrc_get_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, unsigned int cfg_num, u32 reg) { - u32 tmp, tmp_t; + unsigned int i; + + for (i = 0; i < cfg_num; i++) { + if (reg == ddrc_cfg[i].reg) + return ddrc_cfg[i].val; + } - int wwt, rrt, wrt, rwt; - int ext_wwt, ext_rrt, ext_wrt, ext_rwt; - int max_wwt, max_rrt, max_wrt, max_rwt; - - /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */ - tmp = readl(REG_DDR_TIMING_CFG_0); - wwt = (tmp >> 24) & 0x3; - rrt = (tmp >> 26) & 0x3; - wrt = (tmp >> 28) & 0x3; - rwt = (tmp >> 30) & 0x3; - - /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */ - tmp_t = readl(REG_DDR_TIMING_CFG_4); - ext_wwt = (tmp >> 8) & 0x1; - ext_rrt = (tmp >> 10) & 0x1; - ext_wrt = (tmp >> 12) & 0x1; - ext_rwt = (tmp >> 14) & 0x3; - - wwt = (ext_wwt << 2) | wwt; - rrt = (ext_rrt << 2) | wwt; - wrt = (ext_wrt << 2) | wrt; - rwt = (ext_rwt << 2) | rwt; - - /* calculate the maximum between controller and cdd values */ - max_wwt = MAX(g_cdd_ww_max[0], wwt); - max_rrt = MAX(g_cdd_rr_max[0], rrt); - max_wrt = MAX(g_cdd_wr_max[0], wrt); - max_rwt = MAX(g_cdd_rw_max[0], rwt); - - /* verify values to see if are bigger then 7 or 15 (3 bits or 4 bits) */ - if (max_wwt > 7) - max_wwt = 7; - if (max_rrt > 7) - max_rrt = 7; - if (max_wrt > 7) - max_wrt = 7; - if (max_rwt > 15) - max_rwt = 15; - - /* recalculate timings for controller registers */ - wwt = max_wwt & 0x3; - rrt = max_rrt & 0x3; - wrt = max_wrt & 0x3; - rwt = max_rwt & 0x3; - - ext_wwt = (max_wwt & 0x4) >> 2; - ext_rrt = (max_rrt & 0x4) >> 2; - ext_wrt = (max_wrt & 0x4) >> 2; - ext_rwt = (max_rwt & 0xC) >> 2; - - /* update timing_cfg_0 and timing_cfg_4 */ - tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) | - (rrt << 26) | (wwt << 24); - writel(tmp, REG_DDR_TIMING_CFG_0); - - tmp_t = (tmp_t & 0xFFFF2AFF) | (ext_rwt << 14) | - (ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8); - writel(tmp_t, REG_DDR_TIMING_CFG_4); + return 0; +} + +static void ddrc_update_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, int cfg_num, + u32 reg, u32 val) +{ + unsigned int i; + + for (i = 0; i < cfg_num; i++) { + if (reg == ddrc_cfg[i].reg) { + ddrc_cfg[i].val = val; + return; + } + } +} + +void update_umctl2_rank_space_setting(struct dram_timing_info *dram_timing, unsigned int pstat_num) +{ + u32 tmp, tmp_t; + u32 wwt, rrt, wrt, rwt; + u32 ext_wwt, ext_rrt, ext_wrt, ext_rwt; + u32 max_wwt, max_rrt, max_wrt, max_rwt; + u32 i; + + for (i = 0; i < pstat_num; i++) { + /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */ + if (!dram_timing->fsp_cfg_num) { + tmp = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg, + dram_timing->ddrc_cfg_num, + REG_DDR_TIMING_CFG_0); + } else { + tmp = ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg, + ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg), + REG_DDR_TIMING_CFG_0); + } + wwt = (tmp >> 24) & 0x3; + rrt = (tmp >> 26) & 0x3; + wrt = (tmp >> 28) & 0x3; + rwt = (tmp >> 30) & 0x3; + + /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */ + if (!dram_timing->fsp_cfg_num) { + tmp_t = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg, + dram_timing->ddrc_cfg_num, + REG_DDR_TIMING_CFG_4); + } else { + tmp_t = ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg, + ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg), + REG_DDR_TIMING_CFG_4); + } + ext_wwt = (tmp_t >> 8) & 0x3; + ext_rrt = (tmp_t >> 10) & 0x3; + ext_wrt = (tmp_t >> 12) & 0x3; + ext_rwt = (tmp_t >> 14) & 0x3; + + wwt = (ext_wwt << 2) | wwt; + rrt = (ext_rrt << 2) | rrt; + wrt = (ext_wrt << 2) | wrt; + rwt = (ext_rwt << 2) | rwt; + + max_wwt = MAX(g_cdd_ww_max[0], wwt); + max_rrt = MAX(g_cdd_rr_max[0], rrt); + max_wrt = MAX(g_cdd_wr_max[0], wrt); + max_rwt = MAX(g_cdd_rw_max[0], rwt); + /* verify values to see if are bigger then 15 (4 bits) */ + if (max_wwt > 15) + max_wwt = 15; + if (max_rrt > 15) + max_rrt = 15; + if (max_wrt > 15) + max_wrt = 15; + if (max_rwt > 15) + max_rwt = 15; + + /* recalculate timings for controller registers */ + wwt = max_wwt & 0x3; + rrt = max_rrt & 0x3; + wrt = max_wrt & 0x3; + rwt = max_rwt & 0x3; + + ext_wwt = (max_wwt & 0xC) >> 2; + ext_rrt = (max_rrt & 0xC) >> 2; + ext_wrt = (max_wrt & 0xC) >> 2; + ext_rwt = (max_rwt & 0xC) >> 2; + + /* update timing_cfg_0 and timing_cfg_4 */ + tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) | + (rrt << 26) | (wwt << 24); + tmp_t = (tmp_t & 0xFFFF00FF) | (ext_rwt << 14) | + (ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8); + + if (!dram_timing->fsp_cfg_num) { + ddrc_update_fsp_reg_setting(dram_timing->ddrc_cfg, + dram_timing->ddrc_cfg_num, + REG_DDR_TIMING_CFG_0, tmp); + ddrc_update_fsp_reg_setting(dram_timing->ddrc_cfg, + dram_timing->ddrc_cfg_num, + REG_DDR_TIMING_CFG_4, tmp_t); + } else { + ddrc_update_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg, + ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg), + REG_DDR_TIMING_CFG_0, tmp); + ddrc_update_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg, + ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg), + REG_DDR_TIMING_CFG_4, tmp_t); + } + } } u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val) @@ -313,13 +367,13 @@ int ddr_init(struct dram_timing_info *dram_timing) debug("DDRINFO: ddrphy config done\n"); + update_umctl2_rank_space_setting(dram_timing, dram_timing->fsp_msg_num - 1); + /* rogram the ddrc registers */ debug("DDRINFO: ddrc config start\n"); ddrc_config(dram_timing); debug("DDRINFO: ddrc config done\n"); - update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); - #ifdef CONFIG_IMX9_DRAM_PM_COUNTER writel(0x200000, REG_DDR_DEBUG_19); #endif -- cgit v1.2.3