From 1b631589d4844a129e1019160fef7aeda6fb50ff Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 19 Sep 2024 12:01:29 +0800 Subject: imx9: Add 233Mhz DDR PLL frequency To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq to DDR PLL for second mission point at 933MTS. Otherwise DDR training will fail. Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/ddr/imx/phy/ddrphy_utils.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/ddr/imx/phy/ddrphy_utils.c') diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index cf5bdad7abe..14278f5ad8f 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -148,6 +148,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(266)); dram_disable_bypass(); break; + case 933: + dram_pll_init(MHZ(233)); + dram_disable_bypass(); + break; case 667: dram_pll_init(MHZ(167)); dram_disable_bypass(); -- cgit v1.2.3