From 672e5598301b63f95d7dcceb4436f3cb40643f88 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 18 Jan 2018 17:16:10 +1300 Subject: ddr: marvell: update ddr controller init and freq Update the calculation for tWR and tPD. This improves the DDR refresh interval and brings the initialization into line with the binary blobs currently being supplied by Marvell. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_topology_def.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/ddr/marvell/a38x/ddr3_topology_def.h') diff --git a/drivers/ddr/marvell/a38x/ddr3_topology_def.h b/drivers/ddr/marvell/a38x/ddr3_topology_def.h index 64a0447dd15..a17eca04187 100644 --- a/drivers/ddr/marvell/a38x/ddr3_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr3_topology_def.h @@ -70,7 +70,8 @@ enum speed_bin_table_elements { SPEED_BIN_TWTR, SPEED_BIN_TRTP, SPEED_BIN_TWR, - SPEED_BIN_TMOD + SPEED_BIN_TMOD, + SPEED_BIN_TXPDLL }; #endif /* _DDR3_TOPOLOGY_DEF_H */ -- cgit v1.2.3