From 2b4ffbf6b4944a0b3125fd2c9c0ba3568264367a Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 10 May 2018 13:28:29 +1200 Subject: ARM: mvebu: a38x: sync ddr training code with upstream This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_ip_static.h | 30 ---------------------- 1 file changed, 30 deletions(-) delete mode 100644 drivers/ddr/marvell/a38x/ddr3_training_ip_static.h (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_static.h') diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_static.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_static.h deleted file mode 100644 index d5760fce082..00000000000 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_static.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) Marvell International Ltd. and its affiliates - */ - -#ifndef _DDR3_TRAINING_IP_STATIC_H_ -#define _DDR3_TRAINING_IP_STATIC_H_ - -#include "ddr3_training_ip_def.h" -#include "ddr3_training_ip.h" - -struct trip_delay_element { - u32 dqs_delay; /* DQS delay (m_sec) */ - u32 ck_delay; /* CK Delay (m_sec) */ -}; - -struct hws_tip_static_config_info { - u32 silicon_delay; - struct trip_delay_element *package_trace_arr; - struct trip_delay_element *board_trace_arr; -}; - -int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq); -int ddr3_tip_init_static_config_db( - u32 dev_num, struct hws_tip_static_config_info *static_config_info); -int ddr3_tip_init_specific_reg_config(u32 dev_num, - struct reg_data *reg_config_arr); -int ddr3_tip_static_phy_init_controller(u32 dev_num); - -#endif /* _DDR3_TRAINING_IP_STATIC_H_ */ -- cgit v1.2.3