From dbaf09590df9add19e738d2de03c0f2d0d8f5433 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 18 Jan 2018 17:16:07 +1300 Subject: ddr: marvell: only assert M_ODT[0] on write for a single CS When using only a single DDR chip select only assert M_ODT[0] on write. Do not assert it on read and do not assert M_ODT[1] at all. Also set tODT_OFF_WR to 0x9 which contradicts the recommendation from the functional spec but is what Marvell's binary training blob does and seems to give better results when ODT is active during writes. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_static.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/ddr/marvell/a38x/ddr3_training_static.c') diff --git a/drivers/ddr/marvell/a38x/ddr3_training_static.c b/drivers/ddr/marvell/a38x/ddr3_training_static.c index 5101f3f3834..b73bbf4f1b0 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_static.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_static.c @@ -21,7 +21,8 @@ u32 g_zpodt_data = 45; /* controller data - P ODT */ u32 g_znodt_data = 45; /* controller data - N ODT */ u32 g_zpodt_ctrl = 45; /* controller data - P ODT */ u32 g_znodt_ctrl = 45; /* controller data - N ODT */ -u32 g_odt_config = 0x120012; +u32 g_odt_config_2cs = 0x120012; +u32 g_odt_config_1cs = 0x10000; u32 g_rtt_nom = 0x44; u32 g_dic = 0x2; -- cgit v1.2.3