From 1dbd0bd599de8cb105c2dbd8aa2361fe2f353702 Mon Sep 17 00:00:00 2001 From: Alex Leibovich Date: Fri, 19 Feb 2021 17:11:12 +0100 Subject: ddr: marvell: a38x: add ddr 32bit ECC support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by: Alex Leibovich Reviewed-by: Kostya Porotchkin Signed-off-by: Marek Behún Tested-by: Chris Packham --- drivers/ddr/marvell/a38x/mv_ddr_topology.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/ddr/marvell/a38x/mv_ddr_topology.c') diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index f2cd7c0ef3f..0cbe8d3d1ea 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -74,6 +74,10 @@ int mv_ddr_topology_map_update(void) /* update device width in topology map */ iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data); + /* overwrite SPD configuration, with what the user set */ + if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) + mv_ddr_spd_die_capacity_user_get(&tm->spd_data, tm->interface_params[0].memory_size); + /* update die capacity in topology map */ iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data); @@ -144,7 +148,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void) unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); if (tm->cfg_src == MV_DDR_CFG_SPD) { - if (tm->bus_act_mask == BUS_MASK_32BIT) + if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32; enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data); -- cgit v1.2.3