From cae6e8993c8eaed7c520b1046766b658e0f97b90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 18 Jun 2024 17:34:35 +0200 Subject: ddr: marvell: a38x: Import old DDR training code from 2017 version of U-Boot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Import DDR training code from commit 1b69ce2fc0ec ("arm: mvebu: ddr3_debug: remove self assignments") into drivers/ddr/marvell/a38x/old/. The code is not used yet. Explanation: Since 2019, on some Turris Omnia boards we have been having problems with newer versions of Marvell's DDR3 training code for Armada 38x, which is ported from mv-ddr-marvell [1] to U-Boot into the drivers/ddr/marvell/a38x/ directory: - sometimes the DDR3 training fails on some older boards, sometime it fails on some newer boards - other times it succeeds, but some boards experience crashes of the operating system after running for some time. Using the stock version of Turris Omnia's U-Boot from solved these issues, but this solution was not satisfactory, since we wanted features from new U-Boot. Back in 2020-2022 we have spent several months trying to debug the issues, working with Marvell, on our own, and also with U-Boot community, but these issues persist still. One solution we used back in 2019 was a "hybrid U-Boot": the SPL part (containing the DDR3 training code) was taken from the stock version, while the proper part was current U-Boot at the time. This solution also has its drawbacks, of which the main one is the need to glue binaries from two separate builds. Since then there have been some more changes to the DDR3 training code in upstream mv-ddr-marvell that have been ported to U-Boot. We have provided our users experimental builds of U-Boot in the TurrisOS so that they could try upgrading the firmware and let us know if those problems still exist. And they do. We do not have the time nor manpower to debug this problem and fix it properly. Marvell was also no able to provide a solution to this, probably because they do not have the manpower as well. I have therefore come up with this "not that pretty" solution: take the DDR3 training code from an older version of U-Boot that is known to work, put it into current U-Boot under old/ subdirectory within drivers/ddr/marvell/a38x/, build into the SPL binary both the old and new versions and make it possible to select the old version via an env variable. [1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell Signed-off-by: Marek Behún --- drivers/ddr/marvell/a38x/old/ddr_topology_def.h | 121 ++++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 drivers/ddr/marvell/a38x/old/ddr_topology_def.h (limited to 'drivers/ddr/marvell/a38x/old/ddr_topology_def.h') diff --git a/drivers/ddr/marvell/a38x/old/ddr_topology_def.h b/drivers/ddr/marvell/a38x/old/ddr_topology_def.h new file mode 100644 index 00000000000..229c3a127a8 --- /dev/null +++ b/drivers/ddr/marvell/a38x/old/ddr_topology_def.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) Marvell International Ltd. and its affiliates + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DDR_TOPOLOGY_DEF_H +#define _DDR_TOPOLOGY_DEF_H + +#include "ddr3_training_ip_def.h" +#include "ddr3_topology_def.h" + +#if defined(CONFIG_ARMADA_38X) +#include "ddr3_a38x.h" +#endif + +/* bus width in bits */ +enum hws_bus_width { + BUS_WIDTH_4, + BUS_WIDTH_8, + BUS_WIDTH_16, + BUS_WIDTH_32 +}; + +enum hws_temperature { + HWS_TEMP_LOW, + HWS_TEMP_NORMAL, + HWS_TEMP_HIGH +}; + +enum hws_mem_size { + MEM_512M, + MEM_1G, + MEM_2G, + MEM_4G, + MEM_8G, + MEM_SIZE_LAST +}; + +enum hws_timing { + HWS_TIM_DEFAULT, + HWS_TIM_1T, + HWS_TIM_2T +}; + +struct bus_params { + /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ + u8 cs_bitmask; + + /* + * mirror enable/disable + * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...) + */ + int mirror_enable_bitmask; + + /* DQS Swap (polarity) - true if enable */ + int is_dqs_swap; + + /* CK swap (polarity) - true if enable */ + int is_ck_swap; +}; + +struct if_params { + /* bus configuration */ + struct bus_params as_bus_params[MAX_BUS_NUM]; + + /* Speed Bin Table */ + enum hws_speed_bin speed_bin_index; + + /* bus width of memory */ + enum hws_bus_width bus_width; + + /* Bus memory size (MBit) */ + enum hws_mem_size memory_size; + + /* The DDR frequency for each interfaces */ + enum hws_ddr_freq memory_freq; + + /* + * delay CAS Write Latency + * - 0 for using default value (jedec suggested) + */ + u8 cas_wl; + + /* + * delay CAS Latency + * - 0 for using default value (jedec suggested) + */ + u8 cas_l; + + /* operation temperature */ + enum hws_temperature interface_temp; + + /* 2T vs 1T mode (by default computed from number of CSs) */ + enum hws_timing timing; +}; + +struct hws_topology_map { + /* Number of interfaces (default is 12) */ + u8 if_act_mask; + + /* Controller configuration per interface */ + struct if_params interface_params[MAX_INTERFACE_NUM]; + + /* BUS per interface (default is 4) */ + u8 num_of_bus_per_interface; + + /* Bit mask for active buses */ + u8 bus_act_mask; +}; + +/* DDR3 training global configuration parameters */ +struct tune_train_params { + u32 ck_delay; + u32 ck_delay_16; + u32 p_finger; + u32 n_finger; + u32 phy_reg3_val; +}; + +#endif /* _DDR_TOPOLOGY_DEF_H */ -- cgit v1.2.3