From 65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:41 -0500 Subject: global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/fpga/virtex2.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers/fpga/virtex2.c') diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 0d536f0d044..8871deaea6f 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -49,8 +49,8 @@ * which yields 11.44 mS. So let's make it bigger in order to handle * an XC2V1000, if anyone can ever get ahold of one. */ -#ifndef CONFIG_SYS_FPGA_WAIT_INIT -#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ +#ifndef CFG_SYS_FPGA_WAIT_INIT +#define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ #endif /* @@ -58,15 +58,15 @@ * This is normally not necessary since for most reasonable configuration * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. */ -#ifndef CONFIG_SYS_FPGA_WAIT_BUSY -#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ +#ifndef CFG_SYS_FPGA_WAIT_BUSY +#define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ #endif /* Default timeout for waiting for FPGA to enter operational mode after * configuration data has been written. */ -#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG -#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ +#ifndef CFG_SYS_FPGA_WAIT_CONFIG +#define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ #endif static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -190,9 +190,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) udelay(10); ts = get_timer(0); do { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); (*fn->abort)(cookie); return FPGA_FAIL; } @@ -209,9 +209,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) ts = get_timer(0); do { CONFIG_FPGA_DELAY(); - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); (*fn->abort)(cookie); return FPGA_FAIL; } @@ -260,9 +260,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, break; } - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) { printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG); (*fn->abort)(cookie); ret_val = FPGA_FAIL; break; @@ -350,10 +350,10 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer(0); while ((*fn->busy)(cookie)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) { printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n", __func__, __LINE__, - CONFIG_SYS_FPGA_WAIT_BUSY); + CFG_SYS_FPGA_WAIT_BUSY); (*fn->abort)(cookie); return FPGA_FAIL; } -- cgit v1.2.3 From f00f676af6bcae0702efbac45b88c1b8b686d400 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:29 -0500 Subject: Convert CONFIG_SYS_FPGA_CHECK_BUSY to Kconfig This converts the following to Kconfig: CONFIG_SYS_FPGA_CHECK_BUSY Signed-off-by: Tom Rini --- drivers/fpga/virtex2.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers/fpga/virtex2.c') diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 8871deaea6f..ed2a4163f6e 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -21,14 +21,11 @@ #include /* - * If the SelectMap interface can be overrun by the processor, define - * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board + * If the SelectMap interface can be overrun by the processor, enable + * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CONFIG_FPGA_DELAY in the board * configuration file and add board-specific support for checking BUSY status. * By default, assume that the SelectMap interface cannot be overrun. */ -#ifndef CONFIG_SYS_FPGA_CHECK_BUSY -#undef CONFIG_SYS_FPGA_CHECK_BUSY -#endif #ifndef CONFIG_FPGA_DELAY #define CONFIG_FPGA_DELAY() -- cgit v1.2.3 From 72fc26450493335ae191afdfcbbbb328b1df6b4d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:57 -0500 Subject: global: Migrate CONFIG_FPGA_DELAY to CFG Perform a simple rename of CONFIG_FPGA_DELAY to CFG_FPGA_DELAY Signed-off-by: Tom Rini --- drivers/fpga/virtex2.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/fpga/virtex2.c') diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index ed2a4163f6e..fc99a5f4831 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -22,13 +22,13 @@ /* * If the SelectMap interface can be overrun by the processor, enable - * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CONFIG_FPGA_DELAY in the board + * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board * configuration file and add board-specific support for checking BUSY status. * By default, assume that the SelectMap interface cannot be overrun. */ -#ifndef CONFIG_FPGA_DELAY -#define CONFIG_FPGA_DELAY() +#ifndef CFG_FPGA_DELAY +#define CFG_FPGA_DELAY() #endif /* @@ -196,7 +196,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) } while (!(*fn->init)(cookie)); (*fn->pgm)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (fn->clk) (*fn->clk)(true, true, cookie); @@ -205,7 +205,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) */ ts = get_timer(0); do { - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); @@ -233,7 +233,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, /* * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. */ - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (fn->cs) (*fn->cs)(false, true, cookie); if (fn->wr) @@ -269,9 +269,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, (*fn->wbulkdata)(&dummy, 1, true, cookie); } else { (*fn->wdata)(0xff, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); } } @@ -335,13 +335,13 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif (*fn->wdata)(data[bytecount++], true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); /* * Cycle the clock pin */ (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); #ifdef CONFIG_SYS_FPGA_CHECK_BUSY @@ -472,9 +472,9 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) for (bit = 7; bit >= 0; --bit) { unsigned char curr_bit = (curr_data >> bit) & 1; (*fn->wdata)(curr_bit, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); } -- cgit v1.2.3