From 6d87b1572f854435a68f868624f91673c91985e1 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 1 Feb 2023 02:55:53 -0700 Subject: arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependencies There are missing Kconfig dependencies in the code which is using firmware interface. The commit 71efd45a5fc7 ("arm64: zynqmp: Change firmware dependency") add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig dependencies were properly described and also sdhci and gem drivers didn't protect the code properly. So, add the missing ZYNQMP_FIRMWARE dependencies. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/fpga/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 61490d6d8de..62cb77b098c 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -75,7 +75,7 @@ config FPGA_XILINX config FPGA_ZYNQMPPL bool "Enable Xilinx FPGA driver for ZynqMP" - depends on FPGA_XILINX + depends on FPGA_XILINX && ZYNQMP_FIRMWARE help Enable FPGA driver for loading bitstream in BIT and BIN format on Xilinx Zynq UltraScale+ (ZynqMP) device. -- cgit v1.2.3 From 749cbcfeacd7063c83506ff5add037cd621fe451 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Tue, 14 Feb 2023 13:19:59 +0000 Subject: fpga: zynqmppl: fix fpga loads command for unencrypted use case When using the fpga loads command, the driver is passing the AES encryption key address is all cases. However, for the authenticated, but not encrypted use case, there is no AES encryption key, and this value is 0. When AES encryption is not used on the fpga bitstream, the pmufw assumes that the AES key address is a bitstream size value like what is used by the unsecure fpga load command. To fix the problem, this patch checks to see if the AES key address is zero. If the AES key address is zero, it means that AES is not being used on the bitstream and the bitstream size should be passed instead. Thus, matching the fpga load functionality. Signed-off-by: Neal Frager Acked-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index d1491da02c3..7b5128fe27a 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -332,10 +332,16 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits((ulong)buf); buf_hi = upper_32_bits((ulong)buf); - ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + if ((u32)(uintptr_t)fpga_sec_info->userkey_addr) + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi, - (u32)(uintptr_t)fpga_sec_info->userkey_addr, - flag, ret_payload); + (u32)(uintptr_t)fpga_sec_info->userkey_addr, + flag, ret_payload); + else + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + buf_hi, (u32)bsize, + flag, ret_payload); + if (ret) puts("PL FPGA LOAD fail\n"); else -- cgit v1.2.3