From 923d89316ae6e48a4ce5abd4324c74aae38dddde Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 20 Oct 2021 23:01:29 -0500 Subject: i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C When the DM_I2C driver is loaded, the pin setup is done automatically from the device tree by the pinctrl driver. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/i2c/sun6i_p2wi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/i2c') diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c index c9e1b3fcd5f..73b808b09bf 100644 --- a/drivers/i2c/sun6i_p2wi.c +++ b/drivers/i2c/sun6i_p2wi.c @@ -102,12 +102,6 @@ static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base, static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base) { - /* Enable p2wi and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); - - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); - /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ writel(P2WI_CTRL_RESET, &base->ctrl); sdelay(0x100); @@ -142,6 +136,12 @@ void p2wi_init(void) { struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + /* Enable p2wi and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); + + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); + sun6i_p2wi_init(base); } #endif -- cgit v1.2.3 From af2ec35c4179620e2655f195ec0fd41e7a1ff784 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 20 Oct 2021 23:01:29 -0500 Subject: i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C When the DM_I2C driver is loaded, the pin setup is done automatically from the device tree by the pinctrl driver. Clean up the code in the process: remove #ifdefs and recognize that the pin configuration is the same for all sun8i/sun50i SoCs, not just those which select CONFIG_MACH_SUN8I. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/i2c/sun8i_rsb.c | 46 +++++++++++++++++++--------------------------- 1 file changed, 19 insertions(+), 27 deletions(-) (limited to 'drivers/i2c') diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c index 716b245a003..0dea8f7a923 100644 --- a/drivers/i2c/sun8i_rsb.c +++ b/drivers/i2c/sun8i_rsb.c @@ -95,27 +95,6 @@ static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base, return sun8i_rsb_do_trans(base); } -static void sun8i_rsb_cfg_io(void) -{ -#ifdef CONFIG_MACH_SUN8I - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); - sunxi_gpio_set_pull(SUNXI_GPL(0), 1); - sunxi_gpio_set_pull(SUNXI_GPL(1), 1); - sunxi_gpio_set_drv(SUNXI_GPL(0), 2); - sunxi_gpio_set_drv(SUNXI_GPL(1), 2); -#elif defined CONFIG_MACH_SUN9I - sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); - sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); - sunxi_gpio_set_pull(SUNXI_GPN(0), 1); - sunxi_gpio_set_pull(SUNXI_GPN(1), 1); - sunxi_gpio_set_drv(SUNXI_GPN(0), 2); - sunxi_gpio_set_drv(SUNXI_GPN(1), 2); -#else -#error unsupported MACH_SUNXI -#endif -} - static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base) { u32 div = 0; @@ -147,12 +126,6 @@ static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base) static int sun8i_rsb_init(struct sunxi_rsb_reg *base) { - /* Enable RSB and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); - - /* Setup external pins */ - sun8i_rsb_cfg_io(); - writel(RSB_CTRL_SOFT_RST, &base->ctrl); sun8i_rsb_set_clk(base); @@ -185,6 +158,25 @@ int rsb_init(void) { struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + /* Enable RSB and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + + if (IS_ENABLED(CONFIG_MACH_SUN9I)) { + sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); + sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); + sunxi_gpio_set_pull(SUNXI_GPN(0), 1); + sunxi_gpio_set_pull(SUNXI_GPN(1), 1); + sunxi_gpio_set_drv(SUNXI_GPN(0), 2); + sunxi_gpio_set_drv(SUNXI_GPN(1), 2); + } else { + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); + sunxi_gpio_set_pull(SUNXI_GPL(1), 1); + sunxi_gpio_set_drv(SUNXI_GPL(0), 2); + sunxi_gpio_set_drv(SUNXI_GPL(1), 2); + } + return sun8i_rsb_init(base); } #endif -- cgit v1.2.3 From 48457f7ab031884d749e84440f4e5ae798e77c39 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 17 Mar 2022 23:52:33 -0500 Subject: i2c: sun6i_p2wi: Initialize chips in .child_pre_probe Chips attached to the P2WI bus require an initialization command before they can be used. (Specifically, this switches the chip from I2C mode to P2WI mode.) The driver does this in its .probe_chip hook, under the assumption that .probe_chip is called during child probe. This is not the case; .probe_chip is only called by dm_i2c_probe, which is intended for use by board-level code, not for chips with OF nodes. Since this initialization command must be run before a child chip can be used, do it before probing each child. Signed-off-by: Samuel Holland Acked-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/i2c/sun6i_p2wi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/i2c') diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c index 73b808b09bf..064d82a6d1f 100644 --- a/drivers/i2c/sun6i_p2wi.c +++ b/drivers/i2c/sun6i_p2wi.c @@ -191,11 +191,12 @@ static int sun6i_p2wi_probe(struct udevice *bus) static int sun6i_p2wi_child_pre_probe(struct udevice *child) { struct dm_i2c_chip *chip = dev_get_parent_plat(child); + struct udevice *bus = child->parent; /* Ensure each transfer is for a single register. */ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS; - return 0; + return sun6i_p2wi_probe_chip(bus, chip->chip_addr, 0); } static const struct dm_i2c_ops sun6i_p2wi_ops = { -- cgit v1.2.3 From 07c411346cb2493e4f59a8affbd35f5efc2ec736 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 17 Mar 2022 23:52:34 -0500 Subject: i2c: sun6i_p2wi: Add support for DM clocks and resets Currently, clock/reset setup for this device is handled by a platform-specific function and is intermixed with non-DM pinctrl setup. Use the devicetree to get clocks/resets, which disentagles it from the pinctrl setup in preparation for moving to DM_PINCTRL. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/i2c/sun6i_p2wi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/i2c') diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c index 064d82a6d1f..d221323295d 100644 --- a/drivers/i2c/sun6i_p2wi.c +++ b/drivers/i2c/sun6i_p2wi.c @@ -14,10 +14,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -180,9 +182,19 @@ static int sun6i_p2wi_probe_chip(struct udevice *bus, uint chip_addr, static int sun6i_p2wi_probe(struct udevice *bus) { struct sun6i_p2wi_priv *priv = dev_get_priv(bus); + struct reset_ctl *reset; + struct clk *clk; priv->base = dev_read_addr_ptr(bus); + reset = devm_reset_control_get(bus, NULL); + if (!IS_ERR(reset)) + reset_deassert(reset); + + clk = devm_clk_get(bus, NULL); + if (!IS_ERR(clk)) + clk_enable(clk); + sun6i_p2wi_init(priv->base); return 0; -- cgit v1.2.3 From c9dd3caae3119c9f77081b5c1ef42553b44ddf20 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 17 Mar 2022 23:52:35 -0500 Subject: i2c: sun8i_rsb: Initialize chips in .child_pre_probe Chips attached to the RSB bus require an initialization command before they can be used. (Specifically, this command programs the chip's runtime address.) The driver does this in its .probe_chip hook, under the assumption that .probe_chip is called during child probe. This is not the case; .probe_chip is only called by dm_i2c_probe, which is intended for use by board-level code, not for chips with OF nodes. Since this initialization command must be run before a child chip can be used, do it before probing each child. Signed-off-by: Samuel Holland Acked-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/i2c/sun8i_rsb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/i2c') diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c index 0dea8f7a923..38d6e87577d 100644 --- a/drivers/i2c/sun8i_rsb.c +++ b/drivers/i2c/sun8i_rsb.c @@ -244,11 +244,12 @@ static int sun8i_rsb_probe(struct udevice *bus) static int sun8i_rsb_child_pre_probe(struct udevice *child) { struct dm_i2c_chip *chip = dev_get_parent_plat(child); + struct udevice *bus = child->parent; /* Ensure each transfer is for a single register. */ chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS; - return 0; + return sun8i_rsb_probe_chip(bus, chip->chip_addr, 0); } static const struct dm_i2c_ops sun8i_rsb_ops = { -- cgit v1.2.3 From f5bfe1575078cea8de0fa4affb529b360a511094 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 17 Mar 2022 23:52:36 -0500 Subject: i2c: sun8i_rsb: Add support for DM clocks and resets Currently, clock/reset setup for this device is handled by a platform-specific function and is intermixed with non-DM pinctrl setup. Use the devicetree to get clocks/resets, which disentagles it from the pinctrl setup in preparation for moving to DM_PINCTRL. This also has the added benefit of picking the right clock/reset bits for H6 and new SoCs that have a rearranged PRCM MMIO space. Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- drivers/i2c/sun8i_rsb.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/i2c') diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c index 38d6e87577d..47fa05b6d1c 100644 --- a/drivers/i2c/sun8i_rsb.c +++ b/drivers/i2c/sun8i_rsb.c @@ -9,10 +9,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -235,9 +237,19 @@ static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr, static int sun8i_rsb_probe(struct udevice *bus) { struct sun8i_rsb_priv *priv = dev_get_priv(bus); + struct reset_ctl *reset; + struct clk *clk; priv->base = dev_read_addr_ptr(bus); + reset = devm_reset_control_get(bus, NULL); + if (!IS_ERR(reset)) + reset_deassert(reset); + + clk = devm_clk_get(bus, NULL); + if (!IS_ERR(clk)) + clk_enable(clk); + return sun8i_rsb_init(priv->base); } -- cgit v1.2.3