From 0c00d03aca356c295daafe82873ecfc9d7769dd9 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 7 Aug 2021 16:00:41 +0800 Subject: driver: misc: Add MU and S400 API to communicate with Sentinel Add MU driver and S400 API. Need enable MISC driver to work Signed-off-by: Ye Li --- drivers/misc/imx8ulp/imx8ulp_mu.c | 247 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) create mode 100644 drivers/misc/imx8ulp/imx8ulp_mu.c (limited to 'drivers/misc/imx8ulp/imx8ulp_mu.c') diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/imx8ulp/imx8ulp_mu.c new file mode 100644 index 00000000000..3f6dd558e63 --- /dev/null +++ b/drivers/misc/imx8ulp/imx8ulp_mu.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct mu_type { + u32 ver; + u32 par; + u32 cr; + u32 sr; + u32 reserved0[68]; + u32 tcr; + u32 tsr; + u32 rcr; + u32 rsr; + u32 reserved1[52]; + u32 tr[16]; + u32 reserved2[16]; + u32 rr[16]; + u32 reserved4[14]; + u32 mu_attr; +}; + +struct imx8ulp_mu { + struct mu_type *base; +}; + +#define MU_SR_TE0_MASK BIT(0) +#define MU_SR_RF0_MASK BIT(0) +#define MU_TR_COUNT 4 +#define MU_RR_COUNT 4 + +static inline void mu_hal_init(struct mu_type *base) +{ + writel(0, &base->tcr); + writel(0, &base->rcr); +} + +static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg) +{ + u32 mask = MU_SR_TE0_MASK << reg_index; + u32 val; + int ret; + + assert(reg_index < MU_TR_COUNT); + + debug("sendmsg sr 0x%x\n", readl(&base->sr)); + + /* Wait TX register to be empty. */ + ret = readl_poll_timeout(&base->tsr, val, val & mask, 10000); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + debug("tr[%d] 0x%x\n", reg_index, msg); + + writel(msg, &base->tr[reg_index]); + + return 0; +} + +static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg) +{ + u32 mask = MU_SR_RF0_MASK << reg_index; + u32 val; + int ret; + + assert(reg_index < MU_TR_COUNT); + + debug("receivemsg sr 0x%x\n", readl(&base->sr)); + + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&base->rsr, val, val & mask, 10000); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + *msg = readl(&base->rr[reg_index]); + + debug("rr[%d] 0x%x\n", reg_index, *msg); + + return 0; +} + +static int imx8ulp_mu_read(struct mu_type *base, void *data) +{ + struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data; + int ret; + u8 count = 0; + + if (!msg) + return -EINVAL; + + /* Read first word */ + ret = mu_hal_receivemsg(base, 0, (u32 *)msg); + if (ret) + return ret; + count++; + + /* Check size */ + if (msg->size > S400_MAX_MSG) { + *((u32 *)msg) = 0; + return -EINVAL; + } + + /* Read remaining words */ + while (count < msg->size) { + ret = mu_hal_receivemsg(base, count % MU_RR_COUNT, + &msg->data[count - 1]); + if (ret) + return ret; + count++; + } + + return 0; +} + +static int imx8ulp_mu_write(struct mu_type *base, void *data) +{ + struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data; + int ret; + u8 count = 0; + + if (!msg) + return -EINVAL; + + /* Check size */ + if (msg->size > S400_MAX_MSG) + return -EINVAL; + + /* Write first word */ + ret = mu_hal_sendmsg(base, 0, *((u32 *)msg)); + if (ret) + return ret; + count++; + + /* Write remaining words */ + while (count < msg->size) { + ret = mu_hal_sendmsg(base, count % MU_TR_COUNT, + msg->data[count - 1]); + if (ret) + return ret; + count++; + } + + return 0; +} + +/* + * Note the function prototype use msgid as the 2nd parameter, here + * we take it as no_resp. + */ +static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg, + int tx_size, void *rx_msg, int rx_size) +{ + struct imx8ulp_mu *priv = dev_get_priv(dev); + u32 result; + int ret; + + /* Expect tx_msg, rx_msg are the same value */ + if (rx_msg && tx_msg != rx_msg) + printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg); + + ret = imx8ulp_mu_write(priv->base, tx_msg); + if (ret) + return ret; + if (!no_resp) { + ret = imx8ulp_mu_read(priv->base, rx_msg); + if (ret) + return ret; + } + + result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0]; + if ((result & 0xff) == 0) + return 0; + + return -EIO; +} + +static int imx8ulp_mu_probe(struct udevice *dev) +{ + struct imx8ulp_mu *priv = dev_get_priv(dev); + fdt_addr_t addr; + + debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (struct mu_type *)addr; + + debug("mu base 0x%lx\n", (ulong)priv->base); + + /* U-Boot not enable interrupts, so need to enable RX interrupts */ + mu_hal_init(priv->base); + + gd->arch.s400_dev = dev; + + return 0; +} + +static int imx8ulp_mu_remove(struct udevice *dev) +{ + return 0; +} + +static int imx8ulp_mu_bind(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static struct misc_ops imx8ulp_mu_ops = { + .call = imx8ulp_mu_call, +}; + +static const struct udevice_id imx8ulp_mu_ids[] = { + { .compatible = "fsl,imx8ulp-mu" }, + { } +}; + +U_BOOT_DRIVER(imx8ulp_mu) = { + .name = "imx8ulp_mu", + .id = UCLASS_MISC, + .of_match = imx8ulp_mu_ids, + .probe = imx8ulp_mu_probe, + .bind = imx8ulp_mu_bind, + .remove = imx8ulp_mu_remove, + .ops = &imx8ulp_mu_ops, + .priv_auto = sizeof(struct imx8ulp_mu), +}; -- cgit v1.2.3 From a6ffde5ea5f65e0b68cdf960d998a381e8a358fd Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 7 Aug 2021 16:00:51 +0800 Subject: drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6 According to latest S400 API doc, the the success indicate value is changed to 0xd6. So update the driver codes. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/misc/imx8ulp/imx8ulp_mu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/misc/imx8ulp/imx8ulp_mu.c') diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/imx8ulp/imx8ulp_mu.c index 3f6dd558e63..f3ca5473e3b 100644 --- a/drivers/misc/imx8ulp/imx8ulp_mu.c +++ b/drivers/misc/imx8ulp/imx8ulp_mu.c @@ -185,7 +185,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg, } result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0]; - if ((result & 0xff) == 0) + if ((result & 0xff) == 0xd6) return 0; return -EIO; -- cgit v1.2.3 From ba472a209b0086cb6e1e573a5e36f0d8ca912b50 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 7 Aug 2021 16:00:55 +0800 Subject: arm: imx8ulp: release and configure XRDC at early phase Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/misc/imx8ulp/imx8ulp_mu.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) (limited to 'drivers/misc/imx8ulp/imx8ulp_mu.c') diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/imx8ulp/imx8ulp_mu.c index f3ca5473e3b..913ebe7ad3f 100644 --- a/drivers/misc/imx8ulp/imx8ulp_mu.c +++ b/drivers/misc/imx8ulp/imx8ulp_mu.c @@ -42,24 +42,27 @@ struct imx8ulp_mu { #define MU_TR_COUNT 4 #define MU_RR_COUNT 4 -static inline void mu_hal_init(struct mu_type *base) +void mu_hal_init(ulong base) { - writel(0, &base->tcr); - writel(0, &base->rcr); + struct mu_type *mu_base = (struct mu_type *)base; + + writel(0, &mu_base->tcr); + writel(0, &mu_base->rcr); } -static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg) +int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg) { + struct mu_type *mu_base = (struct mu_type *)base; u32 mask = MU_SR_TE0_MASK << reg_index; u32 val; int ret; assert(reg_index < MU_TR_COUNT); - debug("sendmsg sr 0x%x\n", readl(&base->sr)); + debug("sendmsg sr 0x%x\n", readl(&mu_base->sr)); /* Wait TX register to be empty. */ - ret = readl_poll_timeout(&base->tsr, val, val & mask, 10000); + ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000); if (ret < 0) { debug("%s timeout\n", __func__); return -ETIMEDOUT; @@ -67,29 +70,30 @@ static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg) debug("tr[%d] 0x%x\n", reg_index, msg); - writel(msg, &base->tr[reg_index]); + writel(msg, &mu_base->tr[reg_index]); return 0; } -static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg) +int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) { + struct mu_type *mu_base = (struct mu_type *)base; u32 mask = MU_SR_RF0_MASK << reg_index; u32 val; int ret; assert(reg_index < MU_TR_COUNT); - debug("receivemsg sr 0x%x\n", readl(&base->sr)); + debug("receivemsg sr 0x%x\n", readl(&mu_base->sr)); /* Wait RX register to be full. */ - ret = readl_poll_timeout(&base->rsr, val, val & mask, 10000); + ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000); if (ret < 0) { debug("%s timeout\n", __func__); return -ETIMEDOUT; } - *msg = readl(&base->rr[reg_index]); + *msg = readl(&mu_base->rr[reg_index]); debug("rr[%d] 0x%x\n", reg_index, *msg); @@ -106,7 +110,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data) return -EINVAL; /* Read first word */ - ret = mu_hal_receivemsg(base, 0, (u32 *)msg); + ret = mu_hal_receivemsg((ulong)base, 0, (u32 *)msg); if (ret) return ret; count++; @@ -119,7 +123,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data) /* Read remaining words */ while (count < msg->size) { - ret = mu_hal_receivemsg(base, count % MU_RR_COUNT, + ret = mu_hal_receivemsg((ulong)base, count % MU_RR_COUNT, &msg->data[count - 1]); if (ret) return ret; @@ -143,14 +147,14 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data) return -EINVAL; /* Write first word */ - ret = mu_hal_sendmsg(base, 0, *((u32 *)msg)); + ret = mu_hal_sendmsg((ulong)base, 0, *((u32 *)msg)); if (ret) return ret; count++; /* Write remaining words */ while (count < msg->size) { - ret = mu_hal_sendmsg(base, count % MU_TR_COUNT, + ret = mu_hal_sendmsg((ulong)base, count % MU_TR_COUNT, msg->data[count - 1]); if (ret) return ret; @@ -207,7 +211,7 @@ static int imx8ulp_mu_probe(struct udevice *dev) debug("mu base 0x%lx\n", (ulong)priv->base); /* U-Boot not enable interrupts, so need to enable RX interrupts */ - mu_hal_init(priv->base); + mu_hal_init((ulong)priv->base); gd->arch.s400_dev = dev; -- cgit v1.2.3 From 4b9423e6f2f7904fe9465d0a3706740c07d9390a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 7 Aug 2021 16:01:09 +0800 Subject: imx8ulp: move struct mu_type to common header Move struct mu_type to common header to make it reusable by upower and S400 Signed-off-by: Peng Fan --- drivers/misc/imx8ulp/imx8ulp_mu.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) (limited to 'drivers/misc/imx8ulp/imx8ulp_mu.c') diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/imx8ulp/imx8ulp_mu.c index 913ebe7ad3f..333ebdf5765 100644 --- a/drivers/misc/imx8ulp/imx8ulp_mu.c +++ b/drivers/misc/imx8ulp/imx8ulp_mu.c @@ -10,29 +10,12 @@ #include #include #include +#include #include #include DECLARE_GLOBAL_DATA_PTR; -struct mu_type { - u32 ver; - u32 par; - u32 cr; - u32 sr; - u32 reserved0[68]; - u32 tcr; - u32 tsr; - u32 rcr; - u32 rsr; - u32 reserved1[52]; - u32 tr[16]; - u32 reserved2[16]; - u32 rr[16]; - u32 reserved4[14]; - u32 mu_attr; -}; - struct imx8ulp_mu { struct mu_type *base; }; -- cgit v1.2.3