From 87c7661b42aa7672539b54b51d3d5c4013ec6f6c Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Fri, 31 Jul 2009 12:08:27 +0530 Subject: 85xx: Added P1020 Processor Support. P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- drivers/misc/fsl_law.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/misc') diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index f7d454dce45..af7b7299349 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ - defined(CONFIG_P2020) + defined(CONFIG_P2020) || defined(CONFIG_P1020) #define FSL_HW_NUM_LAWS 12 #else #error FSL_HW_NUM_LAWS not defined for this platform -- cgit v1.2.3