From 60262cd041529cabd5fbabb6f2077495fa922fca Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 12 Dec 2018 06:12:27 -0800 Subject: timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- drivers/timer/riscv_timer.c | 56 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 drivers/timer/riscv_timer.c (limited to 'drivers/timer/riscv_timer.c') diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c new file mode 100644 index 00000000000..9f9f070e0b3 --- /dev/null +++ b/drivers/timer/riscv_timer.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * RISC-V privileged architecture defined generic timer driver + * + * This driver relies on RISC-V platform codes to provide the essential API + * riscv_get_time() which is supposed to return the timer counter as defined + * by the RISC-V privileged architecture spec. + * + * This driver can be used in both M-mode and S-mode U-Boot. + */ + +#include +#include +#include +#include +#include + +/** + * riscv_get_time() - get the timer counter + * + * Platform codes should provide this API in order to make this driver function. + * + * @time: the 64-bit timer count as defined by the RISC-V privileged + * architecture spec. + * @return: 0 on success, -ve on error. + */ +extern int riscv_get_time(u64 *time); + +static int riscv_timer_get_count(struct udevice *dev, u64 *count) +{ + return riscv_get_time(count); +} + +static int riscv_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + /* clock frequency was passed from the cpu driver as driver data */ + uc_priv->clock_rate = dev->driver_data; + + return 0; +} + +static const struct timer_ops riscv_timer_ops = { + .get_count = riscv_timer_get_count, +}; + +U_BOOT_DRIVER(riscv_timer) = { + .name = "riscv_timer", + .id = UCLASS_TIMER, + .probe = riscv_timer_probe, + .ops = &riscv_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.3