From 47d7e3b5eb72fd540930c830d568ece19b3defa0 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sun, 25 Oct 2020 21:46:58 -0400 Subject: riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Reviewed-by: Rick Chen --- drivers/timer/sifive_clint_timer.c | 47 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 drivers/timer/sifive_clint_timer.c (limited to 'drivers/timer/sifive_clint_timer.c') diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c new file mode 100644 index 00000000000..00ce0f08d6e --- /dev/null +++ b/drivers/timer/sifive_clint_timer.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Sean Anderson + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include + +/* mtime register */ +#define MTIME_REG(base) ((ulong)(base) + 0xbff8) + +static u64 sifive_clint_get_count(struct udevice *dev) +{ + return readq((void __iomem *)MTIME_REG(dev->priv)); +} + +static const struct timer_ops sifive_clint_ops = { + .get_count = sifive_clint_get_count, +}; + +static int sifive_clint_probe(struct udevice *dev) +{ + dev->priv = dev_read_addr_ptr(dev); + if (!dev->priv) + return -EINVAL; + + return timer_timebase_fallback(dev); +} + +static const struct udevice_id sifive_clint_ids[] = { + { .compatible = "riscv,clint0" }, + { } +}; + +U_BOOT_DRIVER(sifive_clint) = { + .name = "sifive_clint", + .id = UCLASS_TIMER, + .of_match = sifive_clint_ids, + .probe = sifive_clint_probe, + .ops = &sifive_clint_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.3