From 74fbd74ed2069985c9d7dd15ffe94f8a95f1022a Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 6 Sep 2023 14:18:13 +0900 Subject: riscv: timer: add timer_get_boot_us for BOOTSTAGE timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- drivers/timer/riscv_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'drivers/timer') diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 28a6a6870b8..169c03dcb5c 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -51,6 +52,27 @@ u64 notrace timer_early_get_count(void) } #endif +#if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE) +ulong timer_get_boot_us(void) +{ + int ret; + u64 ticks = 0; + u32 rate; + + ret = dm_timer_init(); + if (!ret) { + rate = timer_get_rate(gd->timer); + timer_get_count(gd->timer, &ticks); + } else { + rate = RISCV_SMODE_TIMER_FREQ; + ticks = riscv_timer_get_count(NULL); + } + + /* Below is converted from time(us) = (tick / rate) * 10000000 */ + return lldiv(ticks * 1000, (rate / 1000)); +} +#endif + static int riscv_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); -- cgit v1.2.3 From 6d78473b3d390c650aa7f418bdd5044ea42ee951 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 6 Sep 2023 14:18:14 +0900 Subject: timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- drivers/timer/riscv_aclint_timer.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'drivers/timer') diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c index e29d527c8d7..73fb8791285 100644 --- a/drivers/timer/riscv_aclint_timer.c +++ b/drivers/timer/riscv_aclint_timer.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -44,6 +45,28 @@ u64 notrace timer_early_get_count(void) } #endif +#if CONFIG_IS_ENABLED(RISCV_MMODE) && CONFIG_IS_ENABLED(BOOTSTAGE) +ulong timer_get_boot_us(void) +{ + int ret; + u64 ticks = 0; + u32 rate; + + ret = dm_timer_init(); + if (!ret) { + rate = timer_get_rate(gd->timer); + timer_get_count(gd->timer, &ticks); + } else { + rate = RISCV_MMODE_TIMER_FREQ; + ticks = readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, + RISCV_MMODE_TIMEROFF)); + } + + /* Below is converted from time(us) = (tick / rate) * 10000000 */ + return lldiv(ticks * 1000, (rate / 1000)); +} +#endif + static const struct timer_ops riscv_aclint_timer_ops = { .get_count = riscv_aclint_timer_get_count, }; -- cgit v1.2.3 From c202426d6ac6bffccf19e958dc176f7d29d0528e Mon Sep 17 00:00:00 2001 From: Kuan Lim Lee Date: Tue, 19 Sep 2023 15:30:36 +0800 Subject: timer: starfive: Add Starfive timer support Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee Reviewed-by: Wei Liang Lim Reviewed-by: Simon Glass --- drivers/timer/Kconfig | 7 ++++ drivers/timer/Makefile | 1 + drivers/timer/starfive-timer.c | 94 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+) create mode 100644 drivers/timer/starfive-timer.c (limited to 'drivers/timer') diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 915b2af160c..a98be9dfae4 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -326,4 +326,11 @@ config XILINX_TIMER Select this to enable support for the timer found on any Xilinx boards (axi timer). +config STARFIVE_TIMER + bool "Starfive timer support" + depends on TIMER + help + Select this to enable support for the timer found on + Starfive SoC. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 1ca74805fd9..1ef814970b9 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o +obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c new file mode 100644 index 00000000000..816402fdbf2 --- /dev/null +++ b/drivers/timer/starfive-timer.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 StarFive, Inc. All rights reserved. + * Author: Lee Kuan Lim + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define STF_TIMER_INT_STATUS 0x00 +#define STF_TIMER_CTL 0x04 +#define STF_TIMER_LOAD 0x08 +#define STF_TIMER_ENABLE 0x10 +#define STF_TIMER_RELOAD 0x14 +#define STF_TIMER_VALUE 0x18 +#define STF_TIMER_INT_CLR 0x20 +#define STF_TIMER_INT_MASK 0x24 + +struct starfive_timer_priv { + void __iomem *base; + u32 timer_size; +}; + +static u64 notrace starfive_get_count(struct udevice *dev) +{ + struct starfive_timer_priv *priv = dev_get_priv(dev); + + /* Read decrement timer value and convert to increment value */ + return priv->timer_size - readl(priv->base + STF_TIMER_VALUE); +} + +static const struct timer_ops starfive_ops = { + .get_count = starfive_get_count, +}; + +static int starfive_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct starfive_timer_priv *priv = dev_get_priv(dev); + int timer_channel; + struct clk clk; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + timer_channel = dev_read_u32_default(dev, "channel", 0); + priv->base = priv->base + (0x40 * timer_channel); + + /* Get clock rate from channel selectecd*/ + ret = clk_get_by_index(dev, timer_channel, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + uc_priv->clock_rate = clk_get_rate(&clk); + + /* Initiate timer, channel 0 */ + /* Unmask Interrupt Mask */ + writel(0, priv->base + STF_TIMER_INT_MASK); + /* Single run mode Setting */ + if (dev_read_bool(dev, "single-run")) + writel(1, priv->base + STF_TIMER_CTL); + /* Set Reload value */ + priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff); + writel(priv->timer_size, priv->base + STF_TIMER_LOAD); + /* Enable to start timer */ + writel(1, priv->base + STF_TIMER_ENABLE); + + return 0; +} + +static const struct udevice_id starfive_ids[] = { + { .compatible = "starfive,jh8100-timers" }, + { } +}; + +U_BOOT_DRIVER(jh8100_starfive_timer) = { + .name = "jh8100_starfive_timer", + .id = UCLASS_TIMER, + .of_match = starfive_ids, + .probe = starfive_probe, + .ops = &starfive_ops, + .priv_auto = sizeof(struct starfive_timer_priv), +}; -- cgit v1.2.3 From 8a0d5f2f51b72b3cabacfe90ff196db3e1c4dc4d Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Fri, 29 Sep 2023 12:03:07 +0800 Subject: riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Samuel Holland --- drivers/timer/Kconfig | 9 ++++++++- drivers/timer/Makefile | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'drivers/timer') diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index a98be9dfae4..60519c3b536 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -59,7 +59,14 @@ config ALTERA_TIMER config ANDES_PLMT_TIMER bool - depends on RISCV_MMODE || SPL_RISCV_MMODE + depends on RISCV_MMODE + help + The Andes PLMT block holds memory-mapped mtime register + associated with timer tick. + +config SPL_ANDES_PLMT_TIMER + bool + depends on SPL_RISCV_MMODE help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 1ef814970b9..b93145e8d43 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -4,7 +4,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o -obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o +obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o -- cgit v1.2.3