From 4c809aee50f5128f815a7f272cdf2d30a1e1e76e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 May 2020 21:58:47 +0800 Subject: uclass: cpu: Add new API to get udevice for current CPU When running on SoC with multiple clusters, the boot CPU may not be fixed, saying booting from cluster A or cluster B. Add a API that can return the udevice for current boot CPU. Cpu driver needs to implement is_current_cpu interface for this feature, otherwise the API only returns the first udevice in cpu uclass. Reviewed-by: Simon Glass Signed-off-by: Peng Fan Signed-off-by: Ye Li --- include/cpu.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'include') diff --git a/include/cpu.h b/include/cpu.h index 6b1b6b37b3b..2f283fe2449 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -89,6 +89,15 @@ struct cpu_ops { * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error */ int (*get_vendor)(struct udevice *dev, char *buf, int size); + + /** + * is_current() - Check if the CPU that U-Boot is currently running from + * + * @dev: Device to check (UCLASS_CPU) + * @return 1 if the CPU that U-Boot is currently running from, 0 + * if not. + */ + int (*is_current)(struct udevice *dev); }; #define cpu_get_ops(dev) ((struct cpu_ops *)(dev)->driver->ops) @@ -137,4 +146,18 @@ int cpu_get_vendor(struct udevice *dev, char *buf, int size); */ int cpu_probe_all(void); +/** + * cpu_is_current() - Check if the CPU that U-Boot is currently running from + * + * Return: 1 if yes, - 0 if not + */ +int cpu_is_current(struct udevice *cpu); + +/** + * cpu_get_current_dev() - Get CPU udevice for current CPU + * + * Return: udevice if OK, - NULL on error + */ +struct udevice *cpu_get_current_dev(void); + #endif -- cgit v1.2.3 From b52fb0b0b5da80a059ba982139401e57ac4e9a2e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 20:09:08 +0200 Subject: ARM: imx: pico-imx8mq: Add support for Technexion Pico-iMX8MQ Add initial support for Technexion Pico-iMX8MQ SoM on PicoPI carrier board. Currently working is ethernet, serial, eMMC. DT is imported from Linux 5.4.28 ("462afcd6e7ea") . Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Fabio Estevam Cc: "NXP i.MX U-Boot Team" Cc: Peng Fan Reviewed-by: Stefano Babic --- include/configs/pico-imx8mq.h | 199 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 include/configs/pico-imx8mq.h (limited to 'include') diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h new file mode 100644 index 00000000000..a2f80cdd671 --- /dev/null +++ b/include/configs/pico-imx8mq.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8M_PICOPI_H +#define __IMX8M_PICOPI_H + +#include +#include + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 1 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "fdt_file=imx8mq-pico-pi.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "booti; " + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MXC_GPIO + +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_OF_SYSTEM_SETUP + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_PMIC +#endif + +#define CONFIG_SYS_BOOTM_LEN SZ_128M + +#endif -- cgit v1.2.3 From 5fe419ef2a6154e83aab04c65ec906fef96eb5be Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 3 May 2020 22:41:14 +0800 Subject: net: Add eth phy generic driver for shared MDIO For dual ethernet controllers, the HW design may connect ETH phys to one MDIO ports. So two different ethernet drivers have to share MDIO bus. Since two ethernet drivers are independent, we can't ensure their probe order. To resolve this problem, introduce an eth phy generic driver and uclass. After eth-uclass binds, we search the mdio node and binds the phy node with the eth-phy-generic driver. When one eth driver get its phy device, the parent of phy device will probe prior than phy device. So this ensure the eth driver ownes the MDIO bus will be probed before using its MDIO. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- include/dm/uclass-id.h | 1 + include/eth_phy.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 include/eth_phy.h (limited to 'include') diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 37ada51f9f7..7837d459f18 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -47,6 +47,7 @@ enum uclass_id { UCLASS_DMA, /* Direct Memory Access */ UCLASS_EFI, /* EFI managed devices */ UCLASS_ETH, /* Ethernet device */ + UCLASS_ETH_PHY, /* Ethernet PHY device */ UCLASS_FIRMWARE, /* Firmware */ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ diff --git a/include/eth_phy.h b/include/eth_phy.h new file mode 100644 index 00000000000..19c496551b4 --- /dev/null +++ b/include/eth_phy.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef _eth_phy_h_ +#define _eth_phy_h_ + +#include +#include + +int eth_phy_binds_nodes(struct udevice *eth_dev); +int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus); +struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev); +int eth_phy_get_addr(struct udevice *dev); + +#endif -- cgit v1.2.3 From 616f03dabacb6c500e8a7ceb920cd08554c9fcae Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 4 May 2020 22:08:50 +0800 Subject: mtd: gpmi: change the BCH layout setting for large oob NAND MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code change updated the NAND driver BCH ECC layout algorithm to support large oob size NAND chips(oob > 1024 bytes) and proposed a new way to set ECC layout. Current implementation requires each chunk size larger than oob size so the bad block marker (BBM) can be guaranteed located in data chunk. The ECC layout always using the unbalanced layout(Ecc for both meta and Data0 chunk), but for the NAND chips with oob larger than 1k, the driver cannot support because BCH doesn’t support GF 15 for 2K chunk. The change keeps the data chunk no larger than 1k and adjust the ECC strength or ECC layout to locate the BBM in data chunk. General idea for large oob NAND chips is 1.Try all ECC strength from the minimum value required by NAND spec to the maximum one that works, any ECC makes the BBM locate in data chunk can be chosen. 2.If none of them works, using separate ECC for meta, which will add one extra ecc with the same ECC strength as other data chunks. This extra ECC can guarantee BBM located in data chunk, of course, we need to check if oob can afford it. Previous code has two methods for ECC layout setting, the legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference between these two methods is, legacy_calc_ecc_layout set the chunk size larger chan oob size and then set the maximum ECC strength that oob can afford. While the calc_ecc_layout_by_info set chunk size and ECC strength according to NAND spec. It has been proved that the first method cannot provide safe ECC strength for some modern NAND chips, so in current code, 1. Driver read NAND parameters first and then chose the proper ECC layout setting method. 2. If the oob is large or NAND required data chunk larger than oob size, chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info 3. legacy_calc_ecc_layout only used for some NAND chips does not contains necessary information. So this is only a backup plan, it is NOT recommended to use these NAND chips. Signed-off-by: Han Xu Signed-off-by: Ye Li Signed-off-by: Peng Fan --- include/mxs_nand.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/mxs_nand.h b/include/mxs_nand.h index ada20483d06..497da77a16d 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -16,22 +16,26 @@ * @gf_len: The length of Galois Field. (e.g., 13 or 14) * @ecc_strength: A number that describes the strength of the ECC * algorithm. - * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note - * the first chunk in the page includes both data and - * metadata, so it's a bit larger than this value. + * @ecc_chunk0_size: The size, in bytes, of a first ECC chunk. + * @ecc_chunkn_size: The size, in bytes, of a single ECC chunk after + * the first chunk in the page. * @ecc_chunk_count: The number of ECC chunks in the page, * @block_mark_byte_offset: The byte offset in the ECC-based page view at * which the underlying physical block mark appears. * @block_mark_bit_offset: The bit offset into the ECC-based page view at * which the underlying physical block mark appears. + * @ecc_for_meta: The flag to indicate if there is a dedicate ecc + * for meta. */ struct bch_geometry { unsigned int gf_len; unsigned int ecc_strength; - unsigned int ecc_chunk_size; + unsigned int ecc_chunk0_size; + unsigned int ecc_chunkn_size; unsigned int ecc_chunk_count; unsigned int block_mark_byte_offset; unsigned int block_mark_bit_offset; + unsigned int ecc_for_meta; /* ECC for meta data */ }; struct mxs_nand_info { -- cgit v1.2.3 From 51cdf83eea45861f9932019db2a1b3a0a6a3af52 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 4 May 2020 22:08:51 +0800 Subject: mtd: gpmi: provide the option to use legacy bch geometry Provide an option in DT to use legacy bch geometry, which compatible with the 3.10 kernel bch setting. To enable the feature, adding "fsl,legacy-bch-geometry" under gpmi-nand node. NOTICE: The feature must be enabled/disabled in both u-boot and kernel. Signed-off-by: Han Xu Signed-off-by: Ye Li Signed-off-by: Peng Fan --- include/mxs_nand.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/mxs_nand.h b/include/mxs_nand.h index 497da77a16d..1ac628d0647 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -43,6 +43,8 @@ struct mxs_nand_info { struct udevice *dev; unsigned int max_ecc_strength_supported; bool use_minimum_ecc; + /* legacy bch geometry flag */ + bool legacy_bch_geometry; int cur_chip; uint32_t cmd_queue_len; -- cgit v1.2.3 From 17282f45abba6f10842adafdd47c0f24cae6b0ef Mon Sep 17 00:00:00 2001 From: Han Xu Date: Mon, 4 May 2020 22:08:58 +0800 Subject: mtd: mxs_nand: fix the gf_13/14 definition issue gf_13/14 mask was not set correctly in register definition. Signed-off-by: Han Xu Signed-off-by: Peng Fan --- include/mxs_nand.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/mxs_nand.h b/include/mxs_nand.h index 1ac628d0647..21d68a909d7 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -88,6 +88,7 @@ struct mxs_nand_layout { u32 ecc0; u32 datan_size; u32 eccn; + u32 gf_len; }; int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info); -- cgit v1.2.3 From f36f8bc627379ef6b732dc2be4f10e972089a744 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 3 May 2020 08:11:33 -0500 Subject: imx: Add support for i.MX8MM Beacon EmbeddedWorks devkit. Beacon EmbeddedWorks, formerly known as Logic PD, is releasing a devkit based on the i.MX8M Mini SoC consisting of baseboard + SOM. It supports eMMC on the SOM, microSD on the baseboard, various GPIO, the PINCTRL, and UART. Signed-off-by: Adam Ford --- include/configs/imx8mm_beacon.h | 152 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 152 insertions(+) create mode 100644 include/configs/imx8mm_beacon.h (limited to 'include') diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h new file mode 100644 index 00000000000..21102d3c14d --- /dev/null +++ b/include/configs/imx8mm_beacon.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +#ifndef __IMX8MM_BEACON_H +#define __IMX8MM_BEACON_H + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE SZ_8K +#endif + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate}" \ + " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ + " ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* FEC*/ +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC +#define IMX_FEC_BASE 0x30BE0000 + +#endif -- cgit v1.2.3 From e6405713d88eeed90c9428552dfc87bfb4b05ca0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 4 May 2020 21:16:49 +0800 Subject: dt-bindings: imx_rsrc: add SC_R_NONE Add SC_R_NONE entry Signed-off-by: Peng Fan --- include/dt-bindings/soc/imx_rsrc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h index 4870eb985b4..fb6878f6e24 100644 --- a/include/dt-bindings/soc/imx_rsrc.h +++ b/include/dt-bindings/soc/imx_rsrc.h @@ -553,5 +553,6 @@ #define SC_R_VPU_ENC_1 539 #define SC_R_VPU 540 #define SC_R_LAST 541 +#define SC_R_NONE 0xFFF0 #endif /* DT_BINDINGS_RSCRC_IMX_H */ -- cgit v1.2.3 From bf9382addf94c9b90033a1eac5522afae9b7a0d7 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Wed, 6 May 2020 20:59:19 +0800 Subject: mtd: nand: raw: mxs_nand changes for nandbcb Add more BCH setting mode and remove the unnecessary platform constrain Signed-off-by: Han Xu Signed-off-by: Peng Fan --- include/mxs_nand.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/mxs_nand.h b/include/mxs_nand.h index 21d68a909d7..c0cefaca90b 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -95,7 +95,8 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info); int mxs_nand_init_spl(struct nand_chip *nand); int mxs_nand_setup_ecc(struct mtd_info *mtd); -void mxs_nand_mode_fcb(struct mtd_info *mtd); +void mxs_nand_mode_fcb_62bit(struct mtd_info *mtd); +void mxs_nand_mode_fcb_40bit(struct mtd_info *mtd); void mxs_nand_mode_normal(struct mtd_info *mtd); u32 mxs_nand_mark_byte_offset(struct mtd_info *mtd); u32 mxs_nand_mark_bit_offset(struct mtd_info *mtd); -- cgit v1.2.3 From 6aead23323bee1d780fd0b9696f512194458e379 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 5 May 2020 20:28:41 +0800 Subject: imx: imx8qm/qxp: Recover SPL data section for partition reboot When doing partition reboot, the boot image won't be reloaded by ROM, it is just CPU reset to boot entry. The SW has to keep the boot image inside the RAM unchanged. It includes both the TEXT section and DATA section. For SPL, the problem is DATA section will be updated at runtime, so in next partition reboot the data is not same as the initial value from cold boot. If any code depends on the initial value, then it will have problem. This patch introduces a mechanism to recover the data section for partition reboot. It adds a new section in image for saving data section. When from cold boot, the data section will be saved to that new section at SPL early phase. When from partition reboot, the data section will be restored from the new section. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- include/spl.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/spl.h b/include/spl.h index 6bf9fd8bebb..90395fedb0f 100644 --- a/include/spl.h +++ b/include/spl.h @@ -582,4 +582,5 @@ void spl_perform_fixups(struct spl_image_info *spl_image); */ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size); +void spl_save_restore_data(void); #endif -- cgit v1.2.3 From e825d3089abbca850d8370bcbeaa8dc6e5d4a69a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 5 May 2020 20:28:44 +0800 Subject: imx: imx8qm: update fdt_file according to m4 state Update fdt_file according to m4 parts state Signed-off-by: Peng Fan --- include/configs/imx8qm_mek.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 97170dc9494..22d80f1747b 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -70,7 +70,7 @@ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ - "fdt_file=imx8qm-mek.dtb\0" \ + "fdt_file=undefined\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ -- cgit v1.2.3 From a6c36f15ebc5e004c5914bb55ef93bb453e640db Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 5 May 2020 20:28:45 +0800 Subject: imx: imx8qxp: update fdt_file according to m4 state Update fdt_file according to m4 parts state Signed-off-by: Peng Fan --- include/configs/imx8qxp_mek.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 0aaca3325bd..341e93e61e7 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -69,7 +69,7 @@ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ - "fdt_file=imx8qxp-mek.dtb\0" \ + "fdt_file=undefined\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ -- cgit v1.2.3