// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2025 NXP
 */

/ {
	binman {
		multiple-images;

		m33-oei-ddrfw {
			pad-byte = <0x00>;
			align-size = <0x8>;
			filename = "m33-oei-ddrfw.bin";

			oei-m33-ddr {
				align-size = <0x4>;
				filename = "oei-m33-ddr.bin";
				type = "blob-ext";
			};

			imx-lpddr {
				type = "nxp-header-ddrfw";

				imx-lpddr-imem {
					filename = "lpddr5_imem_v202311.bin";
					type = "blob-ext";
				};

				imx-lpddr-dmem {
					filename = "lpddr5_dmem_v202311.bin";
					type = "blob-ext";
				};
			};

			imx-lpddr-qb {
				type = "nxp-header-ddrfw";

				imx-lpddr-imem-qb {
					filename = "lpddr5_imem_qb_v202311.bin";
					type = "blob-ext";
				};

				imx-lpddr-dmem-qb {
					filename = "lpddr5_dmem_qb_v202311.bin";
					type = "blob-ext";
				};
			};
		};

		imx-boot {
			filename = "flash.bin";
			pad-byte = <0x00>;

			spl {
				align = <0x400>;
				align-size = <0x400>;
				type = "mkimage";
				args = "-n spl/u-boot-spl.cfgout -T imx8image";
			};

			u-boot {
				type = "mkimage";
				args = "-n u-boot-container.cfgout -T imx8image";
			};
		};
	};
};

&A55_0 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_1 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_2 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_3 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_4 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_5 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&aips1 {
	bootph-all;
};

&aips2 {
	bootph-all;
};

&aips3 {
	bootph-pre-ram;
};

&clk_ext1 {
	bootph-all;
};

&elemu1 {
	bootph-all;
	status = "okay";
};

&elemu3 {
	bootph-all;
	status = "okay";
};

&{/firmware} {
	bootph-all;
};

&{/firmware/scmi} {
	bootph-all;
};

&{/firmware/scmi/protocol@11} {
	bootph-all;
};

&{/firmware/scmi/protocol@13} {
	bootph-all;
};

&{/firmware/scmi/protocol@14} {
	bootph-all;
};

&{/firmware/scmi/protocol@19} {
	bootph-all;
};

&gpio2 {
	bootph-pre-ram;
};

&gpio3 {
	bootph-pre-ram;
};

&gpio4 {
	bootph-pre-ram;
};

&gpio5 {
	bootph-pre-ram;
};

&mu2 {
	bootph-all;
};

&osc_24m {
	bootph-all;
};

&{/soc} {
	bootph-all;
};

&sram0 {
	bootph-all;
};

&scmi_buf0 {
	reg = <0x0 0x400>;
	bootph-all;
};

&scmi_buf1 {
	bootph-all;
};