// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
 */

#include "rockchip-u-boot.dtsi"

/ {
	aliases {
		spi5 = &sfc;
	};

	chosen {
		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
	};

	dmc {
		compatible = "rockchip,rk3588-dmc";
		bootph-all;
	};
};

#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
&binman {
	simple-bin-spi {
		mkimage {
			args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
			offset = <0x8000>;
		};
	};
};
#endif

&cru {
	bootph-all;
};

&emmc_bus8 {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_clk {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_cmd {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_data_strobe {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_rstnout {
	bootph-pre-ram;
	bootph-some-ram;
};

&ioc {
	bootph-all;
};

&otp {
	bootph-some-ram;
};

&pcfg_pull_down {
	bootph-all;
};

&pcfg_pull_none {
	bootph-all;
};

&pcfg_pull_up {
	bootph-all;
};

&pcfg_pull_up_drv_level_2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&php_grf {
	bootph-all;
};

&pinctrl {
	bootph-all;
};

&pmu1grf {
	bootph-all;
};

&scmi {
	bootph-pre-ram;
	bootph-some-ram;
};

&scmi_clk {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdhci {
	bootph-pre-ram;
	bootph-some-ram;
	u-boot,spl-fifo-mode;
};

&sdmmc {
	bootph-pre-ram;
	bootph-some-ram;
	u-boot,spl-fifo-mode;
};

&sdmmc_bus4 {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_clk {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_cmd {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_det {
	bootph-pre-ram;
	bootph-some-ram;
};

&sfc {
	u-boot,spl-sfc-no-dma;
};

&sys_grf {
	bootph-all;
};

&uart2 {
	bootph-all;
	clock-frequency = <24000000>;
};

&uart2m0_xfer {
	bootph-all;
};

&xin24m {
	bootph-all;
};