# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence NAND controller

maintainers:
  - Dinesh Maniyam <dinesh.maniyam@intel.com>

properties:
  compatible:
    enum:
      - cdns,nand

  reg-names:
    description: |
      There are two register regions:
        reg:  register interface
        sdma: host data/command interface
    items:
      - const: reg
      - const: sdma

  reg:
    minItems: 2
    maxItems: 2

  interrupts:
    maxItems: 1

  clocks:
    description: |
      There is one controller core clock
    maxItems: 1

  resets:
    description: |
      There are two resets:
        controller core reset
        combo-phy register reset
    minItems: 1
    maxItems: 2

  cdns,board-delay-ps:
     description: |
        Estimated Board delay. The value includes the total
        round trip delay for the signals and is used for deciding on values
        associated with data read capture. The example formula for SDR mode is
        the following:
        board delay = RE#PAD delay + PCB trace to device + PCB trace from device
        + DQ PAD delay
     enum:
       - 4830

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
    properties:
      compatible:
        const: cdns,nand

      reg:
        maxItems: 1

      label:
        maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - cdns,board-delay-ps

unevaluatedProperties: false

examples:
  - |
    nand-controller@60000000 {
        compatible = "cdns,nand";
        reg = <0x60000000 0x10000>, <0x80000000 0x1000>;
        reg-names = "reg", "sdma";
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&clk>;
        cdns,board-delay-ps = <4830>;
        interrupts = <2 0>;
        nand@0 {
            label = "nand-0";
            reg = <0>;
        };
        nand@1 {
            label = "nand-1";
            reg = <1>;
        };
    };