/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __UFS_H #define __UFS_H #include #include #include "ufshci.h" #include "unipro.h" struct udevice; #define UFS_CDB_SIZE 16 #define UPIU_TRANSACTION_UIC_CMD 0x1F #define UIC_CMD_SIZE (sizeof(u32) * 4) #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 #define UFS_MAX_LUNS 0x7F /* UFS device power modes */ enum ufs_dev_pwr_mode { UFS_ACTIVE_PWR_MODE = 1, UFS_SLEEP_PWR_MODE = 2, UFS_POWERDOWN_PWR_MODE = 3, }; enum ufs_notify_change_status { PRE_CHANGE, POST_CHANGE, }; struct ufs_pa_layer_attr { u32 gear_rx; u32 gear_tx; u32 lane_rx; u32 lane_tx; u32 pwr_rx; u32 pwr_tx; u32 hs_rate; }; struct ufs_pwr_mode_info { bool is_valid; struct ufs_pa_layer_attr info; }; enum ufs_desc_def_size { QUERY_DESC_DEVICE_DEF_SIZE = 0x40, QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90, QUERY_DESC_UNIT_DEF_SIZE = 0x23, QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06, QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48, QUERY_DESC_POWER_DEF_SIZE = 0x62, QUERY_DESC_HEALTH_DEF_SIZE = 0x25, }; struct ufs_desc_size { int dev_desc; int pwr_desc; int geom_desc; int interc_desc; int unit_desc; int conf_desc; int hlth_desc; }; /* * Request Descriptor Definitions */ /* Transfer request command type */ enum { UTP_CMD_TYPE_SCSI = 0x0, UTP_CMD_TYPE_UFS = 0x1, UTP_CMD_TYPE_DEV_MANAGE = 0x2, }; /* UTP Transfer Request Command Offset */ #define UPIU_COMMAND_TYPE_OFFSET 28 /* Offset of the response code in the UPIU header */ #define UPIU_RSP_CODE_OFFSET 8 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req)) #define QUERY_DESC_MAX_SIZE 255 #define QUERY_DESC_MIN_SIZE 2 #define QUERY_DESC_HDR_SIZE 2 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \ (sizeof(struct utp_upiu_header))) #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\ cpu_to_be32(((byte3) << 24) | ((byte2) << 16) |\ ((byte1) << 8) | (byte0)) /* * UFS Protocol Information Unit related definitions */ /* Task management functions */ enum { UFS_ABORT_TASK = 0x01, UFS_ABORT_TASK_SET = 0x02, UFS_CLEAR_TASK_SET = 0x04, UFS_LOGICAL_RESET = 0x08, UFS_QUERY_TASK = 0x80, UFS_QUERY_TASK_SET = 0x81, }; /* UTP UPIU Transaction Codes Initiator to Target */ enum { UPIU_TRANSACTION_NOP_OUT = 0x00, UPIU_TRANSACTION_COMMAND = 0x01, UPIU_TRANSACTION_DATA_OUT = 0x02, UPIU_TRANSACTION_TASK_REQ = 0x04, UPIU_TRANSACTION_QUERY_REQ = 0x16, }; /* UTP UPIU Transaction Codes Target to Initiator */ enum { UPIU_TRANSACTION_NOP_IN = 0x20, UPIU_TRANSACTION_RESPONSE = 0x21, UPIU_TRANSACTION_DATA_IN = 0x22, UPIU_TRANSACTION_TASK_RSP = 0x24, UPIU_TRANSACTION_READY_XFER = 0x31, UPIU_TRANSACTION_QUERY_RSP = 0x36, UPIU_TRANSACTION_REJECT_UPIU = 0x3F, }; /* UPIU Read/Write flags */ enum { UPIU_CMD_FLAGS_NONE = 0x00, UPIU_CMD_FLAGS_WRITE = 0x20, UPIU_CMD_FLAGS_READ = 0x40, }; /* UPIU Task Attributes */ enum { UPIU_TASK_ATTR_SIMPLE = 0x00, UPIU_TASK_ATTR_ORDERED = 0x01, UPIU_TASK_ATTR_HEADQ = 0x02, UPIU_TASK_ATTR_ACA = 0x03, }; /* UPIU Query request function */ enum { UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01, UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81, }; /* Offset of the response code in the UPIU header */ #define UPIU_RSP_CODE_OFFSET 8 enum { MASK_SCSI_STATUS = 0xFF, MASK_TASK_RESPONSE = 0xFF00, MASK_RSP_UPIU_RESULT = 0xFFFF, MASK_QUERY_DATA_SEG_LEN = 0xFFFF, MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF, MASK_RSP_EXCEPTION_EVENT = 0x10000, MASK_TM_SERVICE_RESP = 0xFF, MASK_TM_FUNC = 0xFF, }; /* UTP QUERY Transaction Specific Fields OpCode */ enum query_opcode { UPIU_QUERY_OPCODE_NOP = 0x0, UPIU_QUERY_OPCODE_READ_DESC = 0x1, UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, UPIU_QUERY_OPCODE_READ_ATTR = 0x3, UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, UPIU_QUERY_OPCODE_READ_FLAG = 0x5, UPIU_QUERY_OPCODE_SET_FLAG = 0x6, UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, }; /* Query response result code */ enum { QUERY_RESULT_SUCCESS = 0x00, QUERY_RESULT_NOT_READABLE = 0xF6, QUERY_RESULT_NOT_WRITEABLE = 0xF7, QUERY_RESULT_ALREADY_WRITTEN = 0xF8, QUERY_RESULT_INVALID_LENGTH = 0xF9, QUERY_RESULT_INVALID_VALUE = 0xFA, QUERY_RESULT_INVALID_SELECTOR = 0xFB, QUERY_RESULT_INVALID_INDEX = 0xFC, QUERY_RESULT_INVALID_IDN = 0xFD, QUERY_RESULT_INVALID_OPCODE = 0xFE, QUERY_RESULT_GENERAL_FAILURE = 0xFF, }; enum { UPIU_COMMAND_SET_TYPE_SCSI = 0x0, UPIU_COMMAND_SET_TYPE_UFS = 0x1, UPIU_COMMAND_SET_TYPE_QUERY = 0x2, }; /* Flag idn for Query Requests*/ enum flag_idn { QUERY_FLAG_IDN_FDEVICEINIT = 0x01, QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, QUERY_FLAG_IDN_BKOPS_EN = 0x04, QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05, QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, QUERY_FLAG_IDN_RESERVED2 = 0x07, QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, QUERY_FLAG_IDN_BUSY_RTC = 0x09, QUERY_FLAG_IDN_RESERVED3 = 0x0A, QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B, }; /* Attribute idn for Query requests */ enum attr_idn { QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, QUERY_ATTR_IDN_RESERVED = 0x01, QUERY_ATTR_IDN_POWER_MODE = 0x02, QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, QUERY_ATTR_IDN_PURGE_STATUS = 0x06, QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, QUERY_ATTR_IDN_EE_CONTROL = 0x0D, QUERY_ATTR_IDN_EE_STATUS = 0x0E, QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, QUERY_ATTR_IDN_CNTX_CONF = 0x10, QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, QUERY_ATTR_IDN_RESERVED2 = 0x12, QUERY_ATTR_IDN_RESERVED3 = 0x13, QUERY_ATTR_IDN_FFU_STATUS = 0x14, QUERY_ATTR_IDN_PSA_STATE = 0x15, QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16, }; /* Descriptor idn for Query requests */ enum desc_idn { QUERY_DESC_IDN_DEVICE = 0x0, QUERY_DESC_IDN_CONFIGURATION = 0x1, QUERY_DESC_IDN_UNIT = 0x2, QUERY_DESC_IDN_RFU_0 = 0x3, QUERY_DESC_IDN_INTERCONNECT = 0x4, QUERY_DESC_IDN_STRING = 0x5, QUERY_DESC_IDN_RFU_1 = 0x6, QUERY_DESC_IDN_GEOMETRY = 0x7, QUERY_DESC_IDN_POWER = 0x8, QUERY_DESC_IDN_HEALTH = 0x9, QUERY_DESC_IDN_MAX, }; enum desc_header_offset { QUERY_DESC_LENGTH_OFFSET = 0x00, QUERY_DESC_DESC_TYPE_OFFSET = 0x01, }; /** * struct utp_upiu_query - upiu request buffer structure for * query request. * @opcode: command to perform B-0 * @idn: a value that indicates the particular type of data B-1 * @index: Index to further identify data B-2 * @selector: Index to further identify data B-3 * @reserved_osf: spec reserved field B-4,5 * @length: number of descriptor bytes to read/write B-6,7 * @value: Attribute value to be written DW-5 * @reserved: spec reserved DW-6,7 */ struct utp_upiu_query { __u8 opcode; __u8 idn; __u8 index; __u8 selector; __be16 reserved_osf; __be16 length; __be32 value; __be32 reserved[2]; }; /** * struct utp_upiu_cmd - Command UPIU structure * @data_transfer_len: Data Transfer Length DW-3 * @cdb: Command Descriptor Block CDB DW-4 to DW-7 */ struct utp_upiu_cmd { __be32 exp_data_transfer_len; u8 cdb[UFS_CDB_SIZE]; }; /** * struct utp_upiu_req - general upiu request structure * @header:UPIU header structure DW-0 to DW-2 * @sc: fields structure for scsi command DW-3 to DW-7 * @qr: fields structure for query request DW-3 to DW-7 */ struct utp_upiu_req { struct utp_upiu_header header; union { struct utp_upiu_cmd sc; struct utp_upiu_query qr; struct utp_upiu_query tr; /* use utp_upiu_query to host the 4 dwords of uic command */ struct utp_upiu_query uc; }; }; /** * struct utp_cmd_rsp - Response UPIU structure * @residual_transfer_count: Residual transfer count DW-3 * @reserved: Reserved double words DW-4 to DW-7 * @sense_data_len: Sense data length DW-8 U16 * @sense_data: Sense data field DW-8 to DW-12 */ struct utp_cmd_rsp { __be32 residual_transfer_count; __be32 reserved[4]; __be16 sense_data_len; u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH]; }; /** * struct utp_upiu_rsp - general upiu response structure * @header: UPIU header structure DW-0 to DW-2 * @sr: fields structure for scsi command DW-3 to DW-12 * @qr: fields structure for query request DW-3 to DW-7 */ struct utp_upiu_rsp { struct utp_upiu_header header; union { struct utp_cmd_rsp sr; struct utp_upiu_query qr; }; }; #define MAX_MODEL_LEN 16 /** * ufs_dev_desc - ufs device details from the device descriptor * * @wmanufacturerid: card details * @model: card model */ struct ufs_dev_desc { u16 wmanufacturerid; char model[MAX_MODEL_LEN + 1]; }; /* Device descriptor parameters offsets in bytes*/ enum device_desc_param { DEVICE_DESC_PARAM_LEN = 0x0, DEVICE_DESC_PARAM_TYPE = 0x1, DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2, DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3, DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4, DEVICE_DESC_PARAM_PRTCL = 0x5, DEVICE_DESC_PARAM_NUM_LU = 0x6, DEVICE_DESC_PARAM_NUM_WLU = 0x7, DEVICE_DESC_PARAM_BOOT_ENBL = 0x8, DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9, DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA, DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB, DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC, DEVICE_DESC_PARAM_SEC_LU = 0xD, DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE, DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF, DEVICE_DESC_PARAM_SPEC_VER = 0x10, DEVICE_DESC_PARAM_MANF_DATE = 0x12, DEVICE_DESC_PARAM_MANF_NAME = 0x14, DEVICE_DESC_PARAM_PRDCT_NAME = 0x15, DEVICE_DESC_PARAM_SN = 0x16, DEVICE_DESC_PARAM_OEM_ID = 0x17, DEVICE_DESC_PARAM_MANF_ID = 0x18, DEVICE_DESC_PARAM_UD_OFFSET = 0x1A, DEVICE_DESC_PARAM_UD_LEN = 0x1B, DEVICE_DESC_PARAM_RTT_CAP = 0x1C, DEVICE_DESC_PARAM_FRQ_RTC = 0x1D, DEVICE_DESC_PARAM_UFS_FEAT = 0x1F, DEVICE_DESC_PARAM_FFU_TMT = 0x20, DEVICE_DESC_PARAM_Q_DPTH = 0x21, DEVICE_DESC_PARAM_DEV_VER = 0x22, DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24, DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25, DEVICE_DESC_PARAM_PSA_TMT = 0x29, DEVICE_DESC_PARAM_PRDCT_REV = 0x2A, }; struct ufs_hba; enum { UFSHCD_MAX_CHANNEL = 0, UFSHCD_MAX_ID = 1, }; enum dev_cmd_type { DEV_CMD_TYPE_NOP = 0x0, DEV_CMD_TYPE_QUERY = 0x1, }; /** * struct uic_command - UIC command structure * @command: UIC command * @argument1: UIC command argument 1 * @argument2: UIC command argument 2 * @argument3: UIC command argument 3 * @cmd_active: Indicate if UIC command is outstanding * @result: UIC command result * @done: UIC command completion */ struct uic_command { u32 command; u32 argument1; u32 argument2; u32 argument3; int cmd_active; int result; }; /* Host <-> Device UniPro Link state */ enum uic_link_state { UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ }; /* UIC command interfaces for DME primitives */ #define DME_LOCAL 0 #define DME_PEER 1 #define ATTR_SET_NOR 0 /* NORMAL */ #define ATTR_SET_ST 1 /* STATIC */ int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set, u32 mib_val, u8 peer); int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, u32 *mib_val, u8 peer); static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, u32 mib_val) { return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, mib_val, DME_LOCAL); } static inline int ufshcd_dme_get(struct ufs_hba *hba, u32 attr_sel, u32 *mib_val) { return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); } static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, u32 attr_sel, u32 *mib_val) { return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); } static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, u32 mib_val) { return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, mib_val, DME_PEER); } /** * struct ufs_query_req - parameters for building a query request * @query_func: UPIU header query function * @upiu_req: the query request data */ struct ufs_query_req { u8 query_func; struct utp_upiu_query upiu_req; }; /** * struct ufs_query_resp - UPIU QUERY * @response: device response code * @upiu_res: query response data */ struct ufs_query_res { u8 response; struct utp_upiu_query upiu_res; }; /** * struct ufs_query - holds relevant data structures for query request * @request: request upiu and function * @descriptor: buffer for sending/receiving descriptor * @response: response upiu and response */ struct ufs_query { struct ufs_query_req request; u8 *descriptor; struct ufs_query_res response; }; /** * struct ufs_dev_cmd - all assosiated fields with device management commands * @type: device management command type - Query, NOP OUT * @tag_wq: wait queue until free command slot is available */ struct ufs_dev_cmd { enum dev_cmd_type type; struct ufs_query query; }; struct ufs_hba_ops { int (*init)(struct ufs_hba *hba); int (*get_max_pwr_mode)(struct ufs_hba *hba, struct ufs_pwr_mode_info *max_pwr_info); int (*hce_enable_notify)(struct ufs_hba *hba, enum ufs_notify_change_status); int (*link_startup_notify)(struct ufs_hba *hba, enum ufs_notify_change_status); int (*phy_initialization)(struct ufs_hba *hba); int (*device_reset)(struct ufs_hba *hba); }; enum ufshcd_quirks { /* Interrupt aggregation support is broken */ UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, /* * delay before each dme command is required as the unipro * layer has shown instabilities */ UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, /* * If UFS host controller is having issue in processing LCC (Line * Control Command) coming from device then enable this quirk. * When this quirk is enabled, host controller driver should disable * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE * attribute of device to 0). */ UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, /* * The attribute PA_RXHSUNTERMCAP specifies whether or not the * inbound Link supports unterminated line in HS mode. Setting this * attribute to 1 fixes moving to HS gear. */ UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, /* * This quirk needs to be enabled if the host controller only allows * accessing the peer dme attributes in AUTO mode (FAST AUTO or * SLOW AUTO). */ UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, /* * This quirk needs to be enabled if the host controller doesn't * advertise the correct version in UFS_VER register. If this quirk * is enabled, standard UFS host driver will call the vendor specific * ops (get_ufs_hci_version) to get the correct version. */ UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, /* * Clear handling for transfer/task request list is just opposite. */ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, /* * This quirk needs to be enabled if host controller doesn't allow * that the interrupt aggregation timer and counter are reset by s/w. */ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, /* * This quirks needs to be enabled if host controller cannot be * enabled via HCE register. */ UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, /* * This quirk needs to be enabled if the host controller regards * resolution of the values of PRDTO and PRDTL in UTRD as byte. */ UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, /* * This quirk needs to be enabled if the host controller reports * OCS FATAL ERROR with device error through sense data */ UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, /* * This quirk needs to be enabled if the host controller has * auto-hibernate capability but it doesn't work. */ UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, /* * This quirk needs to disable manual flush for write booster */ UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, /* * This quirk needs to disable unipro timeout values * before power mode change */ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, /* * This quirk needs to be enabled if the host controller does not * support UIC command */ UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, /* * This quirk needs to be enabled if the host controller cannot * support physical host configuration. */ UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, /* * This quirk needs to be enabled if the host controller has * 64-bit addressing supported capability but it doesn't work. */ UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, /* * This quirk needs to be enabled if the host controller has * auto-hibernate capability but it's FASTAUTO only. */ UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, /* * This quirk needs to be enabled if the host controller needs * to reinit the device after switching to maximum gear. */ UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, /* * Some host raises interrupt (per queue) in addition to * CQES (traditional) when ESI is disabled. * Enable this quirk will disable CQES and use per queue interrupt. */ UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, /* * Some host does not implement SQ Run Time Command (SQRTC) register * thus need this quirk to skip related flow. */ UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, /* * This quirk needs to be enabled if the host controller supports inline * encryption but it needs to initialize the crypto capabilities in a * nonstandard way and/or needs to override blk_crypto_ll_ops. If * enabled, the standard code won't initialize the blk_crypto_profile; * ufs_hba_variant_ops::init() must do it instead. */ UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22, /* * This quirk needs to be enabled if the host controller supports inline * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e. * host controller initialization fails if that bit is set. */ UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23, /* * This quirk needs to be enabled if the host controller driver copies * cryptographic keys into the PRDT in order to send them to hardware, * and therefore the PRDT should be zeroized after each request (as per * the standard best practice for managing keys). */ UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24, /* * This quirk indicates that the controller reports the value 1 (not * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the * Controller Capabilities register although it supports the legacy * single doorbell mode. */ UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25, }; struct ufs_hba { struct udevice *dev; void __iomem *mmio_base; struct ufs_hba_ops *ops; struct ufs_desc_size desc_size; u32 capabilities; u32 version; u32 intr_mask; enum ufshcd_quirks quirks; /* Virtual memory reference */ struct utp_transfer_cmd_desc *ucdl; struct utp_transfer_req_desc *utrdl; /* TODO: Add Task Manegement Support */ struct utp_task_req_desc *utmrdl; struct utp_upiu_req *ucd_req_ptr; struct utp_upiu_rsp *ucd_rsp_ptr; struct ufshcd_sg_entry *ucd_prdt_ptr; /* Power Mode information */ enum ufs_dev_pwr_mode curr_dev_pwr_mode; struct ufs_pa_layer_attr pwr_info; struct ufs_pwr_mode_info max_pwr_info; struct ufs_dev_cmd dev_cmd; }; static inline int ufshcd_ops_init(struct ufs_hba *hba) { if (hba->ops && hba->ops->init) return hba->ops->init(hba); return 0; } static inline int ufshcd_ops_get_max_pwr_mode(struct ufs_hba *hba, struct ufs_pwr_mode_info *max_pwr_info) { if (hba->ops && hba->ops->get_max_pwr_mode) return hba->ops->get_max_pwr_mode(hba, max_pwr_info); return 0; } static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba, bool status) { if (hba->ops && hba->ops->hce_enable_notify) return hba->ops->hce_enable_notify(hba, status); return 0; } static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba, bool status) { if (hba->ops && hba->ops->link_startup_notify) return hba->ops->link_startup_notify(hba, status); return 0; } static inline int ufshcd_vops_device_reset(struct ufs_hba *hba) { if (hba->ops && hba->ops->device_reset) return hba->ops->device_reset(hba); return 0; } /* Interrupt disable masks */ enum { /* Interrupt disable mask for UFSHCI v1.0 */ INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, INTERRUPT_MASK_RW_VER_10 = 0x30000, /* Interrupt disable mask for UFSHCI v1.1 */ INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, /* Interrupt disable mask for UFSHCI v2.1 */ INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, }; #define ufshcd_writel(hba, val, reg) \ writel((val), (hba)->mmio_base + (reg)) #define ufshcd_readl(hba, reg) \ readl((hba)->mmio_base + (reg)) /** * ufshcd_rmwl - perform read/modify/write for a controller register * @hba: per adapter instance * @mask: mask to apply on read value * @val: actual value to write * @reg: register address */ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) { u32 tmp; tmp = ufshcd_readl(hba, reg); tmp &= ~mask; tmp |= (val & mask); ufshcd_writel(hba, tmp, reg); } int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops); #endif