summaryrefslogtreecommitdiff
path: root/arch/arm/dts/imx8qxp-capricorn.dtsi
blob: db5653ea1ff4a4037c2e09af9915ab4b9e46d324 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017 NXP
 *
 * Copyright 2019 Siemens AG
 *
 */

/dts-v1/;

#include "fsl-imx8qxp.dtsi"
#include "imx8qxp-capricorn-u-boot.dtsi"

/ {
	model = "Siemens Giedi";
	compatible = "siemens,capricorn", "fsl,imx8qxp";

	chosen {
		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
		stdout-path = &lpuart2;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		run {
			label = "run";
			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		flt {
			label = "flt";
			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		svc {
			label = "svc";
			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		com1_tx {
			label = "com1-tx";
			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		com1_rx {
			label = "com1-rx";
			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		com2_tx {
			label = "com2-tx";
			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		com2_rx {
			label = "com2-rx";
			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		cloud {
			label = "cloud";
			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		wlan {
			label = "wlan";
			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		dbg1 {
			label = "dbg1";
			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		dbg2 {
			label = "dbg2";
			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		dbg3 {
			label = "dbg3";
			gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		dbg4 {
			label = "dbg4";
			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};
};

&iomuxc {
	pinctrl-names = "default";

	muxcgrp: imx8qxp-som {
		pinctrl_gpio_leds: gpioledsgrp {
			fsl,pins = <
			SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021
			SC_P_ESAI0_TX0_LSIO_GPIO0_IO04		0x06000021
			SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x06000021
			SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x06000021
			SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17	0x06000021
			SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18	0x06000021
			SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x06000021
			SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021
			SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x06000021
			SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021
			SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x06000021
			SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
			>;
		};

		pinctrl_lpi2c0: lpi2c0grp {
			fsl,pins = <
			SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x0C000020
			SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x0C000020
			>;
		};

		pinctrl_lpi2c1: lpi2c1grp {
			fsl,pins = <
			SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x0C000020
			SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x0C000020
			>;
		};

		pinctrl_lpuart2: lpuart2grp {
			fsl,pins = <
				SC_P_UART2_RX_ADMA_UART2_RX	0x06000020
				SC_P_UART2_TX_ADMA_UART2_TX	0x06000020
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
				SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29	0x06000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK	0x06000041
				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
				SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B	0x06000021
				//SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x06000021
			>;
		};

		pinctrl_fec2: fec2grp {
			fsl,pins = <
				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0

				SC_P_ENET0_MDC_CONN_ENET1_MDC                   0x00000060
				SC_P_ENET0_MDIO_CONN_ENET1_MDIO                 0x00000060

				SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN            0x00000060
				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x00000060
				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x00000060
				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER        0x00000060
				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x00000060
				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x00000060
				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x00000060
				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x00000060	/* ERST: Reset pin */
			>;
		};
	};
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c0>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";
};

&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	clock-frequency=<52000000>;
	no-1-8-v;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpio3 {
	status = "okay";
};

&gpio4 {
	status = "okay";
};

&gpio5 {
	status = "okay";
};

&fec1 {
	status ="disabled";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rmii";

	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};