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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <config.h>
#include <efi_loader.h>
#include <env.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
#define IMX_BOOT_IMAGE_GUID \
EFI_GUID(0xead2005e, 0x7780, 0x400b, 0x93, 0x48, \
0xa2, 0x82, 0xeb, 0x85, 0x8b, 0x6b)
struct efi_fw_image fw_images[] = {
{
.image_type_id = IMX_BOOT_IMAGE_GUID,
.fw_name = u"IMX8MM-EVK-RAW",
.image_index = 1,
},
};
struct efi_capsule_update_info update_info = {
.dfu_string = "mmc 2=flash-bin raw 0x42 0x2000 mmcpart 1",
.num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
#if IS_ENABLED(CONFIG_FEC_MXC)
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
board_late_mmc_env_init();
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
env_set("board_name", "EVK");
env_set("board_rev", "iMX8MM");
}
return 0;
}
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