blob: 4c4e72763e128dfdfa5c0689678943d0c78d1859 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
/*
* Configuration of the external SDRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
#define CONFIG_SYS_RAM_BASE 0xD0000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
#define CONFIG_SYS_LOAD_ADDR 0xD0400000
#define CONFIG_LOADADDR 0xD0400000
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_ENV_OFFSET (256 << 10)
#define CONFIG_ENV_SECT_SIZE (128 << 10)
#define CONFIG_ENV_SIZE (8 << 10)
#define CONFIG_RED_LED 110
#define CONFIG_GREEN_LED 109
#define CONFIG_STM32_FLASH
#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MALLOC_LEN (2 << 20)
#define CONFIG_BOOTCOMMAND \
"run bootcmd_romfs"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
"bootm 0x08044000 - 0x08042000\0"
/*
* Command line configuration.
*/
#endif /* __CONFIG_H */
|
