diff options
author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
---|---|---|
committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
commit | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch) | |
tree | f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/calmrisc32 | |
parent | f157da5337118d3c5cd464266796de4262ac9dbd (diff) |
Added the OS files
Diffstat (limited to 'ecos/packages/hal/calmrisc32')
43 files changed, 6887 insertions, 0 deletions
diff --git a/ecos/packages/hal/calmrisc32/arch/current/ChangeLog b/ecos/packages/hal/calmrisc32/arch/current/ChangeLog new file mode 100644 index 0000000..d04df1c --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/ChangeLog @@ -0,0 +1,60 @@ +2004-04-22 Jani Monoses <jani@iv.ro> + + * cdl/hal_calm32.cdl : + Invoke tail with stricter syntax that works in latest coreutils. + +2003-12-08 Gary Thomas <gary@mlbassoc.com> + + * src/hal_misc.c: Only declare __mem_fault_handler if GDB stubs + are included (and it will be used). + +2003-01-31 Mark Salter <msalter@redhat.com> + + * src/hal_syscall.c (hal_syscall_handler): Let generic syscall code + handle exit. + +2002-04-15 Jonathan Larmour <jlarmour@redhat.com> + + * src/hal_syscall.c (hal_syscall_handler): Add extra sig argument to + __do_syscall. + +2001-11-16 Nick Garnett <nickg@redhat.com> + + * src/hal_misc.c (hal_msbit_index): Fixed this function so that it + actually works! + +2001-06-08 Jonathan Larmour <jlarmour@redhat.com> + + * include/hal_cache.h: Correctly indicate absence of cache. + +2001-03-26 Mark Salter <msalter@redhat.com> + + * src/vectors.S: Fix saving of R8 in exception handlers. + + * src/calm32-stub.c (__read_prog_uint32): Add missing return val. + + * include/calm32-stub.h: Add extern declaration for __sp_regnum. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/calmrisc32/arch/current/cdl/hal_calm32.cdl b/ecos/packages/hal/calmrisc32/arch/current/cdl/hal_calm32.cdl new file mode 100644 index 0000000..c695369 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/cdl/hal_calm32.cdl @@ -0,0 +1,100 @@ +# ==================================================================== +# +# hal_calm32.cdl +# +# CalmRISC32 architectural HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Original data: bartv, nickg +# Contributors: +# Date: 1999-11-02 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_CALM32 { + display "CalmRISC32 architecture" + parent CYGPKG_HAL + hardware + include_dir cyg/hal + define_header hal_calm32.h + description " + The CalmRISC32 architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a CPU variant and a specific target platform HAL + package." + + cdl_interface CYGINT_HAL_CALM32_VARIANT { + display "Number of variant implementations in this configuration" + requires 1 == CYGINT_HAL_CALM32_VARIANT + } + + compile hal_misc.c context.S calm32-stub.c hal_syscall.c + + make { + <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S + $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 vectors.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm vectors.tmp + } + + cdl_option CYGHWR_HAL_CALM32_CPU_FREQ { + display "CPU frequency" + flavor data + legal_values 0 to 1000000 + default_value 50 + description " + This option contains the frequency of the CPU in MegaHertz. + Choose the frequency to match the processor you have. This + may affect thing like serial device, interval clock and + memory access speed settings." + } + + cdl_option CYGDBG_HAL_CALM32_DEBUG_GDB_CTRLC_SUPPORT { + display "Architecture GDB CTRLC support" + calculated { CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT } + active_if { CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0 } + description " + If either the CTRLC or BREAK support options in hal.h are set + then set our own option to turn on shared generic support for + control C handling." + } +} diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/arch.inc b/ecos/packages/hal/calmrisc32/arch/current/include/arch.inc new file mode 100644 index 0000000..55cb216 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/arch.inc @@ -0,0 +1,156 @@ +#ifndef CYGONCE_HAL_ARCH_INC +#define CYGONCE_HAL_ARCH_INC +##============================================================================= +## +## arch.inc +## +## CalmRISC32 assembler header file +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): msalter +## Contributors: nickg, dmoseley +## Date: 1997-10-16 +## Purpose: Architecture definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the CalmRISC32 CPU family. +## Usage: +## #include <cyg/hal/arch.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/calm32.inc> + +#include <cyg/hal/variant.inc> + +##----------------------------------------------------------------------------- +## CalmRISC32 thread and interrupt saved state. This must match the layout of +## the HAL_SavedRegisters in hal_arch.h. Do not change this without changing +## the layout there, or viceversa. + + +##----------------------------------------------------------------------------- +## CPU specific macros. These provide a common assembler interface to +## operations that may have CPU specific implementations on different +## variants of the architecture. + + # Initialize CPU + .macro hal_cpu_init + .endm + + # Enable interrupts + .macro hal_cpu_int_enable + .endm + + # Disable interrupts + .macro hal_cpu_int_disable + .endm + +#------------------------------------------------------------------------------ +# MMU macros. + +#ifndef CYGPKG_HAL_CALM32_MMU_DEFINED + + .macro hal_mmu_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# MEMC macros. + +#ifndef CYGPKG_HAL_CALM32_MEMC_DEFINED + + .macro hal_memc_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Cache macros. + +#ifndef CYGPKG_HAL_CALM32_CACHE_DEFINED + + .macro hal_cache_init + .endm +#endif + + +#------------------------------------------------------------------------------ +# Diagnostics macros. + +#ifndef CYGPKG_HAL_CALM32_DIAG_DEFINED + + .macro hal_diag_init + .endm + + .macro hal_diag_excpt_start + .endm + + .macro hal_diag_intr_start + .endm + + .macro hal_diag_restore + .endm +#endif + +#------------------------------------------------------------------------------ +# Timer initialization. + +#ifndef CYGPKG_HAL_CALM32_TIMER_DEFINED + + .macro hal_timer_init + .endm + +#endif + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_CALM32_MON_DEFINED + + .macro hal_mon_init + .endm + +#endif + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_ARCH_INC +# end of arch.inc diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/basetype.h b/ecos/packages/hal/calmrisc32/arch/current/include/basetype.h new file mode 100644 index 0000000..2742d3f --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/basetype.h @@ -0,0 +1,74 @@ +#ifndef CYGONCE_HAL_BASETYPE_H +#define CYGONCE_HAL_BASETYPE_H + +//============================================================================= +// +// basetype.h +// +// Standard types for this architecture. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, msalter +// Date: 1998-02-05 +// Purpose: Define architecture base types. +// Usage: Included by <cyg/infra/cyg_types.h>, do not use directly +// +//####DESCRIPTIONEND#### +// + +#include <pkgconf/hal.h> + +//----------------------------------------------------------------------------- +// Characterize the architecture + +#define CYG_BYTEORDER CYG_MSBFIRST // Big endian + + + +//----------------------------------------------------------------------------- +// CalmRISC32 does not usually use labels with undersores. + +#define CYG_LABEL_NAME(_name_) _name_ + +//----------------------------------------------------------------------------- +// Define the standard variable sizes + + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_BASETYPE_H +// End of basetype.h diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/calm32-regs.h b/ecos/packages/hal/calmrisc32/arch/current/include/calm32-regs.h new file mode 100644 index 0000000..a2c5832 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/calm32-regs.h @@ -0,0 +1,86 @@ +#ifndef CYGONCE_HAL_CALM32_REGS_H +#define CYGONCE_HAL_CALM32_REGS_H +//======================================================================== +// +// calm32-regs.h +// +// Register defines for CalmRISC 16 processors +// +//======================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Red Hat, msalter +// Contributors: Red Hat, msalter +// Date: 2001-02-12 +// Purpose: +// Description: Register defines for CalmRISC 16 processors +// Usage: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#include <pkgconf/hal.h> + +#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +// This value must agree with NUMREGS in calm32-stub.h. + +#define NUM_REGS 23 + +#define REG_SIZE 4 + +// Status register fields +#define SR_T 0x00000001 // TRUE flag +#define SR_V 0x00000008 // Overflow flag +#define SR_Z0 0x00000010 // R6 Zero flag +#define SR_Z1 0x00000020 // R7 Zero flag. +#define SR_DS 0x00000040 // Divisor sign +#define SR_QT 0x00000080 // Quotient +#define SR_BX 0x00001000 // Byte sign extension +#define SR_HX 0x00002000 // Halfword sign extension +#define SR_SYSX_MASK 0x000f0000 // system extension +#define SR_SYSX_SHIFT 16 +#define SR_IE 0x01000000 // IRQ enable +#define SR_FE 0x02000000 // FIQ enable +#define SR_TE 0x04000000 // Trace enable +#define SR_BS 0x10000000 // FIQ enable +#define SR_RS0 0x20000000 // Register bank select +#define SR_RS1 0x40000000 // Register bank select +#define SR_PM 0x80000000 // Privilege mode + +#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +#endif // ifndef CYGONCE_HAL_CALM32_REGS_H diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/calm32-stub.h b/ecos/packages/hal/calmrisc32/arch/current/include/calm32-stub.h new file mode 100644 index 0000000..5144861 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/calm32-stub.h @@ -0,0 +1,171 @@ +#ifndef CYGONCE_HAL_MIPS_STUB_H +#define CYGONCE_HAL_MIPS_STUB_H +//======================================================================== +// +// mips-stub.h +// +// CalmRISC32-specific definitions for generic stub +// +//======================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Red Hat, msalter +// Contributors: Red Hat, msalter +// Date: 2001-02-12 +// Purpose: +// Description: CalmRISC32-specific definitions for generic stub +// Usage: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + + +#include <pkgconf/system.h> + +#include <cyg/hal/hal_io.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define TARGET_HAS_HARVARD_MEMORY 1 +typedef unsigned long long target_addr_t; +#define TARGET_ADDR_IS_PROGMEM(x) (((unsigned long long)(x)) >= 0x100000000ULL) +#define TARGET_ADDR_TO_PTR(x) ((char *) (((unsigned)(x)) & 0xffffffff)) + +#define NUMREGS 43 + +#define REGSIZE(X) 4 +typedef unsigned long target_register_t; + +enum regnames { + REG_B0R0, REG_B0R1, REG_B0R2, REG_B0R3, REG_B0R4, REG_B0R5, REG_B0R6, REG_B0R7, + REG_B0R8, REG_B0R9, REG_B0R10, REG_B0R11, REG_B0R12, REG_B0R13, REG_B0R14, REG_B0R15, + REG_B1R0, REG_B1R1, REG_B1R2, REG_B1R3, REG_B1R4, REG_B1R5, REG_B1R6, REG_B1R7, + REG_B1R8, REG_B1R9, REG_B1R10, REG_B1R11, REG_B1R12, REG_B1R13, REG_B1R14, REG_B1R15, + REG_PC, REG_VBR, REG_SR, + REG_SSR_FIQ, REG_SPC_FIQ, REG_SSR_IRQ, REG_SPC_IRQ, + REG_SSR_SWI, REG_SPC_SWI, REG_SSR_EXPT, REG_SPC_EXPT +}; + +typedef enum regnames regnames_t; + +#define PC REG_PC +#define SP __sp_regnum() +extern int __sp_regnum(void); + +#define HAL_STUB_ADD_T_REG(__ptr__,__reg__,__val__) \ + *__ptr__++ = __tohex (__reg__ >> 4); \ + *__ptr__++ = __tohex (__reg__); \ + *__ptr__++ = ':'; \ + __val__ = get_register (__reg__); \ + __ptr__ = __mem2hex((char *)&__val__, __ptr__, sizeof(__val__), 0); \ + *ptr++ = ';' + +#define HAL_STUB_ARCH_T_PACKET_EXTRAS(__ptr__) \ +{ \ + target_register_t __val__; \ + \ + HAL_STUB_ADD_T_REG(__ptr__,REG_SR,__val__); \ + if ((__val__ & CYGARC_SR_PM) == 0 || (__val__ & CYGARC_SR_BS) == 0){ \ + HAL_STUB_ADD_T_REG(__ptr__,REG_B0R13,__val__); \ + } else { \ + HAL_STUB_ADD_T_REG(__ptr__,REG_B1R13,__val__); \ + } \ +} + +/* Given a trap value TRAP, return the corresponding signal. */ +extern int __computeSignal (unsigned int trap_number); + +/* Return the SPARC trap number corresponding to the last-taken trap. */ +extern int __get_trap_number (void); + +/* Return the currently-saved value corresponding to register REG. */ +extern target_register_t get_register (regnames_t reg); + +/* Store VALUE in the register corresponding to WHICH. */ +extern void put_register (regnames_t which, target_register_t value); + +/* Set the currently-saved pc register value to PC. */ +#if !defined(SET_PC_PROTOTYPE_EXISTS) && !defined(set_pc) +#define SET_PC_PROTOTYPE_EXISTS +extern void set_pc (target_register_t pc); +#endif + +/* Set things up so that the next user resume will execute one instruction. + This may be done by setting breakpoints or setting a single step flag + in the saved user registers, for example. */ +#ifndef __single_step +void __single_step (void); +#endif + +/* Clear the single-step state. */ +void __clear_single_step (void); + +extern int __is_bsp_syscall(void); + +extern int hal_syscall_handler(void); + +/* If the breakpoint we hit is in the breakpoint() instruction, return a + non-zero value. */ +#ifndef __is_breakpoint_function +extern int __is_breakpoint_function (void); +#endif + +/* Skip the current instruction. */ +extern void __skipinst (void); + +extern void __install_breakpoints (void); + +extern void __clear_breakpoints (void); + +extern void __install_breakpoint_list (void); + +extern void __clear_breakpoint_list (void); + +extern unsigned char __read_prog_uint8(void *addr); +extern unsigned short __read_prog_uint16(void *addr); +extern unsigned int __read_prog_uint32(void *addr); + +extern void __write_prog_uint8(void *addr, unsigned char val); +extern void __write_prog_uint16(void *addr, unsigned short val); +extern void __write_prog_uint32(void *addr, unsigned int val); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif // ifndef CYGONCE_HAL_MIPS_STUB_H diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/calm32.inc b/ecos/packages/hal/calmrisc32/arch/current/include/calm32.inc new file mode 100644 index 0000000..69653c0 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/calm32.inc @@ -0,0 +1,77 @@ +#ifndef CYGONCE_HAL_CALM32_INC +#define CYGONCE_HAL_CALM32_INC + +##============================================================================= +## +## calm32.inc +## +## CalmRISC32 assembler header file +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): msalter +## Contributors: msalter +## Date: 2001-02-12 +## Purpose: CalmRISC32 definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the MIPS CPU family. +## Usage: +## #include <cyg/hal/calm32.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + + +#------------------------------------------------------------------------------ + +#define SYM_NAME(x) x +.macro FUNC_START name + .type \name,@function + .globl \name +\name: +.endm + +.macro FUNC_END name +\name\(_end): +.endm + + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_CALM32_INC +# end of calm32.inc diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/hal_arch.h b/ecos/packages/hal/calmrisc32/arch/current/include/hal_arch.h new file mode 100644 index 0000000..94b88df --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/hal_arch.h @@ -0,0 +1,363 @@ +#ifndef CYGONCE_HAL_HAL_ARCH_H +#define CYGONCE_HAL_HAL_ARCH_H + +//========================================================================== +// +// hal_arch.h +// +// Architecture specific abstractions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, dmoseley +// Date: 1999-02-17 +// Purpose: Define architecture abstractions +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#ifndef __ASSEMBLER__ +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/var_arch.h> + +//-------------------------------------------------------------------------- +// Processor saved states: +// The layout of this structure is also defined in "arch.inc", for assembly +// code. Do not change this without changing that (or vice versa). +// Notes: This structure is carefully laid out. It is a multiple of 8 +// bytes and the pc and badvr fields are positioned to ensure that +// they are on 8 byte boundaries. + + +typedef struct +{ + CYG_WORD32 vector; + CYG_WORD32 vbr; + CYG_WORD32 spc_irq; + CYG_WORD32 spc_fiq; + CYG_WORD32 spc_swi; + CYG_WORD32 spc_expt; + CYG_WORD32 ssr_irq; + CYG_WORD32 ssr_fiq; + CYG_WORD32 ssr_swi; + CYG_WORD32 ssr_expt; + CYG_WORD32 bank0[16]; + CYG_WORD32 bank1[16]; +} HAL_SavedRegisters; + +//-------------------------------------------------------------------------- +// Exception handling function. +// This function is defined by the kernel according to this prototype. It is +// invoked from the HAL to deal with any CPU exceptions that the HAL does +// not want to deal with itself. It usually invokes the kernel's exception +// delivery mechanism. + +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); + +//-------------------------------------------------------------------------- +// Bit manipulation macros + +externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); +externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); + +#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask); + +#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask); + +//-------------------------------------------------------------------------- +// Context Initialization + +// Optional FPU context initialization +#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) + +// Initialize the context of a thread. +// Arguments: +// _sparg_ name of variable containing current sp, will be written with new sp +// _thread_ thread object address, passed as argument to entry point +// _entry_ entry point address. +// _id_ bit pattern used in initializing registers, for debugging. +#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ +{ \ +} + +//-------------------------------------------------------------------------- +// Context switch macros. +// The arguments are pointers to locations where the stack pointer +// of the current thread is to be stored, and from where the sp of the +// next thread is to be fetched. + +externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); +externC void hal_thread_load_context( CYG_ADDRESS to ) + __attribute__ ((noreturn)); + +#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ + hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \ + (CYG_ADDRESS)_fspptr_); + +#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ + hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); + +//-------------------------------------------------------------------------- +// Execution reorder barrier. +// When optimizing the compiler can reorder code. In multithreaded systems +// where the order of actions is vital, this can sometimes cause problems. +// This macro may be inserted into places where reordering should not happen. +// The "memory" keyword is potentially unnecessary, but it is harmless to +// keep it. + +#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) + +//-------------------------------------------------------------------------- +// Breakpoint support +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to +// happen if executed. +// HAL_BREAKINST is the value of the breakpoint instruction and +// HAL_BREAKINST_SIZE is its size in bytes. +// HAL_BREAKINST_TYPE is the type. + +#define HAL_BREAKPOINT(_label_) \ +asm volatile (" .globl " #_label_ "\n" \ + #_label_":" \ + " .short 0x80e0 \n" \ + ); + +#define HAL_BREAKINST 0x80e0 + +#define HAL_BREAKINST_SIZE 2 + +#define HAL_BREAKINST_TYPE cyg_uint16 + +//-------------------------------------------------------------------------- +// Thread register state manipulation for GDB support. + +// Default to a 32 bit register size for GDB register dumps. +#ifndef CYG_HAL_GDB_REG +#define CYG_HAL_GDB_REG CYG_WORD32 +#endif + +// Translate a stack pointer as saved by the thread context macros above into +// a pointer to a HAL_SavedRegisters structure. +#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ + (_regs_) = (HAL_SavedRegisters *)(_sp_) + +// Copy a set of registers from a HAL_SavedRegisters structure into a +// GDB ordered array. +#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ +{ \ + CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \ + int _i_; \ + \ + for( _i_ = 0; _i_ < 16; _i_++ ) \ + _regval_[_i_] = (_regs_)->bank0[_i_]; \ + for( _i_ = 0; _i_ < 16; _i_++ ) \ + _regval_[16+_i_] = (_regs_)->bank1[_i_]; \ + _regval_[REG_VBR] = (_regs_)->vbr; \ + _regval_[REG_SSR_FIQ] = (_regs_)->ssr_fiq; \ + _regval_[REG_SSR_IRQ] = (_regs_)->ssr_irq; \ + _regval_[REG_SSR_SWI] = (_regs_)->ssr_swi; \ + _regval_[REG_SSR_EXPT] = (_regs_)->ssr_expt; \ + _regval_[REG_SPC_FIQ] = (_regs_)->spc_fiq; \ + _regval_[REG_SPC_IRQ] = (_regs_)->spc_irq; \ + _regval_[REG_SPC_SWI] = (_regs_)->spc_swi; \ + _regval_[REG_SPC_EXPT] = (_regs_)->spc_expt; \ + switch ((_regs_)->vector) { \ + case CYGNUM_HAL_VECTOR_SWI: \ + _regval_[REG_SR] = (_regs_)->ssr_swi; \ + _regval_[REG_PC] = (_regs_)->spc_swi; break; \ + case CYGNUM_HAL_VECTOR_IRQ: \ + _regval_[REG_SR] = (_regs_)->ssr_irq; \ + _regval_[REG_PC] = (_regs_)->spc_irq; break; \ + case CYGNUM_HAL_VECTOR_FIQ: \ + _regval_[REG_SR] = (_regs_)->ssr_fiq; \ + _regval_[REG_PC] = (_regs_)->spc_fiq; break; \ + default: \ + _regval_[REG_SR] = (_regs_)->ssr_expt; \ + _regval_[REG_PC] = (_regs_)->spc_expt; break; \ + } \ + \ +} + +// Copy a GDB ordered array into a HAL_SavedRegisters structure. +#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ +{ \ + CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \ + int _i_; \ + \ + for( _i_ = 0; _i_ < 16; _i_++ ) \ + (_regs_)->bank0[_i_] = _regval_[_i_]; \ + for( _i_ = 0; _i_ < 16; _i_++ ) \ + (_regs_)->bank1[_i_] = _regval_[16+_i_]; \ + (_regs_)->vbr = _regval_[REG_VBR]; \ + (_regs_)->ssr_fiq = _regval_[REG_SSR_FIQ]; \ + (_regs_)->ssr_irq = _regval_[REG_SSR_IRQ]; \ + (_regs_)->ssr_swi = _regval_[REG_SSR_SWI]; \ + (_regs_)->ssr_expt = _regval_[REG_SSR_EXPT]; \ + (_regs_)->spc_fiq = _regval_[REG_SPC_FIQ]; \ + (_regs_)->spc_irq = _regval_[REG_SPC_IRQ]; \ + (_regs_)->spc_swi = _regval_[REG_SPC_SWI]; \ + (_regs_)->spc_expt = _regval_[REG_SPC_EXPT]; \ + switch (__get_trap_number()) { \ + case CYGNUM_HAL_VECTOR_SWI: \ + (_regs_)->ssr_swi = _regval_[REG_SR]; \ + (_regs_)->spc_swi = _regval_[REG_PC]; break; \ + case CYGNUM_HAL_VECTOR_IRQ: \ + (_regs_)->ssr_irq = _regval_[REG_SR]; \ + (_regs_)->spc_irq = _regval_[REG_PC]; break; \ + case CYGNUM_HAL_VECTOR_FIQ: \ + (_regs_)->ssr_fiq = _regval_[REG_SR]; \ + (_regs_)->spc_fiq = _regval_[REG_PC]; break; \ + default: \ + (_regs_)->ssr_expt = _regval_[REG_SR]; \ + (_regs_)->spc_expt = _regval_[REG_PC]; break; \ + } \ + \ +} + +#define CYGARC_HAL_GET_PC_REG(_regs_, _val_) \ +{ \ + switch ((_regs_)->vector) { \ + case CYGNUM_HAL_VECTOR_SWI: \ + (_val_) = (_regs_)->spc_swi; break; \ + case CYGNUM_HAL_VECTOR_IRQ: \ + (_val_) = (_regs_)->spc_irq; break; \ + case CYGNUM_HAL_VECTOR_FIQ: \ + (_val_) = (_regs_)->spc_fiq; break; \ + default: \ + (_val_) = (_regs_)->spc_expt; break; \ + } \ +} + +//-------------------------------------------------------------------------- +// HAL setjmp +// Note: These definitions are repeated in context.S. If changes are +// required remember to update both sets. + +#define CYGARC_JMP_BUF_R4 0 +#define CYGARC_JMP_BUF_R5 2 +#define CYGARC_JMP_BUF_R12 4 +#define CYGARC_JMP_BUF_R13 8 +#define CYGARC_JMP_BUF_R14 12 +#define CYGARC_JMP_BUF_R15 16 + +#define CYGARC_JMP_BUF_SIZE 20 + +typedef cyg_uint16 hal_jmp_buf[CYGARC_JMP_BUF_SIZE/sizeof(cyg_uint16)]; + +externC int hal_setjmp(hal_jmp_buf env); +externC void hal_longjmp(hal_jmp_buf env, int val); + +//------------------------------------------------------------------------- +// Idle thread code. +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. + +externC void hal_idle_thread_action(cyg_uint32 loop_count); + +#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) + +//-------------------------------------------------------------------------- +// Minimal and sensible stack sizes: the intention is that applications +// will use these to provide a stack size in the first instance prior to +// proper analysis. Idle thread stack should be this big. + +// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. +// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. +// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! + +// This is not a config option because it should not be adjusted except +// under "enough rope" sort of disclaimers. + +// Typical case stack frame size: return link + 4 pushed registers + some locals. +#define CYGNUM_HAL_STACK_FRAME_SIZE (48) + +// Stack needed for a context switch: +#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*CYG_HAL_MIPS_REG_SIZE) + +// Interrupt + call to ISR, interrupt_end() and the DSR +#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE) + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + +// An interrupt stack which is large enough for all possible interrupt +// conditions (and only used for that purpose) exists. "User" stacks +// can be much smaller + +#define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \ + CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \ + CYGNUM_HAL_STACK_FRAME_SIZE*8) +#define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024) + +#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + +// No separate interrupt stack exists. Make sure all threads contain +// a stack sufficiently large. + +#define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096) +#define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096) + +#endif + +#endif /* __ASSEMBLER__ */ + + +//-------------------------------------------------------------------------- +// Macros for switching context between two eCos instances (jump from +// code in ROM to code in RAM or vice versa). +#define CYGARC_HAL_SAVE_GP() +#define CYGARC_HAL_RESTORE_GP() + +//-------------------------------------------------------------------------- +// Defines for status register bit access + +#define CYGARC_SR_PM (1<<31) +#define CYGARC_SR_RS1 (1<<30) +#define CYGARC_SR_RS0 (1<<29) +#define CYGARC_SR_BS (1<<28) +#define CYGARC_SR_TE (1<<26) +#define CYGARC_SR_FE (1<<25) +#define CYGARC_SR_IE (1<<24) + + + +//-------------------------------------------------------------------------- +#endif // CYGONCE_HAL_HAL_ARCH_H +// End of hal_arch.h diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/hal_cache.h b/ecos/packages/hal/calmrisc32/arch/current/include/hal_cache.h new file mode 100644 index 0000000..c50722c --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/hal_cache.h @@ -0,0 +1,264 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/var_cache.h> + + +//----------------------------------------------------------------------------- +// Cache dimensions. +// These really should be defined in var_cache.h. If they are not, then provide +// a set of numbers that are typical of many variants. + +#ifndef HAL_DCACHE_SIZE + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +//#define HAL_DCACHE_SETS 0 +//#define HAL_ICACHE_SETS 0 + +#endif + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +// There is no default mechanism for enabling or disabling the caches. +#ifndef HAL_DCACHE_ENABLE_DEFINED +#define HAL_DCACHE_ENABLE() +#endif + +// Disable the data cache +#ifndef HAL_DCACHE_DISABLE_DEFINED +#define HAL_DCACHE_DISABLE() +#endif + +#ifndef HAL_DCACHE_IS_ENABLED_DEFINED +#define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1; +#endif + +// Invalidate the entire cache +// We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this +// is not quite what we want, but there is no index-invalidate operation +// available. +#ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED +#define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC() +#endif + +// Synchronize the contents of the cache with memory. +// This uses the index-writeback-invalidate operation. +#ifndef HAL_DCACHE_SYNC_DEFINED +#define HAL_DCACHE_SYNC() \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +// This uses the fetch-and-lock cache operation. +#ifndef HAL_DCACHE_LOCK_DEFINED +#define HAL_DCACHE_LOCK(_base_, _asize_) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// Undo a previous lock operation. +// Do this by flushing the cache, which is defined to clear the lock bit. +#ifndef HAL_DCACHE_UNLOCK_DEFINED +#define HAL_DCACHE_UNLOCK(_base_, _size_) \ + HAL_DCACHE_FLUSH( _base_, _size_ ) +#endif + +// Unlock entire cache +#ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED +#define HAL_DCACHE_UNLOCK_ALL() \ + HAL_DCACHE_INVALIDATE_ALL() +#endif + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +// This uses the hit-writeback-invalidate cache operation. +#ifndef HAL_DCACHE_FLUSH_DEFINED +#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// Invalidate cache lines in the given range without writing to memory. +// This uses the hit-invalidate cache operation. +#ifndef HAL_DCACHE_INVALIDATE_DEFINED +#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// Write dirty cache lines to memory for the given address range. +// This uses the hit-writeback cache operation. +#ifndef HAL_DCACHE_STORE_DEFINED +#define HAL_DCACHE_STORE( _base_ , _asize_ ) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +// There is no default mechanism for enabling or disabling the caches. +#ifndef HAL_ICACHE_ENABLE_DEFINED +#define HAL_ICACHE_ENABLE() +#endif + +// Disable the instruction cache +#ifndef HAL_ICACHE_DISABLE_DEFINED +#define HAL_ICACHE_DISABLE() +#endif + +#ifndef HAL_ICACHE_IS_ENABLED_DEFINED +#define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1; +#endif + +// Invalidate the entire cache +// This uses the index-invalidate cache operation. +#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED +#define HAL_ICACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// Synchronize the contents of the cache with memory. +// Simply force the cache to reload. +#ifndef HAL_ICACHE_SYNC_DEFINED +#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL() +#endif + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +// This uses the fetch-and-lock cache operation. +#ifndef HAL_ICACHE_LOCK_DEFINED +#define HAL_ICACHE_LOCK(_base_, _asize_) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + +// Undo a previous lock operation. +// Do this by invalidating the cache, which is defined to clear the lock bit. +#ifndef HAL_ICACHE_UNLOCK_DEFINED +#define HAL_ICACHE_UNLOCK(_base_, _size_) \ + HAL_ICACHE_INVALIDATE( _base_, _size_ ) +#endif + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +// This uses the hit-invalidate cache operation. +#ifndef HAL_ICACHE_INVALIDATE_DEFINED +#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif + + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/hal_intr.h b/ecos/packages/hal/calmrisc32/arch/current/include/hal_intr.h new file mode 100644 index 0000000..de5a310 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/hal_intr.h @@ -0,0 +1,301 @@ +#ifndef CYGONCE_HAL_HAL_INTR_H +#define CYGONCE_HAL_HAL_INTR_H + +//========================================================================== +// +// hal_intr.h +// +// HAL Interrupt and clock support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov, +// gthomas, jlarmour, msalter +// Date: 1999-02-16 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock. +// +// Usage: +// #include <cyg/hal/hal_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/var_intr.h> + +//-------------------------------------------------------------------------- +// MIPS vectors. + +// These are the exception codes presented in the Cause register and +// correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET + + +#define CYGNUM_HAL_VECTOR_FIQ 0 // External Fast Interrupt +#define CYGNUM_HAL_VECTOR_IRQ 1 // External Interrupt +#define CYGNUM_HAL_VECTOR_COP 2 // Coprocessor Exception +#define CYGNUM_HAL_VECTOR_DABRT 3 // Data abort +#define CYGNUM_HAL_VECTOR_IABRT 4 // Instruction abort +#define CYGNUM_HAL_VECTOR_PRIV 5 // Privilege violation +#define CYGNUM_HAL_VECTOR_UNIMPL 6 // Unimplemented Insn +#define CYGNUM_HAL_VECTOR_TRACE 7 // Single-step +#define CYGNUM_HAL_VECTOR_SWI 8 // SWI + +#define CYGNUM_HAL_VSR_MIN 0 +#define CYGNUM_HAL_VSR_MAX 8 +#define CYGNUM_HAL_VSR_COUNT 9 + +// Min/Max exception numbers and how many there are +#define CYGNUM_HAL_EXCEPTION_MIN 0 +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX + +#define CYGNUM_HAL_EXCEPTION_COUNT \ + ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 ) + + +#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED +#define CYGNUM_HAL_FAST_INTERRUPT 0 +#define CYGNUM_HAL_INTERRUPT 1 + +// Min/Max ISR numbers and how many there are +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 1 +#define CYGNUM_HAL_ISR_COUNT 2 + +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED +#endif + +//-------------------------------------------------------------------------- +// Static data used by HAL + +// ISR tables +externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +// VSR table +externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1]; + +//-------------------------------------------------------------------------- +// Default ISR +// The #define is used to test whether this routine exists, and to allow +// us to call it. + +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); + +#define HAL_DEFAULT_ISR hal_default_isr + +//-------------------------------------------------------------------------- +// Interrupt state storage + +typedef cyg_uint32 CYG_INTERRUPT_STATE; + +//-------------------------------------------------------------------------- +// Interrupt control macros +// Beware of nops in this code. They fill delay slots and avoid CP0 hazards +// that might otherwise cause following code to run in the wrong state or +// cause a resource conflict. + +#define HAL_DISABLE_INTERRUPTS(_old_) +#define HAL_ENABLE_INTERRUPTS() +#define HAL_RESTORE_INTERRUPTS(_old_) +#define HAL_QUERY_INTERRUPTS( _state_ ) + +//-------------------------------------------------------------------------- +// Routine to execute DSRs using separate interrupt stack + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +externC void hal_interrupt_stack_call_pending_DSRs(void); +#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ + hal_interrupt_stack_call_pending_DSRs() + +// these are offered solely for stack usage testing +// if they are not defined, then there is no interrupt stack. +#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base +#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack +// use them to declare these extern however you want: +// extern char HAL_INTERRUPT_STACK_BASE[]; +// extern char HAL_INTERRUPT_STACK_TOP[]; +// is recommended +#endif + +//-------------------------------------------------------------------------- +// Vector translation. +// For chained interrupts we only have a single vector though which all +// are passed. For unchained interrupts we have a vector per interrupt. + +#ifndef HAL_TRANSLATE_VECTOR + +#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) + +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0 + +#else + +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_) + +#endif + +#endif + +//-------------------------------------------------------------------------- +// Interrupt and VSR attachment macros + +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ +{ \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ + \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ + { \ + hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ + hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ + hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ + } \ +} + +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ +{ \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ + \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ + { \ + hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \ + hal_interrupt_data[_index_] = 0; \ + hal_interrupt_objects[_index_] = 0; \ + } \ +} + +#define HAL_VSR_GET( _vector_, _pvsr_ ) \ + *(_pvsr_) = (void (*)())hal_vsr_table[_vector_]; + + +#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \ + if( (void*)_poldvsr_ != NULL) \ + *(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \ + hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ +CYG_MACRO_END + +// This is an ugly name, but what it means is: grab the VSR back to eCos +// internal handling, or if you like, the default handler. But if +// cooperating with GDB and CygMon, the default behaviour is to pass most +// exceptions to CygMon. This macro undoes that so that eCos handles the +// exception. So use it with care. + +externC void __default_exception_vsr(void); +externC void __default_interrupt_vsr(void); +externC void __break_vsr_springboard(void); + +#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \ + HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \ + ? (CYG_ADDRESS)__default_interrupt_vsr \ + : _vector_ == CYGNUM_HAL_VECTOR_BREAKPOINT \ + ? (CYG_ADDRESS)__break_vsr_springboard \ + : (CYG_ADDRESS)__default_exception_vsr, \ + _poldvsr_ ); \ +CYG_MACRO_END + +//-------------------------------------------------------------------------- +// Interrupt controller access +// The default code here simply uses the fields present in the CP0 status +// and cause registers to implement this functionality. +// Beware of nops in this code. They fill delay slots and avoid CP0 hazards +// that might otherwise cause following code to run in the wrong state or +// cause a resource conflict. + +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#define HAL_INTERRUPT_MASK( _vector_ ) + +#define HAL_INTERRUPT_UNMASK( _vector_ ) + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) + +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#endif + +//-------------------------------------------------------------------------- +// Clock control. +// This code uses the count and compare registers that are present in many +// MIPS variants. +// Beware of nops in this code. They fill delay slots and avoid CP0 hazards +// that might otherwise cause following code to run in the wrong state or +// cause a resource conflict. + +#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED + +externC CYG_WORD32 cyg_hal_clock_period; +#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED + +#define HAL_CLOCK_INITIALIZE( _period_ ) + +#define HAL_CLOCK_RESET( _vector_, _period_ ) + +#define HAL_CLOCK_READ( _pvalue_ ) + +#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED + +#endif + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_HAL_INTR_H +// End of hal_intr.h diff --git a/ecos/packages/hal/calmrisc32/arch/current/include/hal_io.h b/ecos/packages/hal/calmrisc32/arch/current/include/hal_io.h new file mode 100644 index 0000000..4cca525 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/include/hal_io.h @@ -0,0 +1,157 @@ +#ifndef CYGONCE_HAL_HAL_IO_H +#define CYGONCE_HAL_HAL_IO_H + +//============================================================================= +// +// hal_io.h +// +// HAL device IO register support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Define IO register support +// Description: The macros defined here provide the HAL APIs for handling +// device IO control registers. +// +// Usage: +// #include <cyg/hal/hal_io.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_io.h> + +//----------------------------------------------------------------------------- +// IO Register address. +// This type is for recording the address of an IO register. + +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; + +//----------------------------------------------------------------------------- +// HAL IO macros. +#ifndef HAL_IO_MACROS_DEFINED + +//----------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + +#define HAL_READ_UINT8( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_BYTE *)(_register_))) + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + (*((volatile CYG_BYTE *)(_register_)) = (_value_)) + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ +} + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ +} + + +//----------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + +#define HAL_READ_UINT16( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD16 *)(_register_))) + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + (*((volatile CYG_WORD16 *)(_register_)) = (_value_)) + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ +} + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ +} + +//----------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD32 *)(_register_))) + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + (*((volatile CYG_WORD32 *)(_register_)) = (_value_)) + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ +} + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ +{ \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ +} + +#define HAL_IO_MACROS_DEFINED + +#endif + + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_HAL_IO_H +// End of hal_io.h diff --git a/ecos/packages/hal/calmrisc32/arch/current/src/calm32-stub.c b/ecos/packages/hal/calmrisc32/arch/current/src/calm32-stub.c new file mode 100644 index 0000000..959164d --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/src/calm32-stub.c @@ -0,0 +1,296 @@ +//======================================================================== +// +// calm32-stub.h +// +// Helper functions for stub, generic to all CalmRISC32 processors +// +//======================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Red Hat, msalter +// Contributors: Red Hat, msalter +// Date: 2001-02-12 +// Purpose: +// Description: Helper functions for stub, generic to CalmRISC32 processors +// Usage: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#include <stddef.h> + +#include <pkgconf/hal.h> + +#ifdef CYGPKG_REDBOOT +#include <pkgconf/redboot.h> +#endif + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/hal/hal_stub.h> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> + +typedef cyg_uint16 t_inst; + +/*---------------------------------------------------------------------- + * Asynchronous interrupt support + */ + +static struct +{ + t_inst *targetAddr; + t_inst savedInstr; +} asyncBuffer; + +/* Called to asynchronously interrupt a running program. + Must be passed address of instruction interrupted. + This is typically called in response to a debug port + receive interrupt. +*/ + +void +install_async_breakpoint(void *pc) +{ + asyncBuffer.targetAddr = pc; + asyncBuffer.savedInstr = *(t_inst *)pc; + *(t_inst *)pc = *(t_inst *)_breakinst; + __instruction_cache(CACHE_FLUSH); + __data_cache(CACHE_FLUSH); +} + +/*--------------------------------------------------------------------*/ +/* Given a trap value TRAP, return the corresponding signal. */ + +int __computeSignal (unsigned int trap_number) +{ + switch (trap_number) { + case CYGNUM_HAL_VECTOR_FIQ: + case CYGNUM_HAL_VECTOR_IRQ: + return SIGINT; + case CYGNUM_HAL_VECTOR_IABRT: + case CYGNUM_HAL_VECTOR_DABRT: + return SIGBUS; + } + return SIGTRAP; +} + +/* Return the trap number corresponding to the last-taken trap. */ + +int __get_trap_number (void) +{ + // The vector is not not part of the GDB register set so get it + // directly from the save context. + return _hal_registers->vector; +} + +#if defined(CYGSEM_REDBOOT_BSP_SYSCALLS) +int __is_bsp_syscall(void) +{ + return __get_trap_number() >= CYGNUM_HAL_VECTOR_SWI; +} +#endif + +/* Set the current pc register value based on current vector. */ + +void set_pc (target_register_t pc) +{ + put_register (REG_PC, pc); + switch (__get_trap_number()) { + case CYGNUM_HAL_VECTOR_SWI: + put_register (REG_SPC_SWI, pc); + break; + case CYGNUM_HAL_VECTOR_FIQ: + put_register (REG_SPC_FIQ, pc); + break; + case CYGNUM_HAL_VECTOR_IRQ: + put_register (REG_SPC_IRQ, pc); + break; + default: + put_register (REG_SPC_EXPT, pc); + break; + } +} + +/* Get the current pc register value based on current vector. */ + +target_register_t get_pc(void) +{ + switch (__get_trap_number()) { + case CYGNUM_HAL_VECTOR_SWI: + return get_register (REG_SPC_SWI); + case CYGNUM_HAL_VECTOR_FIQ: + return get_register (REG_SPC_FIQ); + case CYGNUM_HAL_VECTOR_IRQ: + return get_register (REG_SPC_IRQ); + default: + break; + } + return get_register (REG_SPC_EXPT); +} + +int __sp_regnum(void) +{ + target_register_t sr = get_register(REG_SR); + + if ((sr & CYGARC_SR_PM) == 0 || (sr & CYGARC_SR_BS) == 0) + return REG_B0R15; + return REG_B1R15; +} + +/*---------------------------------------------------------------------- + * Single-step support + */ + +/* Set things up so that the next user resume will execute one instruction. + This may be done by setting breakpoints or setting a single step flag + in the saved user registers, for example. */ + +void __single_step (void) +{ + put_register(REG_SR, get_register(REG_SR) | CYGARC_SR_TE); +} + + +/* Clear the single-step state. */ + +void __clear_single_step (void) +{ + put_register(REG_SR, get_register(REG_SR) & ~CYGARC_SR_TE); +} + + +void __install_breakpoints () +{ + /* Install the breakpoints in the breakpoint list */ + __install_breakpoint_list(); +} + +void __clear_breakpoints (void) +{ + __clear_breakpoint_list(); +} + + +/* If the breakpoint we hit is in the breakpoint() instruction, return a + non-zero value. */ + +int +__is_breakpoint_function () +{ + return get_pc() == (target_register_t)(unsigned long)&_breakinst; +} + + +/* Skip the current instruction. Since this is only called by the + stub when the PC points to a breakpoint or trap instruction, + we can safely just skip 2. */ + +void __skipinst (void) +{ + set_pc(get_pc() + 2); +} + +int __is_prog_addr(unsigned long long addr) +{ + return addr >= 0x100000000ULL; +} + +char *__addr_to_ptr(unsigned long long addr) +{ + return (char *)((unsigned)(addr & 0xffffffff)); +} + +unsigned short __read_prog_uint16(void *addr) +{ + unsigned val; + asm("ldch %0, @%1" : "=r"(val) : "r"(addr) ); + return val; +} + +unsigned char __read_prog_uint8(void *addr) +{ + unsigned short s; + int is_odd = ((unsigned)addr & 1) == 1; + + s = __read_prog_uint16((void *)((unsigned)addr & ~1)); + if (is_odd) + return s & 0xff; + else + return (s >> 8) & 0xff; +} + +unsigned int __read_prog_uint32(void *addr) +{ + unsigned int u; + + u = __read_prog_uint16(addr) << 16; + u |= __read_prog_uint16((void *)((unsigned)addr + 2)); + + return u; +} + +void __write_prog_uint16(void *addr, unsigned short val) +{ + hal_plf_write_prog_halfword((unsigned)addr, val); +} + +void __write_prog_uint32(void *addr, unsigned int val) +{ + hal_plf_write_prog_halfword((unsigned)addr, (val >> 16) & 0xffff); + hal_plf_write_prog_halfword((unsigned)addr + 2, val & 0xffff); +} + +void __write_prog_uint8(void *addr, unsigned char val) +{ + unsigned short s; + int is_odd = ((unsigned)addr & 1) == 1; + + s = __read_prog_uint16((void *)((unsigned)addr & ~1)); + + if (is_odd) + s = (s & 0xff00) | val; + else + s = (s & 0xff) | (val << 8); + + hal_plf_write_prog_halfword((unsigned)addr & ~1, s); +} + + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS diff --git a/ecos/packages/hal/calmrisc32/arch/current/src/context.S b/ecos/packages/hal/calmrisc32/arch/current/src/context.S new file mode 100644 index 0000000..2da235f --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/src/context.S @@ -0,0 +1,152 @@ +##=============================================================================## +## context.S +## +## CalmRISC32 context switch code +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): msalter +## Contributors: msalter +## Date: 2001-02-12 +## Purpose: CalmRISC32 context switch code +## Description: This file contains implementations of the thread context +## switch routines. It also contains the longjmp() and setjmp() +## routines. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/arch.inc> + +#------------------------------------------------------------------------------ +# hal_thread_switch_context +# Switch thread contexts +# A0 = address of sp of next thread to execute +# A1 = address of sp save location of current thread + + .global hal_thread_switch_context +hal_thread_switch_context: + // FIXME + # Now load the destination thread by dropping through + # to hal_thread_load_context + +#------------------------------------------------------------------------------ +# hal_thread_load_context +# Load thread context +# A0 = address of sp of next thread to execute +# Note that this function is also the second half of hal_thread_switch_context +# and is simply dropped into from it. + + .global hal_thread_load_context +hal_thread_load_context: + // FIXME + +#------------------------------------------------------------------------------ +# HAL longjmp, setjmp implementations +# hal_setjmp saves only callee save registers into given buffer +# Note: These definitions are repeated in hal_arch.h. If changes are required +# remember to update both sets. + +#define CYGARC_JMP_BUF_R0 0 +#define CYGARC_JMP_BUF_R1 1 +#define CYGARC_JMP_BUF_R2 2 +#define CYGARC_JMP_BUF_R3 3 +#define CYGARC_JMP_BUF_R4 4 +#define CYGARC_JMP_BUF_R5 5 +#define CYGARC_JMP_BUF_R6 6 +#define CYGARC_JMP_BUF_R7 7 +#define CYGARC_JMP_BUF_R12 8 +#define CYGARC_JMP_BUF_R13 9 +#define CYGARC_JMP_BUF_R14 10 +#define CYGARC_JMP_BUF_R15 11 + +#define CYGARC_JMP_BUF_SIZE 48 + +// FIXME: The follwing restricts us to using only 32 bit registers +// in jump buffers. If/when we move to a full 64 bit architecture, +// this will need to change, as will the instructions that we use to +// save and restore them. + +#define jmpbuf_regsize 4 + + .globl hal_setjmp +hal_setjmp: + ld r8, r0 + ldw @[r8+0], r0 + ldw @[r8+4], r1 + ldw @[r8+8], r2 + ldw @[r8+12], r3 + ldw @[r8+16], r4 + ldw @[r8+20], r5 + ldw @[r8+24], r6 + ldw @[r8+28], r7 + ldw @[r8+32], r12 + ldw @[r8+36], r13 + ldw @[r8+40], r14 + ldw @[r8+44], sp + + jmpd r14 + ldw r0, #0 + + .globl hal_longjmp +hal_longjmp: + ld r9, r0 + ld r8, r1 + ldw sp, @[r9+44] + ldw r14, @[r9+40] + ldw r13, @[r9+36] + ldw r12, @[r9+32] + ldw r7, @[r9+28] + ldw r6, @[r9+24] + ldw r5, @[r9+20] + ldw r4, @[r9+16] + ldw r3, @[r9+12] + ldw r2, @[r9+8] + ldw r1, @[r9+4] + # Value to return is in r8. If zero, return 1 + ld r0, r8 + cmp eq r0, #0 + brf 0f + ldw r0, #1 + 0: + jmpd r14 + nop + + +#------------------------------------------------------------------------------ +# end of context.S diff --git a/ecos/packages/hal/calmrisc32/arch/current/src/hal_misc.c b/ecos/packages/hal/calmrisc32/arch/current/src/hal_misc.c new file mode 100644 index 0000000..0082120 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/src/hal_misc.c @@ -0,0 +1,323 @@ +//========================================================================== +// +// hal_misc.c +// +// HAL miscellaneous functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour +// Date: 1999-01-21 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/hal_arch.h> // architectural definitions + +#include <cyg/hal/hal_intr.h> // Interrupt handling + +#include <cyg/hal/hal_cache.h> // Cache handling + +/*------------------------------------------------------------------------*/ +/* If required, define a variable to store the clock period. */ + +#ifdef CYGHWR_HAL_CLOCK_PERIOD_DEFINED + +CYG_WORD32 cyg_hal_clock_period; + +#endif + +/*------------------------------------------------------------------------*/ +/* First level C exception handler. */ + +externC void __handle_exception (void); + +externC HAL_SavedRegisters *_hal_registers; + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +externC void* volatile __mem_fault_handler; +#endif + +externC cyg_uint32 cyg_hal_exception_handler(HAL_SavedRegisters *regs) +{ + int vec = regs->vector; + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + + // If we caught an exception inside the stubs, see if we were expecting it + // and if so jump to the saved address + if (__mem_fault_handler) { + switch (vec) { + case CYGNUM_HAL_VECTOR_SWI: + regs->spc_swi = (CYG_ADDRWORD)__mem_fault_handler; + break; + case CYGNUM_HAL_VECTOR_FIQ: + regs->spc_fiq = (CYG_ADDRWORD)__mem_fault_handler; + break; + case CYGNUM_HAL_VECTOR_IRQ: + regs->spc_irq = (CYG_ADDRWORD)__mem_fault_handler; + break; + default: + regs->spc_expt = (CYG_ADDRWORD)__mem_fault_handler; + break; + } + return 0; // Caught an exception inside stubs + } + + // Set the pointer to the registers of the current exception + // context. At entry the GDB stub will expand the + // HAL_SavedRegisters structure into a (bigger) register array. + _hal_registers = regs; + __handle_exception(); + +#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && defined(CYGPKG_HAL_EXCEPTIONS) + + // We should decode the vector and pass a more appropriate + // value as the second argument. For now we simply pass a + // pointer to the saved registers. We should also divert + // breakpoint and other debug vectors into the debug stubs. + + cyg_hal_deliver_exception( vec, (CYG_ADDRWORD)regs ); + +#else + + CYG_FAIL("Exception!!!"); + +#endif + return 0; +} + +/*------------------------------------------------------------------------*/ +/* default ISR */ + +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ +#if defined(CYGDBG_HAL_CALM32_DEBUG_GDB_CTRLC_SUPPORT) && \ + defined(CYGHWR_HAL_GDB_PORT_VECTOR) && \ + defined(HAL_CTRLC_ISR) + +#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN + if( vector == CYGHWR_HAL_GDB_PORT_VECTOR ) +#endif + { + cyg_uint32 result = HAL_CTRLC_ISR( vector, data ); + if( result != 0 ) return result; + } + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) +#if defined(HAL_DIAG_IRQ_CHECK) + { + cyg_uint32 ret; + /* let ROM monitor handle unexpected interrupts */ + HAL_DIAG_IRQ_CHECK(vector, ret); + if (ret<=0) + return ret; + } +#endif // def HAL_DIAG_IRQ_CHECK +#endif // def CYGSEM_HAL_USE_ROM_MONITOR_CygMon +#endif + + CYG_TRACE1(true, "Interrupt: %d", vector); + CYG_FAIL("Spurious Interrupt!!!"); + return 0; +} + +#else // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + +externC cyg_uint32 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ +#if defined(CYGDBG_HAL_CALM32_DEBUG_GDB_CTRLC_SUPPORT) && \ + defined(CYGHWR_HAL_GDB_PORT_VECTOR) && \ + defined(HAL_CTRLC_ISR) + +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) +#if defined(HAL_DIAG_IRQ_CHECK) + { + cyg_uint32 ret; + /* let ROM monitor handle unexpected interrupts */ + HAL_DIAG_IRQ_CHECK(vector, ret); + if (ret<=0) + return ret; + } +#endif // def HAL_DIAG_IRQ_CHECK +#endif // def CYGSEM_HAL_USE_ROM_MONITOR_CygMon +#endif + + return 0; +} + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + +/*------------------------------------------------------------------------*/ +/* data copy and bss zero functions */ + +typedef void (CYG_SYM_ADDRESS)(void); + +// All these must use this type of address to stop them being given relocations +// relative to $gp (i.e. assuming they would be in .sdata) +extern CYG_SYM_ADDRESS __ram_data_start; +extern CYG_SYM_ADDRESS __ram_data_end; +extern CYG_SYM_ADDRESS __rom_data_start; + +#ifdef CYG_HAL_STARTUP_ROM +void hal_copy_data(void) +{ + short *p = (short *)&__ram_data_start; + short *q = (short *)&__rom_data_start; + short x; + + while( p != (short *)&__ram_data_end ) { + asm volatile( "ldch %0,@%1\n" : "=r"(x) : "r"(q) ); + *p++ = x; + q++; + } +} +#endif + +extern CYG_SYM_ADDRESS __bss_start; +extern CYG_SYM_ADDRESS __bss_end; + +void hal_zero_bss(void) +{ + short *p = (short *)&__bss_start; + + while( p != (short *)&__bss_end ) + *p++ = 0; +} + +/*------------------------------------------------------------------------*/ + +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG +cyg_bool cyg_hal_stop_constructors; +#endif + +typedef void (*pfunc) (void); +extern pfunc __CTOR_LIST__[]; +extern pfunc __CTOR_END__[]; + +void +cyg_hal_invoke_constructors(void) +{ +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + static pfunc *p = &__CTOR_END__[-1]; + + cyg_hal_stop_constructors = 0; + for (; p >= __CTOR_LIST__; p--) { + (*p) (); + if (cyg_hal_stop_constructors) { + p--; + break; + } + } +#else + pfunc *p; + + for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) + (*p) (); +#endif + +} // cyg_hal_invoke_constructors() + +/*------------------------------------------------------------------------*/ +/* Determine the index of the ls bit of the supplied mask. */ + +cyg_uint32 hal_lsbit_index(cyg_uint32 mask) +{ + cyg_uint32 n = mask; + + static const signed char tab[64] = + { -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10, + 4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11, + 5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0, + 0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0 + }; + + n &= ~(n-1UL); + n = (n<<16)-n; + n = (n<<6)+n; + n = (n<<4)+n; + + return tab[n>>26]; +} + +/*------------------------------------------------------------------------*/ +/* Determine the index of the ms bit of the supplied mask. */ + +cyg_uint32 hal_msbit_index(cyg_uint32 mask) +{ + cyg_uint32 x = mask; + cyg_uint32 w; + + /* Phase 1: make word with all ones from that one to the right */ + x |= x >> 16; + x |= x >> 8; + x |= x >> 4; + x |= x >> 2; + x |= x >> 1; + + /* Phase 2: calculate number of "1" bits in the word */ + w = (x & 0x55555555) + ((x >> 1) & 0x55555555); + w = (w & 0x33333333) + ((w >> 2) & 0x33333333); + w = w + (w >> 4); + w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F); + return (cyg_uint32)((w + (w >> 16)) & 0xFF) - 1; + +} + +/*------------------------------------------------------------------------*/ +/* Idle thread action */ + +#include <cyg/infra/diag.h> + +void hal_idle_thread_action( cyg_uint32 count ) +{ +} + +/*------------------------------------------------------------------------*/ +/* End of hal_misc.c */ diff --git a/ecos/packages/hal/calmrisc32/arch/current/src/hal_syscall.c b/ecos/packages/hal/calmrisc32/arch/current/src/hal_syscall.c new file mode 100644 index 0000000..b43847b --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/src/hal_syscall.c @@ -0,0 +1,119 @@ +//============================================================================= +// +// hal_syscall.c +// +// +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors:msalter +// Date: 2000-11-5 +// Purpose: +// Description: +// +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#ifdef CYGPKG_REDBOOT +#include <pkgconf/redboot.h> +#endif + +#if defined(CYGSEM_REDBOOT_BSP_SYSCALLS) + +#include <cyg/hal/hal_stub.h> // Our header +#include <cyg/hal/hal_arch.h> // HAL_BREAKINST +#include <cyg/hal/hal_cache.h> // HAL_xCACHE_x +#include <cyg/hal/hal_intr.h> // interrupt disable/restore + +#include <cyg/hal/hal_if.h> // ROM calling interface +#include <cyg/hal/hal_misc.h> // Helper functions + +extern CYG_ADDRWORD __do_syscall(CYG_ADDRWORD func, // syscall function number + CYG_ADDRWORD arg1, CYG_ADDRWORD arg2, // up to four args. + CYG_ADDRWORD arg3, CYG_ADDRWORD arg4, + CYG_ADDRWORD *retval, // syscall return value + CYG_ADDRWORD *sig); // signal to return (or 0) + +#define SYS_exit 1 +#define SYS_interrupt 1000 + +int +hal_syscall_handler(void) +{ + CYG_ADDRWORD func, arg1, arg2, arg3, arg4; + CYG_ADDRWORD err, sig; + int retreg; + target_register_t sr = get_register(REG_SR); + + if ((sr & CYGARC_SR_PM) == 0 || (sr & CYGARC_SR_BS) == 0) { + // bank zero regs + func = get_register(REG_B0R0); + arg1 = get_register(REG_B0R1); + arg2 = get_register(REG_B0R2); + arg3 = get_register(REG_B0R3); + arg4 = 0; + retreg = REG_B0R0; + } else { + func = get_register(REG_B1R0); + arg1 = get_register(REG_B1R1); + arg2 = get_register(REG_B1R2); + arg3 = get_register(REG_B1R3); + retreg = REG_B1R0; + } + + set_pc(get_pc()+2); + + if (func == SYS_interrupt) { + // A console interrupt landed us here. + // Invoke the debug agent so as to cause a SIGINT. + return SIGINT; + } + + if (__do_syscall(func, arg1, arg2, arg3, arg4, &err, &sig)) { + put_register(retreg, err); + return (int)sig; + } + + return SIGTRAP; +} + +#endif // CYGSEM_REDBOOT_BSP_SYSCALLS diff --git a/ecos/packages/hal/calmrisc32/arch/current/src/vectors.S b/ecos/packages/hal/calmrisc32/arch/current/src/vectors.S new file mode 100644 index 0000000..c0fa106 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/arch/current/src/vectors.S @@ -0,0 +1,674 @@ +##============================================================================= +## +## vectors.S +## +## CalmRISC32 exception vectors +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): msalter +## Contributors: msalter +## Date: 2001-02-12 +## Purpose: CalmRISC32 exception vectors +## Description: This file defines the code placed into the exception +## vectors. It also contains the first level default VSRs +## that save and restore state for both exceptions and +## interrupts. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_calm32.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#else +# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT +# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +#endif + +#include <cyg/hal/arch.inc> +#include <cyg/hal/hal_arch.h> + + .macro txreg reg + 99: + cld r0,fr29 + cmp eq r0,#0 + brfd 99b + nop + cld fr30,\reg + ld r0,#1 + cld fr29,r0 + .endm + + .extern cyg_instrument + +##----------------------------------------------------------------------------- +## Hardware supplied vectors + + .macro cpu_vector vsr_nr + setsr bs + clrsr rs0 + clrsr rs1 + nop + push r8 + brad __exc_trampoline + ld r8,#\vsr_nr + .endm + +##========================================================================== +## Hardware exception vectors. +## + .section ".vectors","ax" + .global reset_vector +reset_vector: + ldw r0,#_start + jmpd r0 + nop + + # 0x20 - FIQ + .p2align 5 + cpu_vector 0 + + # 0x40 - IRQ + .p2align 5 + cpu_vector 1 + + # 0x50 - COP + .p2align 4 + cpu_vector 2 + + # 0x60 - DABRT + .p2align 4 + cpu_vector 3 + + # 0x70 - IABRT + .p2align 4 + cpu_vector 4 + + # 0x80 - PRIV + .p2align 4 + cpu_vector 5 + + # 0xA0 - UNIMPL + .p2align 5 + cpu_vector 6 + + # 0xC0 - TRACE + .p2align 5 + cpu_vector 7 + + # 0x100 - SWI 0 + .p2align 6 + cpu_vector 8 + + # SWI 1 + .p2align 4 + cpu_vector 8 + + # SWI 2 + .p2align 4 + cpu_vector 8 + + # SWI 3 + .p2align 4 + cpu_vector 8 + + # SWI 4 + .p2align 4 + cpu_vector 8 + + # SWI 5 + .p2align 4 + cpu_vector 8 + + # SWI 6 + .p2align 4 + cpu_vector 8 + + # SWI 7 + .p2align 4 + cpu_vector 8 + + # SWI 8 + .p2align 4 + cpu_vector 8 + + # SWI 9 + .p2align 4 + cpu_vector 8 + + # SWI 10 + .p2align 4 + cpu_vector 8 + + # SWI 11 + .p2align 4 + cpu_vector 8 + + # SWI 12 + .p2align 4 + cpu_vector 8 + + # SWI 13 + .p2align 4 + cpu_vector 8 + + # SWI 14 + .p2align 4 + cpu_vector 8 + + # SWI 15 + .p2align 4 + cpu_vector 8 + +__exc_trampoline: + push r8 // vsr number + sl2 r8 // offset into vsr table + ldw r8,@[r8 + 0] + jmpd r8 + pop r8 + +##----------------------------------------------------------------------------- +## Startup code + + .text + +FUNC_START _start + # default vector table + ld r0,#0 + ld vbr,r0 + + # ensure privileged mode with all bank1 register view + setsr pm + setsr bs + clrsr rs0 + clrsr rs1 + + # Initialize hardware + hal_cpu_init + hal_diag_init + hal_memc_init + hal_cache_init + hal_timer_init + + # load initial stack pointer + ldw sp,#__startup_stack + + clrsr bs + nop + ldw sp,#__user_stack + setsr bs + nop + + hal_mon_init + +#ifdef CYG_HAL_STARTUP_ROM + # Copy data from ROM to RAM + + .extern hal_copy_data + ldw r0,#hal_copy_data + jsrd r0 + nop +#endif + + # Zero BSS + + .extern hal_zero_bss + ldw r0,#hal_zero_bss + jsrd r0 + nop + + # Call variant and platform HAL + # initialization routines. + + .extern hal_variant_init + ldw r0,#hal_variant_init + jsrd r0 + nop + + .extern hal_platform_init + ldw r0,#hal_platform_init + jsrd r0 + nop + + # Call constructors + .extern cyg_hal_invoke_constructors + ldw r0,#cyg_hal_invoke_constructors + jsrd r0 + nop + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + .extern initialize_stub + ldw r0,#initialize_stub + jsrd r0 + nop +#endif + +#if defined(CYGDBG_HAL_CALM32_DEBUG_GDB_CTRLC_SUPPORT) + .extern hal_ctrlc_isr_init + ldw r0,#hal_ctrlc_isr_init + jsrd r0 + nop +#endif + + # Call cyg_start + + .extern cyg_start +#if 0 + clrsr pm + nop + clrsr bs + nop +#endif + ld fp,sp + + ldw lr,#_start + ldw r0,#cyg_start + jmpd r0 + nop +FUNC_END _start + + + .macro switch_stack_and_save_regs tmpvar + // save vector number temporarily + push r9 + ldw r9,#\tmpvar + ldw @[r9 + 0],r8 + pop r9 + + // Make sure we use the gdb stack + ldw r8,#__GDB_stack + cmpu gt sp,r8 + brtd 0f + nop + ldw r8,#__GDB_stack_base + cmpu gt sp,r8 + brtd 1f + nop + 0: + // need to switch stack + ld r8,sp + add r8,#4 + ldw sp,#__GDB_stack + push r8 + push r14 + push r13 + push r12 + sub r8,#4 + brad 2f + ldw r8,@[r8+0] + 1: + // already using gdb stack + pop r8 + // save bank 1 regs + push q3 + 2: + // save rest of bank1 regs + push q2 + push q1 + push q0 + + // save bank 0 regs + setsr rs1 + nop + push q1 + push q0 + clrsr rs1 + setsr rs0 + nop + push q1 + push q0 + clrsr rs0 + nop + // save special regs + ld r0,ssr_expt + push r0 + ld r0,ssr_swi + push r0 + ld r0,ssr_fiq + push r0 + ld r0,ssr_irq + push r0 + ld r0,spc_expt + push r0 + ld r0,spc_swi + push r0 + ld r0,spc_fiq + push r0 + ld r0,spc_irq + push r0 + ld r0,vbr + push r0 + + ldw r8,#\tmpvar + ldw r8,@[r8+0] + push r8 + .endm + + .macro restore_regs + // discard vector + pop r0 + // restore special regs + pop r0 + ld vbr,r0 + pop r0 + ld spc_irq,r0 + pop r0 + ld spc_fiq,r0 + pop r0 + ld spc_swi,r0 + pop r0 + ld spc_expt,r0 + pop r0 + ld ssr_irq,r0 + pop r0 + ld ssr_fiq,r0 + pop r0 + ld ssr_swi,r0 + pop r0 + ld ssr_expt,r0 + // restore bank 0 regs + setsr rs1 + nop + pop q0 + pop q1 + clrsr rs1 + setsr rs0 + nop + pop q0 + pop q1 + clrsr rs0 + nop + // restore bank 1 regs + pop q0 + pop q1 + pop q2 + pop q3 + .endm + + +##----------------------------------------------------------------------------- +## Default exception VSR. +## Saves machine state and calls external handling code. +## On entry, the original R8 has been pushed on the stack and R8 now +## contains the vector number. + +FUNC_START __default_exception_vsr + + switch_stack_and_save_regs __expt_temp + + // call exception handler + ldw r8,#cyg_hal_exception_handler + jsrd r8 + ld r0,sp + + restore_regs + + ret_expt + nop + +FUNC_END __default_exception_vsr + +##----------------------------------------------------------------------------- +## Default swi VSR. +## Saves machine state and calls external handling code. +## On entry, the original R8 has been pushed on the stack and R8 now +## contains the vector number. + +FUNC_START __default_swi_vsr + + switch_stack_and_save_regs __swi_temp + + // call exception handler + ldw r8,#cyg_hal_exception_handler + jsrd r8 + ld r0,sp + + restore_regs + + ret_swi + nop + +FUNC_END __default_swi_vsr + +##------------------------------------------------------------------------------ +## Default interrupt VSR. +## Saves machine state and calls appropriate ISR. When done, calls +## interrupt_end() to finish up and possibly reschedule. + +FUNC_START __default_fiq_vsr + switch_stack_and_save_regs __fiq_temp + + ldw r8,#hal_interrupt_data + ldw r1,@[r8 + 0] + ldw r8,#hal_interrupt_handlers + ldw r8,@[r8 + 0] + + // call fiq handler + jsrd r8 + ld r0,#0 + + restore_regs + + ret_fiq + nop +FUNC_END __default_fiq_vsr + +FUNC_START __default_irq_vsr + switch_stack_and_save_regs __irq_temp + + ldw r8,#hal_interrupt_data + ldw r1,@[r8 + 4] + ldw r8,#hal_interrupt_handlers + ldw r8,@[r8 + 4] + + // call fiq handler + jsrd r8 + ld r0,#1 + + restore_regs + + ret_irq + nop +FUNC_END __default_irq_vsr + +##----------------------------------------------------------------------------- +## Execute pending DSRs on the interrupt stack with interrupts enabled. +## Note: this can only be called from code running on a thread stack + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + .extern cyg_interrupt_call_pending_DSRs + +FUNC_START hal_interrupt_stack_call_pending_DSRs +FUNC_END hal_interrupt_stack_call_pending_DSRs +#endif + +##----------------------------------------------------------------------------- +## Short circuit in case any code tries to use "__gccmain()" + +FUNC_START __gccmain + jmpd lr + nop +FUNC_END __gccmain + +##----------------------------------------------------------------------------- +## Interrupt Stack. +## Used during intialization and for executing ISRs. + + .section ".bss" + + .balign 16 + .global cyg_interrupt_stack_base +cyg_interrupt_stack_base: +__interrupt_stack_base: + .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + .byte 0 + .endr + .balign 16 + .global cyg_interrupt_stack +cyg_interrupt_stack: +__interrupt_stack: + + .long 0 + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + .balign 16 +__GDB_stack_base: + .rept 0x400 + .byte 0 + .endr +__GDB_stack: + .long 0 +#endif + .balign 16 +__startup_stack_base: +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + .rept 512 +#else + .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +#endif + .byte 0 + .endr + .balign 16 +__startup_stack: + .long 0 + + .balign 16 +__user_stack_base: +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + .rept 512 +#else + .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +#endif + .byte 0 + .endr + .balign 16 +__user_stack: + .long 0 + +__expt_temp: + .long 0 +__swi_temp: + .long 0 +__irq_temp: + .long 0 +__fiq_temp: + .long 0 + + +##----------------------------------------------------------------------------- +## VSR table. +## The main interrupt code indirects through here to find the VSR +## to execute for each architecture defined interrupt. +## This is only used for simulated targets, on real targets a fixed location VSR +## table is now allocated at 0x80000100. + +#ifndef CYG_HAL_CALM32_VSR_TABLE_DEFINED + +## .section ".vsr_table","a" + + .data + + .globl hal_vsr_table +hal_vsr_table: + .long __default_fiq_vsr // FIQ + .long __default_irq_vsr // IRQ + .long __default_exception_vsr // COP + .long __default_exception_vsr // DABRT + .long __default_exception_vsr // IABRT + .long __default_exception_vsr // PRIV + .long __default_exception_vsr // UNIMPL + .long __default_exception_vsr // TRACE + .long __default_swi_vsr // SWI +#endif + + .balign 16 +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + ## Vectors used to communicate between eCos and ROM environments + .globl hal_virtual_vector_table +hal_virtual_vector_table: + .rept 64 + .long 0 + .endr +#endif + +#------------------------------------------------------------------------------ +# Interrupt vector tables. +# These tables contain the isr, data and object pointers used to deliver +# interrupts to user code. +# hal_interrupt_level contains the interrupt level set by +# HAL_INTERRUPT_CONFIGURE(). +# This is a default set that provide support only for the single external +# interrupt. Platforms or boards are expected to define their own versions +# of these if they have their own interrupt mappings. + +#ifndef CYG_HAL_CALM32_ISR_TABLES_DEFINED + + .extern hal_default_isr + + .data + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .long hal_default_isr + .long hal_default_isr + + + .globl hal_interrupt_data +hal_interrupt_data: + .long 0 + .long 0 + + .globl hal_interrupt_objects +hal_interrupt_objects: + .long 0 + .long 0 +#endif + + .data + .globl __break_inst_in_data +__break_inst_in_data: + .short 0x80e0 + + +##----------------------------------------------------------------------------- +## end of vectors.S + + diff --git a/ecos/packages/hal/calmrisc32/ceb/current/ChangeLog b/ecos/packages/hal/calmrisc32/ceb/current/ChangeLog new file mode 100644 index 0000000..afd5ec7 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/ChangeLog @@ -0,0 +1,37 @@ +2002-08-06 Gary Thomas <gary@chez-thomas.org> +2002-08-06 Motoya Kurotsu <kurotsu@allied-telesis.co.jp> + + * src/ser.c: I/O channel data can't be constant - contains + timeout information which can be changed. + +2001-03-26 Mark Salter <msalter@redhat.com> + + * src/plf_misc.c (hal_delay_us): Fix loop count for better accuracy. + + * src/platform.S: Remove unneeded ceb_program_new_stack. + + * cdl/hal_calm32_ceb.cdl: Remove HAL_ARCH_PROGRAM_NEW_STACK. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/calmrisc32/ceb/current/cdl/hal_calm32_ceb.cdl b/ecos/packages/hal/calmrisc32/ceb/current/cdl/hal_calm32_ceb.cdl new file mode 100644 index 0000000..c0e2c8e --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/cdl/hal_calm32_ceb.cdl @@ -0,0 +1,269 @@ +# ==================================================================== +# +# hal_calm32_ceb.cdl +# +# CalmRISC32 Core Eval Board HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Original data: bartv +# Contributors: +# Date: 2001-02-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_CALM32_CEB { + display "CalmRISC32 core evaluation board" + parent CYGPKG_HAL_CALM32 + include_dir cyg/hal + description " + The Core eval board HAL package should be used when targetting the + actual hardware." + + compile hal_diag.c platform.S plf_misc.c ser.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED + + cdl_option CYGBLD_HAL_TARGET_H { + display "Variant header" + flavor data + no_define + calculated { "<pkgconf/hal_calm32_core.h>" } + define -file system.h CYGBLD_HAL_TARGET_H + description "Variant header." + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_calm32_ceb.h>" + puts $::cdl_system_header "" + puts $::cdl_system_header "/* Make sure we get the CORE type definitions for HAL_PLATFORM_CPU */" + puts $::cdl_system_header "#include CYGBLD_HAL_TARGET_H" + puts $::cdl_system_header "#define HAL_PLATFORM_BOARD \"Core Eval Board\"" + puts $::cdl_system_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_system_header "" + } + + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM"} + default_value {"ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + Currently only ROM startup type is supported." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 57600 + default_value 57600 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 57600 + default_value 57600 + description " + This option controls the baud rate used for the GDB connection." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + parent CYGBLD_GLOBAL_OPTIONS + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + + + cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE { + display "Number of breakpoints supported by the HAL." + flavor data + default_value 25 + description " + This option determines the number of breakpoints supported by the HAL." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The Atlas board has only one serial port. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The Atlas board has only one serial port. This option + chooses which port will be used for diagnostic output." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "calm32_ceb_ram" : \ + "calm32_ceb_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_calm32_ceb_ram.ldi>" : \ + "<pkgconf/mlt_calm32_ceb_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_calm32_ceb_ram.h>" : \ + "<pkgconf/mlt_calm32_ceb_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "Generic" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for three different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"CygMon\" provides support for the Cygnus ROM Monitor. + And finally, \"GDB_stubs\" provides support when GDB stubs are + included in the ROM monitor or boot ROM." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 1 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + compile -library=libextras.a + + make -priority 325 { + <PREFIX>/bin/redboot.srec : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-all $< $(@:.srec=.img) + $(OBJCOPY) -O srec $< $@ + } + } + } + +} diff --git a/ecos/packages/hal/calmrisc32/ceb/current/include/hal_diag.h b/ecos/packages/hal/calmrisc32/ceb/current/include/hal_diag.h new file mode 100644 index 0000000..d4088af --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/include/hal_diag.h @@ -0,0 +1,94 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-11 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else // everything by steam + +/*---------------------------------------------------------------------------*/ +/* functions implemented in hal_diag.c */ + +externC void hal_diag_init(void); +externC void hal_diag_write_char(char c); +externC void hal_diag_read_char(char *c); + +/*---------------------------------------------------------------------------*/ + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +/*---------------------------------------------------------------------------*/ +// LED + +externC void hal_diag_led(int n); + +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */ +#endif /* CYGONCE_HAL_DIAG_H */ diff --git a/ecos/packages/hal/calmrisc32/ceb/current/include/pkgconf/mlt_calm32_ceb_rom.h b/ecos/packages/hal/calmrisc32/ceb/current/include/pkgconf/mlt_calm32_ceb_rom.h new file mode 100644 index 0000000..fdb2ad7 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/include/pkgconf/mlt_calm32_ceb_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Fri Oct 20 06:10:29 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x80000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x100000000) +#define CYGMEM_REGION_rom_SIZE (0x80000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x80000 - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/calmrisc32/ceb/current/include/pkgconf/mlt_calm32_ceb_rom.ldi b/ecos/packages/hal/calmrisc32/ceb/current/include/pkgconf/mlt_calm32_ceb_rom.ldi new file mode 100644 index 0000000..834b177 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/include/pkgconf/mlt_calm32_ceb_rom.ldi @@ -0,0 +1,40 @@ +// eCos memory layout - Fri Oct 20 06:10:29 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x000000, LENGTH = 0x80000 + rom : ORIGIN = 0x100000000, LENGTH = 0x80000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0x100000000, LMA_EQ_VMA) + SECTION_ROMISC (rom, ALIGN (0x40), LMA_EQ_VMA) + SECTION_RELOCS (rom, ALIGN (0x40), LMA_EQ_VMA) + SECTION_init (rom, ALIGN (0x40), LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x40), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x40), LMA_EQ_VMA) + SECTION_data (ram, 0x00000000, FOLLOWING (.fini)) + SECTION_data1 (ram, ALIGN (0x40), FOLLOWING (.data)) + SECTION_rodata (ram, ALIGN (0x40), FOLLOWING (.data1)) + SECTION_rodata1 (ram, ALIGN (0x40), FOLLOWING (.rodata)) + SECTION_eh_frame (ram, ALIGN (0x40), FOLLOWING (.rodata1)) + SECTION_gcc_except_table (ram, ALIGN (0x40), FOLLOWING (.eh_frame)) + SECTION_ctors (ram, ALIGN (0x40), FOLLOWING (.gcc_except_table)) + SECTION_dtors (ram, ALIGN (0x40), FOLLOWING (.ctors)) + SECTION_devtab (ram, ALIGN (0x40), FOLLOWING (.dtors)) + SECTION_got (ram, ALIGN (0x40), FOLLOWING (.devtab)) + SECTION_dynamic (ram, ALIGN (0x40), FOLLOWING (.got)) + SECTION_sdata (ram, ALIGN (0x40), FOLLOWING (.dynamic)) + SECTION_lit8 (ram, ALIGN (0x40), FOLLOWING (.sdata)) + SECTION_lit4 (ram, ALIGN (0x40), FOLLOWING (.lit8)) + SECTION_sbss (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x40), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/calmrisc32/ceb/current/include/platform.inc b/ecos/packages/hal/calmrisc32/ceb/current/include/platform.inc new file mode 100644 index 0000000..5edf13e --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/include/platform.inc @@ -0,0 +1,95 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## CalmRISC32 core eval board assembler header file +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): msalter +## Contributors: msalter +## Date: 2001-02-12 +## Purpose: Core eval board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the core eval board. +## Usage: +## #include <cyg/hal/platform.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <cyg/hal/calm32.inc> + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/plf_io.h> + +#define CYGPKG_HAL_RESET_VECTOR_FIRST_CODE + .macro hal_reset_vector_first_code + .endm + +#define CYGPKG_HAL_EARLY_INIT + .macro hal_early_init + .endm + +#------------------------------------------------------------------------------ +# Diagnostic macros + +#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED + + .macro hal_diag_init + .endm + + .macro hal_diag_excpt_start + .endm + + .macro hal_diag_intr_start + .endm + + .macro hal_diag_restore + .endm + +#define CYGPKG_HAL_MIPS_DIAG_DEFINED + +#endif // ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_PLATFORM_INC +# end of platform.inc diff --git a/ecos/packages/hal/calmrisc32/ceb/current/include/plf_cache.h b/ecos/packages/hal/calmrisc32/ceb/current/include/plf_cache.h new file mode 100644 index 0000000..82aa1fc --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/include/plf_cache.h @@ -0,0 +1,72 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-02-17 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/plf_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_cache.h> + +//============================================================================= + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h + diff --git a/ecos/packages/hal/calmrisc32/ceb/current/include/plf_intr.h b/ecos/packages/hal/calmrisc32/ceb/current/include/plf_intr.h new file mode 100644 index 0000000..15b16df --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/include/plf_intr.h @@ -0,0 +1,122 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Atlas Interrupt and clock support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jskov, +// gthomas, jlarmour, dmoseley +// Date: 2000-06-06 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the Atlas board. +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/plf_io.h> + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +// These are decoded via the IP bits of the cause +// register when an external interrupt is delivered. + +#define CYGNUM_HAL_INTERRUPT_IRQ 0 +#define CYGNUM_HAL_INTERRUPT_FIQ 1 + +// Min/Max ISR numbers and how many there are +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 1 +#define CYGNUM_HAL_ISR_COUNT 2 + +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +#endif + +//-------------------------------------------------------------------------- +// Interrupt controller access. + + + +//-------------------------------------------------------------------------- +// Control-C support. + +#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) + +# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_SER + +externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); + +# define HAL_CTRLC_ISR hal_ctrlc_isr + +#endif + + +//---------------------------------------------------------------------------- +// Reset. +#ifndef CYGHWR_HAL_RESET_DEFINED +#define CYGHWR_HAL_RESET_DEFINED +#define HAL_PLATFORM_RESET() + +#define HAL_PLATFORM_RESET_ENTRY 0x00000000 + +#endif // CYGHWR_HAL_RESET_DEFINED + +//--------------------------------------------------------------------------- +// Delay +#define HAL_DELAY_US(x) hal_delay_us(x) + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h diff --git a/ecos/packages/hal/calmrisc32/ceb/current/include/plf_io.h b/ecos/packages/hal/calmrisc32/ceb/current/include/plf_io.h new file mode 100644 index 0000000..de66a9d --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/include/plf_io.h @@ -0,0 +1,122 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific IO support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2001-02-12 +// Purpose: CalmRISC32 platform IO support +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_misc.h> + +// coprocessor regs +#define HAL_COP_SR_RBR 0x1c +#define HAL_COP_SR_TBR 0x1d +#define HAL_COP_TBR 0x1e +#define HAL_COP_RBR 0x1f + +#ifndef __ASSEMBLER__ + +static inline void cyg_hal_plf_write_sr_rbr(int val) +{ + asm volatile ("cld fr28,%0\n" : : "r"(val)); +} + +static inline void cyg_hal_plf_write_sr_tbr(int val) +{ + asm volatile ("cld fr29,%0\n" : : "r"(val)); +} + +static inline void cyg_hal_plf_write_tbr(int val) +{ + asm volatile ("cld fr30,%0\n" : : "r"(val)); +} + +static inline void cyg_hal_plf_write_rbr(int val) +{ + asm volatile ("cld fr31,%0\n" : : "r"(val)); +} + +static inline int cyg_hal_plf_read_sr_rbr(void) +{ + int val; + + asm volatile ("cld %0,fr28\n" : "=r"(val) : ); + return val; +} + +static inline int cyg_hal_plf_read_sr_tbr(void) +{ + int val; + + asm volatile ("cld %0,fr29\n" : "=r"(val) : ); + return val; +} + +static inline int cyg_hal_plf_read_tbr(void) +{ + int val; + + asm volatile ("cld %0,fr30\n" : "=r"(val) : ); + return val; +} + +static inline int cyg_hal_plf_read_rbr(void) +{ + int val; + + asm volatile ("cld %0,fr31\n" : "=r"(val) : ); + return val; +} +#endif + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_PLF_IO_H diff --git a/ecos/packages/hal/calmrisc32/ceb/current/include/plf_stub.h b/ecos/packages/hal/calmrisc32/ceb/current/include/plf_stub.h new file mode 100644 index 0000000..538f28e --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/include/plf_stub.h @@ -0,0 +1,93 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors:msalter +// Date: 2001-02-12 +// Purpose: Platform HAL stub support for CalmRISC32 eval boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/calm32-stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +// Syscall support. +#ifdef CYGPKG_CYGMON +// Cygmon provides syscall handling for this board +#define SIGSYSCALL SIGSYS +extern int __get_syscall_num (void); +#endif + +extern void hal_plf_write_prog_halfword(unsigned addr, unsigned short val); + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h diff --git a/ecos/packages/hal/calmrisc32/ceb/current/misc/readme.txt b/ecos/packages/hal/calmrisc32/ceb/current/misc/readme.txt new file mode 100644 index 0000000..f91f32a --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/misc/readme.txt @@ -0,0 +1,80 @@ +RedBoot for the Samsung CalmRISC32 core evaluation board +May 7th 2001 +README +======================================================================== + +This ReadMe contains instructions for running Redboot on the Samsung +calmRISC32 core evaluation board, and building RedBoot and ecosconfig. + +You will need the GNUPro calmrisc32-elf toolchain which should be +installed in /usr/cygnus. + +Overview +-------- +This implementation of RedBoot supports the calmRISC32 core evaluation board. +The core board has no communication channel and requires an MDSChip board to +provide a serial channel for host communication. The calmRISC32 is a harvard +architecture with separate 32-bit program and data addresses. The instruction +set provides no instruction for writing to program memory. The MDSChip board +firmware (called CalmBreaker) provides a pseudo register interface so that +code running on the core has access to a serial channel and a mechanism to +write to program memory. The serial channel is fixed at 57600-8-N-1 by the +firmware. The CalmBreaker firmware also provides a serial protocol which +allows a host to download a program and to start or stop the core board. + + +Downloading and running RedBoot +-------------------------------- +All storage on the core board is volatile, so RedBoot must be downloaded to +the board after every power cycle. Downloads require the use of a utility +program. The source file and build instructions for this utility are provided +in the RedBoot sources at: + + .../packages/hal/calmrisc32/ceb/current/support + +To download the RedBoot image, first press the reset button on the MDSChip +board. The green 'Run' LED on the core board should go off. Now, use the +utility to download the RedBoot image with: + + % calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf + +Note that the '-p /dev/term/b' specifies the serial port to use and will vary +from system to syetm. The download will take about two minutes. After it +finishes, start RedBoot with: + + % calmbreaker -p /dev/term/b --run + +The 'Run' LED on the core board should be on. Connecting to the MDSboard with +a terminal and typing enter should result in RedBoot reprinting the command +prompt. + +Rebuilding RedBoot +------------------ + +Assuming that the provided RedBoot source tree is located in the current +directory, the build process is: + + % export TOPDIR=`pwd` + % export ECOS_REPOSITORY=${TOPDIR}/packages + % mkdir ${TOPDIR}/build + % cd ${TOPDIR}/build + % ecosconfig new calm32_ceb redboot + % ecosconfig import ${ECOS_REPOSITORY}/hal/calmrisc32/current/misc/redboot_ROM.ecm + % ecosconfig tree + % make + + +Building ecosconfig +------------------- + +An ecosconfig binary is supplied in the bin directory, but you may wish +to build it from source. + +Detailed instructions for building the command-line tool ecosconfig +can be found in host/README. For example: + + mkdir $TEMP/redboot-build + cd $TEMP/redboot-build + $TOPDIR/host/configure --prefix=$TEMP/redboot-build --with-tcl=/usr + make + diff --git a/ecos/packages/hal/calmrisc32/ceb/current/misc/redboot_ROM.ecm b/ecos/packages/hal/calmrisc32/ceb/current/misc/redboot_ROM.ecm new file mode 100644 index 0000000..0f06b31 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/misc/redboot_ROM.ecm @@ -0,0 +1,65 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware ceb ; + template redboot ; + package -hardware CYGPKG_HAL_CALM32 current ; + package -hardware CYGPKG_HAL_CALM32_CORE current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS { + user_value 1 +}; + + diff --git a/ecos/packages/hal/calmrisc32/ceb/current/src/hal_diag.c b/ecos/packages/hal/calmrisc32/ceb/current/src/hal_diag.c new file mode 100644 index 0000000..af9970f --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/src/hal_diag.c @@ -0,0 +1,182 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, dmoseley +// Date: 1998-03-02 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/hal_intr.h> + +#include <cyg/hal/hal_io.h> + +//----------------------------------------------------------------------------- +// Select which diag channels to use + +//#define CYG_KERNEL_DIAG_LCD +#define CYG_KERNEL_DIAG_SERIAL + +/*---------------------------------------------------------------------------*/ + +void hal_diag_led(int x) +{ +} + +externC void diag_write_string (const char*); + +#ifdef CYG_KERNEL_DIAG_SERIAL +extern void cyg_hal_plf_comms_init(void); +extern void cyg_hal_plf_serial_putc(void*, cyg_uint8); +extern cyg_uint8 cyg_hal_plf_serial_getc(void*); +#endif + +void hal_diag_init(void) +{ +#if defined(CYGSEM_HAL_ROM_MONITOR) && !defined(CYG_KERNEL_DIAG_SERIAL) + // It's handy to have the LCD initialized at reset when using it + // for debugging output. + // The serial port likely doesn't work yet. Let's wait. + diag_write_string ("eCos ROM " __TIME__ "\n"); + diag_write_string (__DATE__ "\n"); +#endif + +#if defined(CYG_KERNEL_DIAG_SERIAL) + cyg_hal_plf_comms_init(); +#endif +} + +#if defined(CYG_KERNEL_DIAG_LCD) +static void hal_diag_clear_lcd(void) +{ + volatile int i = 0x20000; + while (--i) ; + + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' '); +} +#endif /* defined(CYG_KERNEL_DIAG_LCD) */ + +void hal_diag_write_char(char c) +{ +#if defined(CYG_KERNEL_DIAG_LCD) + static volatile CYG_WORD* reg = HAL_DISPLAY_ASCIIPOS0; +#endif + + unsigned long __state; + + HAL_DISABLE_INTERRUPTS(__state); + + if(c == '\n') + { +#if defined(CYG_KERNEL_DIAG_LCD) + reg = HAL_DISPLAY_ASCIIPOS0; + hal_diag_clear_lcd(); +#endif +#if defined (CYG_KERNEL_DIAG_SERIAL) + cyg_hal_plf_serial_putc(NULL, '\r'); + cyg_hal_plf_serial_putc(NULL, '\n'); +#endif + } + else if (c == '\r') + { + // Ignore '\r' + } + else + { +#if defined(CYG_KERNEL_DIAG_LCD) + if (reg == HAL_DISPLAY_ASCIIPOS0) + hal_diag_clear_lcd(); + + HAL_WRITE_UINT32(reg, c); + + // Advance to next LED position. + if (reg == HAL_DISPLAY_ASCIIPOS0) + reg = HAL_DISPLAY_ASCIIPOS1; + else if (reg == HAL_DISPLAY_ASCIIPOS1) + reg = HAL_DISPLAY_ASCIIPOS2; + else if (reg == HAL_DISPLAY_ASCIIPOS2) + reg = HAL_DISPLAY_ASCIIPOS3; + else if (reg == HAL_DISPLAY_ASCIIPOS3) + reg = HAL_DISPLAY_ASCIIPOS4; + else if (reg == HAL_DISPLAY_ASCIIPOS4) + reg = HAL_DISPLAY_ASCIIPOS5; + else if (reg == HAL_DISPLAY_ASCIIPOS5) + reg = HAL_DISPLAY_ASCIIPOS6; + else if (reg == HAL_DISPLAY_ASCIIPOS6) + reg = HAL_DISPLAY_ASCIIPOS7; + else // reg == HAL_DISPLAY_ASCIIPOS7 or UNKNOWN + reg = HAL_DISPLAY_ASCIIPOS0; +#endif +#if defined(CYG_KERNEL_DIAG_SERIAL) + cyg_hal_plf_serial_putc(NULL, c); +#endif + } + + HAL_RESTORE_INTERRUPTS(__state); +} + +void hal_diag_read_char(char* c) +{ + *c = cyg_hal_plf_serial_getc(NULL); +} + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */ diff --git a/ecos/packages/hal/calmrisc32/ceb/current/src/platform.S b/ecos/packages/hal/calmrisc32/ceb/current/src/platform.S new file mode 100644 index 0000000..f301726 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/src/platform.S @@ -0,0 +1,85 @@ +## +#============================================================================= +## platform.S +## +## CalmRISC32 CEB platform code +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): msalter +## Contributors: msalter +## Date: 2001-02-12 +## Purpose: CalmRISC32 platform code +## Description: Platform specific code for CalmRISC32 core evb +## +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/hal/arch.inc> +#include <cyg/hal/plf_io.h> +#include <cyg/hal/hal_arch.h> + +##----------------------------------------------------------------------------- + +##----------------------------------------------------------------------------- +# Platform Initialization. +# This code performs platform specific initialization. + +##----------------------------------------------------------------------------- +## MEMC initialization. +## + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + +#endif /* defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) */ + + +##----------------------------------------------------------------------------- +# This code sets up a stack for applications running on redboot + +##----------------------------------------------------------------------------- +## end of platform.S diff --git a/ecos/packages/hal/calmrisc32/ceb/current/src/plf_misc.c b/ecos/packages/hal/calmrisc32/ceb/current/src/plf_misc.c new file mode 100644 index 0000000..ace0281 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/src/plf_misc.c @@ -0,0 +1,120 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour, dmoseley, msalter +// Date: 2000-06-06 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // architectural definitions + +#include <cyg/hal/hal_intr.h> // Interrupt handling + +#include <cyg/hal/hal_cache.h> // Cache handling + +#include <cyg/hal/hal_if.h> + +/*------------------------------------------------------------------------*/ + +#if defined(CYGPKG_CYGMON) +#include CYGHWR_MEMORY_LAYOUT_H +extern unsigned long cygmon_memsize; +#endif + +void hal_platform_init(void) +{ + // Set up eCos/ROM interfaces + hal_if_init(); +} + + +/*------------------------------------------------------------------------*/ +/* Delay for some number of useconds. */ +void +hal_delay_us(int us) +{ + us /= 20; // horrible code genration right now + while (us-- > 0) ; +} + +/*------------------------------------------------------------------------*/ +/* Reset support */ + +void hal_ceb_reset(void) +{ +} + +void hal_plf_write_prog_halfword(unsigned addr, unsigned short val) +{ + unsigned short pch = addr >> 16; + unsigned short pcl = addr & 0xffff; + + while(cyg_hal_plf_read_sr_tbr() & 1); // while TXD_FULL + cyg_hal_plf_write_tbr(pch); + cyg_hal_plf_write_sr_tbr(0x03); // addr_high short + + while(cyg_hal_plf_read_sr_tbr() & 1); // while TXD_FULL + cyg_hal_plf_write_tbr(pcl); + cyg_hal_plf_write_sr_tbr(0x05); // addr_low short + + while(cyg_hal_plf_read_sr_tbr() & 1); // while TXD_FULL + cyg_hal_plf_write_tbr(val); + cyg_hal_plf_write_sr_tbr(0x07); // program data value + + while(cyg_hal_plf_read_sr_tbr() & 1); // while TXD_FULL +} + + +/*------------------------------------------------------------------------*/ +/* End of plf_misc.c */ diff --git a/ecos/packages/hal/calmrisc32/ceb/current/src/ser.c b/ecos/packages/hal/calmrisc32/ceb/current/src/ser.c new file mode 100644 index 0000000..d0bcc31 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/src/ser.c @@ -0,0 +1,292 @@ +//============================================================================= +// +// ser.c +// +// Simple driver for the MDSChip serial port +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors:msalter +// Date: 2001-02-12 +// Description: Simple driver for the MDSChip serial port +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +// We have no control over baud rate +#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600 +#define CYG_DEV_SERIAL_BAUD_DIVISOR BAUD_57600 +#endif + +#ifndef CYG_DEV_SERIAL_BAUD_DIVISOR +#error Missing/incorrect serial baud rate defined - CDL error? +#endif + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +static channel_data_t channels[1] = { + { (cyg_uint8*)0, 1000, 0} +}; + +//----------------------------------------------------------------------------- +// The minimal init, get and put functions. All by polling. + +void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + cyg_hal_plf_write_sr_rbr(0); + cyg_hal_plf_write_sr_tbr(0); + cyg_hal_plf_write_tbr(0); + cyg_hal_plf_write_rbr(0); +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch) +{ + // wait for tx rdy + while (cyg_hal_plf_read_sr_tbr() != 0) ; + + // Now, write it + cyg_hal_plf_write_tbr(__ch); + + // and set TBR + cyg_hal_plf_write_sr_tbr(1); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + if (cyg_hal_plf_read_sr_rbr() == 0) + return false; + + *ch = cyg_hal_plf_read_rbr(); + + cyg_hal_plf_write_sr_rbr(0); + + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + return ch; +} + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); +} + + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan; + cyg_bool res; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + CYGACC_CALL_IF_DELAY_US(100); + } + + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan; + int ret = 0; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + + HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + + HAL_INTERRUPT_MASK(chan->isr_vector); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + break; + case __COMMCTL_SETBAUD: + { + cyg_uint32 baud_rate; + va_list ap; + + va_start(ap, __func); + baud_rate = va_arg(ap, cyg_uint32); + va_end(ap); + + switch (baud_rate) + { + case 57600: break; + default: return -1; + } + } + break; + + case __COMMCTL_GETBAUD: + break; + default: + break; + } + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + *__ctrlc = 0; + return 0; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Disable interrupts. + HAL_INTERRUPT_MASK(channels[0].isr_vector); + + // Init channels + cyg_hal_plf_serial_init_channel((void*)&channels[0]); + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +} + +//----------------------------------------------------------------------------- +// end of ser16c550c.c + diff --git a/ecos/packages/hal/calmrisc32/ceb/current/support/README b/ecos/packages/hal/calmrisc32/ceb/current/support/README new file mode 100644 index 0000000..bc1dc00 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/support/README @@ -0,0 +1,23 @@ + +The support directory provides a tool for downloading code to the calmRISC +board. This simple application communicates over a serial line (57600-8-N-1) +with the MDSChip board which in turn controls the core eval board. + +Building the tool: + + % gcc -g -O2 calmbreaker.c -o calmbreaker + +Using the tool: + + calmbreaker [--reset] [--run] [-p serialdev] [--srec-code | --srec-data] + [-f filename] + + --reset ==> Reset the board. Stops the core. + --run ==> Start the core running at the reset vector + -p ==> Specify the serial device + --srec-code ==> Download s-records to program memory + --srec-date ==> Download s-records to data memory + -f ==> Specify s-record file. If -f is missing, use + stdin. + + diff --git a/ecos/packages/hal/calmrisc32/ceb/current/support/calmbreaker.c b/ecos/packages/hal/calmrisc32/ceb/current/support/calmbreaker.c new file mode 100644 index 0000000..dc04a63 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/ceb/current/support/calmbreaker.c @@ -0,0 +1,540 @@ +/*============================================================================= +// +// calmbreaker.c +// +// Host to CalmBreaker communication utility. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2001-03-02 +// Purpose: +// Description: Host to CalmBreaker communication utility. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <termios.h> +#include <fcntl.h> +#include <stdio.h> + +int ser_fd; // The com port +int is_risc16; + +void +tty_setup(int fd) +{ + struct termios t; + + memset(&t, 0, sizeof(struct termios)); + + t.c_oflag = 0; + t.c_lflag = 0; + + t.c_cflag &= ~(CSIZE | PARENB); + t.c_cflag |= CS8 | CREAD /*| CSTOPB*/; + t.c_cflag |= CLOCAL; // ignore modem status lines + + t.c_iflag = IGNBRK | IGNPAR /* | ISTRIP */ ; + + t.c_lflag &= ~ICANON; // non-canonical mode + t.c_lflag &= ~(ECHO|ECHOE|ECHOK|ECHOKE); + + t.c_cc[VMIN] = 0; + t.c_cc[VTIME] = 10; // 1 second timeout + + t.c_cflag &= ~CRTSCTS; + + /* set speed */ + cfsetispeed(&t, B57600); + cfsetospeed(&t, B57600); + + tcdrain(fd); + + if (tcsetattr(fd, TCSANOW, &t) < 0) + { + perror("tcssetattr"); + exit(1); + } +} + +static void +do_putc(unsigned char ch) +{ + // keep retrying until sent or an error is returned + while (write(ser_fd, &ch, 1) == 0); +} + +static int +do_getc(unsigned char *ucp) +{ + return read(ser_fd, ucp, 1); +} + +static int +wait_for_ack(void) +{ + unsigned char ch; + int i; + + // try for 5 seconds + for (i = 0; i < 5; i++) { + if (do_getc(&ch)) { + if (ch == '+') + return 1; + printf("Bad ack [0x%x]\n", ch); + } + } + printf("No ack\n"); + return 0; +} + +// Add prefix and checksum to packet and send to MDS board. +void +send_packet_noack(unsigned char *pkt, int len) +{ + unsigned char cksum = 0; + + do_putc(':'); + + while (len-- > 0) { + cksum += *pkt; + do_putc(*pkt++); + } + + do_putc(0x100 - cksum); +} + +// Add prefix and checksum to packet and send to MDS board. +void +send_packet(unsigned char *pkt, int len) +{ + send_packet_noack(pkt, len); + wait_for_ack(); +} + + + +// Send a packet of code or data (max 0xff bytes) +int +send_data_packet(int is_data, unsigned addr, unsigned char *buf, int buflen) +{ + unsigned char uc, cksum = 0; + int i; + + do_putc(':'); + + // code or data? + uc = is_data ? 0x52 : 0x51; + cksum += uc; + do_putc(uc); + + // code/data nwords? + uc = buflen >> 1; + cksum += uc; + do_putc(uc); + + // code/data address + uc = (unsigned char)(addr >> 24); + cksum += uc; + do_putc(uc); + uc = (unsigned char)(addr >> 16); + cksum += uc; + do_putc(uc); + uc = (unsigned char)(addr >> 8); + cksum += uc; + do_putc(uc); + uc = (unsigned char)addr; + cksum += uc; + do_putc(uc); + + while (buflen-- > 0) { + cksum += *buf; + do_putc(*buf++); + } + + do_putc(0x100 - cksum); + + return wait_for_ack(); +} + + +void +send_command(unsigned char uc) +{ + send_packet(&uc, 1); +} + +void +send_command_noack(unsigned char uc) +{ + send_packet_noack(&uc, 1); +} + +// Simple single-byte commands +void target_reset(void) { send_command(0x20); } +void target_singlestep(void) { send_command(0x22); } +void target_singlecycle(void) { send_command(0x23); } +void target_stop(void) { send_command(0x24); } +void target_run(void) { send_command_noack(0x25); } + +#define DOWNLOAD_CHUNK_SIZE 254 + +int +download_words(int is_data, unsigned addr, unsigned char *buf, int buflen) +{ + while (buflen >= DOWNLOAD_CHUNK_SIZE) { + if (!send_data_packet(is_data, addr, buf, DOWNLOAD_CHUNK_SIZE)) { + printf("Error downloading %d bytes of %s to 0x%x\n", + DOWNLOAD_CHUNK_SIZE, (is_data ? "data" : "code"), addr); + return 0; + } + addr += DOWNLOAD_CHUNK_SIZE; + buf += DOWNLOAD_CHUNK_SIZE; + buflen -= DOWNLOAD_CHUNK_SIZE; + } + if (buflen && !send_data_packet(is_data, addr, buf, buflen)) { + printf("Error downloading %d bytes of %s to 0x%x\n", + buflen, (is_data ? "data" : "code"), addr); + return 0; + } + return 1; +} + +static inline int +gethexnibble(FILE *fp) +{ + int ch; + + ch = getc(fp); + if (ch >= '0' && ch <= '9') + return (ch - '0'); + if (ch >= 'a' && ch <= 'f') + return (ch - 'a' + 10); + if (ch >= 'A' && ch <= 'F') + return (ch - 'A' + 10); + + if (ch == EOF) + fprintf(stderr, "Unexpected EOF\n"); + else + fprintf(stderr, "Bad hex char\n"); + + return -1; +} + + +static inline int +gethexbyte(FILE *fp) +{ + int nib; + unsigned char n; + + if ((nib = gethexnibble(fp)) < 0) + return -1; + n = nib << 4; + if ((nib = gethexnibble(fp)) < 0) + return -1; + n |= nib; + return n; +} + +static inline int +chk_cksum(FILE *fp, unsigned int cksum) +{ + int n; + + if ((n = gethexbyte(fp)) < 0) + return -1; + + cksum = ~cksum & 0xff; + + if (cksum != n) { + fprintf(stderr, "Bad cksum[%02x]\n", cksum); + return -1; + } + return 0; +} + +int +load_srec(FILE *fp, int is_data) +{ + int count, dcount, data, n, addr_bytes = 0, is_term, is_comment; + unsigned long address, cksum; + unsigned char data_buf[256]; + + is_comment = is_term = 0; + + do { + if ((n = getc(fp)) == EOF) + return 1; + } while (n != 'S'); + + switch (n = gethexnibble(fp)) { + case 0: + case 5: + is_comment = 1; + break; + + case 1: + case 2: + case 3: + addr_bytes = n + 1; + break; + + case 7: + case 8: + case 9: + is_term = 1; + addr_bytes = 11 - n; + break; + + default: + if (n < 0) + return -1; + fprintf(stderr, "Bad record type: %d\n", n); + return -1; + } + + if ((count = gethexbyte(fp)) < 0) + return -1; + + cksum = count; + + --count; // don't count chksum + + if (is_comment) { + while (count > 0) { + if ((n = gethexbyte(fp)) < 0) + return -1; + cksum += n; + --count; + } + if (chk_cksum(fp,cksum) < 0) + return -1; + return 0; + } + + address = 0; + while (count > 0 && addr_bytes) { + if ((n = gethexbyte(fp)) < 0) + return -1; + cksum += n; + address = (address << 8) | n; + --addr_bytes; + --count; + } + + if (is_risc16 && (address & 0x400000)) + address &= 0x3fffff; + + if (is_term) { + if (count || addr_bytes) { + fprintf(stderr, "Malformed record cnt[%d] abytes[%d]\n", + count, addr_bytes); + return -1; + } + if (chk_cksum(fp, cksum) == 0) { + fprintf(stderr, "Setting start address: 0x%08x\n", address); + return 1; + } + return -1; + } + + for (dcount = 0; dcount < count; dcount++) { + if ((data = gethexbyte(fp)) < 0) + return -1; + cksum += data; + data_buf[dcount] = data; + } + + if (chk_cksum(fp, cksum) < 0) + return -1; + + if (dcount & 1) + dcount++; + + if (!download_words(is_data, address, data_buf, dcount)) + return -1; + + return 0; +} + + +int +load_hex(FILE *fp, int is_data) +{ + int count, n, i; + unsigned long address; + unsigned char data_buf[256]; + + do { + if ((n = getc(fp)) == EOF) + return 1; + } while (n == '\r' || n == '\n'); + + if (n == '#') { + do { + if ((n = getc(fp)) == EOF) + return 1; + } while (n != '\r' && n != '\n'); + return 0; + } + + if (n != ':') { + fprintf(stderr, "Unrecognized HEX line start.\n"); + return -1; + } + + if ((count = gethexbyte(fp)) < 0) + return -1; + + address = 0; + for (i = 0; i < 4; i++) { + if ((n = gethexbyte(fp)) < 0) + return -1; + address = (address << 8) | n; + } + + // skip type byte + if ((n = gethexbyte(fp)) < 0) + return -1; + + for (i = 0; i < count; i++) { + if ((n = gethexbyte(fp)) < 0) + return -1; + data_buf[i] = n; + } + + // skip chksum byte + if ((n = gethexbyte(fp)) < 0) + return -1; + + if (count & 1) + ++count; + + if (!download_words(is_data, address, data_buf, count)) + return -1; + + return 0; +} + + +int +main(int argc, char *argv[]) +{ + int i; + int do_download = 0, is_data, is_hex; + int do_run = 0, do_reset = 0; + char *filename = NULL; + char *portname = "/dev/ttyS0"; + FILE *infile; + + if (argc == 1) { + fprintf(stderr, "Usage: mds_talk [--run] [--reset] [--srec-code | --srec-date | --hex-code | --hex-data] [-f filename] [-p serial_dev]\n"); + exit(1); + } + + is_risc16 = 0; + for (i = 1; i < argc; i++) { + if (!strcmp(argv[i], "--srec-code")) { + do_download = 1; + is_data = 0; + is_hex = 0; + } else if (!strcmp(argv[i], "--srec-data")) { + do_download = 1; + is_data = 1; + is_hex = 0; + } else if (!strcmp(argv[i], "--hex-code")) { + do_download = 1; + is_data = 0; + is_hex = 1; + } else if (!strcmp(argv[i], "--hex-data")) { + do_download = 1; + is_data = 1; + is_hex = 1; + } else if (!strcmp(argv[i], "--reset")) + do_reset = 1; + else if (!strcmp(argv[i], "--run")) + do_run = 1; + else if (!strcmp(argv[i], "-f")) { + if (++i >= argc) { + fprintf(stderr, "Missing filename\n"); + exit(1); + } + filename = argv[i]; + } else if (!strcmp(argv[i], "-p")) { + if (++i >= argc) { + fprintf(stderr, "Missing serial port name\n"); + exit(1); + } + portname = argv[i]; + } else if (!strcmp(argv[i], "--risc16")) { + is_risc16 = 1; + } else { + fprintf(stderr, "Unknown argument \"%s\"\n", argv[i]); + exit(1); + } + } + + if ((ser_fd = open(portname, O_RDWR | O_NOCTTY)) < 0) { + fprintf(stderr, "Can't open port %s\n", portname); + exit(1); + } + tty_setup(ser_fd); + + if (filename) { + if ((infile = fopen(filename, "r")) == NULL) { + fprintf(stderr, "Can't open file %s\n", filename); + exit(1); + } + } else + infile = stdin; + + if (do_reset) + target_reset(); + + if (do_download) { + if (is_hex) + while (!load_hex(infile, is_data)) ; + else + while (!load_srec(infile, is_data)) ; + } + + if (do_run) + target_run(); +} diff --git a/ecos/packages/hal/calmrisc32/core/current/ChangeLog b/ecos/packages/hal/calmrisc32/core/current/ChangeLog new file mode 100644 index 0000000..37a9cd3 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/ChangeLog @@ -0,0 +1,47 @@ +2009-01-31 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_calm32_core.cdl: update compiler flags for gcc 4.x + +2004-04-22 Jani Monoses <jani@iv.ro> + + * cdl/hal_calm32_core.cdl : + Invoke tail with stricter syntax that works in latest coreutils. + +2003-04-10 Nick Garnett <nickg@balti.calivar.com> + + * src/calm32_core.ld: + Added libsupc++.a to GROUP() directive for GCC versions later than + 3.0. + +2003-04-09 Jonathan Larmour <jifl@eCosCentric.com> + + * src/calm32_core.ld: + Fix .gnulinkonce.s -> .gnu.linkonce.s typo. + +2001-06-08 Jonathan Larmour <jlarmour@redhat.com> + + * include/var_cache.h: Correctly indicate absence of cache. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/calmrisc32/core/current/cdl/hal_calm32_core.cdl b/ecos/packages/hal/calmrisc32/core/current/cdl/hal_calm32_core.cdl new file mode 100644 index 0000000..ececbf2 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/cdl/hal_calm32_core.cdl @@ -0,0 +1,128 @@ +# ==================================================================== +# +# hal_calm32_core.cdl +# +# CalmRISC32 core variant architectural HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Original data: bartv, nickg +# Contributors: +# Date: 2001-02-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_CALM32_CORE { + display "Core variant" + parent CYGPKG_HAL_CALM32 + hardware + include_dir cyg/hal + description " + The Calm32 core architecture HAL package provides generic support + for this processor architecture. It is also necessary to + select a specific target platform HAL package." + + implements CYGINT_HAL_CALM32_VARIANT + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_calm32.h>" + } + + compile var_misc.c variant.S + + make { + <PREFIX>/lib/target.ld: <PACKAGE>/src/calm32_core.ld + $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 target.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm target.tmp + } + + cdl_option CYGBLD_LINKER_SCRIPT { + display "Linker script" + flavor data + no_define + calculated { "src/calm32_core.ld" } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "calmrisc32-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-fno-builtin -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions " } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-g -nostdlib -Wl,--gc-sections -Wl,-static -Wl,-Map,redboot.map" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + } + +} diff --git a/ecos/packages/hal/calmrisc32/core/current/include/var_arch.h b/ecos/packages/hal/calmrisc32/core/current/include/var_arch.h new file mode 100644 index 0000000..6b3bf5e --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/include/var_arch.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H + +//========================================================================== +// +// var_arch.h +// +// Architecture specific abstractions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Original work: nickg, dmoseley +// Date: 1999-02-17 +// Purpose: Define architecture abstractions +// Description: This file contains any extra or modified definitions for +// this variant of the architecture. +// Usage: #include <cyg/hal/var_arch.h> +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#ifndef __ASSEMBLER__ +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#endif + +//-------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_ARCH_H +// End of var_arch.h diff --git a/ecos/packages/hal/calmrisc32/core/current/include/var_cache.h b/ecos/packages/hal/calmrisc32/core/current/include/var_cache.h new file mode 100644 index 0000000..589d517 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/include/var_cache.h @@ -0,0 +1,181 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H + +//============================================================================= +// +// var_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2001-02-12 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/var_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/plf_cache.h> +#include <cyg/hal/var_arch.h> + + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +//#define HAL_DCACHE_SETS 0 +//#define HAL_ICACHE_SETS 0 + +//#define HAL_DCACHE_WRITETHRU_MODE 1 +//#define HAL_DCACHE_WRITEBACK_MODE 0 + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL_DEFINED +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC_DEFINED +#define HAL_DCACHE_SYNC() + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_asize_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +#define HAL_DCACHE_LOCK_DEFINED +#define HAL_DCACHE_LOCK(_base_, _asize_) + +// Undo a previous lock operation +#define HAL_DCACHE_UNLOCK_DEFINED +#define HAL_DCACHE_UNLOCK(_base_, _asize_) + +// Unlock entire cache +#define HAL_DCACHE_UNLOCK_ALL_DEFINED +#define HAL_DCACHE_UNLOCK_ALL() + + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH_DEFINED +#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) + + +// Write dirty cache lines to memory for the given address range. +#define HAL_DCACHE_STORE_DEFINED +#define HAL_DCACHE_STORE( _base_ , _asize_ ) + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE_DEFINED +#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) + + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL_DEFINED +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC_DEFINED +#define HAL_ICACHE_SYNC() + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_asize_) + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +#define HAL_ICACHE_LOCK_DEFINED +#define HAL_ICACHE_LOCK(_base_, _asize_) + +// Undo a previous lock operation +#define HAL_ICACHE_UNLOCK_DEFINED +#define HAL_ICACHE_UNLOCK(_base_, _asize_) + +// Unlock entire cache +#define HAL_ICACHE_UNLOCK_ALL_DEFINED +#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_ICACHE_INVALIDATE_DEFINED +#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) + +//----------------------------------------------------------------------------- +// For the flash driver. + +#define HAL_FLASH_CACHES_WANT_OPTIMAL + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h diff --git a/ecos/packages/hal/calmrisc32/core/current/include/var_intr.h b/ecos/packages/hal/calmrisc32/core/current/include/var_intr.h new file mode 100644 index 0000000..858e457 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/include/var_intr.h @@ -0,0 +1,70 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H + +//========================================================================== +// +// imp_intr.h +// +// CalmRISC32 Core Interrupt and clock support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): msalter +// Contributors: msalter +// Date: 2001-02-12 +// Purpose: MIPS32 Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for variants of the MIPS32 +// architecture. +// +// Usage: +// #include <cyg/hal/var_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/plf_intr.h> + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_VAR_INTR_H +// End of var_intr.h diff --git a/ecos/packages/hal/calmrisc32/core/current/include/variant.inc b/ecos/packages/hal/calmrisc32/core/current/include/variant.inc new file mode 100644 index 0000000..5767303 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/include/variant.inc @@ -0,0 +1,128 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC +##============================================================================= +## +## variant.inc +## +## CalmRISC32 Core family assembler header file +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): msalter +## Contributors: msalter +## Date: 2001-02-12 +## Purpose: Calm32 Core family definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the CalmRISC32 family. +## Usage: +## #include <cyg/hal/variant.inc> +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/calm32.inc> + +#include <cyg/hal/platform.inc> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/var_arch.h> + +##----------------------------------------------------------------------------- +## Define CPU variant for architecture HAL. + +#define CYG_HAL_CALM32_CORE + +#------------------------------------------------------------------------------ +# Cache macros. + +#ifndef CYGPKG_HAL_CALM32_CACHE_DEFINED + + .macro hal_cache_init + .endm + +#define CYGPKG_HAL_CALM32_CACHE_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_CALM32_MON_DEFINED + +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + # If we are starting up from ROM, or we are starting in + # RAM and NOT using a ROM monitor, initialize the VSR table. + + .macro hal_mon_init + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vector, + # the rest are left to the ROM for now... + + .macro hal_mon_init + .endm + +#else + + .macro hal_mon_init + .endm + +#endif + + +#define CYGPKG_HAL_CALM32_MON_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# Decide whether the VSR table is defined externally, or is to be defined +# here. + +//#define CYG_HAL_CALM32_VSR_TABLE_DEFINED + +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_VARIANT_INC +# end of variant.inc diff --git a/ecos/packages/hal/calmrisc32/core/current/src/calm32_core.ld b/ecos/packages/hal/calmrisc32/core/current/src/calm32_core.ld new file mode 100644 index 0000000..7106398 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/src/calm32_core.ld @@ -0,0 +1,366 @@ +//=========================================================================== +// +// MLT linker script for CalmRISC32 Core +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== + +#include <pkgconf/system.h> + +OUTPUT_FORMAT("elf64-calmrisc32", "elf64-calmrisc32", + "elf64-calmrisc32") + +OUTPUT_ARCH(calmrisc32) + +STARTUP(vectors.o) +ENTRY(reset_vector) +#ifdef EXTRAS +INPUT(extras.o) +#endif +#if (__GNUC__ >= 3) +GROUP(libtarget.a libgcc.a libsupc++.a) +#else +GROUP(libtarget.a libgcc.a) +#endif + +#define ALIGN_LMA 0x40 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#define SECTIONS_BEGIN + +#if defined(CYG_HAL_STARTUP_RAM) + +/* this version for RAM startup */ +#define SECTION_vectors(_region_, _vma_, _lma_) \ + .vectors _vma_ : _lma_ \ + { KEEP (*(.vectors)) } \ + > _region_ + +#elif defined(CYG_HAL_STARTUP_ROM) + +/* this version for ROM startup */ +#define SECTION_vectors(_region_, _vma_, _lma_) \ + .vectors _vma_ : _lma_ \ + { KEEP (*(.vectors)) } > _region_ + +#endif /* ROM startup version of ROM vectors */ + +#define SECTION_ROMISC(_region_, _vma_, _lma_) \ + .interp _vma_ : _lma_ { *(.interp) } > _region_ \ + .hash : FOLLOWING(.interp) { *(.hash) } > _region_ \ + .dynsym : FOLLOWING(.hash) { *(.dynsym) } > _region_ \ + .dynstr : FOLLOWING(.dynsym) { *(.dynstr) } > _region_ \ + .gnu.version : FOLLOWING(.dynstr) { *(.gnu.version) } > _region_ \ + .gnu.version_d : FOLLOWING(.gnu.version) { *(.gnu.version_d) } > _region_ \ + .gnu.version_r : FOLLOWING(.gnu.version_d) { *(.gnu.version_r) } > _region_ + +#define SECTION_RELOCS(_region_, _vma_, _lma_) \ + .rel.text : \ + { \ + *(.rel.text) \ + *(.rel.text.*) \ + *(.rel.gnu.linkonce.t*) \ + } > _region_ \ + .rela.text : \ + { \ + *(.rela.text) \ + *(.rela.text.*) \ + *(.rela.gnu.linkonce.t*) \ + } > _region_ \ + .rel.data : \ + { \ + *(.rel.data) \ + *(.rel.data.*) \ + *(.rel.gnu.linkonce.d*) \ + } > _region_ \ + .rela.data : \ + { \ + *(.rela.data) \ + *(.rela.data.*) \ + *(.rela.gnu.linkonce.d*) \ + } > _region_ \ + .rel.rodata : \ + { \ + *(.rel.rodata) \ + *(.rel.rodata.*) \ + *(.rel.gnu.linkonce.r*) \ + } > _region_ \ + .rela.rodata : \ + { \ + *(.rela.rodata) \ + *(.rela.rodata.*) \ + *(.rela.gnu.linkonce.r*) \ + } > _region_ \ + .rel.got : { *(.rel.got) } > _region_ \ + .rela.got : { *(.rela.got) } > _region_ \ + .rel.ctors : { *(.rel.ctors) } > _region_ \ + .rela.ctors : { *(.rela.ctors) } > _region_ \ + .rel.dtors : { *(.rel.dtors) } > _region_ \ + .rela.dtors : { *(.rela.dtors) } > _region_ \ + .rel.init : { *(.rel.init) } > _region_ \ + .rela.init : { *(.rela.init) } > _region_ \ + .rel.fini : { *(.rel.fini) } > _region_ \ + .rela.fini : { *(.rela.fini) } > _region_ \ + .rel.bss : { *(.rel.bss) } > _region_ \ + .rela.bss : { *(.rela.bss) } > _region_ \ + .rel.plt : { *(.rel.plt) } > _region_ \ + .rela.plt : { *(.rela.plt) } > _region_ \ + .rel.dyn : { *(.rel.dyn) } > _region_ + +#define SECTION_init(_region_, _vma_, _lma_) \ + .init _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; KEEP (*(.init)) \ + } > _region_ =0x9e90 + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { \ + _stext = .; _ftext = . ; \ + *(.text) \ + *(.text.*) \ + *(.stub) \ + *(.gnu.warning) \ + *(.gnu.linkonce.t*) \ + } > _region_ =0x9e90 \ + _etext = .; PROVIDE (etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; KEEP (*(.fini)) \ + } > _region_ =0x9e90 + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) \ + } > _region_ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.rodata1) *(.rodata1.*) \ + } > _region_ + +#define SECTION_vsr_table(_region_, _vma_, _lma_) \ + .vsr_table _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.vsr_table) \ + } > _region_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { \ + __ram_data_start = ABSOLUTE (.); _fdata = . ; \ + *(.data) *(.data.*) *(.gnu.linkonce.d*) \ + . = ALIGN (8); \ + SORT(CONSTRUCTORS) \ + } > _region_ \ + __rom_data_start = LOADADDR(.data); + +#define SECTION_data1(_region_, _vma_, _lma_) \ + .data1 _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.data1) *(.data1.*) \ + } > _region_ + +#define SECTION_eh_frame(_region_, _vma_, _lma_) \ + .eh_frame _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.eh_frame) \ + } > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.gcc_except_table) \ + } > _region_ + + + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + + /* We don't want to include the .ctors section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + +/* FIXME: We shouldn't need to define __CTOR_LIST__/__CTOR_END__ + and __DTOR_LIST__/__DTOR_END__ except by the PROVIDE lines. + However this doesn't work for old (99r1-era) toolchains, so + leave it for now. */ + +#define SECTION_ctors(_region_, _vma_, _lma_) \ + .ctors _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + KEEP (*crtbegin.o(.ctors)) \ + __CTOR_LIST__ = .; \ + PROVIDE (__CTOR_LIST__ = .); \ + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) \ + KEEP (*(SORT(.ctors.*))) \ + KEEP (*(.ctors)) \ + __CTOR_END__ = .; \ + PROVIDE (__CTOR_END__ = .); \ + } > _region_ + +#define SECTION_dtors(_region_, _vma_, _lma_) \ + .dtors _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + KEEP (*crtbegin.o(.dtors)) \ + __DTOR_LIST__ = .; \ + PROVIDE (__DTOR_LIST__ = .); \ + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) \ + KEEP (*(SORT(.dtors.*))) \ + KEEP (*(.dtors)) \ + __DTOR_END__ = .; \ + PROVIDE (__DTOR_END__ = .); \ + } > _region_ + +#define SECTION_devtab(_region_, _vma_, _lma_) \ + .devtab _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + KEEP(*( SORT (.ecos.table.*))) ; \ + } > _region_ + +#define SECTION_got(_region_, _vma_, _lma_) \ + _gp = ALIGN(16) + 0x7ff0; \ + .got _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.got.plt) *(.got) \ + } > _region_ + +#define SECTION_dynamic(_region_, _vma_, _lma_) \ + .dynamic _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.dynamic) \ + } > _region_ + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + +#define SECTION_sdata(_region_, _vma_, _lma_) \ + .sdata _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \ + } > _region_ + +#define SECTION_lit8(_region_, _vma_, _lma_) \ + .lit8 _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.lit8) \ + } > _region_ + +#define SECTION_lit4(_region_, _vma_, _lma_) \ + .lit4 : FOLLOWING(.lit8) \ + { \ + FORCE_OUTPUT; *(.lit4) \ + } > _region_ \ + __ram_data_end = .; _edata = . ; \ + PROVIDE (edata = .); + +#define SECTION_sbss(_region_, _vma_, _lma_) \ + __bss_start = .; _fbss = .; \ + .sbss _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.dynsbss) *(.sbss) *(.sbss.*) *(.gnu.linkonce.sb.*) *(.scommon) \ + } > _region_ + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { \ + *(.dynbss) *(.bss) *(.bss.*) *(.gnu.linkonce.b.*) *(COMMON) \ + } > _region_ \ + __bss_end = .; + +/* The /DISCARD/ section ensures that the output will not contain a + * .mdebug section as it confuses GDB. This is a workaround for CR 100804. + */ + +#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \ + /* Stabs debugging sections. */ \ + .stab 0 : { *(.stab) } \ + .stabstr 0 : { *(.stabstr) } \ + .stab.excl 0 : { *(.stab.excl) } \ + .stab.exclstr 0 : { *(.stab.exclstr) } \ + .stab.index 0 : { *(.stab.index) } \ + .stab.indexstr 0 : { *(.stab.indexstr) } \ + .comment 0 : { *(.comment) } \ + /* DWARF debug sections. \ + Symbols in the DWARF debugging sections are relative to \ + the beginning of the section so we begin them at 0. */ \ + /* DWARF 1 */ \ + .debug 0 : { *(.debug) } \ + .line 0 : { *(.line) } \ + /* GNU DWARF 1 extensions */ \ + .debug_srcinfo 0 : { *(.debug_srcinfo) } \ + .debug_sfnames 0 : { *(.debug_sfnames) } \ + /* DWARF 1.1 and DWARF 2 */ \ + .debug_aranges 0 : { *(.debug_aranges) } \ + .debug_pubnames 0 : { *(.debug_pubnames) } \ + /* DWARF 2 */ \ + .debug_info 0 : { *(.debug_info) } \ + .debug_abbrev 0 : { *(.debug_abbrev) } \ + .debug_line 0 : { *(.debug_line) } \ + .debug_frame 0 : { *(.debug_frame) } \ + .debug_str 0 : { *(.debug_str) } \ + .debug_loc 0 : { *(.debug_loc) } \ + .debug_macinfo 0 : { *(.debug_macinfo) } \ + /* SGI/MIPS DWARF 2 extensions */ \ + .debug_weaknames 0 : { *(.debug_weaknames) } \ + .debug_funcnames 0 : { *(.debug_funcnames) } \ + .debug_typenames 0 : { *(.debug_typenames) } \ + .debug_varnames 0 : { *(.debug_varnames) } \ + /* These must appear regardless of . */ \ + .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } \ + .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } \ + /DISCARD/ 0 : { *(.mdebug) } + +#include CYGHWR_MEMORY_LAYOUT_LDI + +_hal_vsr_table = 0x0; +_hal_virtual_vector_table = 0x100; diff --git a/ecos/packages/hal/calmrisc32/core/current/src/var_misc.c b/ecos/packages/hal/calmrisc32/core/current/src/var_misc.c new file mode 100644 index 0000000..db8fa36 --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/src/var_misc.c @@ -0,0 +1,104 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg, jlarmour, dmoseley, msalter +// Date: 2000-07-14 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // Base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_intr.h> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/var_arch.h> +#include <cyg/hal/plf_io.h> +#include <cyg/hal/hal_cache.h> + +/*------------------------------------------------------------------------*/ +// Array which stores the configured priority levels for the configured +// interrupts. + +volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; + +/*------------------------------------------------------------------------*/ + +void hal_variant_init(void) +{ +} + + +/*------------------------------------------------------------------------*/ +// Initialize the caches + +int hal_init_icache(unsigned long config1_val) +{ +} + +int hal_init_dcache(unsigned long config1_val) +{ +} + +void hal_c_cache_init(unsigned long config1_val) +{ +} + +void hal_icache_sync(void) +{ +} + +void hal_dcache_sync(void) +{ +} + +/*------------------------------------------------------------------------*/ +/* End of var_misc.c */ diff --git a/ecos/packages/hal/calmrisc32/core/current/src/variant.S b/ecos/packages/hal/calmrisc32/core/current/src/variant.S new file mode 100644 index 0000000..01eac7d --- /dev/null +++ b/ecos/packages/hal/calmrisc32/core/current/src/variant.S @@ -0,0 +1,75 @@ +##============================================================================= +## +## variant.S +## +## CalmRISC32 Core variant code +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): msalter +## Contributors: msalter +## Date: 2001-02-12 +## Purpose: CalmRISC32 Core variant code +## Description: Variant specific code for CalmRISC32 architecture. +## +## +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +#include <cyg/hal/arch.inc> + +#include <cyg/hal/var_arch.h> +#include <cyg/hal/hal_arch.h> + +##----------------------------------------------------------------------------- +# Variant Initialization. +# This code performs variant specific initialization. + +##----------------------------------------------------------------------------- +## end of variant.S + |