diff options
| author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
|---|---|---|
| committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
| commit | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch) | |
| tree | f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/coldfire | |
| parent | f157da5337118d3c5cd464266796de4262ac9dbd (diff) | |
Added the OS files
Diffstat (limited to 'ecos/packages/hal/coldfire')
50 files changed, 8097 insertions, 0 deletions
diff --git a/ecos/packages/hal/coldfire/arch/current/ChangeLog b/ecos/packages/hal/coldfire/arch/current/ChangeLog new file mode 100644 index 0000000..4695921 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/ChangeLog @@ -0,0 +1,46 @@ +2005-06-24 Enrico Piria <epiriaNOSPAM@NOSPAMfastwebnet.it> + + * src/coldfire.ld: + * src/coldfire_stub.c: + * src/context.S: + * src/hal_misc.c: + * src/hal_mk_defs.c: + * src/hal_startup.c: + * src/vectors.S: + * include/arch.inc: + * include/basetype.h: + * include/coldfire_regs.h: + * include/coldfire_stub.h: + * include/hal_arch.h: + * include/hal_cache.h: + * include/hal_intr.h: + * include/hal_io.h: + * include/hal_startup.h: + * cdl/hal_coldfire.cdl: + * doc/readme.txt: + Rework of the original ColdFire architecture HAL contributed by + Wade Jensen. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/coldfire/arch/current/cdl/hal_coldfire.cdl b/ecos/packages/hal/coldfire/arch/current/cdl/hal_coldfire.cdl new file mode 100644 index 0000000..64a3043 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/cdl/hal_coldfire.cdl @@ -0,0 +1,107 @@ +# ==================================================================== +# +# hal_coldfire.cdl +# +# ColdFire architecture HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Enrico Piria +## Contributors: Wade Jensen +## Date: 2005-25-06 +## +######DESCRIPTIONEND#### +##======================================================================== + +cdl_package CYGPKG_HAL_COLDFIRE { + display "ColdFire architecture" + parent CYGPKG_HAL + hardware + include_dir cyg/hal + define_header hal_coldfire.h + description " + The ColdFire architecture HAL package provides generic + support for this processor architecture. It is also + necessary to select a specific target platform HAL + package." + + cdl_interface CYGINT_HAL_COLDFIRE_VARIANT { + display "Number of variant implementations in this configuration" + no_define + requires 1 == CYGINT_HAL_COLDFIRE_VARIANT + } + + compile hal_startup.c hal_misc.c coldfire_stub.c vectors.S context.S + + # The "-o file" is a workaround for CR100958 - without it the + # output file would end up in the source directory under CygWin. + # n.b. grep does not behave itself under win32 + make -priority 1 { + <PREFIX>/include/cyg/hal/cf_offsets.inc : <PACKAGE>/src/hal_mk_defs.c + $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,cf_offsets.tmp -o hal_mk_defs.tmp -S $< + fgrep .equ hal_mk_defs.tmp | sed s/#// > $@ + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 cf_offsets.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm cf_offsets.tmp hal_mk_defs.tmp + } + + make { + <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S + $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -c -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 vectors.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm vectors.tmp + } + + make { + <PREFIX>/lib/target.ld: <PACKAGE>/src/coldfire.ld + $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 target.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm target.tmp + } + + cdl_option CYGBLD_LINKER_SCRIPT { + display "Linker script" + flavor data + no_define + calculated { "src/coldfire.ld" } + } + +} diff --git a/ecos/packages/hal/coldfire/arch/current/doc/readme.txt b/ecos/packages/hal/coldfire/arch/current/doc/readme.txt new file mode 100644 index 0000000..67976d4 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/doc/readme.txt @@ -0,0 +1,70 @@ +SOME NOTES ON THE USAGE OF THE HAL FOR COLDFIRE + +This HAL was obtained by rewriting the original port of eCos to ColdFire done +by Wade Jensen. The following guidelines give you hints about using this +software. + +* Use at least GCC version 3.4.1. This version has an improved support for + ColdFire processors. However, this compiler might not be able to build the + "cxxsupp.cxx" test in the "infra" package. + +* The version of the binutils I used is 2.15.90.0.1.1. + +* The version of newlib I used is 1.13.0. + +* The version of the BDM tools I used is 1.3.0. + +* If you want to debug code by means of the serial connection to eCos, don't +use a version of GDB with BDM support compiled into. There is some kind of +interaction between BDM and serial targets that prevents the latter from +functioning correctly. Do not even use a clean GDB 6.3 distribution to debug +through the serial cable. The downloading of code to the target is broken in +that version. Instead, use a version of GDB grabbed from CVS repository. I +used a version downloaded after June 13, 2005, and the bug had been corrected. + +* Currently (version 6.3), GDB doesn't support the ColdFire MAC unit. Thus, it +is not possible to show the MAC registers, via the "info registers" command, +when debugging an eCos application through a serial connection. The BDM addon +to GDB doesn't suffer from a similar limitation. However, there is a little +hack in order to show and modify the MAC registers even with a serial +connection. When a breakpoint is hit, the GDB module of eCos stores the +current register values in a structure of type HAL_SavedRegisters, pointed to +by the _hal_registers variable. If you included the GDB stub in your +application, it is then possible to display the MAC registers (and all of the +others) by issuing at the GDB prompt the following command: + +print *(struct HAL_SavedRegisters *)_hal_registers + +In case you are using a GDB stub burned in ROM to debug an application in RAM, +you first have to determine where the GDB stub stores the _hal_registers +variable in its own private region of RAM: use the tool m68k-elf-objdump to +find that. For example, if the address of the _hal_registers variable used by +the GDB stub is 0x1e88, then you should use the following command to display +the registers of the application being debugged: + +print *(struct HAL_SavedRegisters *)*0x1e88 + +It is also possible to modify the value of the MAC registers, by updating the +relative field of the HAL_SavedRegisters structure. Don't try to modify the +other registers because the modifications will be discarded when the +application is restarted: use the usual GDB commands instead. Finally, the +correct value of the PC register is the one shown by the "info registers" +command. + +* I added at the architecture level only the features that I could directly +test. When I developed the architecture HAL, I had a ColdFire MCF5272 at +hands, which has a MAC unit. That's why in the architecture HAL there is +currently only support for the MAC unit, and no support for the EMAC and +floating point units. However, I tried to write the HAL in the most generic +fashion I could imagine, in order to make it easy to add new architectural +features and new processor variants. + +* If you want to burn an eCos image into the flash ROM, you cannot rely on the +ROM monitor provided with the board, but you have to use the BDM interface. +If you work under Windows, you can use the free CFFlasher utility, available +on the Freescale Semiconductor web site. The BDM tools also contain a +text-mode utility to do that, but I have not tested it. + + +Enrico Piria (epiria AT fastwebnet DOT it) +November 16, 2005 diff --git a/ecos/packages/hal/coldfire/arch/current/include/arch.inc b/ecos/packages/hal/coldfire/arch/current/include/arch.inc new file mode 100644 index 0000000..64d7fcd --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/arch.inc @@ -0,0 +1,258 @@ +#ifndef CYGONCE_HAL_ARCH_INC +#define CYGONCE_HAL_ARCH_INC +|============================================================================= +| +| arch.inc +| +| ColdFire architecture assembler header file +| +|============================================================================= +| ####ECOSGPLCOPYRIGHTBEGIN#### +| ------------------------------------------- +| This file is part of eCos, the Embedded Configurable Operating System. +| Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +| +| eCos is free software; you can redistribute it and/or modify it under +| the terms of the GNU General Public License as published by the Free +| Software Foundation; either version 2 or (at your option) any later +| version. +| +| eCos is distributed in the hope that it will be useful, but WITHOUT +| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +| FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +| for more details. +| +| You should have received a copy of the GNU General Public License +| along with eCos; if not, write to the Free Software Foundation, Inc., +| 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +| +| As a special exception, if other files instantiate templates or use +| macros or inline functions from this file, or you compile this file +| and link it with other works to produce a work based on this file, +| this file does not by itself cause the resulting work to be covered by +| the GNU General Public License. However the source code for this file +| must still be made available in accordance with section (3) of the GNU +| General Public License v2. +| +| This exception does not invalidate any other reasons why a work based +| on this file might be covered by the GNU General Public License. +| ------------------------------------------- +| ####ECOSGPLCOPYRIGHTEND#### +|============================================================================= +|#####DESCRIPTIONBEGIN#### +| +| Author(s): Enrico Piria +| Contributors: +| Date: 2005-25-06 +| Purpose: MCF5272 variant definitions. +| Description: This file contains macro definitions used in the +| architecture HAL assembler file. +| +|####DESCRIPTIONEND#### +|========================================================================== + + +#define FUNC_START(name) \ + .text; \ + .balign 4; \ + .type name,@function; \ + .globl name; \ +name: + + +| ---------------------------------------------------------------------------- +| Macros to deal with the interrupt priority level in the status register. + + .macro hal_cpu_int_disable + move.w #0x2700,%sr + .endm + + + .macro hal_cpu_int_enable work + move.w %sr,\work + and.l #0xf8ff,\work + move.w \work,%sr + .endm + + + .macro hal_cpu_int_merge from work + move.w %sr,\work + and.l #0xf8ff,\work + and.l #0x0700,\from + or.l \from,\work + move.w \work,%sr + .endm + +| ---------------------------------------------------------------------------- +| Macro to find the value the SP register had before an exception. + + .macro find_original_sp out + move.b CYGARC_CF_FMTVECWORD(%sp),\out + lsr.l #4,\out + and.l #0x00000003,\out + add.l #CYGARC_CF_EXCEPTION_SIZE,\out + add.l %sp,\out + .endm + + +| ---------------------------------------------------------------------------- +| Macros used to save and restore MAC registers during interrupts/exceptions. + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + .macro save_mac_registers work + | Store MACSR register + move.l %macsr,\work + move.l \work,CYGARC_CFREG_MACSR(%sp) + + | Switch to integer mode. This allows to save the contents of ACC + | without rounding + and.l #0x000000df,\work + move.l \work,%macsr + + | Store ACC register + move.l %acc,\work + move.l \work,CYGARC_CFREG_MACC(%sp) + + | Store MASK register + move.l %mask,\work + move.l \work,CYGARC_CFREG_MASK(%sp) + .endm + + + .macro restore_mac_registers work + | Load MACSR register + move.l CYGARC_CFREG_MACSR(%sp),\work + move.l \work,%macsr + + | Load ACC register + move.l CYGARC_CFREG_MACC(%sp),\work + move.l \work,%acc + + | Load MASK register + move.l CYGARC_CFREG_MASK(%sp),\work + move.l \work,%mask + .endm +#endif + + +| ---------------------------------------------------------------------------- +| Macros used to save registers in interrupt handlers. During an interrupt, +| we save registers %d0-%d1 and %a0-%a1 because of the GNU C calling +| conventions. During the handler we also need register %d2. + +#ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + .macro int_pres_regs + lea.l -CYGARC_CF_EXCEPTION_DECREMENT(%sp),%sp + movem.l %d0-%d2,CYGARC_CFREG_DREGS(%sp) + movem.l %a0-%a1,CYGARC_CFREG_AREGS(%sp) + .endm + + + .macro int_rest_regs + movem.l CYGARC_CFREG_AREGS(%sp),%a0-%a1 + movem.l CYGARC_CFREG_DREGS(%sp),%d0-%d2 + lea.l CYGARC_CF_EXCEPTION_DECREMENT(%sp),%sp + .endm + +#else /* CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT */ + + .macro int_pres_regs + lea.l -CYGARC_CF_EXCEPTION_DECREMENT(%sp),%sp + movem.l %d0-%d7,CYGARC_CFREG_DREGS(%sp) + movem.l %a0-%a6,CYGARC_CFREG_AREGS(%sp) + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + save_mac_registers %d0 +#endif + + | Save old SP (before interrupt) + find_original_sp %d0 + move.l %d0,CYGARC_CFREG_SP(%sp) + .endm + + + .macro int_rest_regs + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + restore_mac_registers %d0 +#endif + + movem.l CYGARC_CFREG_AREGS(%sp),%a0-%a6 + movem.l CYGARC_CFREG_DREGS(%sp),%d0-%d7 + lea.l CYGARC_CF_EXCEPTION_DECREMENT(%sp),%sp + .endm + +#endif /* CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT */ + + +| ---------------------------------------------------------------------------- +| Macros used to save/restore registers during context switches. +| We don't save registers %d0-%d1 and %a0-%a1 because of the GNU C calling +| conventions: these macros are used in a routine called by C code. + +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + + .macro ctx_save_registers + lea -CYGARC_CF_CONTEXT_SIZE(%sp),%sp + movem.l %d2-%d7,CYGARC_CFREG_D2(%sp) + movem.l %a2-%a6,CYGARC_CFREG_A2(%sp) +#ifdef CYGHWR_HAL_COLDFIRE_MAC + save_mac_registers %d0 +#endif + | Save SR and interrupt level + move.w %sr,%d0 + move.w %d0,CYGARC_CF_SR(%sp) + .endm + + + .macro ctx_restore_registers + | Restore SR and interrupt level + move.w CYGARC_CF_SR(%sp),%d0 + move.w %d0,%sr + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + restore_mac_registers %d0 +#endif + movem.l CYGARC_CFREG_D2(%sp),%d2-%d7 + movem.l CYGARC_CFREG_A2(%sp), %a2-%a6 + lea CYGARC_CF_CONTEXT_SIZE(%sp),%sp + .endm + +#else /* CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM */ + + .macro ctx_save_registers + | Save all of the registers + lea -CYGARC_CF_CONTEXT_SIZE(%sp),%sp + movem.l %d0-%d7,CYGARC_CFREG_DREGS(%sp) + movem.l %a0-%a7,CYGARC_CFREG_AREGS(%sp) +#ifdef CYGHWR_HAL_COLDFIRE_MAC + save_mac_registers %d0 +#endif + + | Save pc (useful during debugging with GDB) + lea (%pc),%a0 + move.l %a0,CYGARC_CFREG_PC(%sp) + + | Save SR and interrupt level + move.w %sr,%d0 + move.w %d0,CYGARC_CF_SR(%sp) + .endm + + + .macro ctx_restore_registers + | Restore SR and interrupt level + move.w CYGARC_CF_SR(%sp),%d0 + move.w %d0,%sr + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + restore_mac_registers %d0 +#endif + movem.l CYGARC_CFREG_DREGS(%sp),%d0-%d7 + movem.l CYGARC_CFREG_AREGS(%sp),%a0-%a6 + lea CYGARC_CF_CONTEXT_SIZE(%sp),%sp + .endm +#endif /* CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM */ + +| ---------------------------------------------------------------------------- +| End of arch.inc +#endif /* ifndef CYGONCE_HAL_ARCH_INC */ diff --git a/ecos/packages/hal/coldfire/arch/current/include/basetype.h b/ecos/packages/hal/coldfire/arch/current/include/basetype.h new file mode 100644 index 0000000..2a7b458 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/basetype.h @@ -0,0 +1,80 @@ +#ifndef CYGONCE_HAL_BASETYPE_H +#define CYGONCE_HAL_BASETYPE_H + +//============================================================================= +// +// basetype.h +// +// Standard types for this architecture +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Provide ColdFire-specific type definitions. +// Usage: Included by "cyg_type.h", do not use directly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +// Include variant specific types +#include <cyg/hal/var_basetype.h> + + +// --------------------------------------------------------------------------- +// Characterize the architecture + +#define CYG_BYTEORDER CYG_MSBFIRST // Big endian + +// The ColdFire architecture uses the default definitions of the base types, +// so we do not need to define any here. + +// --------------------------------------------------------------------------- +// Override the alignment definitions from cyg_type.h + +#ifndef CYGARC_ALIGNMENT +#define CYGARC_ALIGNMENT 4 +#endif + +// The corresponding power of two alignment +#ifndef CYGARC_P2ALIGNMENT +#define CYGARC_P2ALIGNMENT 2 +#endif + +// --------------------------------------------------------------------------- +// End of basetype.h +#endif // CYGONCE_HAL_BASETYPE_H diff --git a/ecos/packages/hal/coldfire/arch/current/include/coldfire_regs.h b/ecos/packages/hal/coldfire/arch/current/include/coldfire_regs.h new file mode 100644 index 0000000..b74b1a0 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/coldfire_regs.h @@ -0,0 +1,66 @@ +#ifndef CYGONCE_HAL_CF_REGS_H +#define CYGONCE_HAL_CF_REGS_H + +//========================================================================== +// +// coldfire_regs.h +// +// ColdFire CPU definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Provide ColdFire register definitions. +// Usage: #include <cyg/hal/coldfire_regs.h> +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/hal/var_regs.h> + + +// Macro to embed movec instructions in C code +#define CYGARC_MOVEC(_value_, _reg_) \ + asm volatile("movec %0,%1" : : "d" (_value_), "i" (_reg_)) + + +// --------------------------------------------------------------------------- +// End of coldfire_regs.h +#endif // ifdef CYGONCE_HAL_CF_REGS_H diff --git a/ecos/packages/hal/coldfire/arch/current/include/coldfire_stub.h b/ecos/packages/hal/coldfire/arch/current/include/coldfire_stub.h new file mode 100644 index 0000000..59d8fce --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/coldfire_stub.h @@ -0,0 +1,136 @@ +#ifndef CYGONCE_HAL_COLDFIRE_STUB_H +#define CYGONCE_HAL_COLDFIRE_STUB_H + +//======================================================================== +// +// coldfire_stub.h +// +// ColdFire-specific definitions for generic stub +// +//======================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: +// Description: ColdFire-specific definitions for generic stub. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#ifdef __cplusplus +extern "C" { +#endif + +#define NUMREGS 18 + +// ColdFire stub has special needs for register handling because flating point +// registers are bigger than the rest. Special put_register and get_register +// are provided. +#define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1 + +#define REGSIZE( _x_ ) (4) + +typedef unsigned long target_register_t; + +enum regnames { + D0, D1, D2, D3, D4, D5, D6, D7, + A0, A1, A2, A3, A4, A5, A6, A7, + SR, PC, +}; + +#define SP A7 + +typedef enum regnames regnames_t; + +// Given a trap value TRAP, return the corresponding signal +extern int __computeSignal(unsigned int trap_number); + +// Return the ColdFire trap number corresponding to the last-taken trap +extern int __get_trap_number(void); + +// Return the currently-saved value corresponding to register REG +extern target_register_t get_register(regnames_t reg); + +// Store VALUE in the register corresponding to WHICH +extern void put_register(regnames_t which, target_register_t value); + +// Read the contents of register WHICH into VALUE as raw bytes +extern int get_register_as_bytes(regnames_t which, char *value); + +// Write the contents of register WHICH into VALUE as raw bytes +extern int put_register_as_bytes(regnames_t which, char *value); + +// Set the currently-saved pc register value to PC. This also updates NPC +// as needed. +extern void set_pc(target_register_t pc); + +// Set things up so that the next user resume will execute one instruction. +// This may be done by setting breakpoints or setting a single step flag +// in the saved user registers, for example. +extern void __single_step(void); + +// Clear the single-step state +extern void __clear_single_step(void); + +// If the breakpoint we hit is in the breakpoint() instruction, return a +// non-zero value +extern int __is_breakpoint_function(void); + +// Skip the current instruction +extern void __skipinst(void); + +extern void __install_breakpoints(void); + +extern void __clear_breakpoints(void); + +// We have to rewind the PC in case of a breakpoint. +#define HAL_STUB_PLATFORM_STUBS_FIXUP() \ +CYG_MACRO_START \ + if (CYGNUM_HAL_VECTOR_DEBUGTRAP == __get_trap_number()) \ + { \ + CYG_ADDRESS pc = get_register(PC) - HAL_BREAKINST_SIZE; \ + put_register(PC, pc); \ + } \ +CYG_MACRO_END + +#ifdef __cplusplus +} // extern "C" +#endif + +// --------------------------------------------------------------------------- +// End of coldfire_stub.h +#endif // ifndef CYGONCE_HAL_COLDFIRE_STUB_H diff --git a/ecos/packages/hal/coldfire/arch/current/include/hal_arch.h b/ecos/packages/hal/coldfire/arch/current/include/hal_arch.h new file mode 100644 index 0000000..57462b9 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/hal_arch.h @@ -0,0 +1,474 @@ +#ifndef CYGONCE_HAL_ARCH_H +#define CYGONCE_HAL_ARCH_H + +//============================================================================= +// +// hal_arch.h +// +// Architecture specific abstractions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: +// Description: Definitions for the ColdFire architecture HAL. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// Include some variant specific architectural defines +#include <cyg/hal/var_arch.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +#include <cyg/hal/coldfire_stub.h> +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +// ---------------------------------------------------------------------------- +// Macros to deal with exception stack frame fields + +// The ColdFire family of processors has a simplified exception stack +// frame that looks like the following: +// +// 8 +----------------+----------------+ +// | Program Counter | +// 4 +----------------+----------------+ +// |Fmt/FS/Vector/FS| SR | +// SP --> 0 +----------------+----------------+ +// The stack self-aligns to a 4-byte boundary at an exception, with +// the Fmt/FS/Vector/FS field indicating the size of the adjustment +// (SP += 0,1,2,3 bytes). + +// Define the Fmt/FS/Vector/FS word. +// Bits 31-28 are the format word which tells the +// RTI instruction how to align the stack. +#define HAL_CF_EXCEPTION_FORMAT_MSK ((CYG_WORD16)0xF000) +// Bits 25-18 are the vector number of the exception. +#define HAL_CF_EXCEPTION_VECTOR_MSK ((CYG_WORD16)0x03FC) +// Bits 27-26, and 17-16 are the fault status used +// for bus and address errors. +#define HAL_CF_EXCEPTION_FS32_MSK ((CYG_WORD16)0x0C00) +#define HAL_CF_EXCEPTION_FS10_MSK ((CYG_WORD16)0x0003) + +// Macros to access fields in the format vector word. + +#define HAL_CF_EXCEPTION_FORMAT(_fmt_vec_word_) \ + ((((CYG_WORD16)(_fmt_vec_word_)) & HAL_CF_EXCEPTION_FORMAT_MSK) >> 12) + +#define HAL_CF_EXCEPTION_VECTOR(_fmt_vec_word_) \ + ((((CYG_WORD16)(_fmt_vec_word_)) & HAL_CF_EXCEPTION_VECTOR_MSK) >> 2) + +#define HAL_CF_EXCEPTION_FS(_fmt_vec_word_) \ + (((((CYG_WORD16)(_fmt_vec_word_)) & HAL_CF_EXCEPTION_FS32_MSK) >> 8) \ + | (((CYG_WORD16)(_fmt_vec_word_)) & HAL_CF_EXCEPTION_FS10_MSK)) + +// ---------------------------------------------------------------------------- +// HAL_SavedRegisters -- Saved by a context switch or by an exception/interrupt + +typedef struct +{ + // These are common to all saved states and are in the order + // stored and loaded by the movem instruction. + + // Data regs D0-D7 + CYG_WORD32 d[8]; + + // Address regs A0-A7 + CYG_ADDRESS a[8]; + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + // MAC registers + CYG_WORD32 macc; + CYG_WORD32 macsr; + CYG_WORD32 mask; +#endif + + // On exception/interrupt PC, SR and exception are pushed on the + // stack automatically, so there is no need to allocate the entire + // structure. + + // 16-bit format/vector word + CYG_WORD16 fmt_vec_word; + + // Status register + CYG_WORD16 sr; + + // Program counter + CYG_ADDRESS pc; + +} __attribute__ ((aligned, packed)) HAL_SavedRegisters; + +#ifndef HAL_THREAD_SWITCH_CONTEXT + +// *************************************************************************** +// HAL_THREAD_SWITCH_CONTEXT +// +// This macro saves the state of the currently running thread and writes +// its stack pointer to *(_fspptr_). +// It then switches to the thread context that *(_tspptr_) points to. +// +// INPUT: +// _fspptr_: A pointer to the location to save the current thread's stack +// pointer to. +// +// _tspptr_: A pointer to the location containing the stack pointer of +// the thread context to switch to. +// +// OUTPUT: +// *(_fspptr_): Contains the stack pointer of the previous thread's context. +// +// *************************************************************************** + +externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); +externC void hal_thread_load_context( CYG_ADDRESS to ) + CYGBLD_ATTRIB_NORET; + +#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ + hal_thread_switch_context((CYG_ADDRESS)_tspptr_,(CYG_ADDRESS)_fspptr_); +#endif // HAL_THREAD_SWITCH_CONTEXT + +#ifndef HAL_THREAD_LOAD_CONTEXT + +// *************************************************************************** +// hal_thread_load_context +// +// This routine loads the thread context that *(_tspptr_) points to. +// This routine does not return. +// +// INPUT: +// _tspptr_: A pointer to the location containing the stack pointer of +// the thread context to switch to. +// +// *************************************************************************** + +#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ + hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); +#endif // HAL_THREAD_LOAD_CONTEXT + + +#ifndef HAL_THREAD_INIT_CONTEXT + +// *************************************************************************** +// HAL_THREAD_INIT_CONTEXT -- Context Initialization +// +// Initialize the context of a thread. +// +// INPUT: +// _sparg_: The name of the variable containing the current sp. This +// will be written with the new sp. +// +// _thread_: The thread object address, passed as argument to entry +// point. +// +// _entry_: The thread's entry point address. +// +// _id_: A bit pattern used in initializing registers, for debugging. +// +// OUTPUT: +// _sparg_: Updated with the value of the new sp. +// +// *************************************************************************** + +#define HAL_THREAD_INIT_CONTEXT(_sparg_, _thread_, _entry_, _id_) \ + CYG_MACRO_START \ + CYG_WORD32 * _sp_ = ((CYG_WORD32*)((CYG_WORD32)(_sparg_) & ~15)); \ + HAL_SavedRegisters * _regs_; \ + int _i_; \ + \ + /* Thread's parameter. */ \ + *(--_sp_) = (CYG_WORD32)(_thread_); \ + /* Fake thread's return addr. Needed because thread is a function */ \ + /* and parameters to functions are always follwed by the return */ \ + /* address on the stack. */ \ + *(--_sp_) = (CYG_WORD32)(0xDEADC0DE); \ + /* Thread's return addr. (used by hal_thread_load_context) */ \ + *(--_sp_) = (CYG_WORD32)(_entry_); \ + \ + _regs_ = (HAL_SavedRegisters *) \ + ((CYG_WORD32)_sp_ - sizeof(HAL_SavedRegisters)); \ + \ + for (_i_=0; _i_ < 8; _i_++) \ + _regs_->a[_i_] = _regs_->d[_i_] = (_id_); \ + /* A6, initial frame pointer should be null */ \ + _regs_->a[6] = (CYG_ADDRESS)0; \ + \ + /* Thread's starting SR. All interrupts enabled. */ \ + _regs_->sr = 0x3000; \ + \ + /* Thread's starting PC */ \ + _regs_->pc = (CYG_ADDRESS)(_entry_); \ + \ + (_sparg_) = (CYG_ADDRESS)_regs_; \ + CYG_MACRO_END +#endif // HAL_THREAD_INIT_CONTEXT + +// ---------------------------------------------------------------------------- +// Bit manipulation routines. + +externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); +externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); + +#define HAL_LSBIT_INDEX(index, mask) (index) = hal_lsbit_index(mask); + +#define HAL_MSBIT_INDEX(index, mask) (index) = hal_msbit_index(mask); + +// ---------------------------------------------------------------------------- +// Idle thread code. +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. + +externC void hal_idle_thread_action(cyg_uint32 loop_count); + +#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) + +// ---------------------------------------------------------------------------- +// Execution reorder barrier. +// When optimizing the compiler can reorder code. In multithreaded systems +// where the order of actions is vital, this can sometimes cause problems. +// This macro may be inserted into places where reordering should not happen. + +#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) + +// ---------------------------------------------------------------------------- +// Breakpoint support +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen +// if executed. +// HAL_BREAKINST is the value of the breakpoint instruction and +// HAL_BREAKINST_SIZE is its size in bytes. + +// The host side of GDB debugger uses trap #15 to install breakpoints. + +#define CYGNUM_HAL_VECTOR_DEBUGTRAP 47 + +#define HAL_BREAKPOINT(_label_) \ +asm volatile (" .globl " #_label_ ";" \ + #_label_":" \ + " trap #15" \ + ); + +#define HAL_BREAKINST 0x4E4F + +#define HAL_BREAKINST_SIZE 2 + + +// ---------------------------------------------------------------------------- +// Thread register state manipulation for GDB support. + +typedef struct { + cyg_uint32 d[8]; + cyg_uint32 a[8]; + cyg_uint32 pc; + cyg_uint32 sr; +} GDB_Registers; + +// Translate a stack pointer as saved by the thread context macros above into +// a pointer to a HAL_SavedRegisters structure. +#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ + (_regs_) = (HAL_SavedRegisters *)(_sp_) + + +// Copy a set of registers from a HAL_SavedRegisters structure into a +// GDB ordered array. +#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ + CYG_MACRO_START \ + union __gdbreguniontype { \ + __typeof__(_aregval_) _aregval2_; \ + GDB_Registers *_gdbr; \ + } __gdbregunion; \ + __gdbregunion._aregval2_ = (_aregval_); \ + GDB_Registers *_gdb_ = __gdbregunion._gdbr; \ + int _i_; \ + \ + for( _i_ = 0; _i_ < 8; _i_++ ) \ + { \ + _gdb_->d[_i_] = (_regs_)->d[_i_]; \ + _gdb_->a[_i_] = (_regs_)->a[_i_]; \ + } \ + \ + _gdb_->pc = (_regs_)->pc; \ + _gdb_->sr = (cyg_uint32) ((_regs_)->sr); \ + CYG_MACRO_END + +// Copy a GDB ordered array into a HAL_SavedRegisters structure. +#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ + CYG_MACRO_START \ + union __gdbreguniontype { \ + __typeof__(_aregval_) _aregval2_; \ + GDB_Registers *_gdbr; \ + } __gdbregunion; \ + __gdbregunion._aregval2_ = (_aregval_); \ + GDB_Registers *_gdb_ = __gdbregunion._gdbr; \ + int _i_; \ + \ + for( _i_ = 0; _i_ < 8; _i_++ ) \ + { \ + (_regs_)->d[_i_] = _gdb_->d[_i_]; \ + (_regs_)->a[_i_] = _gdb_->a[_i_]; \ + } \ + \ + (_regs_)->pc = _gdb_->pc; \ + (_regs_)->sr = (CYG_WORD16)(_gdb_->sr); \ + CYG_MACRO_END + + +#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + defined(CYGPKG_HAL_EXCEPTIONS) + +// ---------------------------------------------------------------------------- +// Exception handling function. +// This function is defined by the kernel according to this prototype. It is +// invoked from the HAL to deal with any CPU exceptions that the HAL does +// not want to deal with itself. It usually invokes the kernel's exception +// delivery mechanism. + +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); + +#endif // defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) + +// ---------------------------------------------------------------------------- +// Minimal and sensible stack sizes: the intention is that applications +// will use these to provide a stack size in the first instance prior to +// proper analysis. Idle thread stack should be this big. + +// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. +// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. +// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! + +// This is not a config option because it should not be adjusted except +// under "enough rope" sort of disclaimers. + +// Stack frame overhead per call: 6 data registers, 5 address registers, +// frame pointer, and return address. We can't guess the local variables so +// just assume that using all of the registers averages out. + +#define CYGNUM_HAL_STACK_FRAME_SIZE ((6 + 5 + 1 + 1) * 4) + +// Stack needed for a context switch. +// All registers + pc + sr + vector. + +#ifndef CYGNUM_HAL_STACK_CONTEXT_SIZE +#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((8+8+1)*4 + (1+1)*2) +#endif // CYGNUM_HAL_STACK_CONTEXT_SIZE + +// Interrupt (rounded up) + call to ISR, interrupt_end() and the DSR. + +#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ + ((CYGNUM_HAL_STACK_CONTEXT_SIZE) + (2*CYGNUM_HAL_STACK_FRAME_SIZE)) + +// We define a minimum stack size as the minimum any thread could ever +// legitimately get away with. We can throw asserts if users ask for less +// than this. Allow enough for four interrupt sources - clock, serial, +// nic, and one other. + +// No separate interrupt stack exists. Make sure all threads contain +// a stack sufficiently large. + +#define CYGNUM_HAL_STACK_SIZE_MINIMUM \ + ((4*CYGNUM_HAL_STACK_INTERRUPT_SIZE) \ + + (16*CYGNUM_HAL_STACK_FRAME_SIZE)) + +// Now make a reasonable choice for a typical thread size. Pluck figures +// from thin air and say 30 call frames with an average of 16 words of +// automatic variables per call frame. + +#define CYGNUM_HAL_STACK_SIZE_TYPICAL \ + (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ + (30 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4)))) + +// ------------------------------------------------------------------------- +// Macros for switching context between two eCos instances (jump from +// code in ROM to code in RAM or vice versa). + +#define CYGARC_HAL_SAVE_GP() +#define CYGARC_HAL_RESTORE_GP() + +// ------------------------------------------------------------------------- +// hal_setjmp/hal_longjmp + + +// We must save all of the registers that are preserved across routine +// calls. The assembly code assumes that this structure is defined in the +// following format. Any changes to this structure will result in changes to +// the assembly code!! + +typedef struct { + // D registers + cyg_uint32 d2; + cyg_uint32 d3; + cyg_uint32 d4; + cyg_uint32 d5; + cyg_uint32 d6; + cyg_uint32 d7; + + // A registers + cyg_uint32 a2; + cyg_uint32 a3; + cyg_uint32 a4; + cyg_uint32 a5; + cyg_uint32 a6; + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + // MAC registers + cyg_uint32 macc; + cyg_uint32 macsr; + cyg_uint32 mask; +#endif + + // SP and PC + cyg_uint32 sp; + cyg_uint32 pc; +} hal_jmp_buf_t; + +// This type is used by normal routines to pass the address of the structure +// into our routines without having to explicitly take the address +// of the structure. + +typedef cyg_uint32 hal_jmp_buf[sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32)]; + +// Define the generic setjmp and longjmp routines +externC int hal_setjmp(hal_jmp_buf env); +externC void hal_longjmp(hal_jmp_buf env, int val); +#define hal_setjmp(_env) hal_setjmp(_env) +#define hal_longjmp(_env, _val) hal_longjmp(_env, _val) + +// --------------------------------------------------------------------------- +// End of hal_arch.h +#endif // CYGONCE_HAL_ARCH_H diff --git a/ecos/packages/hal/coldfire/arch/current/include/hal_cache.h b/ecos/packages/hal/coldfire/arch/current/include/hal_cache.h new file mode 100644 index 0000000..7012760 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/hal_cache.h @@ -0,0 +1,61 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Provide ColdFire-specific cache control definitions. +// Usage: #include <cyg/hal/hal_cache.h> +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/var_cache.h> + +// --------------------------------------------------------------------------- +// End of hal_cache.h +#endif // ifndef CYGONCE_HAL_CACHE_H diff --git a/ecos/packages/hal/coldfire/arch/current/include/hal_intr.h b/ecos/packages/hal/coldfire/arch/current/include/hal_intr.h new file mode 100644 index 0000000..b609d88 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/hal_intr.h @@ -0,0 +1,345 @@ +#ifndef CYGONCE_HAL_HAL_INTR_H +#define CYGONCE_HAL_HAL_INTR_H + +//========================================================================== +// +// hal_intr.h +// +// ColdFire interrupt/exception support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Provide ColdFire-specific interrupt and exception +// definitions. +// Usage: #include <cyg/hal/hal_intr.h> +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_arch.h> + +#include <cyg/hal/var_intr.h> + +#include <cyg/infra/cyg_ass.h> // CYG_FAIL + +// ------------------------------------------------------------------------- +// ColdFire exception vectors. These correspond to VSRs and are the values +// to use for HAL_VSR_GET/SET. + +#define CYGNUM_HAL_VECTOR_RESETSP 0 +#define CYGNUM_HAL_VECTOR_RESETPC 1 +#define CYGNUM_HAL_VECTOR_BUSERR 2 +#define CYGNUM_HAL_VECTOR_ADDRERR 3 +#define CYGNUM_HAL_VECTOR_ILLINST 4 +#define CYGNUM_HAL_VECTOR_ZERODIV 5 + +// Exception vectors 6-7 are reserved + +#define CYGNUM_HAL_VECTOR_PRIVVIOLATION 8 +#define CYGNUM_HAL_VECTOR_TRACE 9 +#define CYGNUM_HAL_VECTOR_L1010 10 +#define CYGNUM_HAL_VECTOR_L1111 11 +#define CYGNUM_HAL_VECTOR_DEBUG12 12 +#define CYGNUM_HAL_VECTOR_DEBUG13 13 +#define CYGNUM_HAL_VECTOR_FORMAT 14 +#define CYGNUM_HAL_VECTOR_UNINITINT 15 + +// Exception vectors 16-23 are reserved + +#define CYGNUM_HAL_VECTOR_SPURINT 24 + +#define CYGNUM_HAL_VECTOR_AUTOVEC1 25 +#define CYGNUM_HAL_VECTOR_AUTOVEC2 26 +#define CYGNUM_HAL_VECTOR_AUTOVEC3 27 +#define CYGNUM_HAL_VECTOR_AUTOVEC4 28 +#define CYGNUM_HAL_VECTOR_AUTOVEC5 29 +#define CYGNUM_HAL_VECTOR_AUTOVEC6 30 +#define CYGNUM_HAL_VECTOR_AUTOVEC7 31 +#define CYGNUM_HAL_NUMAUTOVEC 7 + +#define CYGNUM_HAL_VECTOR_TRAPFIRST 32 +#define CYGNUM_HAL_VECTOR_TRAPLAST 47 +#define CYGNUM_HAL_NUMTRAPS 16 + +#define CYGNUM_HAL_VECTOR_FP_BRANCH 48 +#define CYGNUM_HAL_VECTOR_FP_INEXACT 49 +#define CYGNUM_HAL_VECTOR_FP_ZERODIV 50 +#define CYGNUM_HAL_VECTOR_FP_UNDERFLOW 51 +#define CYGNUM_HAL_VECTOR_FP_OPERAND 52 +#define CYGNUM_HAL_VECTOR_FP_OVERFLOW 53 +#define CYGNUM_HAL_VECTOR_FP_NAN 54 +#define CYGNUM_HAL_VECTOR_FP_DENORM 55 + +// Exception vectors 56-60 are reserved + +#define CYGNUM_HAL_VECTOR_UNSUPINST 61 + +// Exception vectors 62-63 are reserved + +#define CYGNUM_HAL_VECTOR_USERINTRFIRST 64 +#define CYGNUM_HAL_VECTOR_USERINTRLAST 255 +#define CYGNUM_HAL_NUMUSERINTR 192 + +// ------------------------------------------------------------------------- +// Interrupt and exception vector table definitions. + +#define CYGNUM_HAL_VSR_MIN 0 +#define CYGNUM_HAL_VSR_MAX 255 +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX - CYGNUM_HAL_VSR_MIN + 1) + +// To simplify things in interrupt handling code, we don't take into account +// autovectored, spurious and uninitialized interrupts. + +#ifndef CYGNUM_HAL_ISR_RANGE_DEFINED +#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_VECTOR_USERINTRFIRST +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_USERINTRLAST +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1) +#endif + +#ifndef CYGNUM_HAL_EXCEPTION_RANGE_DEFINED +#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VECTOR_BUSERR +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VECTOR_UNSUPINST +#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX -\ + CYGNUM_HAL_EXCEPTION_MIN + 1) +#endif + +// ------------------------------------------------------------------------- +// Equivalence between ColdFire exception names and target independent +// exception names. +// These are the values used when passed out to an +// external exception handler using cyg_hal_deliver_exception(). + +#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION CYGNUM_HAL_VECTOR_ILLINST +#define CYGNUM_HAL_EXCEPTION_DIV_BY_ZERO CYGNUM_HAL_VECTOR_ZERODIV +#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_BUSERR +#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_BUSERR + +// ------------------------------------------------------------------------- +// Spurious interrupt definition. + +#ifndef CYGNUM_HAL_SPURIOUS_INTERRUPT +#define CYGNUM_HAL_SPURIOUS_INTERRUPT CYGNUM_HAL_VECTOR_SPURINT +#endif + +// ------------------------------------------------------------------------- +// Static data used by HAL. + +// ISR tables +externC volatile CYG_ADDRESS cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRESS cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +// VSR table +externC volatile CYG_ADDRESS cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; + +// ROM VSR table +externC CYG_ADDRESS rom_vsr_table[CYGNUM_HAL_VSR_COUNT]; + +// ------------------------------------------------------------------------- +// Interrupt stack definitions. + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + +externC void hal_interrupt_stack_call_pending_DSRs(void); +#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ + hal_interrupt_stack_call_pending_DSRs() + +#endif + +// A separate stack always exist to allow the processor to initialize itself. +// It depends on CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK macro +// definition if this stack is used for interrupts too. + +#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base +#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack + +externC char HAL_INTERRUPT_STACK_BASE[]; +externC char HAL_INTERRUPT_STACK_TOP[]; + +// -------------------------------------------------------------------------- +// Translate a vector number into an ISR table index. + +#ifndef HAL_TRANSLATE_VECTOR +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_- CYGNUM_HAL_ISR_MIN) +#endif + +// ------------------------------------------------------------------------- +// Interrupt state storage. + +typedef cyg_uint16 CYG_INTERRUPT_STATE; + +// -------------------------------------------------------------------------- +// Interrupt and VSR attachment macros. + +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); + +externC void hal_default_exception_handler(CYG_WORD vector, + HAL_SavedRegisters *regs); + +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ +CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if (cyg_hal_interrupt_handlers[_index_] \ + == (CYG_ADDRESS) &hal_default_isr) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ +CYG_MACRO_END + +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ +CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR((_vector_), _index_); \ + \ + if (cyg_hal_interrupt_handlers[_index_] \ + == (CYG_ADDRESS) &hal_default_isr) \ + { \ + cyg_hal_interrupt_handlers[_index_] = (CYG_ADDRESS)(_isr_); \ + cyg_hal_interrupt_data[_index_] = (CYG_ADDRWORD)(_data_); \ + cyg_hal_interrupt_objects[_index_] = (CYG_ADDRESS)(_object_); \ + } \ +CYG_MACRO_END + +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ +CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_INTERRUPT_MASK(_vector_); \ + HAL_TRANSLATE_VECTOR((_vector_), _index_); \ + if (cyg_hal_interrupt_handlers[_index_] \ + == (CYG_ADDRESS)(_isr_)) \ + { \ + cyg_hal_interrupt_handlers[_index_] = \ + (CYG_ADDRESS)&hal_default_isr; \ + cyg_hal_interrupt_data[_index_] = 0; \ + cyg_hal_interrupt_objects[_index_] = 0; \ + } \ +CYG_MACRO_END + +#define HAL_VSR_GET( _vector_, _pvsr_ ) \ + *((CYG_ADDRESS *)(_pvsr_)) = cyg_hal_vsr_table[(_vector_)]; + + +#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \ +CYG_MACRO_START \ + if( (_poldvsr_) != NULL ) \ + *(CYG_ADDRESS *)(_poldvsr_) = cyg_hal_vsr_table[(_vector_)]; \ + cyg_hal_vsr_table[(_vector_)] = (CYG_ADDRESS)(_vsr_); \ +CYG_MACRO_END + + +// This is an ugly name, but what it means is: grab the VSR back to eCos +// internal handling, or if you like, the default handler. But if +// cooperating with a ROM monitor, the default behaviour is to pass most +// exceptions to it. This macro undoes that so that eCos handles the +// exception. So use it with care. + +#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \ + CYG_MACRO_START \ + if( (void*)_poldvsr_ != (void*)NULL ) \ + *(CYG_ADDRESS *)_poldvsr_ = cyg_hal_vsr_table[_vector_]; \ + cyg_hal_vsr_table[_vector_] = rom_vsr_table[_vector_]; \ + CYG_MACRO_END + +// ------------------------------------------------------------------------- +// Interrupt control macros. + +// The following interrupt control macros are the default for the ColdFire +// architecture. Some processor variants will override these definitions in +// their var_intr.h file. + +#ifndef HAL_CF_SET_SR +#define HAL_CF_SET_SR(__newsr__) \ + CYG_MACRO_START \ + asm volatile ("move.w %0,%%sr\n" \ + : \ + : "d" ((CYG_INTERRUPT_STATE)(__newsr__))); \ + CYG_MACRO_END +#endif // HAL_CF_SET_SR + +#ifndef HAL_ENABLE_INTERRUPTS +#define HAL_ENABLE_INTERRUPTS() \ + CYG_MACRO_START \ + CYG_INTERRUPT_STATE _msk_; \ + HAL_QUERY_INTERRUPTS(_msk_); \ + HAL_CF_SET_SR((_msk_ & (CYG_INTERRUPT_STATE)0xf8ff)); \ + CYG_MACRO_END +#endif // HAL_ENABLE_INTERRUPTS + +#ifndef HAL_DISABLE_INTERRUPTS +#define HAL_DISABLE_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + HAL_QUERY_INTERRUPTS(_old_); \ + HAL_CF_SET_SR((_old_ | (CYG_INTERRUPT_STATE)0x0700)); \ + CYG_MACRO_END +#endif //HAL_DISABLE_INTERRUPTS + +#ifndef HAL_RESTORE_INTERRUPTS +#define HAL_RESTORE_INTERRUPTS(_prev_) \ + CYG_MACRO_START \ + CYG_INTERRUPT_STATE _msk_; \ + HAL_QUERY_INTERRUPTS(_msk_); \ + _msk_ &= (CYG_INTERRUPT_STATE)0xf8ff; \ + _msk_ |= (((CYG_INTERRUPT_STATE)(_prev_)) \ + & (CYG_INTERRUPT_STATE)0x0700); \ + asm volatile ("move.w %0,%%sr\n" \ + : \ + : "d" (_msk_)); \ + CYG_MACRO_END +#endif // HAL_RESTORE_INTERRUPTS + +// Use the extra assignment to avoid warnings. +// The compiler should optimize it out. +#ifndef HAL_QUERY_INTERRUPTS +#define HAL_QUERY_INTERRUPTS(__oldmask__) \ + CYG_MACRO_START \ + CYG_INTERRUPT_STATE _omsk_ = (CYG_INTERRUPT_STATE)(__oldmask__); \ + asm volatile ("move.w %%sr,%0\n" \ + : "=d" (_omsk_) \ + : ); \ + (__oldmask__) = (__typeof__(__oldmask__))_omsk_; \ + CYG_MACRO_END +#endif // HAL_QUERY_INTERRUPTS + +// --------------------------------------------------------------------------- +// End of hal_intr.h +#endif // ifndef CYGONCE_HAL_HAL_INTR_H diff --git a/ecos/packages/hal/coldfire/arch/current/include/hal_io.h b/ecos/packages/hal/coldfire/arch/current/include/hal_io.h new file mode 100644 index 0000000..77536c1 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/hal_io.h @@ -0,0 +1,155 @@ +#ifndef CYGONCE_HAL_HAL_IO_H +#define CYGONCE_HAL_HAL_IO_H + +//============================================================================= +// +// hal_io.h +// +// HAL device IO register support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Provide ColdFire-specific IO register definitions. +// Usage: #include <cyg/hal/hal_io.h> +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <cyg/infra/cyg_type.h> + +// --------------------------------------------------------------------------- +// IO Register address. +// This type is for recording the address of an IO register. + +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; + +// --------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + +#define HAL_READ_UINT8( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_BYTE *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + + +// --------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + +#define HAL_READ_UINT16( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_WORD16 *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + +// --------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_WORD32 *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + +// --------------------------------------------------------------------------- +// End of hal_io.h +#endif // ifndef CYGONCE_HAL_HAL_IO_H diff --git a/ecos/packages/hal/coldfire/arch/current/include/hal_startup.h b/ecos/packages/hal/coldfire/arch/current/include/hal_startup.h new file mode 100644 index 0000000..5c7f012 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/include/hal_startup.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_HAL_STARTUP_H +#define CYGONCE_HAL_STARTUP_H + +//============================================================================= +// +// hal_startup.h +// +// HAL startup definitions for the ColdFire architecture +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Provide ColdFire-specific startup definitions. +// Usage: #include <cyg/hal/hal_startup.h> +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_intr.h> + +// Include the variant-specific startup header +#include <cyg/hal/var_startup.h> + +externC void hal_reset(void) __attribute__ ((section (".boot"))); + +// --------------------------------------------------------------------------- +// End of hal_startup.h +#endif // CYGONCE_HAL_STARTUP_H diff --git a/ecos/packages/hal/coldfire/arch/current/src/coldfire.ld b/ecos/packages/hal/coldfire/arch/current/src/coldfire.ld new file mode 100644 index 0000000..a1465cd --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/src/coldfire.ld @@ -0,0 +1,266 @@ +//========================================================================== +// +// coldfire.ld +// +// Linker script +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Coldfire-specific linker script definitions. +// +//####DESCRIPTIONEND#### +//======================================================================== + +STARTUP(vectors.o) +ENTRY(_start) +#ifdef EXTRAS +INPUT(extras.o) +#endif +#if (__GNUC__ >= 3) +GROUP(libtarget.a libgcc.a libsupc++.a) +#else +GROUP(libtarget.a libgcc.a) +#endif + +#define ALIGN_LMA 4 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#define SECTIONS_BEGIN + +#define SECTION_boot(_region_, _vma_, _lma_) \ + .boot _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + *(.boot*) \ + . = ALIGN(4); \ + } \ + > _region_ + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { \ + _stext = .; \ + *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) \ + . = ALIGN(4); \ + } \ + > _region_ \ + _etext = .; PROVIDE (etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + *(.fini) \ + . = ALIGN(4); \ + } \ + > _region_ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + *(.rodata1*) \ + . = ALIGN(4); \ + } \ + > _region_ + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + *(.rodata*) \ + . = ALIGN(4); \ + } \ + > _region_ + +#define SECTION_fixup(_region_, _vma_, _lma_) \ + .fixup _vma_ : _lma_ \ + { \ + __FIXUP_START__ = ABSOLUTE(.); \ + *(.fixup) \ + . = ALIGN(4); \ + __FIXUP_END__ = ABSOLUTE(.); \ + } \ + > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { \ + __EXCEPT_START__ = ABSOLUTE(.); \ + *(.gcc_except_table) \ + . = ALIGN(4); \ + __EXCEPT_END__ = ABSOLUTE(.); \ + } \ + > _region_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { \ + __ram_data_start = ABSOLUTE(.); \ + *(.data*) \ + __GOT1_START__ = ABSOLUTE(.); \ + *(.got1) \ + __GOT1_END__ = ABSOLUTE(.); \ + . = ALIGN (4); \ + /* Put .ctors and .dtors next to the .got2 section, so that */ \ + /* the pointers get relocated with -mrelocatable. */ \ + __CTOR_LIST__ = ABSOLUTE(.); \ + KEEP(*(SORT(.ctors*))); \ + __CTOR_END__ = ABSOLUTE(.); \ + __DTOR_LIST__ = ABSOLUTE(.); \ + KEEP(*(SORT(.dtors*))) \ + __DTOR_END__ = ABSOLUTE(.); \ + . = ALIGN(4); \ + KEEP(*( SORT (.ecos.table.*))); \ + . = ALIGN (4); \ + *( .2ram.*) ; \ + __GOT2_START__ = ABSOLUTE(.); \ + *(.got2) \ + __GOT2_END__ = ABSOLUTE(.); \ + __GOT_START = ABSOLUTE(.); \ + _GLOBAL_OFFSET_TABLE_ = ABSOLUTE(. + 32768); \ + _SDA_BASE_ = ABSOLUTE(.); \ + *(.got.plt) *(.got) \ + __GOT_END__ = ABSOLUTE(.); \ + *(.dynamic) \ + *(.eh_frame) \ + /* We want the small data sections together, so single-instruction */ \ + /* offsets can access them all, and initialized data all before */ \ + /* uninitialized, so we can shorten the on-disk segment size. */ \ + __SDATA_START__ = ABSOLUTE(.); \ + *(.sdata) *(.sdata.*) \ + __SDATA2_START__ = ABSOLUTE(.); \ + *(.sdata2*) \ + . = ALIGN(4); \ + __ram_data_end = ABSOLUTE(.); \ + __ram_data_size = ABSOLUTE (.) - ABSOLUTE(__ram_data_start); \ + } \ + > _region_ \ + __rom_data_start = LOADADDR(.data); \ + __rom_data_size = SIZEOF(.data); \ + __rom_data_end = __rom_data_start + __rom_data_size; + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { \ + __bss_start = ABSOLUTE (.); \ + FORCE_OUTPUT; \ + *(.dynbss*) *(.bss*) *(COMMON) *(.sbss*) *(.scommon*) \ + . = ALIGN(4); \ + __bss_end = ABSOLUTE (.); \ + __bss_size = ABSOLUTE (.) - ABSOLUTE(__bss_start); \ + } \ + > _region_ + +#define SECTION_stab \ + .stab 0 (NOLOAD) : \ + { \ + *(.stab) \ + } + +#define SECTION_stabstr \ + .stabstr 0 (NOLOAD) : \ + { \ + *(.stabstr) \ + } + +#define SECTION_comment \ + .comment 0 (NOLOAD) : \ + { \ + *(.comment) \ + } + +#define SECTION_uninvar(_region_, _vma_, _lma_) \ + .uninvar _vma_ : _lma_ \ + { \ + __uninvar_start = ABSOLUTE (.); \ + FORCE_OUTPUT; \ + *(.uninvar); \ + . = ALIGN(4); \ + __uninvar_end = ABSOLUTE (.); \ + __uninvar_size = ABSOLUTE (.) - ABSOLUTE(__uninvar_start); \ + } \ + > _region_ + +#define SECTION_romvec(_region_, _vma_, _lma_) \ + .romvec _vma_ : _lma_ \ + { \ + __romvec_start = ABSOLUTE (.); \ + FORCE_OUTPUT; \ + KEEP(*(.romvec)); \ + . = ALIGN(4); \ + __romvec_end = ABSOLUTE (.); \ + __romvec_size = ABSOLUTE (.) - ABSOLUTE(__romvec_start); \ + } \ + > _region_ + +#define SECTION_ramvec(_region_, _vma_, _lma_) \ + .ramvec _vma_ : _lma_ \ + { \ + __ramvec_start = ABSOLUTE (.); \ + FORCE_OUTPUT; \ + KEEP(*(.ramvec)); \ + . = ALIGN(4); \ + __ramvec_end = ABSOLUTE (.); \ + __ramvec_size = ABSOLUTE (.) - ABSOLUTE(__ramvec_start); \ + } \ + > _region_ + +#define SECTION_virtual_vec_table(_region_, _vma_, _lma_) \ + .virtual_vec_table _vma_ : _lma_ \ + { \ + __virtual_vec_table_start = ABSOLUTE (.); \ + . += 0x100; \ + __virtual_vec_table_end = ABSOLUTE (.); \ + __virtual_vec_table_size = ABSOLUTE (.) - ABSOLUTE(__virtual_vec_table_start); \ + } \ + > _region_ + +#define SECTIONS_END \ + SECTION_stab \ + SECTION_stabstr \ + SECTION_comment \ + . = ALIGN(0x4); _end = .; PROVIDE (end = .); + +#include <pkgconf/system.h> +#include CYGHWR_MEMORY_LAYOUT_LDI + +hal_virtual_vector_table = __virtual_vec_table_start; diff --git a/ecos/packages/hal/coldfire/arch/current/src/coldfire_stub.c b/ecos/packages/hal/coldfire/arch/current/src/coldfire_stub.c new file mode 100644 index 0000000..b6f662e --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/src/coldfire_stub.c @@ -0,0 +1,269 @@ +//======================================================================== +// +// coldfire_stub.c +// +// Helper functions for stub +// +//======================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Helper functions for stub, generic to all ColdFire +// processors. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <stddef.h> +#include <string.h> // memcpy, memset + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +#include <cyg/hal/hal_stub.h> + +#include <cyg/hal/hal_stub.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT +#include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id +#endif + +// Given a trap value TRAP, return the corresponding signal. +int __computeSignal (unsigned int trap_number) +{ + switch (trap_number) + { + + case CYGNUM_HAL_VECTOR_BUSERR: + case CYGNUM_HAL_VECTOR_ADDRERR: + return SIGBUS; + + case CYGNUM_HAL_VECTOR_ILLINST: + case CYGNUM_HAL_VECTOR_UNSUPINST: + return SIGILL; + + case CYGNUM_HAL_VECTOR_ZERODIV: + case CYGNUM_HAL_VECTOR_FP_BRANCH: + case CYGNUM_HAL_VECTOR_FP_INEXACT: + case CYGNUM_HAL_VECTOR_FP_ZERODIV: + case CYGNUM_HAL_VECTOR_FP_UNDERFLOW: + case CYGNUM_HAL_VECTOR_FP_OPERAND: + case CYGNUM_HAL_VECTOR_FP_OVERFLOW: + case CYGNUM_HAL_VECTOR_FP_NAN: + case CYGNUM_HAL_VECTOR_FP_DENORM: + // Although not quite accurate, use this signal also for + // integer division. + return SIGFPE; + + case CYGNUM_HAL_VECTOR_PRIVVIOLATION: + return SIGILL; + case CYGNUM_HAL_VECTOR_TRACE: + // Instruction trace + return SIGTRAP; + + case CYGNUM_HAL_VECTOR_L1010: + case CYGNUM_HAL_VECTOR_L1111: + case CYGNUM_HAL_VECTOR_UNINITINT: + case CYGNUM_HAL_VECTOR_SPURINT: + return SIGTRAP; + + case CYGNUM_HAL_VECTOR_TRAPFIRST ... CYGNUM_HAL_VECTOR_TRAPLAST: + return SIGTRAP; + + case CYGNUM_HAL_VECTOR_AUTOVEC1 ... CYGNUM_HAL_VECTOR_AUTOVEC7: + case CYGNUM_HAL_VECTOR_USERINTRFIRST ... CYGNUM_HAL_VECTOR_USERINTRLAST: + // External interrupt + return SIGINT; + + default: + return SIGTERM; + } +} + + +// Return the trap number corresponding to the last-taken trap. +int __get_trap_number (void) +{ + // The vector is not not part of the GDB register set so get it + // directly from the saved context. + return HAL_CF_EXCEPTION_VECTOR(_hal_registers->fmt_vec_word); +} + + +// Set the currently-saved pc register value to PC. +void set_pc (target_register_t pc) +{ + put_register (PC, pc); +} + + +// Return the offset of a register in the GDB_Registers structure. +static int reg_offset(regnames_t reg) +{ + switch(reg) + { + case D0 ... A7: + return reg * 4; + + case SR: + return offsetof(GDB_Registers, sr); + + default: + case PC: + return offsetof(GDB_Registers, pc); + } +} + + +// Return the currently-saved value corresponding to register REG of +// the exception context. +target_register_t get_register(regnames_t reg) +{ + target_register_t val; + int offset = reg_offset(reg); + + if (REGSIZE(reg) > sizeof(target_register_t)) + return -1; + + val = _registers[offset/sizeof(target_register_t)]; + + return val; +} + + +// Store VALUE in the register corresponding to WHICH in the exception +// context. +void put_register(regnames_t which, target_register_t value) +{ + int offset = reg_offset(which); + + if (REGSIZE(which) > sizeof(target_register_t)) + return; + + _registers[offset/sizeof(target_register_t)] = value; +} + + +// Write the contents of register WHICH into VALUE as raw bytes. This +// is only used for registers larger than sizeof(target_register_t). +// Return non-zero if it is a valid register. +int get_register_as_bytes(regnames_t which, char *value) +{ + int offset = reg_offset(which); + + memcpy (value, (char *)_registers + offset, REGSIZE(which)); + return 1; +} + + +// Alter the contents of saved register WHICH to contain VALUE. This +// is only used for registers larger than sizeof(target_register_t). +// Return non-zero if it is a valid register. +int put_register_as_bytes(regnames_t which, char *value) +{ + int offset = reg_offset(which); + + memcpy ((char *)_registers + offset, value, REGSIZE(which)); + return 1; +} + + +// --------------------------------------------------------------------- +// Single-step support + +// Set things up so that the next user resume will execute one instruction. +// This may be done by setting breakpoints or setting a single step flag +// in the saved user registers, for example. + +#define SR_TRACE 0x8000 + +void __single_step(void) +{ + target_register_t sr = get_register (SR); + + // Set trace flag in the exception context. + sr |= SR_TRACE; + + put_register (SR, sr); +} + + +// Clear the single-step state. +void __clear_single_step(void) +{ + target_register_t sr = get_register (SR); + + // Clear single-step flag in the exception context. + sr &= ~SR_TRACE; + + put_register (SR, sr); +} + + +void __install_breakpoints(void) +{ + // NOP since single-step HW exceptions are used instead of + // breakpoints. +} + + +void __clear_breakpoints(void) +{ + // NOP since single-step HW exceptions are used instead of + // breakpoints. +} + + +// If the breakpoint we hit is in the breakpoint() instruction, return a +// non-zero value. +int __is_breakpoint_function(void) +{ + return (get_register(PC) == (target_register_t) &CYG_LABEL_NAME(_breakinst)); +} + + +// Skip the current instruction. Since this is only called by the +// stub when the PC points to a breakpoint or trap instruction, +// we can safely just skip 2. +void __skipinst(void) +{ + put_register (PC, get_register (PC) + HAL_BREAKINST_SIZE); +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS diff --git a/ecos/packages/hal/coldfire/arch/current/src/context.S b/ecos/packages/hal/coldfire/arch/current/src/context.S new file mode 100644 index 0000000..60e02b2 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/src/context.S @@ -0,0 +1,250 @@ +|============================================================================= +| +| context.S +| +| ColdFire architecture context switch code +| +|============================================================================= +| ####ECOSGPLCOPYRIGHTBEGIN#### +| ------------------------------------------- +| This file is part of eCos, the Embedded Configurable Operating System. +| Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +| +| eCos is free software; you can redistribute it and/or modify it under +| the terms of the GNU General Public License as published by the Free +| Software Foundation; either version 2 or (at your option) any later +| version. +| +| eCos is distributed in the hope that it will be useful, but WITHOUT +| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +| FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +| for more details. +| +| You should have received a copy of the GNU General Public License +| along with eCos; if not, write to the Free Software Foundation, Inc., +| 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +| +| As a special exception, if other files instantiate templates or use +| macros or inline functions from this file, or you compile this file +| and link it with other works to produce a work based on this file, +| this file does not by itself cause the resulting work to be covered by +| the GNU General Public License. However the source code for this file +| must still be made available in accordance with section (3) of the GNU +| General Public License v2. +| +| This exception does not invalidate any other reasons why a work based +| on this file might be covered by the GNU General Public License. +| ------------------------------------------- +| ####ECOSGPLCOPYRIGHTEND#### +|============================================================================= +|#####DESCRIPTIONBEGIN#### +| +| Author(s): Enrico Piria +| Contributors: +| Date: 2005-25-06 +| Purpose: This file contains implementations of the thread context +| switch routines. It also contains the longjmp() and setjmp() +| routines. +| +|####DESCRIPTIONEND#### +|======================================================================== + + +#include <pkgconf/hal.h> +#include <cyg/hal/cf_offsets.inc> +#include <cyg/hal/arch.inc> + + +| ---------------------------------------------------------------------------- +| hal_thread_switch_context - Switch between two threads +| +| externC void hal_thread_switch_context(CYG_ADDRESS to, CYG_ADDRESS from) +| +| INPUT: +| 0(%sp) : return address +| 4(%sp) : to - address of sp of next thread to execute +| 8(%sp) : from - address of sp save location of current thread +| +| OUTPUT: +| None +| +| RETURN VALUE: +| None +| +| d0, d1, a0, a1 are ours to abuse. Other registers are not touched. + +FUNC_START(hal_thread_switch_context) + + ctx_save_registers + + | Read to and from parameters from the stack + move.l CYGARC_CF_CONTEXT_SIZE+4(%sp),%a0 + move.l CYGARC_CF_CONTEXT_SIZE+8(%sp),%a1 + + | Store this thread's current stack pointer to *from + move.l %sp,(%a1) + + | Load the stack pointer for the next thread from *to + move.l (%a0),%sp + + ctx_restore_registers + + | Return to caller + rts + + +| ---------------------------------------------------------------------------- +| hal_thread_load_context - Load thread context +| +| externC void hal_thread_load_context(CYG_ADDRESS to) +| +| INPUT: +| 4(%sp) : to - address of sp of next thread to execute +| +| OUTPUT: +| None +| +| RETURN VALUE: +| None +| +| d0, d1, a0, a1 are ours to abuse. + +FUNC_START(hal_thread_load_context) + + | Read the to parameter from the stack and switch to that stack + | pointer + move.l 4(%sp),%a0 + move.l (%a0),%sp + + | Load all of the preserved registers from the stack + movem.l CYGARC_CFREG_DREGS(%sp),%d0-%d7 + movem.l CYGARC_CFREG_AREGS(%sp),%a0-%a6 + + | Starting SR + move.w CYGARC_CF_SR(%sp), %d0 + move.w %d0,%sr + + | Deallocate context frame + lea CYGARC_CF_CONTEXT_SIZE(%sp),%sp + + | Return + rts + + +| ---------------------------------------------------------------------------- +| The following routines are based on the hal_jmp_buf structure layout, defined +| in hal_arch.h + +| ---------------------------------------------------------------------------- +| hal_setjmp - setjmp for the ColdFire architecture +| +| externC int hal_setjmp(hal_jmp_buf env) +| +| INPUT: +| 0(%sp) : return address +| 4(%sp) : env - address of a hal_jmp_buf structure +| +| OUTPUT: +| None +| +| RETURN VALUE: +| This routine always returns zero in d0.l. +| +| d0, d1, a0, a1 are ours to abuse. + +FUNC_START(hal_setjmp) + + | Get a pointer to the register buffer + move.l 4(%sp),%a0 + + | Store all of the preserved registers + movem.l %d2-%d7,CYGARC_JMPBUF_REG_D2(%a0) + movem.l %a2-%a6,CYGARC_JMPBUF_REG_A2(%a0) + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + | Store MAC registers + + | Store MACSR register + move.l %macsr,%d0 + move.l %d0,CYGARC_JMPBUF_REG_MACSR(%a0) + + | Switch to integer mode. This allows to save the contents of ACC + | without rounding + and.l #0x000000df,%d0 + move.l %d0,%macsr + + | Store ACC register + move.l %acc,%d0 + move.l %d0,CYGARC_JMPBUF_REG_MACC(%a0) + + | Store MASK register + move.l %mask,%d0 + move.l %d0,CYGARC_JMPBUF_REG_MASK(%a0) +#endif + + | Store the stack pointer + move.l %sp,CYGARC_JMPBUF_REG_SP(%a0) + + | Store the return address into the structure + move.l (%sp),CYGARC_JMPBUF_REG_PC(%a0) + + | Load a zero return value + clr.l %d0 + + | Return + rts + + +| ---------------------------------------------------------------------------- +| hal_longjmp - longjmp for the ColdFire architecture +| +| externC void hal_longjmp(hal_jmp_buf env, int val) +| +| INPUT: +| 0(%sp): return address +| 4(%sp): env - address of a hal_jmp_buf structure +| 8(%sp): val - the non-zero value to return +| +| OUTPUT: +| None +| +| RETURN VALUE: +| This routine always returns the value from the val parameter in d0.l +| and to the location of the PC in the env structure. + +FUNC_START(hal_longjmp) + + | Load the return value parameter + move.l 8(%sp),%d0 + + | Get a pointer to the buffer to read our state from + move.l 4(%sp),%a0 + + | Load all of the preserved registers + movem.l CYGARC_JMPBUF_REG_D2(%a0),%d2-%d7 + movem.l CYGARC_JMPBUF_REG_A2(%a0),%a2-%a6 + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + | Load MAC registers + + | Load MACSR register + move.l CYGARC_JMPBUF_REG_MACSR(%a0),%d1 + move.l %d1,%macsr + + | Load ACC register + move.l CYGARC_JMPBUF_REG_MACC(%a0),%d1 + move.l %d1,%acc + + | Load MASK register + move.l CYGARC_JMPBUF_REG_MASK(%a0),%d1 + move.l %d1,%mask +#endif + + | Load the stack pointer + move.l CYGARC_JMPBUF_REG_SP(%a0),%sp + + | Load return address and store it on stack + move.l CYGARC_JMPBUF_REG_PC(%a0),(%sp) + + | Return to caller + rts diff --git a/ecos/packages/hal/coldfire/arch/current/src/hal_misc.c b/ecos/packages/hal/coldfire/arch/current/src/hal_misc.c new file mode 100644 index 0000000..e8b4bc0 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/src/hal_misc.c @@ -0,0 +1,199 @@ +//========================================================================== +// +// hal_misc.c +// +// HAL miscellaneous functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Miscellaneous routine and variable definitions. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros +#include <cyg/infra/diag.h> // diag_printf + +#include <cyg/hal/hal_arch.h> // HAL header + +#include <cyg/hal/hal_intr.h> // VSR/ISR defines + +// ------------------------------------------------------------------------- +// ISR table + +volatile CYG_ADDRESS cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +volatile CYG_ADDRESS cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +// ------------------------------------------------------------------------- +// VSR table + +externC void __handle_exception(void); + +externC HAL_SavedRegisters * _hal_registers; + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +externC void* volatile __mem_fault_handler; +#endif + +// Defined in variant HAL +externC void hal_interrupt_update_level(void); + +// -------------------------------------------------------------------------- +// Default exception handler. + +void hal_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs) +{ + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + + // If we caught an exception inside the stubs, see if we were expecting it + // and if so jump to the saved address. + if (__mem_fault_handler) { + regs->pc = (CYG_ADDRWORD)__mem_fault_handler; + // Caught an exception inside stubs + return; + } + + // Set the pointer to the registers of the current exception + // context. At entry the GDB stub will expand the + // HAL_SavedRegisters structure into a (bigger) register array. + _hal_registers = regs; + + __handle_exception(); + +#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + defined(CYGPKG_HAL_EXCEPTIONS) + + // We should decode the vector and pass a more appropriate + // value as the second argument. For now we simply pass a + // pointer to the saved registers. We should also divert + // breakpoint and other debug vectors into the debug stubs. + + cyg_hal_deliver_exception(vector, (CYG_ADDRWORD)regs); + +#else + + CYG_FAIL("Exception!!!"); + +#endif + + return; +} + +// -------------------------------------------------------------------------- +// Default ISR handler. + +cyg_uint32 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + CYG_FAIL("Unexpected ISR"); + return 0; +} + +// -------------------------------------------------------------------------- +// Default spurious interrupt handler. This routine is called with all +// interrupts disabled. + +#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + +void hal_spurious_interrupt(HAL_SavedRegisters *regs) CYGBLD_ATTRIB_WEAK; + +void hal_spurious_interrupt(HAL_SavedRegisters *regs) +{ + CYG_FAIL("Spurious interrupt!!"); +} + +#endif + +// -------------------------------------------------------------------------- +// Idle thread action. + +void hal_idle_thread_action(cyg_uint32 count) +{ +} + +// ----------------------------------------------------------------------- +// Determine the index of the ls bit of the supplied mask. + +cyg_uint32 hal_lsbit_index(cyg_uint32 mask) +{ + cyg_uint32 n = mask; + + static const signed char tab[64] = + { -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10, + 4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11, + 5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0, + 0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0 + }; + + n &= ~(n-1UL); + n = (n<<16)-n; + n = (n<<6)+n; + n = (n<<4)+n; + + return tab[n>>26]; +} + +// ----------------------------------------------------------------------- +// Determine the index of the ms bit of the supplied mask. + +cyg_uint32 hal_msbit_index(cyg_uint32 mask) +{ + cyg_uint32 x = mask; + cyg_uint32 w; + + // Phase 1: make word with all ones from that one to the right + x |= x >> 16; + x |= x >> 8; + x |= x >> 4; + x |= x >> 2; + x |= x >> 1; + + // Phase 2: calculate number of "1" bits in the word + w = (x & 0x55555555) + ((x >> 1) & 0x55555555); + w = (w & 0x33333333) + ((w >> 2) & 0x33333333); + w = w + (w >> 4); + w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F); + return (cyg_uint32)((w + (w >> 16)) & 0xFF) - 1; + +} diff --git a/ecos/packages/hal/coldfire/arch/current/src/hal_mk_defs.c b/ecos/packages/hal/coldfire/arch/current/src/hal_mk_defs.c new file mode 100644 index 0000000..ab57c4d --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/src/hal_mk_defs.c @@ -0,0 +1,125 @@ +//========================================================================== +// +// hal_mk_defs.c +// +// HAL "make defs" program +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: gthomas, jskov +// Date: 2005-25-06 +// Purpose: ColdFire architecture dependent definition generator +// Description: This file contains code that can be compiled by the target +// compiler and used to generate machine specific definitions +// suitable for use in assembly code. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +# include <cyg/kernel/instrmnt.h> +#endif + +// This program is used to generate definitions needed by +// assembly language modules. +// +// This technique was first used in the OSF Mach kernel code: +// generate asm statements containing #defines, +// compile this file to assembler, and then extract the +// #defines from the assembly-language output. + +#define DEFINE(sym, val) \ + asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val)) + +int +main(void) +{ + // Exception/interrupt/context save buffer + DEFINE(CYGARC_CFREG_AREGS, offsetof(HAL_SavedRegisters, a[0])); + DEFINE(CYGARC_CFREG_DREGS, offsetof(HAL_SavedRegisters, d[0])); + DEFINE(CYGARC_CFREG_A0, offsetof(HAL_SavedRegisters, a[0])); + DEFINE(CYGARC_CFREG_A1, offsetof(HAL_SavedRegisters, a[1])); + DEFINE(CYGARC_CFREG_A2, offsetof(HAL_SavedRegisters, a[2])); + DEFINE(CYGARC_CFREG_A6, offsetof(HAL_SavedRegisters, a[6])); + DEFINE(CYGARC_CFREG_D0, offsetof(HAL_SavedRegisters, d[0])); + DEFINE(CYGARC_CFREG_D1, offsetof(HAL_SavedRegisters, d[1])); + DEFINE(CYGARC_CFREG_D2, offsetof(HAL_SavedRegisters, d[2])); + DEFINE(CYGARC_CFREG_PC, offsetof(HAL_SavedRegisters, pc)); + DEFINE(CYGARC_CFREG_SP, offsetof(HAL_SavedRegisters, a[7])); + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + DEFINE(CYGARC_CFREG_MACC, offsetof(HAL_SavedRegisters, macc)); + DEFINE(CYGARC_CFREG_MACSR, offsetof(HAL_SavedRegisters, macsr)); + DEFINE(CYGARC_CFREG_MASK, offsetof(HAL_SavedRegisters, mask)); +#endif + + DEFINE(CYGARC_CF_CONTEXT_SIZE, sizeof(HAL_SavedRegisters)); + + // Below only saved on exceptions/interrupts + DEFINE(CYGARC_CF_FMTVECWORD, offsetof(HAL_SavedRegisters, fmt_vec_word)); + DEFINE(CYGARC_CF_SR, offsetof(HAL_SavedRegisters, sr)); + DEFINE(CYGARC_CF_EXCEPTION_SIZE, sizeof(HAL_SavedRegisters)); + DEFINE(CYGARC_CF_EXCEPTION_DECREMENT, offsetof(HAL_SavedRegisters, fmt_vec_word)); + + // Some other exception related definitions + DEFINE(CYGNUM_HAL_ISR_MIN, CYGNUM_HAL_ISR_MIN); + DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT); + DEFINE(CYGNUM_HAL_SPURIOUS_INTERRUPT, CYGNUM_HAL_SPURIOUS_INTERRUPT); + DEFINE(CYGNUM_HAL_VECTOR_DEBUGTRAP, CYGNUM_HAL_VECTOR_DEBUGTRAP); + + // setjmp/longjmp related definitions + DEFINE(CYGARC_JMPBUF_REG_D2, offsetof(hal_jmp_buf_t, d2)); + DEFINE(CYGARC_JMPBUF_REG_A2, offsetof(hal_jmp_buf_t, a2)); + DEFINE(CYGARC_JMPBUF_REG_SP, offsetof(hal_jmp_buf_t, sp)); + DEFINE(CYGARC_JMPBUF_REG_PC, offsetof(hal_jmp_buf_t, pc)); + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + DEFINE(CYGARC_JMPBUF_REG_MACC, offsetof(hal_jmp_buf_t, macc)); + DEFINE(CYGARC_JMPBUF_REG_MACSR, offsetof(hal_jmp_buf_t, macsr)); + DEFINE(CYGARC_JMPBUF_REG_MASK, offsetof(hal_jmp_buf_t, mask)); +#endif + + return 0; +} + +// ------------------------------------------------------------------------- +// EOF hal_mk_defs.c diff --git a/ecos/packages/hal/coldfire/arch/current/src/hal_startup.c b/ecos/packages/hal/coldfire/arch/current/src/hal_startup.c new file mode 100644 index 0000000..4cda925 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/src/hal_startup.c @@ -0,0 +1,253 @@ +//========================================================================== +// +// hal_startup.c +// +// ColdFire architecture HAL startup code +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Architecture startup code. +// Description: This module contains code that sets up the hardware and the +// memory sections. All the code must be contained in the +// section called ".boot", in order for the ROMRAM startup +// to work properly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_startup.h> +#include CYGHWR_MEMORY_LAYOUT_H +#include <cyg/hal/hal_if.h> // hal_if_init +#include <cyg/hal/hal_intr.h> // Interrupt definitions +#include <cyg/hal/hal_stub.h> // initialize_stub + +externC void cyg_start(void); +externC void hal_ctrlc_isr_init(void); + +static void hal_vsr_init(void) __attribute__ ((section (".boot"))); +static void hal_isr_init(void) __attribute__ ((section (".boot"))); +static void hal_init_ram_sections(void) __attribute__ ((section (".boot"))); +static void cyg_hal_invoke_constructors(void) __attribute__ ((section (".boot"))); + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + +externC unsigned char __romram_copy_source[]; +externC unsigned char __romram_copy_dest[]; +externC unsigned char __romram_copy_length[]; + +#endif + + +// ------------------------------------------------------------------------- +// Reset vector routine. + +void hal_reset(void) +{ + // Do any variant-specific reset initialization + var_reset(); + + // Do any platform-specific reset initialization + plf_reset(); + + // Initialize the RAM sections that the rest of the C code requires + hal_init_ram_sections(); + + // All program sections are now in place + + // Make sure that every instruction above this one has been output by + // the compiler + HAL_REORDER_BARRIER(); + + // Now it is safe to use a stack in RAM + asm volatile ("lea cyg_interrupt_stack, %sp"); + + // It is now safe to call C functions which may rely on initialized + // data + hal_vsr_init(); + hal_isr_init(); + + // Initialize variant HAL private data + var_init_data(); + + // Initialize platform HAL private data + plf_init_data(); + + // Initialize the virtual vector table + hal_if_init(); + + // Call C++ constructors + cyg_hal_invoke_constructors(); + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + initialize_stub(); +#endif + + // Init Ctrl-C debug ISR +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ + || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) + hal_ctrlc_isr_init(); +#endif + + // Call cyg_start. This routine should not return. + cyg_start(); +} + + +// ------------------------------------------------------------------------- +// Initialize the vector table. + +static void hal_vsr_init(void) +{ + unsigned int i; + + // If we are starting up from ROM, or we are starting in + // RAM and NOT using a ROM monitor, initialize the VSR and ISR tables. +#if defined(CYG_HAL_STARTUP_ROM) || \ + defined(CYG_HAL_STARTUP_ROMRAM) || \ + (defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + // Initialize the HAL's vector table with the ROM vector table + for (i = 0; i < CYGNUM_HAL_VSR_COUNT; i++) + cyg_hal_vsr_table[i] = rom_vsr_table[i]; + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + // We only take control of the interrupt vectors, + // the rest are left to the ROM for now. + cyg_hal_vsr_table[CYGNUM_HAL_VECTOR_UNINITINT] = + rom_vsr_table[CYGNUM_HAL_VECTOR_UNINITINT]; + + cyg_hal_vsr_table[CYGNUM_HAL_VECTOR_SPURINT] = + rom_vsr_table[CYGNUM_HAL_VECTOR_SPURINT]; + + for(i = 0; i < CYGNUM_HAL_NUMAUTOVEC; i++) + cyg_hal_vsr_table[CYGNUM_HAL_VECTOR_AUTOVEC1 + i] = + rom_vsr_table[CYGNUM_HAL_VECTOR_AUTOVEC1 + i]; + + for(i = 0; i < CYGNUM_HAL_NUMUSERINTR; i++) + cyg_hal_vsr_table[CYGNUM_HAL_VECTOR_USERINTRFIRST + i] = + rom_vsr_table[CYGNUM_HAL_VECTOR_USERINTRFIRST + i]; + +#endif +} + + +// ------------------------------------------------------------------------- +// Initialize the ISRs. + +static void hal_isr_init(void) +{ + int i; + + // Initialize all ISR entries to default + for (i = 0; i < CYGNUM_HAL_ISR_COUNT; i++) + { + cyg_hal_interrupt_handlers[i] = (CYG_ADDRESS) &hal_default_isr; + cyg_hal_interrupt_data[i] = (CYG_ADDRWORD) 0; + cyg_hal_interrupt_objects[i] = (CYG_ADDRESS) 0; + } +} + + +// ------------------------------------------------------------------------- +// Initialize the RAM sections +// For an efficient copy, we suppose that the sections are aligned at a +// 4-byte boundary and are a multiple of 4 bytes. Linker scripts should +// guarantee this. + +static void hal_init_ram_sections(void) +{ + cyg_uint32 *m; + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) + { + // Initialize the RAM data section from the ROM image of the data + // section. + cyg_uint32 *p = (cyg_uint32 *) __romram_copy_dest; + cyg_uint32 *q = (cyg_uint32 *) __romram_copy_source; + cyg_uint32 length = 0; + + while (length < (cyg_uint32) __romram_copy_length) + { + *p++ = *q++; + length += 4; + } + } +#endif + + // Initialize the bss sections to zero + m = (cyg_uint32 *) __bss_start; + while (m != (cyg_uint32 *) __bss_end) + *m++ = 0x0; +} + + +// ------------------------------------------------------------------------- +// Call static constructors. + +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG +cyg_bool cyg_hal_stop_constructors; +#endif + +typedef void (*pfunc) (void); +extern pfunc __CTOR_LIST__[]; +extern pfunc __CTOR_END__[]; + +static void cyg_hal_invoke_constructors(void) +{ +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + static pfunc *p = &__CTOR_END__[-1]; + + cyg_hal_stop_constructors = 0; + for (; p >= __CTOR_LIST__; p--) { + (*p) (); + if (cyg_hal_stop_constructors) { + p--; + break; + } + } +#else + pfunc *p; + + for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) + (*p) (); +#endif +} diff --git a/ecos/packages/hal/coldfire/arch/current/src/vectors.S b/ecos/packages/hal/coldfire/arch/current/src/vectors.S new file mode 100644 index 0000000..bf1ab06 --- /dev/null +++ b/ecos/packages/hal/coldfire/arch/current/src/vectors.S @@ -0,0 +1,647 @@ +|========================================================================== +| +| vectors.S +| +| ColdFire exception vectors +| +|========================================================================== +| ####ECOSGPLCOPYRIGHTBEGIN#### +| ------------------------------------------- +| This file is part of eCos, the Embedded Configurable Operating System. +| Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +| +| eCos is free software; you can redistribute it and/or modify it under +| the terms of the GNU General Public License as published by the Free +| Software Foundation; either version 2 or (at your option) any later +| version. +| +| eCos is distributed in the hope that it will be useful, but WITHOUT +| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +| FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +| for more details. +| +| You should have received a copy of the GNU General Public License +| along with eCos; if not, write to the Free Software Foundation, Inc., +| 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +| +| As a special exception, if other files instantiate templates or use +| macros or inline functions from this file, or you compile this file +| and link it with other works to produce a work based on this file, +| this file does not by itself cause the resulting work to be covered by +| the GNU General Public License. However the source code for this file +| must still be made available in accordance with section (3) of the GNU +| General Public License v2. +| +| This exception does not invalidate any other reasons why a work based +| on this file might be covered by the GNU General Public License. +| ------------------------------------------- +| ####ECOSGPLCOPYRIGHTEND#### +|============================================================================= +|#####DESCRIPTIONBEGIN#### +| +| Author(s): Enrico Piria +| Contributors: Wade Jensen +| Date: 2005-25-06 +| Purpose: ColdFire exception vectors +| Description: This file contains the first level default VSRs +| that save and restore state for both exceptions and +| interrupts. +| +|####DESCRIPTIONEND#### +|========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <cyg/hal/cf_offsets.inc> +#include <cyg/hal/arch.inc> +#include <cyg/hal/variant.inc> + +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +| ---------------------------------------------------------------------------- +| Hardware reset vector + + .section ".boot","x" + .balign 4 + .globl cyg_hal_reset_vsr +cyg_hal_reset_vsr: + + | Define the entry point for the linker. + .globl _start +_start: + + | Make sure that all interrupts are masked. + hal_cpu_int_disable + + | Initial setup. Just do the minimum to be able to perform + | initialization in C. + + | Initialize CPU variant + hal_cpu_init + + | Platform specific hardware initialization. + | This may include memory controller initialization. + hal_hardware_init + + | Setup boot stack + hal_boot_stack_init + + | Set up the initial frame pointer. + lea 0,%fp + link %fp,#0 + + | Call the C routine to complete the reset process. + .extern hal_reset + jsr hal_reset + + | If we return, stop. +9: + stop #0x2000 + bra 9b + + +| ---------------------------------------------------------------------------- +| Default exception vector handler +| +| The default handler for all machine exceptions. We save the +| machine state and call the default C exception handler. This routine passes a +| pointer to the saved state to the C exception handler. The stack pointer in +| the saved state points to the the sp before the exception. +| The format/vector word in the exception stack contains the vector +| number. + +| void hal_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs); + + .text + .balign 4 + .globl cyg_hal_default_exception_vsr +cyg_hal_default_exception_vsr: + + | Disable all interrupts + hal_cpu_int_disable + + | Preserve the entire state. + | Allocate space for all registers (including the stack pointer). + | Write all registers to the stack space. + lea.l -CYGARC_CF_EXCEPTION_DECREMENT(%sp),%sp + movem.l %d0-%d7,CYGARC_CFREG_DREGS(%sp) + movem.l %a0-%a6,CYGARC_CFREG_AREGS(%sp) + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + save_mac_registers %d0 +#endif + + | Write the original stack pointer value to the stack. + | The format/vector word, sr, and pc are already on the stack. + find_original_sp %d0 + move.l %d0,CYGARC_CFREG_SP(%sp) + + | Calculate the vector number. The format/vector word on the stack + | contains the vector number. + move.w CYGARC_CF_FMTVECWORD(%sp),%d0 + and.l #0x000003fc,%d0 + lsr.l #2,%d0 + + | Pass a pointer to the saved state to the exception handler. + pea.l (%sp) + + | Push the vector number parameter. + move.l %d0,-(%sp) + + | Call the default exception handler. This routine may modify + | the exception context. + .extern hal_exception_handler + jsr hal_exception_handler + + | Remove the vector number and the state pointer from the stack. + addq.l #2*4,%sp + + | Get a pointer to the location following the exception context. + find_original_sp %d0 + + | Restore all of the registers that we do not need in the following + | code. We will copy all registers that are not restored here + | to the new stack before restoring them. + +#ifdef CYGHWR_HAL_COLDFIRE_MAC + restore_mac_registers %d0 +#endif + + movem.l CYGARC_CFREG_D2(%sp),%d2-%d7 + movem.l CYGARC_CFREG_A1(%sp),%a1-%a6 + + | Load the address of the new SP. + move.l CYGARC_CFREG_SP(%sp),%d1 + + | We now have: + | d0.l : original stack pointer + | d1.l : final stack pointer + + | ColdFire programmer's manual doesn't tell if rte instruction expects + | the stack frame to be aligned at 32-bit boundaries. + | So, we align the new stack value, and adjust the format field + | accordingly. At the end of rte instruction the stack will thus point + | to the desired location. + + | Compare the new stack address to the end of the exception context. + | This will tell us the order that we need to copy the exception + | stack and the remaining registers from the old exception context to + | the new one. The order is important because the stack frames might + | overlap. + cmp.l %d0,%d1 + + | If the new SP and the old one coincide. + beq 2f + + | If the new SP is at a higher address than the old one. + bgt 1f + + | The new SP is at a lower address than the old one. Copy from the + | lowest address to the highest address. + + | Align stack at longword boundary + move.l %d1,%d0 + and.l #0xfffffffc,%d0 + move.l %d0,%a0 + + | Allocate new frame + sub.l #CYGARC_CF_CONTEXT_SIZE,%a0 + + | Copy D0, D1, A0, FVW, SR, and PC from the old stack to the new stack. + | Note that we copy in ascending order. + + | Copy D0, D1, A0 + move.l CYGARC_CFREG_D0(%sp),CYGARC_CFREG_D0(%a0) + move.l CYGARC_CFREG_D1(%sp),CYGARC_CFREG_D1(%a0) + move.l CYGARC_CFREG_A0(%sp),CYGARC_CFREG_A0(%a0) + + | Based on target SP address, construct new format field + and.l #0x00000003,%d1 + or.l #0x4,%d1 + lsl.l #8,%d1 + lsl.l #4,%d1 + + | Load old format field + move.w CYGARC_CF_FMTVECWORD(%sp),%d0 + + | Clear old format field + and.l #0x0fff,%d0 + + | Write the new one + or.l %d1,%d0 + move.w %d0,CYGARC_CF_FMTVECWORD(%a0) + + | Copy SR and PC + move.w CYGARC_CF_SR(%sp),CYGARC_CF_SR(%a0) + move.l CYGARC_CFREG_PC(%sp),CYGARC_CFREG_PC(%a0) + + | A0 points to the top of the new stack + move.l %a0,%sp + + | Restore remaining registers and exit + jmp 2f + +1: + + | The new SP is at a higher address than the old one. Copy from the + | highest address to the lowest address. + + | Align stack at longword boundary + move.l %d1,%d0 + and.l #0xfffffffc,%d0 + move.l %d0,%a0 + + | Allocate new frame + sub.l #CYGARC_CF_CONTEXT_SIZE,%a0 + + | Copy D0, D1, A0, FVW, SR, and PC from the old stack to the new stack. + | Note that we copy in descending order. + + | Copy PC and SR + move.l CYGARC_CFREG_PC(%sp),CYGARC_CFREG_PC(%a0) + move.w CYGARC_CF_SR(%sp),CYGARC_CF_SR(%a0) + + | Based on target SP address, construct new format field + and.l #0x00000003,%d1 + or.l #0x4,%d1 + lsl.l #8,%d1 + lsl.l #4,%d1 + + | Load old format field + move.w CYGARC_CF_FMTVECWORD(%sp),%d0 + + | Clear old format field + and.l #0x0fff,%d0 + + | Write the new one + or.l %d1,%d0 + move.w %d0,CYGARC_CF_FMTVECWORD(%a0) + + | Copy A0, D1, D0 + move.l CYGARC_CFREG_A0(%sp),CYGARC_CFREG_A0(%a0) + move.l CYGARC_CFREG_D1(%sp),CYGARC_CFREG_D1(%a0) + move.l CYGARC_CFREG_D0(%sp),CYGARC_CFREG_D0(%a0) + + | A0 points to the top of the new stack + move.l %a0,%sp + +2: + | Restore remaining registers + move.l CYGARC_CFREG_D0(%sp),%d0 + move.l CYGARC_CFREG_D1(%sp),%d1 + move.l CYGARC_CFREG_A0(%sp),%a0 + add.l #CYGARC_CF_EXCEPTION_DECREMENT,%sp + + | Return from exception + rte + + +| ---------------------------------------------------------------------------- +| Spurious interrupt vector handler +| +| Used for spurious and uninitialized interrupts. +| It is unknown at which priority spurious interrupts are generated. So, the +| safest thing to do is to disable all interrupts while processing spurious +| ones. + + .text + .balign 4 + .globl cyg_hal_default_spurious_vsr +cyg_hal_default_spurious_vsr: + +#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS + + | Disable all interrupts. On the first instruction, interrupt sampling + | is always disabled. + hal_cpu_int_disable + + | Preserve all registers that this handler needs to preserve. + | The C code will preserve all other registers. + int_pres_regs + + | Pass a pointer to the saved state to the interrupt handler. + pea.l (%sp) + + | Call spurious interrupt handler + .extern hal_spurious_interrupt + jsr hal_spurious_interrupt + + | Remove the arguments from the stack. + addq.l #4,%sp + + | Restore the preserved registers for the current thread. + int_rest_regs + +#endif /* ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS */ + + | Just return from interrupt. + rte + + +| ---------------------------------------------------------------------------- +| User interrupt vector handler +| +| Control is transferred here from a user interrupt vector (#64-255). +| Before branching to common code, load a value to translate the +| vector table offset to the ISR table offset. + + .text + .balign 4 + .globl cyg_hal_default_interrupt_vsr +cyg_hal_default_interrupt_vsr: + + | Disable all interrupts. On the first instruction, interrupt sampling + | is always disabled. + hal_cpu_int_disable + + | Preserve all registers that this handler needs to preserve. + | The C code will preserve all other registers. + int_pres_regs + + | It is safe to use breakpoints below this point. + .globl _cyg_hal_default_interrupt_vsr_bp_safe +_cyg_hal_default_interrupt_vsr_bp_safe: + + | Adding this value to the vector table offset will result in the + | corresponding offset into the ISR table. + move.l #(-CYGNUM_HAL_ISR_MIN)*4,%d2 + + | d2.l: Contains a value to translate the vector table offset to + | the ISR table offset. + + | Calculate the vector offset. The format/vector word on the stack + | contains the vector number. Mask off all unused bits. The bit + | position of the vector number field makes it automatically multiplied + | by four. + move.w CYGARC_CF_FMTVECWORD(%sp),%d1 + and.l #0x000003fc,%d1 + + | Calculate the ISR table offset. Add the vector table offset to the + | translation value. + add.l %d1,%d2 + + | Calculate the vector number using the vector table offset. + asr.l #2,%d1 + + | d2.l: Contains the offset into the ISR table. + | d1.l: Contains the vector number. + +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ + || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) + + | If we are supporting Ctrl-C interrupts from GDB, we must squirrel + | away a pointer to the saved interrupt state here so that we can + | plant a breakpoint at some later time. + + .extern hal_saved_interrupt_state + move.l %sp,(hal_saved_interrupt_state) + +#endif + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + + | Lock the scheduler if we are using the kernel. + .extern cyg_scheduler_sched_lock + addq.l #1,cyg_scheduler_sched_lock + +#endif /* CYGFUN_HAL_COMMON_KERNEL_SUPPORT */ + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + + | a0 = sp. We'll need it later + move.l %sp,%a0 + + cmp.l #__interrupt_stack_base,%sp + + | If sp < base : not on istack + blt 1f + + cmp.l #__interrupt_stack,%sp + + | If sp <= top : already on istack + ble 2f + +1: + | Switch to istack + lea __interrupt_stack,%sp + +2: + | Save old SP on istack + pea (%a0) + +#endif + +#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) + + .extern cyg_instrument + + | Save d1 + move.l %d1,-(%sp) + + | arg2 = 0 + move.l #0,-(%sp) + + | arg1 = vector number + move.l %d1,-(%sp) + + | type = INTR,RAISE + move.l #0x0301,-(%sp) + + | Call instrumentation + jsr cyg_instrument + + | Remove args from stack + add.l #12,%sp + + | Restore %d1 + move.l (%sp)+,%d1 + +#endif + + +#ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING + + | If interrupt nesting is enabled, we have to determine the IPL of the + | current interrupt. We inline the following macro, which is defined + | by ColdFire variants. The vector number of the current interrupt + | is passed in d0, and the return value is in d0. + | Registers a0-a1/d0-d1 are for use by the macro, other registers + | must be saved explicitly before being used. + + | Save %d1 + move.l %d1,-(%sp) + + | Pass d1 as argument to macro + move.l %d1,%d0 + + | Retrieve IPL, which will be contained in d0 + hal_variant_retrieve_ipl + + | Shift IPL up to the same position occupied in sr + lsl.l #8,%d0 + + | Transform d0 in a mask to be applied to sr + or.l #0xfffff0ff,%d0 + + | Update sr. Use d1 as working register + move.w %sr,%d1 + and.l %d0,%d1 + move.w %d1,%sr + + | Restore d1 + move.l (%sp)+,%d1 + +#endif + + | We need to call the following routines. The isr address, data, and + | intr are all from the ISR table. The interrupt_end routine is + | only called if we are using the kernel. regs points to the saved + | registers on the stack. isr_ret is the return value from the ISR. + | vector is the vector number. + + | static cyg_uint32 isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) + + | externC void interrupt_end(cyg_uint32 isr_ret, Cyg_Interrupt *intr, + | HAL_SavedRegisters *regs) + + + | Push the data value from the table. + .extern cyg_hal_interrupt_data + lea cyg_hal_interrupt_data,%a0 + move.l (%a0,%d2.l),-(%sp) + + | Get the address of the ISR from the table. + .extern cyg_hal_interrupt_handlers + lea cyg_hal_interrupt_handlers,%a0 + move.l (%a0,%d2.l),%a0 + + | Push the vector number parameter. + move.l %d1,-(%sp) + + | Call the ISR. + jsr (%a0) + + | Remove the isr parameters from the stack. + addq.l #4*2,%sp + + | d0.l now contains the return value from the ISR. + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + + | If we are returning from the last nested interrupt, move back + | to the thread stack. interrupt_end() must be called on the + | thread stack since it potentially causes a context switch. + | Since we have arranged for the top of stack location to + | contain the sp we need to go back to here, just pop it off + | and put it in SP. + + move.l (%sp),%sp | sp = *sp + +#endif + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + + | We only need to call interrupt_end() when there is a kernel + | present to do any tidying up. To keep the following code simple, + | we enable all interrupts before calling DSRs only if a common + | interrupt stack is in use. + + | Push the regs pointer. + pea (%sp) + + | Push the intr object pointer from the table. + .extern cyg_hal_interrupt_objects + lea cyg_hal_interrupt_objects,%a0 + move.l (%a0,%d2.l),-(%sp) + + | Push ISR return value + move.l %d0,-(%sp) + + | Even when this is not the last nested interrupt, we must call + | interrupt_end() to post the DSR and decrement the scheduler + | lock. + + | Call the interrupt_end C routine. + .extern interrupt_end + jsr interrupt_end + + | Remove the isr_ret, intr, and regs parameters from the stack. + lea (4*3)(%sp),%sp + +#endif /* ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT */ + + | Restore the preserved registers for the current thread. + int_rest_regs + + | Restore the SR and PC. + rte + + +| ---------------------------------------------------------------------------- +| Execute pending DSRs on the interrupt stack with interrupts enabled. +| Note: this can only be called from code running on a thread stack + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + + .extern cyg_interrupt_call_pending_DSRs + +FUNC_START(hal_interrupt_stack_call_pending_DSRs) + | Change to interrupt stack, save state and set up stack for + | calls to C code. + | By virtue of GNU C calling conventions, we are free to use registers + | %d0-%d1 and %a0-%a1 without saving them. + + | a0 = sp + move.l %sp, %a0 + + | Switch to istack + lea __interrupt_stack,%sp + + | Save old SP on istack + pea (%a0) + + | Save sr + move.w %sr,%d0 + move.l %d0,-(%sp) + + | Enable interrupts + hal_cpu_int_enable %d0 + + | Call into kernel which will execute DSRs + jsr cyg_interrupt_call_pending_DSRs + + move.l (%sp)+,%d0 + + | Restore previous interrupt state + hal_cpu_int_merge %d0,%d1 + + | Restore sp + move.l (%sp),%sp + + | return to caller + rts + +#endif + + +| ---------------------------------------------------------------------------- +| Interrupt and reset stack +| +| WARNING: Do not put this in any memory section that gets initialized. +| Doing so may cause the C code to initialize its own stack. + + .section ".uninvar","aw",@nobits + + .balign 16 + .global cyg_interrupt_stack_base +cyg_interrupt_stack_base: +__interrupt_stack_base: + .skip CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + .balign 16 + .global cyg_interrupt_stack +cyg_interrupt_stack: +__interrupt_stack: + .skip 0x10 + diff --git a/ecos/packages/hal/coldfire/m5272c3/current/ChangeLog b/ecos/packages/hal/coldfire/m5272c3/current/ChangeLog new file mode 100644 index 0000000..5a2709f --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/ChangeLog @@ -0,0 +1,49 @@ +2009-01-31 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_coldfire_m5272c3.cdl: update compiler flags for gcc 4.x + +2006-05-09 Andrew Lunn <andrew.lunn@ascom.ch> + + * include/pkgconf/mlt_coldfire_m5272c3_*.h: Added CYGMEM_REGION_RAM* + so that the test cases compile. + +2005-06-24 Enrico Piria <epiriaNOSPAM@NOSPAMfastwebnet.it> + + * src/plf_mk_defs.c: + * src/plf_startup.c: + * include/hal_memmap.h: + * include/platform.inc: + * include/plf_intr.h: + * include/plf_serial.h: + * include/plf_startup.h: + * include/plf_stub.h: + * include/pkgconf/mlt_coldfire_m5272c3_ram.h: + * include/pkgconf/mlt_coldfire_m5272c3_ram.ldi: + * include/pkgconf/mlt_coldfire_m5272c3_rom.h: + * include/pkgconf/mlt_coldfire_m5272c3_rom.ldi: + * cdl/hal_coldfire_m5272c3.cdl: + Rework of the original M5272C3 platform HAL contributed by Wade Jensen. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/coldfire/m5272c3/current/cdl/hal_coldfire_m5272c3.cdl b/ecos/packages/hal/coldfire/m5272c3/current/cdl/hal_coldfire_m5272c3.cdl new file mode 100644 index 0000000..de9b95e --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/cdl/hal_coldfire_m5272c3.cdl @@ -0,0 +1,359 @@ +# ==================================================================== +# +# hal_coldfire_m5272c3.cdl +# +# Freescale M5272C3 evaluation board HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Enrico Piria +## Contributors: Wade Jensen +## Date: 2005-25-06 +## +######DESCRIPTIONEND#### +##======================================================================== + +cdl_package CYGPKG_HAL_COLDFIRE_M5272C3 { + display "Freescale M5272C3 evaluation board" + parent CYGPKG_HAL_COLDFIRE_MCF5272 + define_header hal_coldfire_m5272c3.h + include_dir cyg/hal + + description "The Freescale M5272C3 evaluation board platform HAL + package should be used when targeting the actual hardware for + the Freescale M5272C3 evaluation board platform." + + compile plf_startup.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_coldfire.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_coldfire_mcf5272.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_coldfire_m5272c3.h>" + puts $::cdl_system_header "#define HAL_PLATFORM_BOARD \"Freescale M5272C3\"" + puts $::cdl_system_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + # The "-o file" is a workaround for CR100958 - without it the + # output file would end up in the source directory under CygWin. + # n.b. grep does not behave itself under win32 + make -priority 1 { + <PREFIX>/include/cyg/hal/plf_offsets.inc : <PACKAGE>/src/plf_mk_defs.c + $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,plf_offsets.tmp -o plf_mk_defs.tmp -S $< + fgrep .equ plf_mk_defs.tmp | sed s/#// > $@ + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 plf_offsets.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm plf_offsets.tmp plf_mk_defs.tmp + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM" "ROMRAM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + + description " + This option is used to control where the application program will + run, either from RAM or ROM (flash) memory. ROM based applications + must be self contained, while RAM applications will typically assume + the existence of a debug environment, such as GDB stubs. + ROMRAM bootstrap is similar to ROM bootstrap, but everything + is copied to RAM before execution starts, thus improving performace, + but at the cost of an increased RAM footprint." + } + + cdl_option CYGHWR_HAL_ROM_LMA { + display "Load address for ROM image" + active_if { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + flavor data + legal_values 0xFFE00000 0xFFF00000 + default_value 0xFFF00000 + + description "This option lets you decide in which half of flash + memory to download the ROM image. As a safety measure, + the default is to use the upper half (starting at + 0xFFF00000), thus preserving the ROM monitor shipped with + the board. This option is meaningful only when ROM or + ROMRAM startup is choosed." + } + + cdl_option CYGHWR_HAL_SYSTEM_CLOCK_MHZ { + display "System clock speed in MHz" + flavor data + legal_values 66 48 + default_value 66 + + description "This option identifies the system clock that the + processor uses. This value is used to set clock dividers + for some devices." + } + + cdl_option CYGHWR_EXT_SRAM_INSTALLED { + display "External 512Kb SRAM module" + flavor bool + default_value 0 + + description "If this option is enabled, chip-select module 2 is + configured to access the optional external 512Kb SRAM module." + } + + cdl_option CYGHWR_INSTALLED_SDRAM_SIZE { + display "Megabytes of SDRAM installed" + flavor data + legal_values 16 4 + default_value 16 + + description "This option selects the size of the SDRAM installed. + Note that the linker scripts have been written for a board with + 16 Mb of RAM. If you modify this option, you will have to change + them by hand." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + description " + Port 0 is the terminal serial port; port 1 is the auxiliary + serial port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option chooses which port will be used to connect to a host + via the GDB remote protocol." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "Debug serial port baud rate" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 19200 + description " + This option controls the baud rate used for the GDB connection." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 19200 + + description "This option selects the baud rate used for the + diagnostic port. Note: this should match the value chosen + for the GDB port if the diagnostic and GDB port are the + same." + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + + description "Set the periodic timer on the MCF5272 to 10 ms or + 10000000 ns." + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 4125 + description " + The default value is calculated as: + 10 ms / ((1 / (66 MHz)) * 16 * 10)." + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + + description "Global build options including control over compiler + flags, linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "m68k-elf" } + + description "This option specifies the command prefix used + when invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-m5206e -malign-int -g -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions " } + description "This option controls the global compiler flags + which are used to compile all packages by default. + Individual packages may define options which + override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-m5206e -g -nostdlib -Wl,--gc-sections -Wl,-static" } + + description "This option controls the global linker flags. + Individual packages may define options which + override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + + description "This option enables the building of the GDB + stubs for the board. The common HAL controls + take care of most of the build process, but the + final conversion from ELF image to binary data is + handled by the platform CDL, allowing relocation + of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -S -O srec $< $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? "coldfire_m5272c3_ram" : \ + (CYG_HAL_STARTUP == "ROMRAM") ? "coldfire_m5272c3_romram" : \ + "coldfire_m5272c3_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_coldfire_m5272c3_ram.ldi>" : \ + (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_coldfire_m5272c3_romram.ldi>" : \ + "<pkgconf/mlt_coldfire_m5272c3_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_coldfire_m5272c3_ram.h>" : \ + (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_coldfire_m5272c3_romram.h>" : \ + "<pkgconf/mlt_coldfire_m5272c3_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + requires { CYG_HAL_STARTUP == "RAM" } + parent CYGPKG_HAL_ROM_MONITOR + + description "Support can be enabled for boot ROMs or ROM + monitors which contain GDB stubs. This support + changes various eCos semantics such as the encoding of + diagnostic output, and the overriding of hardware + interrupt vectors." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + + description "Enable this option if this program is to be used as + a ROM monitor, i.e. applications will be loaded into + RAM on the board, and this ROM monitor may process + exceptions or interrupts generated from the + application. This enables features such as utilizing + a separate interrupt stack when exceptions are + generated." + } +} diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/hal_memmap.h b/ecos/packages/hal/coldfire/m5272c3/current/include/hal_memmap.h new file mode 100644 index 0000000..66e010f --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/hal_memmap.h @@ -0,0 +1,74 @@ +#ifndef CYGONCE_HAL_MEMMAP_H +#define CYGONCE_HAL_MEMMAP_H + +//============================================================================= +// +// hal_memmap.h +// +// Platform specific memory section definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Memory section definitions specific to the M5272C3 board +// Usage: Included via CYGHWR_MEMORY_LAYOUT_H +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <cyg/infra/cyg_type.h> + +// WARNING: DO NOT CHANGE THE TYPE OF THESE LABELS. THE LINKER DEFINES +// THESE AND WE WANT TO USE THE VARIABLE ADDRESSES NOT THE VARIABLES +// THEMSELVES. + +#define SECTION_DEC(_name_) \ + externC unsigned char __ ## _name_ ## _start[]; \ + externC unsigned char __ ## _name_ ## _end[]; \ + externC unsigned char __ ## _name_ ## _size[]; + +SECTION_DEC(bss) +SECTION_DEC(ram_data) +SECTION_DEC(rom_data) +SECTION_DEC(uninvar) +SECTION_DEC(romvec) +SECTION_DEC(ramvec) + +// --------------------------------------------------------------------------- +// End of hal_memmap.h +#endif // CYGONCE_HAL_MEMMAP_H diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_ram.h b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_ram.h new file mode 100644 index 0000000..50d732a --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_ram.h @@ -0,0 +1,85 @@ +#ifndef CYGONCE_MLT_COLDFIRE_RAM_H +#define CYGONCE_MLT_COLDFIRE_RAM_H + +//============================================================================= +// +// mlt_coldfire_m5272c3_ram.h +// +// Platform specific memory section definitions for RAM startup +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Memory section definitions specific to the M5272C3 board, +// used for RAM startup configuration. +// +//####DESCRIPTIONEND#### +//======================================================================== + +// eCos memory layout + +#include <cyg/hal/hal_memmap.h> + +#define CYGMEM_REGION_sdram (0x00000000) +#define CYGMEM_REGION_sdram_SIZE (0x01000000) + +#define CYGMEM_REGION_devs (0x10000000) +#define CYGMEM_REGION_devs_SIZE (0x00001800) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00001000) + +#define CYGMEM_REGION_ext_sram (0x30000000) +#define CYGMEM_REGION_ext_sram_SIZE (0x00080000) + +#define CYGMEM_REGION_flash (0xFFE00000) +#define CYGMEM_REGION_flash_SIZE (0x00200000) + +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x01000000 - (size_t) CYG_LABEL_NAME (__heap1)) +externC unsigned char CYG_LABEL_NAME (__heap1) []; + +// These symbols are required by the test cases. Normally the memory tool would generate them, +// but this file was been generated by hand and so is a little +// different to normal. +#define CYGMEM_REGION_ram CYGMEM_REGION_sdram +#define CYGMEM_REGION_ram_SIZE CYGMEM_REGION_sdram_SIZE + +// --------------------------------------------------------------------------- +// End of mlt_coldfire_m5272c3_ram.h +#endif // CYGONCE_MLT_COLDFIRE_RAM_H diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_ram.ldi b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_ram.ldi new file mode 100644 index 0000000..d7817fd --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_ram.ldi @@ -0,0 +1,86 @@ +//=========================================================================== +// +// mlt_coldfire_m5272c3_ram.ldi +// +// RAM startup linker control script +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Linker script specific to the M5272C3 board, used for +// RAM startup. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sdram : ORIGIN = 0x00000000, LENGTH = 0x01000000 + devs : ORIGIN = 0x10000000, LENGTH = 0x00001800 + sram : ORIGIN = 0x20000000, LENGTH = 0x00001000 + ext_sram : ORIGIN = 0x30000000, LENGTH = 0x00080000 + flash : ORIGIN = 0xFFE00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + SECTIONS_BEGIN + + SECTION_ramvec (sdram, 0x00000000 (NOLOAD), LMA_EQ_VMA) + SECTION_virtual_vec_table (sdram, ALIGN(0x4) (NOLOAD), LMA_EQ_VMA) + + // Reserve some space to the ROM monitor + SECTION_romvec (sdram, 0x00020000, LMA_EQ_VMA) + SECTION_boot (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_text (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_fini (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_rodata1 (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_rodata (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_fixup (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_data (sdram, ALIGN(0x4), LMA_EQ_VMA) + SECTION_bss (sdram, ALIGN(0x4) (NOLOAD), LMA_EQ_VMA) + SECTION_uninvar (sdram, ALIGN(0x4) (NOLOAD), LMA_EQ_VMA) + + // The heap starts here. + CYG_LABEL_DEFN(__heap1) = ALIGN (0x4); + + SECTIONS_END +} diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_rom.h b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_rom.h new file mode 100644 index 0000000..86b20a5 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_rom.h @@ -0,0 +1,85 @@ +#ifndef CYGONCE_MLT_COLDFIRE_ROM_H +#define CYGONCE_MLT_COLDFIRE_ROM_H + +//============================================================================= +// +// mlt_coldfire_m5272c3_rom.h +// +// Platform specific memory section definitions for ROM startup +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Memory section definitions specific to the M5272C3 board, +// used for ROM startup configuration. +// +//####DESCRIPTIONEND#### +//======================================================================== + +// eCos memory layout + +#include <cyg/hal/hal_memmap.h> + +#define CYGMEM_REGION_sdram (0x00000000) +#define CYGMEM_REGION_sdram_SIZE (0x01000000) + +#define CYGMEM_REGION_devs (0x10000000) +#define CYGMEM_REGION_devs_SIZE (0x00001800) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00001000) + +#define CYGMEM_REGION_ext_sram (0x30000000) +#define CYGMEM_REGION_ext_sram_SIZE (0x00080000) + +#define CYGMEM_REGION_flash (0xFFE00000) +#define CYGMEM_REGION_flash_SIZE (0x00200000) + +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x01000000 - (size_t) CYG_LABEL_NAME (__heap1)) +externC unsigned char CYG_LABEL_NAME (__heap1) []; + +// These symbols are required by the test cases. Normally the memory tool would generate them, +// but this file was been generated by hand and so is a little +// different to normal. +#define CYGMEM_REGION_ram CYGMEM_REGION_sdram +#define CYGMEM_REGION_ram_SIZE CYGMEM_REGION_sdram_SIZE + +// --------------------------------------------------------------------------- +// End of mlt_coldfire_m5272c3_rom.h +#endif // CYGONCE_MLT_COLDFIRE_ROM_H diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_rom.ldi b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_rom.ldi new file mode 100644 index 0000000..cd16f90 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_rom.ldi @@ -0,0 +1,95 @@ +//=========================================================================== +// +// mlt_coldfire_m5272c3_rom.ldi +// +// ROM startup linker control script +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Linker script specific to the M5272C3 board, used for +// ROM startup. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <cyg/infra/cyg_type.inc> +#include CYGBLD_HAL_PLATFORM_H + +MEMORY +{ + sdram : ORIGIN = 0x00000000, LENGTH = 0x01000000 + devs : ORIGIN = 0x10000000, LENGTH = 0x00001800 + sram : ORIGIN = 0x20000000, LENGTH = 0x00001000 + ext_sram : ORIGIN = 0x30000000, LENGTH = 0x00080000 + flash : ORIGIN = 0xFFE00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + SECTIONS_BEGIN + +#if (CYGHWR_HAL_ROM_LMA == 0xFFF00000) + SECTION_romvec (flash, 0xFFF00000, LMA_EQ_VMA) +#else + SECTION_romvec (flash, 0xFFE00000, LMA_EQ_VMA) +#endif + + SECTION_boot (flash, ALIGN (0x4), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x4),LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x4),LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x4),LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x4),LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x4),LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x4),LMA_EQ_VMA) + + SECTION_ramvec (sdram, 0x00000000 (NOLOAD), LMA_EQ_VMA) + SECTION_virtual_vec_table (sdram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + SECTION_data (sdram, ALIGN (0x4), FOLLOWING (.gcc_except_table)) + SECTION_bss (sdram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + SECTION_uninvar (sdram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + + // The heap starts here. + CYG_LABEL_DEFN(__heap1) = ALIGN (0x4); + + CYG_LABEL_DEFN(__romram_copy_source) = LOADADDR(.data); + CYG_LABEL_DEFN(__romram_copy_dest) = ADDR(.data); + CYG_LABEL_DEFN(__romram_copy_length) = SIZEOF(.data); + + SECTIONS_END +} diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_romram.h b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_romram.h new file mode 100644 index 0000000..5d04ca3 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_romram.h @@ -0,0 +1,85 @@ +#ifndef CYGONCE_MLT_COLDFIRE_ROMRAM_H +#define CYGONCE_MLT_COLDFIRE_ROMRAM_H + +//============================================================================= +// +// mlt_coldfire_m5272c3_romram.h +// +// Platform specific memory section definitions for ROMRAM startup +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Memory section definitions specific to the M5272C3 board, +// used for ROMRAM startup configuration. +// +//####DESCRIPTIONEND#### +//======================================================================== + +// eCos memory layout + +#include <cyg/hal/hal_memmap.h> + +#define CYGMEM_REGION_sdram (0x00000000) +#define CYGMEM_REGION_sdram_SIZE (0x01000000) + +#define CYGMEM_REGION_devs (0x10000000) +#define CYGMEM_REGION_devs_SIZE (0x00001800) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00001000) + +#define CYGMEM_REGION_ext_sram (0x30000000) +#define CYGMEM_REGION_ext_sram_SIZE (0x00080000) + +#define CYGMEM_REGION_flash (0xFFE00000) +#define CYGMEM_REGION_flash_SIZE (0x00200000) + +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x01000000 - (size_t) CYG_LABEL_NAME (__heap1)) +externC unsigned char CYG_LABEL_NAME (__heap1) []; + +// These symbols are required by the test cases. Normally the memory tool would generate them, +// but this file was been generated by hand and so is a little +// different to normal. +#define CYGMEM_REGION_ram CYGMEM_REGION_sdram +#define CYGMEM_REGION_ram_SIZE CYGMEM_REGION_sdram_SIZE + +// --------------------------------------------------------------------------- +// End of mlt_coldfire_m5272c3_romram.h +#endif // CYGONCE_MLT_COLDFIRE_ROMRAM_H diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_romram.ldi b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_romram.ldi new file mode 100644 index 0000000..3f72695 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/pkgconf/mlt_coldfire_m5272c3_romram.ldi @@ -0,0 +1,96 @@ +//=========================================================================== +// +// mlt_coldfire_m5272c3_romram.ldi +// +// ROMRAM startup linker control script +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Linker script specific to the M5272C3 board, used for +// ROMRAM startup. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <cyg/infra/cyg_type.inc> +#include CYGBLD_HAL_PLATFORM_H + +MEMORY +{ + sdram : ORIGIN = 0x00000000, LENGTH = 0x01000000 + devs : ORIGIN = 0x10000000, LENGTH = 0x00001800 + sram : ORIGIN = 0x20000000, LENGTH = 0x00001000 + ext_sram : ORIGIN = 0x30000000, LENGTH = 0x00080000 + flash : ORIGIN = 0xFFE00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + SECTIONS_BEGIN + +#if (CYGHWR_HAL_ROM_LMA == 0xFFF00000) + SECTION_romvec (flash, 0xFFF00000, LMA_EQ_VMA) +#else + SECTION_romvec (flash, 0xFFE00000, LMA_EQ_VMA) +#endif + + SECTION_boot (flash, ALIGN(0x4), FOLLOWING(.romvec)) + + SECTION_ramvec (sdram, 0x00000000 (NOLOAD), LMA_EQ_VMA) + SECTION_virtual_vec_table (sdram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + + SECTION_text (sdram, ALIGN (0x4),FOLLOWING(.boot)) + SECTION_fini (sdram, ALIGN (0x4),FOLLOWING(.text)) + SECTION_rodata1 (sdram, ALIGN (0x4),FOLLOWING(.fini)) + SECTION_rodata (sdram, ALIGN (0x4),FOLLOWING(.rodata1)) + SECTION_fixup (sdram, ALIGN (0x4),FOLLOWING(.rodata)) + SECTION_gcc_except_table (sdram, ALIGN (0x4),FOLLOWING(.fixup)) + SECTION_data (sdram, ALIGN (0x4), FOLLOWING (.gcc_except_table)) + SECTION_bss (sdram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + SECTION_uninvar (sdram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + + // The heap starts here. + CYG_LABEL_DEFN(__heap1) = ALIGN (0x4); + + CYG_LABEL_DEFN(__romram_copy_source) = LOADADDR(.text); + CYG_LABEL_DEFN(__romram_copy_dest) = ADDR(.text); + CYG_LABEL_DEFN(__romram_copy_length) = SIZEOF(.text) + SIZEOF(.fini) + SIZEOF(.rodata1) + SIZEOF(.rodata) + SIZEOF(.fixup) + SIZEOF(.gcc_except_table) + SIZEOF(.data); + + SECTIONS_END +} diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/platform.inc b/ecos/packages/hal/coldfire/m5272c3/current/include/platform.inc new file mode 100644 index 0000000..4c46ea8 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/platform.inc @@ -0,0 +1,77 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC + +|============================================================================= +| +| platform.inc +| +| M5272C3 board assembler header file +| +|============================================================================= +| ####ECOSGPLCOPYRIGHTBEGIN#### +| ------------------------------------------- +| This file is part of eCos, the Embedded Configurable Operating System. +| Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +| +| eCos is free software; you can redistribute it and/or modify it under +| the terms of the GNU General Public License as published by the Free +| Software Foundation; either version 2 or (at your option) any later +| version. +| +| eCos is distributed in the hope that it will be useful, but WITHOUT +| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +| FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +| for more details. +| +| You should have received a copy of the GNU General Public License +| along with eCos; if not, write to the Free Software Foundation, Inc., +| 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +| +| As a special exception, if other files instantiate templates or use +| macros or inline functions from this file, or you compile this file +| and link it with other works to produce a work based on this file, +| this file does not by itself cause the resulting work to be covered by +| the GNU General Public License. However the source code for this file +| must still be made available in accordance with section (3) of the GNU +| General Public License v2. +| +| This exception does not invalidate any other reasons why a work based +| on this file might be covered by the GNU General Public License. +| ------------------------------------------- +| ####ECOSGPLCOPYRIGHTEND#### +|============================================================================= +|#####DESCRIPTIONBEGIN#### +| +| Author(s): Enrico Piria +| Contributors: +| Date: 2005-25-06 +| Purpose: Assembler macro definitions specific to the M5272C3 board. +| Usage: Included by "variant.inc". Do not use directly. +| +|####DESCRIPTIONEND#### +|======================================================================== + +#include <cyg/hal/plf_offsets.inc> + +|------------------------------------------------------------------------------- +| Platform initialization macros + + .macro hal_hardware_init + | Initialize RAMBAR: locate SRAM and validate it. + move.l #CYGMEM_REGION_sram,%d0 + add.l #0x21,%d0 + movec %d0,%rambar0 + .endm + + + | Setup stack for startup routines. Use SRAM module. + .macro hal_boot_stack_init + | Point Stack Pointer into SRAM temporarily. + move.l #CYGMEM_REGION_sram,%d0 + add.l #CYGMEM_REGION_sram_SIZE,%d0 + move.l %d0,%sp + .endm + +|----------------------------------------------------------------------------- +| End of platform.inc +#endif // CYGONCE_HAL_PLATFORM_INC diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/plf_intr.h b/ecos/packages/hal/coldfire/m5272c3/current/include/plf_intr.h new file mode 100644 index 0000000..8ee2632 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/plf_intr.h @@ -0,0 +1,74 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Platform specific interrupt and clock support +// +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Interrupt and clock definitions specific to the M5272C3 board. +// Usage: Included via "var_intr.h". Do not use directly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// --------------------------------------------------------------------------- +// Reset + +#ifndef CYGHWR_HAL_RESET_DEFINED + +externC void cyg_hal_reset_vsr( void ); + +#define CYGHWR_HAL_RESET_DEFINED +#define HAL_PLATFORM_RESET() cyg_hal_reset_vsr() + +#define HAL_PLATFORM_RESET_ENTRY &cyg_hal_reset_vsr + +#endif // CYGHWR_HAL_RESET_DEFINED + +// --------------------------------------------------------------------------- +// End of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/plf_serial.h b/ecos/packages/hal/coldfire/m5272c3/current/include/plf_serial.h new file mode 100644 index 0000000..4ff1ba4 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/plf_serial.h @@ -0,0 +1,99 @@ +#ifndef CYGONCE_PLF_SERIAL_H +#define CYGONCE_PLF_SERIAL_H + +//============================================================================= +// +// plf_serial.h +// +// Platform specific definitions for diagnstic ouput via serial port +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Definitions for diagnostic output via serial port +// Usage: #include <cyg/hal/plf_serial.h> +// +//####DESCRIPTIONEND#### +//======================================================================== + +#define MCF5272_UART_UMR_8BNP (0x13) +#define MCF5272_UART_UMR_1S (0x07) + +#define MCF5272_UART_USR_RRDY (1<<0) +#define MCF5272_UART_USR_FFUL (1<<1) +#define MCF5272_UART_USR_TXRDY (1<<2) +#define MCF5272_UART_USR_TXEMP (1<<3) +#define MCF5272_UART_USR_OE (1<<4) +#define MCF5272_UART_USR_PE (1<<5) +#define MCF5272_UART_USR_FE (1<<6) +#define MCF5272_UART_USR_RB (1<<7) + +#define MCF5272_UART_UCSR_CLKIN (0xDD) + +#define MCF5272_UART_UCR_RMR (0x01<<4) +#define MCF5272_UART_UCR_RRX (0x02<<4) +#define MCF5272_UART_UCR_RTX (0x03<<4) +#define MCF5272_UART_UCR_RES (0x04<<4) +#define MCF5272_UART_UCR_RBC (0x05<<4) +#define MCF5272_UART_UCR_TXEN (1<<2) +#define MCF5272_UART_UCR_TXDE (1<<3) +#define MCF5272_UART_UCR_RXEN (1<<0) +#define MCF5272_UART_UCR_RXDE (1<<1) + +#define MCF5272_UART_UCR_TXRXEN \ + (MCF5272_UART_UCR_TXEN | \ + MCF5272_UART_UCR_RXEN) + +#define MCF5272_UART_UIMR_FFULL (0x02) + +#define MCF5272_UART_UTF_TXB (0x1F) + +#define MCF5272_UART_UOP0_RTS (0x01) +#define MCF5272_UART_UOP1_RTS (0x01) + +#define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155) +#define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000) +#define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF) + +#define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA) +#define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000) +#define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF) + +// --------------------------------------------------------------------------- +// End of plf_serial.h +#endif // CYGONCE_PLF_SERIAL_H diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/plf_startup.h b/ecos/packages/hal/coldfire/m5272c3/current/include/plf_startup.h new file mode 100644 index 0000000..0474ea0 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/plf_startup.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_PLF_STARTUP_H +#define CYGONCE_PLF_STARTUP_H + +//============================================================================= +// +// plf_startup.h +// +// M5272C3 platform startup header +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: M5272C3 platform startup header. +// Usage: Included via "var_startup.h". Do not use directly. +// +//####DESCRIPTIONEND#### +//========================================================================== + +// Platform specific reset vector initialization routine +externC void plf_reset(void) __attribute__ ((section (".boot"))); + +// Platform specific data initialization routine +externC void plf_init_data(void) __attribute__ ((section (".boot"))); + +// --------------------------------------------------------------------------- +// End of plf_startup.h +#endif // CYGONCE_PLF_STARTUP_H diff --git a/ecos/packages/hal/coldfire/m5272c3/current/include/plf_stub.h b/ecos/packages/hal/coldfire/m5272c3/current/include/plf_stub.h new file mode 100644 index 0000000..be8745e --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/include/plf_stub.h @@ -0,0 +1,80 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//======================================================================== +// +// plf_stub.h +// +// Platform specific definitions for generic stub +// +//======================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: GDB stub definitions specific to the M5272C3 board. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/coldfire_stub.h> // architecture stub support + + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int,(baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +// --------------------------------------------------------------------------- +// Stub initializer + +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +// --------------------------------------------------------------------------- +// End of plf_stub.h +#endif // CYGONCE_HAL_PLF_STUB_H diff --git a/ecos/packages/hal/coldfire/m5272c3/current/src/plf_mk_defs.c b/ecos/packages/hal/coldfire/m5272c3/current/src/plf_mk_defs.c new file mode 100644 index 0000000..9ad0711 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/src/plf_mk_defs.c @@ -0,0 +1,85 @@ +//========================================================================== +// +// plf_mk_defs.c +// +// "make defs" program for M5272C3 platform +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: gthomas, jskov +// Date: 2005-25-06 +// Purpose: Definition generator for M5272C3 board. +// Description: This file contains code that can be compiled by the target +// compiler and used to generate machine specific definitions +// suitable for use in assembly code. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include CYGHWR_MEMORY_LAYOUT_H + +// This program is used to generate definitions needed by +// assembly language modules. +// +// This technique was first used in the OSF Mach kernel code: +// generate asm statements containing #defines, +// compile this file to assembler, and then extract the +// #defines from the assembly-language output. + +#define DEFINE(sym, val) \ + asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val)) + +int +main(void) +{ + // Memory layout values + DEFINE(CYGMEM_REGION_sdram, CYGMEM_REGION_sdram); + DEFINE(CYGMEM_REGION_sdram_SIZE, CYGMEM_REGION_sdram_SIZE); + DEFINE(CYGMEM_REGION_devs, CYGMEM_REGION_devs); + DEFINE(CYGMEM_REGION_devs_SIZE, CYGMEM_REGION_devs_SIZE); + DEFINE(CYGMEM_REGION_sram, CYGMEM_REGION_sram); + DEFINE(CYGMEM_REGION_sram_SIZE, CYGMEM_REGION_sram_SIZE); + DEFINE(CYGMEM_REGION_flash, CYGMEM_REGION_flash); + DEFINE(CYGMEM_REGION_flash_SIZE, CYGMEM_REGION_flash_SIZE); + + return 0; +} + +// ------------------------------------------------------------------------- +// EOF hal_mk_defs.c diff --git a/ecos/packages/hal/coldfire/m5272c3/current/src/plf_startup.c b/ecos/packages/hal/coldfire/m5272c3/current/src/plf_startup.c new file mode 100644 index 0000000..fccd155 --- /dev/null +++ b/ecos/packages/hal/coldfire/m5272c3/current/src/plf_startup.c @@ -0,0 +1,256 @@ +//========================================================================== +// +// plf_startup.c +// +// M5272C3 platform HAL startup code +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Platform startup code. +// Description: This module contains code that sets up the platform specific +// hardware and data. All the code must be contained in the +// section called ".boot", in order for the ROMRAM startup +// to work properly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <cyg/infra/cyg_type.h> +#include <pkgconf/hal.h> +#include <cyg/hal/hal_startup.h> +#include CYGHWR_MEMORY_LAYOUT_H +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/coldfire_regs.h> + +static void plf_init_sim(void) __attribute__ ((section (".boot"))); +static void plf_init_intc(void) __attribute__ ((section (".boot"))); +static void plf_init_cs(void) __attribute__ ((section (".boot"))); +static void plf_init_sdramc(void) __attribute__ ((section (".boot"))); +static void plf_init_cache_acr(void) __attribute__ ((section (".boot"))); + + +// Platform-specific reset vector initialization routine +void plf_reset(void) +{ + plf_init_sim(); + plf_init_intc(); + plf_init_cs(); + plf_init_sdramc(); + + // Call a routine to set up the cache and ACRs for this specific + // platform. + plf_init_cache_acr(); +} + + +// Initialize the cache and access control registers. +// The reset procedure already invalidated the cache and ACRs. +// This routine only needs to enable the ACRs that it will use. +static void plf_init_cache_acr(void) +{ + // Enable the instruction cache with the following options: + // Enable CPUSHL invalidation. + // No freeze. + // Invalidate all cache lines (flush). + // No external arbiter control. + // Disable non-cacheable instruction bursting. + // Default memory is cacheable. + // Enable buffered writes. + // Read and write access permitted by default. + // Instruction fetch size is cache line. + +#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP + CYGARC_MOVEC((CYG_WORD32) 0x81000102, CYGARC_REG_CACR); +#endif + + // Leave the access control registers disabled. +} + + +// Initialize SIM module and system configuration registers +void plf_init_sim(void) +{ + // Set up the mapping of our internal registers. The LSB indicates that + // the register contents are valid. + CYGARC_MOVEC((CYG_WORD32)(CYGMEM_REGION_devs | 1), CYGARC_REG_MBAR); + + // Initialize System Config Register + // Setup Watch Dog Timeout + HAL_WRITE_UINT16(&MCF5272_DEVS->cfg.scr, MCF5272_SIM_SCR_HWWD_1024); + + // Initialize System Protection Register + // Enable all bus error exceptions + HAL_WRITE_UINT16(&MCF5272_DEVS->cfg.spr, + (0 | MCF5272_SIM_SPR_ADC | MCF5272_SIM_SPR_ADCEN + | MCF5272_SIM_SPR_WPV | MCF5272_SIM_SPR_WPVEN + | MCF5272_SIM_SPR_SMV | MCF5272_SIM_SPR_SMVEN + | MCF5272_SIM_SPR_SBE | MCF5272_SIM_SPR_SBEEN + | MCF5272_SIM_SPR_HWT | MCF5272_SIM_SPR_HWTEN + | MCF5272_SIM_SPR_RPV | MCF5272_SIM_SPR_RPVEN + | MCF5272_SIM_SPR_EXT | MCF5272_SIM_SPR_EXTEN + | MCF5272_SIM_SPR_SUV | MCF5272_SIM_SPR_SUVEN + )) ; +} + + +// Initialize interrupt controller +void plf_init_intc(void) +{ + int i; + + // Initialize the vector base register in the interrupt controller. + HAL_WRITE_UINT8(&MCF5272_DEVS->intc.ipvr, HAL_PROG_INT_VEC_BASE); + + // Initialize the interrupt control register. + // Disable all interrupts by setting all priorities to zero. + for (i = 0; i < 4; i++) + { + HAL_WRITE_UINT32(&MCF5272_DEVS->intc.icr[i], 0x88888888); + } + + // Initialize the processor's vector base register (align to 1M boundary). + CYGARC_MOVEC((CYG_WORD32) __ramvec_start & 0xFFF00000, CYGARC_REG_VBR); +} + + +// Initialize chip-select modules +void plf_init_cs(void) +{ + // ChipSelect 0 - 2MB FLASH + // At startup, CS0 is configured so that addresses starting at 0xXXX00000 + // are aliased to 0x00000000, so, in ROM startup configuration, code can + // be placed starting at VMA address 0xFFE00000. When we are here, + // the PC points to addresses in 0xFFE00000 space, and we can safely + // reconfigure CS0 to respond uniquely to those addresses. + HAL_WRITE_UINT32(&MCF5272_DEVS->cs[0].csbr, (0 + | MCF5272_CS_BR_BASE(CYGMEM_REGION_flash) + | MCF5272_CS_BR_SRAM + | MCF5272_CS_BR_PS_16 + | MCF5272_CS_BR_EN)); + + HAL_WRITE_UINT32(&MCF5272_DEVS->cs[0].csor, + (0 | MCF5272_CS_OR_MASK_2M + | MCF5272_CS_OR_WS(5))); + +#ifdef CYGHWR_EXT_SRAM_INSTALLED + // Chip Select 2 - 512KB SRAM + HAL_WRITE_UINT32(&MCF5272_DEVS->cs[2].csbr, (0 + | MCF5272_CS_BR_BASE(CYGMEM_REGION_ext_sram) + | MCF5272_CS_BR_SRAM + | MCF5272_CS_BR_PS_32 + | MCF5272_CS_BR_EN)); + + HAL_WRITE_UINT32(&MCF5272_DEVS->cs[2].csor, (0 + | MCF5272_CS_OR_MASK_512K + | MCF5272_CS_OR_WS(0))); +#endif // CYGHWR_EXT_SRAM_INSTALLED + + // ChipSelect 7 - 16MB SDRAM + HAL_WRITE_UINT32(&MCF5272_DEVS->cs[7].csbr, (0 + | MCF5272_CS_BR_BASE(CYGMEM_REGION_sdram) + | MCF5272_CS_BR_SDRAM + | MCF5272_CS_BR_PS_LINE + | MCF5272_CS_BR_EN)); + + HAL_WRITE_UINT32(&MCF5272_DEVS->cs[7].csor, (0 +#if (CYGHWR_INSTALLED_SDRAM_SIZE == 4) + | MCF5272_CS_OR_MASK_4M +#else + | MCF5272_CS_OR_MASK_16M +#endif + | MCF5272_CS_OR_WS(0x1F))); +} + + +// Initialize SDRAM controller +void plf_init_sdramc(void) +{ + cyg_uint16 sdcr; + + + HAL_READ_UINT16(&MCF5272_DEVS->sdramc.sdcr, sdcr); + + // Do not initialize SDRAM if it is already active + if (!(sdcr & MCF5272_SDRAMC_SDCCR_ACT)) + { +#if (CYGHWR_HAL_SYSTEM_CLOCK_MHZ == 66) + HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdtr, (0 + | MCF5272_SDRAMC_SDCTR_RTP_66MHz + | MCF5272_SDRAMC_SDCTR_RC(0) + | MCF5272_SDRAMC_SDCTR_RP(1) + | MCF5272_SDRAMC_SDCTR_RCD(1) + | MCF5272_SDRAMC_SDCTR_CLT_2)); +#else + // Clock frequency must be 48 Mhz + HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdtr, (0 + | MCF5272_SDRAMC_SDCTR_RTP_48MHz + | MCF5272_SDRAMC_SDCTR_RC(0) + | MCF5272_SDRAMC_SDCTR_RP(1) + | MCF5272_SDRAMC_SDCTR_RCD(0) + | MCF5272_SDRAMC_SDCTR_CLT_2)); +#endif + + HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdcr, (0 + | MCF5272_SDRAMC_SDCCR_MCAS_A9 +#if (CYGHWR_INSTALLED_SDRAM_SIZE == 4) + | MCF5272_SDRAMC_SDCCR_BALOC_A21 +#else + | MCF5272_SDRAMC_SDCCR_BALOC_A22 +#endif + | MCF5272_SDRAMC_SDCCR_REG + | MCF5272_SDRAMC_SDCCR_INIT)); + + // Start SDRAM controller with a memory write + *((volatile char *) CYGMEM_REGION_sdram) = 0; + + // Wait until controller is ready + do + { + HAL_READ_UINT16(&MCF5272_DEVS->sdramc.sdcr, sdcr); + } while(!(sdcr & MCF5272_SDRAMC_SDCCR_ACT)); + } +} + + +// Platform specific data initialization routine +void plf_init_data(void) +{ + // Nothing to do +} diff --git a/ecos/packages/hal/coldfire/mcf5272/current/ChangeLog b/ecos/packages/hal/coldfire/mcf5272/current/ChangeLog new file mode 100644 index 0000000..9daf47b --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/ChangeLog @@ -0,0 +1,41 @@ +2005-06-24 Enrico Piria <epiriaNOSPAM@NOSPAMfastwebnet.it> + + * src/var_misc.c: + * src/var_startup.c: + * src/hal_diag.c: + * src/variant.S: + * include/hal_diag.h: + * include/mcf5272_devs.h: + * include/var_arch.h: + * include/var_basetype.h: + * include/var_cache.h: + * include/var_intr.h: + * include/var_regs.h: + * include/var_startup.h: + * include/variant.inc: + * cdl/hal_coldfire_mcf5272.cdl: + Rework of the original MCF5272 variant HAL contributed by Wade Jensen. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/coldfire/mcf5272/current/cdl/hal_coldfire_mcf5272.cdl b/ecos/packages/hal/coldfire/mcf5272/current/cdl/hal_coldfire_mcf5272.cdl new file mode 100644 index 0000000..c39244b --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/cdl/hal_coldfire_mcf5272.cdl @@ -0,0 +1,95 @@ +# ==================================================================== +# +# hal_coldfire_mcf5272.cdl +# +# MCF5272 variant architectural HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Enrico Piria +## Contributors: Wade Jensen +## Date: 2005-25-06 +## +######DESCRIPTIONEND#### +##======================================================================== + +cdl_package CYGPKG_HAL_COLDFIRE_MCF5272 { + display "MCF5272 ColdFire variant HAL" + parent CYGPKG_HAL_COLDFIRE + requires CYGPKG_HAL_COLDFIRE + implements CYGINT_HAL_COLDFIRE_VARIANT + implements CYGARC_HAL_COLDFIRE_V2_CORE + implements CYGARC_HAL_COLDFIRE_MAC + implements CYGARC_HAL_COLDFIRE_ISA_A + hardware + include_dir cyg/hal + define_header hal_coldfire_mcf5272.h + + description "The ColdFire 5272 variant HAL package provides + generic support for the ColdFire 5272 processor. It is also + necessary to select a specific target platform HAL package." + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_coldfire.h>" + } + + compile var_startup.c var_misc.c variant.S + + cdl_option CYGHWR_HAL_COLDFIRE_MAC { + display "MAC support" + flavor bool + default_value 0 + description " + Enable or disable support for MAC operations. MAC registers will be + saved during context switches, during exceptions, and in the + setjmp/longjmp routines. If you don't use the MAC unit, you can + leave this option disabled." + } + + # With this calculated option, code for diagnostic/debug output is compiled + # only if it is really needed. + cdl_option CYGBLD_HAL_COLDFIRE_MCF5272_DIAG { + display "Compile HAL diagnostic output code" + flavor bool + no_define + calculated { is_active(CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL) || + is_active(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL) } + compile hal_diag.c + description " + This calculated option is enabled only when code for + diagnostic/debug output is really needed." + } +} diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/hal_diag.h b/ecos/packages/hal/coldfire/mcf5272/current/include/hal_diag.h new file mode 100644 index 0000000..a97591d --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/hal_diag.h @@ -0,0 +1,68 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL support for kernel diagnostic routines +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Provide ColdFire-specific diagnostic system definitions. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +// We suppose that CYGSEM_HAL_VIRTUAL_VECTOR_DIAG is always defined + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +// --------------------------------------------------------------------------- +// End of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/mcf5272_devs.h b/ecos/packages/hal/coldfire/mcf5272/current/include/mcf5272_devs.h new file mode 100644 index 0000000..93905c1 --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/mcf5272_devs.h @@ -0,0 +1,709 @@ +#ifndef CYGONCE_MCF5272_DEVS_H +#define CYGONCE_MCF5272_DEVS_H + +//============================================================================= +// +// mcf5272_devs.h +// +// Definitions for the MCF5272 on-chip peripherals +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria, Wade Jensen +// Contributors: +// Date: 2005-25-06 +// Purpose: Definitions for the MCF5272 on-chip peripherals. +// Usage: #include <cyg/hal/mcf5272_devs.h> +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// General configuration registers +typedef struct +{ + + // Module base address register + cyg_uint32 mbar; + + // System configuration register + cyg_uint16 scr; + + // System protection register + cyg_uint16 spr; + + // Power management register + cyg_uint32 pmr; + + // Gap + cyg_uint16 _res1; + + // Active low power register + cyg_uint16 alpr; + + // Device identification register + cyg_uint32 dir; + + // Gap + cyg_uint32 _res2[3]; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_cfg_t; + +// Configuration registers macros + +#define MCF5272_SIM_SCR_HWWD_1024 0x0003 + +#define MCF5272_SIM_SPR_ADC 0x8000 +#define MCF5272_SIM_SPR_ADCEN 0x0080 +#define MCF5272_SIM_SPR_WPV 0x4000 +#define MCF5272_SIM_SPR_WPVEN 0x0040 +#define MCF5272_SIM_SPR_SMV 0x2000 +#define MCF5272_SIM_SPR_SMVEN 0x0020 +#define MCF5272_SIM_SPR_SBE 0x1000 +#define MCF5272_SIM_SPR_SBEEN 0x0010 +#define MCF5272_SIM_SPR_HWT 0x0800 +#define MCF5272_SIM_SPR_HWTEN 0x0008 +#define MCF5272_SIM_SPR_RPV 0x0400 +#define MCF5272_SIM_SPR_RPVEN 0x0004 +#define MCF5272_SIM_SPR_EXT 0x0200 +#define MCF5272_SIM_SPR_EXTEN 0x0002 +#define MCF5272_SIM_SPR_SUV 0x0100 +#define MCF5272_SIM_SPR_SUVEN 0x0001 + +// --------------------------------------------------------------------------- + +// Interrupt controller registers +typedef struct +{ + + // Interrupt control register 1-4 + cyg_uint32 icr[4]; + + // Interrupt source register + cyg_uint32 isr; + + // Programmable interrupt transition register + cyg_uint32 pitr; + + // Programmable interrupt wakeup register + cyg_uint32 piwr; + + // Gap + cyg_uint8 _res1[3]; + + // Programmable interrupt vector register + cyg_uint8 ipvr; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_int_t; + +// Interrupt controller related macros + +#define MCF5272_SIM_PITR_INT1_POS_EDGE (0x80000000) +#define MCF5272_SIM_PITR_INT2_POS_EDGE (0x40000000) +#define MCF5272_SIM_PITR_INT3_POS_EDGE (0x20000000) +#define MCF5272_SIM_PITR_INT4_POS_EDGE (0x10000000) +#define MCF5272_SIM_PITR_INT5_POS_EDGE (0x00000040) +#define MCF5272_SIM_PITR_INT6_POS_EDGE (0x00000020) + +#define MCF5272_SIM_PIWR_INT1_WAKE (0x80000000) +#define MCF5272_SIM_PIWR_INT2_WAKE (0x40000000) +#define MCF5272_SIM_PIWR_INT3_WAKE (0x20000000) +#define MCF5272_SIM_PIWR_INT4_WAKE (0x10000000) +#define MCF5272_SIM_PIWR_TMR0_WAKE (0x08000000) +#define MCF5272_SIM_PIWR_TMR1_WAKE (0x04000000) +#define MCF5272_SIM_PIWR_TMR2_WAKE (0x02000000) +#define MCF5272_SIM_PIWR_TMR3_WAKE (0x01000000) +#define MCF5272_SIM_PIWR_UART1_WAKE (0x00800000) +#define MCF5272_SIM_PIWR_UART2_WAKE (0x00400000) +#define MCF5272_SIM_PIWR_PLIP_WAKE (0x00200000) +#define MCF5272_SIM_PIWR_PLIA_WAKE (0x00100000) +#define MCF5272_SIM_PIWR_USB0_WAKE (0x00080000) +#define MCF5272_SIM_PIWR_USB1_WAKE (0x00040000) +#define MCF5272_SIM_PIWR_USB2_WAKE (0x00020000) +#define MCF5272_SIM_PIWR_USB3_WAKE (0x00010000) +#define MCF5272_SIM_PIWR_USB4_WAKE (0x00008000) +#define MCF5272_SIM_PIWR_USB5_WAKE (0x00004000) +#define MCF5272_SIM_PIWR_USB6_WAKE (0x00002000) +#define MCF5272_SIM_PIWR_USB7_WAKE (0x00001000) +#define MCF5272_SIM_PIWR_DMA_WAKE (0x00000800) +#define MCF5272_SIM_PIWR_ERX_WAKE (0x00000400) +#define MCF5272_SIM_PIWR_ETX_WAKE (0x00000200) +#define MCF5272_SIM_PIWR_ENTC_WAKE (0x00000100) +#define MCF5272_SIM_PIWR_QSPI_WAKE (0x00000080) +#define MCF5272_SIM_PIWR_INT5_WAKE (0x00000040) +#define MCF5272_SIM_PIWR_INT6_WAKE (0x00000020) +#define MCF5272_SIM_PIWR_SWTO_WAKE (0x00000010) + +// --------------------------------------------------------------------------- + +// Chip-select module +typedef struct +{ + + // CS base register + cyg_uint32 csbr; + + // CS option register + cyg_uint32 csor; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_cs_t; + +// Chip-select modules related macros + +#define MCF5272_CS_BR_BASE(a) ((a) & 0xFFFFF000) + +#define MCF5272_CS_OR_MASK_128M (0xF8000000) +#define MCF5272_CS_OR_MASK_64M (0xFC000000) +#define MCF5272_CS_OR_MASK_32M (0xFE000000) +#define MCF5272_CS_OR_MASK_16M (0xFF000000) +#define MCF5272_CS_OR_MASK_8M (0xFF800000) +#define MCF5272_CS_OR_MASK_4M (0xFFC00000) +#define MCF5272_CS_OR_MASK_2M (0xFFE00000) +#define MCF5272_CS_OR_MASK_1M (0xFFF00000) +#define MCF5272_CS_OR_MASK_512K (0xFFF80000) +#define MCF5272_CS_OR_MASK_256K (0xFFFC0000) +#define MCF5272_CS_OR_MASK_128K (0xFFFE0000) +#define MCF5272_CS_OR_MASK_64K (0xFFFF0000) +#define MCF5272_CS_OR_MASK_32K (0xFFFF8000) +#define MCF5272_CS_OR_MASK_16K (0xFFFFC000) +#define MCF5272_CS_OR_MASK_8K (0xFFFFE000) +#define MCF5272_CS_OR_MASK_4K (0xFFFFF000) +#define MCF5272_CS_OR_WS_MASK (0x007C) +#define MCF5272_CS_OR_WS(a) (((a) & 0x1F) << 2) +#define MCF5272_CS_OR_BRST (0x0100) +#define MCF5272_CS_OR_WR_ONLY (0x0003) +#define MCF5272_CS_OR_RD_ONLY (0x0001) + +#define MCF5272_CS_BR_PS_8 (0x0100) +#define MCF5272_CS_BR_PS_16 (0x0200) +#define MCF5272_CS_BR_PS_32 (0x0000) +#define MCF5272_CS_BR_PS_LINE (0x0300) +#define MCF5272_CS_BR_ROM (0x0000) +#define MCF5272_CS_BR_SRAM (0x0000) +#define MCF5272_CS_BR_SRAM_8 (0x0C00) +#define MCF5272_CS_BR_SDRAM (0x0400) +#define MCF5272_CS_BR_ISA (0x0800) +#define MCF5272_CS_BR_SV (0x0080) +#define MCF5272_CS_BR_EN (0x0001) + +// --------------------------------------------------------------------------- + +// General purpose I/O module +typedef struct +{ + + // Port A control register + cyg_uint32 pacnt; + + // Port A data direction register + cyg_uint16 paddr; + + // Port A data register + cyg_uint16 padat; + + // Port B control register + cyg_uint32 pbcnt; + + // Port B data direction register + cyg_uint16 pbddr; + + // Port B data register + cyg_uint16 pbdat; + + // Gap + cyg_uint32 _res1; + + // Port C data direction register + cyg_uint16 pcddr; + + // Port C data register + cyg_uint16 pcdat; + + // Port D control register + cyg_uint32 pdcnt; + + // Gap + cyg_uint16 _res2; + cyg_uint16 _res3; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_gpio_t; + +// GPIO ports related macros + +#define MCF5272_GPIO_DDR_IN (0) +#define MCF5272_GPIO_DDR_OUT (1) + +#define MCF5272_GPIO_PBCNT_ETH_EN (0x55550000) +#define MCF5272_GPIO_PBCNT_ETH_DE (0x00000000) +#define MCF5272_GPIO_PBCNT_ETH_MSK (0xFFFF0000) + +#define MCF5272_GPIO_PBCNT_TA_EN (0x00000400) +#define MCF5272_GPIO_PBCNT_TA_DE (0x00000000) +#define MCF5272_GPIO_PBCNT_TA_MSK (0x00000C00) + +#define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155) +#define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000) +#define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF) + +#define MCF5272_GPIO_PDCNT_INT4_EN (0x00000C00) +#define MCF5272_GPIO_PDCNT_INT4_DE (0x00000000) +#define MCF5272_GPIO_PDCNT_INT4_MSK (0x00000C00) + +#define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA) +#define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000) +#define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF) + +// --------------------------------------------------------------------------- + +// UART module +typedef struct +{ + + // UART mode register + cyg_uint8 umr; + + // Gap + cyg_uint8 _res1[3]; + + // UART status register (R) and clock-select register (W) + cyg_uint8 usr_ucsr; + + // Gap + cyg_uint8 _res2[3]; + + // UART command register + cyg_uint8 ucr; + + // Gap + cyg_uint8 _res3[3]; + + // UART receiver buffers (R) and transmitter buffers (W) + cyg_uint8 urb_utb; + + // Gap + cyg_uint8 _res4[3]; + + // UART input port change register (R) and auxiliary control register (W) + cyg_uint8 uipcr_uacr; + + // Gap + cyg_uint8 _res5[3]; + + // UART interrupt status register (R) and interrupt mask register (W) + cyg_uint8 uisr_uimr; + + // Gap + cyg_uint8 _res6[3]; + + // UART divider upper register + cyg_uint8 udu; + + // Gap + cyg_uint8 _res7[3]; + + // UART divider lower register + cyg_uint8 udl; + + // Gap + cyg_uint8 _res8[3]; + + // UART autobaud register MSB + cyg_uint8 uabu; + + // Gap + cyg_uint8 _res9[3]; + + // UART autobaud register LSB + cyg_uint8 uabl; + + // Gap + cyg_uint8 _res10[3]; + + // UART transmitter FIFO register + cyg_uint8 utf; + + // Gap + cyg_uint8 _res11[3]; + + // UART receiver FIFO register + cyg_uint8 urf; + + // Gap + cyg_uint8 _res12[3]; + + // UART fractional precision divider register + cyg_uint8 ufpd; + + // Gap + cyg_uint8 _res13[3]; + + // UART input port register + cyg_uint8 uip; + + // Gap + cyg_uint8 _res14[3]; + + // UART output port register 1 + cyg_uint8 uop1; + + // Gap + cyg_uint8 _res15[3]; + + // UART output port register 0 + cyg_uint8 uop0; + + // Gap + cyg_uint8 _res16[3]; + +} __attribute__ ((aligned (4), packed)) mcf5272_uart_t; + +// --------------------------------------------------------------------------- + +// SDRAM controller +typedef struct +{ + + // Gap + cyg_uint8 _res1[2]; + + // SDRAM configuration register + cyg_uint16 sdcr; + + // Gap + cyg_uint8 _res2[2]; + + // SDRAM timing register + cyg_uint16 sdtr; + + // Gap + cyg_uint8 _res3[120]; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_sdramctrl_t; + +// SDRAM controller related macros + +#define MCF5272_SDRAMC_SDCCR_MCAS_A7 (0x0 << 13) +#define MCF5272_SDRAMC_SDCCR_MCAS_A8 (0x1 << 13) +#define MCF5272_SDRAMC_SDCCR_MCAS_A9 (0x2 << 13) +#define MCF5272_SDRAMC_SDCCR_MCAS_A10 (0x3 << 13) +#define MCF5272_SDRAMC_SDCCR_BALOC_A19 (0x0 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A20 (0x1 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A21 (0x2 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A22 (0x3 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A23 (0x4 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A24 (0x5 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A25 (0x6 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A26 (0x7 << 8) +#define MCF5272_SDRAMC_SDCCR_GSL (0x00000080) +#define MCF5272_SDRAMC_SDCCR_REG (0x00000010) +#define MCF5272_SDRAMC_SDCCR_INV (0x00000008) +#define MCF5272_SDRAMC_SDCCR_SLEEP (0x00000004) +#define MCF5272_SDRAMC_SDCCR_ACT (0x00000002) +#define MCF5272_SDRAMC_SDCCR_INIT (0x00000001) + +#define MCF5272_SDRAMC_SDCTR_RTP_66MHz (0x3D << 10) +#define MCF5272_SDRAMC_SDCTR_RTP_48MHz (0x2B << 10) +#define MCF5272_SDRAMC_SDCTR_RTP_33MHz (0x1D << 10) +#define MCF5272_SDRAMC_SDCTR_RTP_25MHz (0x16 << 10) +#define MCF5272_SDRAMC_SDCTR_RC(x) ((x & 0x3) << 8) +#define MCF5272_SDRAMC_SDCTR_RP(x) ((x & 0x3) << 4) +#define MCF5272_SDRAMC_SDCTR_RCD(x) ((x & 0x3) << 2) +#define MCF5272_SDRAMC_SDCTR_CLT_2 (0x00000001) +#define MCF5272_SDRAMC_SDCTR_CLT_3 (0x00000002) +#define MCF5272_SDRAMC_SDCTR_CLT_4 (0x00000003) + +// --------------------------------------------------------------------------- + +// Timer module +typedef struct +{ + + // Timer mode register + cyg_uint16 tmr; + + // Gap + cyg_uint16 _res1; + + // Timer reference register + cyg_uint16 trr; + + // Gap + cyg_uint16 _res2; + + // Timer capture register + cyg_uint16 tcap; + + // Gap + cyg_uint16 _res3; + + // Timer counter register + cyg_uint16 tcn; + + // Gap + cyg_uint16 _res4; + + // Timer event register + cyg_uint16 ter; + + // Gap + cyg_uint16 _res5; + + // Gap + cyg_uint32 _res6[3]; + +} __attribute__ ((aligned (4), packed)) mcf5272_timer_t; + +// Related macros + +#define MCF5272_TIMER_TMR_PS (0xFF00) +#define MCF5272_TIMER_TMR_PS_BIT (8) +#define MCF5272_TIMER_TMR_CE (0x00C0) +#define MCF5272_TIMER_TMR_CE_BIT (6) +#define MCF5272_TIMER_TMR_OM (0x0020) +#define MCF5272_TIMER_TMR_OM_BIT (5) +#define MCF5272_TIMER_TMR_ORI (0x0010) +#define MCF5272_TIMER_TMR_ORI_BIT (4) +#define MCF5272_TIMER_TMR_FRR (0x0008) +#define MCF5272_TIMER_TMR_FRR_BIT (3) +#define MCF5272_TIMER_TMR_CLK (0x0006) +#define MCF5272_TIMER_TMR_CLK_BIT (1) +#define MCF5272_TIMER_TMR_RST (0x0001) +#define MCF5272_TIMER_TMR_RST_BIT (0) +#define MCF5272_TIMER_TER_REF (0x0002) +#define MCF5272_TIMER_TER_REF_BIT (1) +#define MCF5272_TIMER_TER_CAP (0x0001) +#define MCF5272_TIMER_TER_CAP_BIT (0) + +// --------------------------------------------------------------------------- + +// Watchdog timer +typedef struct +{ + + // Watchdog reset reference register + cyg_uint16 wrrr; + + // Gap + cyg_uint16 _res1; + + // Watchdog interrupt reference register + cyg_uint16 wirr; + + // Gap + cyg_uint16 _res2; + + // Watchdog counter register + cyg_uint16 wcr; + + // Gap + cyg_uint16 _res3; + + // Watchdog event register + cyg_uint16 wer; + + // Gap + cyg_uint16 _res4; + + // Gap + cyg_uint32 _res5[28]; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_wdtmr_t; + +// --------------------------------------------------------------------------- + +// Fast Ethernet Controller module +typedef struct +{ + + // Ethernet control register + cyg_uint32 ecr; + + // Ethernet interrupt event register + cyg_uint32 eir; + + // Ethernet interrupt mask register + cyg_uint32 eimr; + + // Interrupt vector status register + cyg_uint32 ivsr; + + // Receive descriptor active register + cyg_uint32 rdar; + + // Transmit descriptor active register + cyg_uint32 tdar; + + // Gap + cyg_uint8 _res2[0x0880 - 0x0858]; + + // MII management frame register + cyg_uint32 mmfr; + + // MII speed control register + cyg_uint32 mscr; + + // Gap + cyg_uint8 _res3[0x08cc - 0x0888]; + + // FIFO receive bound register + cyg_uint32 frbr; + + // FIFO receive start register + cyg_uint32 frsr; + + // Gap + cyg_uint8 _res4[0x08e4 - 0x08d4]; + + // Transmit FIFO watermark + cyg_uint32 tfwr; + + // Gap + cyg_uint8 _res5[0x08ec - 0x08e8]; + + // Transmit FIFO start register + cyg_uint32 tfsr; + + // Gap + cyg_uint8 _res6[0x0944 - 0x08f0]; + + // Receive control register + cyg_uint32 rcr; + + // Maximum frame length register + cyg_uint32 mflr; + + // Gap + cyg_uint8 _res7[0x0984 - 0x094c]; + + // Transmit control register + cyg_uint32 tcr; + + // Gap + cyg_uint8 _res8[0x0c00 - 0x0988]; + + // RAM perfect match address low register + cyg_uint32 malr; + + // RAM perfect match address high register + cyg_uint32 maur; + + // Hash table high register + cyg_uint32 htur; + + // Hash table low register + cyg_uint32 htlr; + + // Pointer to receive descriptor ring + cyg_uint32 erdsr; + + // Pointer to transmit descriptor ring + cyg_uint32 etdsr; + + // Maximum receive buffer size + cyg_uint32 emrbr; + + // Gap + cyg_uint8 _res9[0x0c40 - 0x0c1c]; + + // FIFO RAM space + cyg_uint8 efifo[0x0e00 - 0x0c40]; + + // Gap + cyg_uint8 _res10[0x1000 - 0x0e00]; + +} __attribute__ ((aligned (4), packed)) mcf5272_fec_t; + +// --------------------------------------------------------------------------- + +// On-chip peripherals: this structure defines each register's offset from the +// current value of the MBAR register. +typedef struct +{ + + // 0x0000: System Integration Module (SIM) general configuration registers + mcf5272_sim_cfg_t cfg; + + // 0x0020: SIM interrupt controller registers + mcf5272_sim_int_t intc; + + // 0x0040: SIM chip-select modules + mcf5272_sim_cs_t cs[8]; + + // 0x0080: SIM general purpose I/O control registers + mcf5272_sim_gpio_t gpio; + + // 0x00a0: QSPI module + // TODO: a specific data structure is needed + cyg_uint32 qspi[8]; + + // 0x00c0: PWM module + // TODO: a specific data structure is needed + cyg_uint32 pwm[8]; + + // 0x00e0: DMA controller + // TODO: a specific data structure is needed + cyg_uint32 dmac[8]; + + // 0x0100: UART modules + mcf5272_uart_t uart[2]; + + // 0x0180: SIM SDRAM controller + mcf5272_sim_sdramctrl_t sdramc; + + // 0x0200: timer module + mcf5272_timer_t timer[4]; + + // 0x0280: SIM watchdog timer module + mcf5272_sim_wdtmr_t wdtimer; + + // 0x0300: physical layer interface controller + // TODO: a specific data structure is needed + cyg_uint32 plic[336]; + + // 0x0840: ethernet module + mcf5272_fec_t fec; + + // 0x1000: USB module + // TODO: a specific data structure is needed + cyg_uint32 usb[512]; + +} __attribute__ ((aligned (4), packed)) mcf5272_devs_t; + +// --------------------------------------------------------------------------- +// End of mcf5272_devs.h +#endif // CYGONCE_MCF5272_DEVS_H diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/var_arch.h b/ecos/packages/hal/coldfire/mcf5272/current/include/var_arch.h new file mode 100644 index 0000000..67a866b --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/var_arch.h @@ -0,0 +1,66 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H + +//============================================================================= +// +// var_arch.h +// +// Processor variant specific definitions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Definitions specific to the MCF5272 processor. +// Usage: Included by "hal_arch.h". Do not use directly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/mcf5272_devs.h> +#include CYGHWR_MEMORY_LAYOUT_H + + +// Declare the global pointer to the peripheral registers. +// Everyone should use the MCF5272_DEVS macro so it can be easily changed. +#define MCF5272_DEVS ((volatile mcf5272_devs_t *) CYGMEM_REGION_devs) + +// --------------------------------------------------------------------------- +// End of var_arch.h +#endif // CYGONCE_HAL_VAR_ARCH_H diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/var_basetype.h b/ecos/packages/hal/coldfire/mcf5272/current/include/var_basetype.h new file mode 100644 index 0000000..52f6363 --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/var_basetype.h @@ -0,0 +1,58 @@ +#ifndef CYGONCE_HAL_VAR_BASETYPE_H +#define CYGONCE_HAL_VAR_BASETYPE_H + +//============================================================================= +// +// var_basetype.h +// +// Standard types for this architecture variant +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Type definitions specific to the MCF5272 processor. +// Usage: Included by "basetype.h". Do not use directly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +// Use defaults for this architecture. + +// --------------------------------------------------------------------------- +// End of var_basetype.h +#endif // CYGONCE_HAL_VAR_BASETYPE_H diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/var_cache.h b/ecos/packages/hal/coldfire/mcf5272/current/include/var_cache.h new file mode 100644 index 0000000..02f9d08 --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/var_cache.h @@ -0,0 +1,188 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H + +//============================================================================= +// +// var_cache.h +// +// Variant HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Definitions specific to the MCF5272 processor cache. +// Usage: Included via "hal_cache.h". Do not use directly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/coldfire_regs.h> + +// We currently just enable the instruction cache on startup. There is +// no data cache. + +// ---------------------------------------------------------------------------- +// Cache dimensions - these vary between the ColdFire sub-models + +// Data cache +#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes + +// Size of a data cache line. Leave this value even if there is no data cache +// on 5272, otherwise some tests won't compile. +#define HAL_DCACHE_LINE_SIZE 16 + +#define HAL_DCACHE_WAYS 1 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 1024 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 1 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +// ---------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +// Note: Any locked lines will not be invalidated. +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +#define HAL_DCACHE_UNLOCK_ALL() + +// ---------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +// ---------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() CYGARC_MOVEC((CYG_WORD32)0x80000102, CYGARC_REG_CACR) + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() CYGARC_MOVEC((CYG_WORD32)0x00000102, CYGARC_REG_CACR) + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() CYGARC_MOVEC((CYG_WORD32)0x81000102, CYGARC_REG_CACR) + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() CYGARC_MOVEC((CYG_WORD32)0x81000102, CYGARC_REG_CACR) + +// Query the state of the instruction cache +//#define HAL_ICACHE_IS_ENABLED(_state_) + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +#define HAL_ICACHE_UNLOCK_ALL() + +// ---------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +// --------------------------------------------------------------------------- +// End of var_cache.h +#endif // ifndef CYGONCE_VAR_CACHE_H diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/var_intr.h b/ecos/packages/hal/coldfire/mcf5272/current/include/var_intr.h new file mode 100644 index 0000000..3a7d869 --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/var_intr.h @@ -0,0 +1,254 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H + +//========================================================================== +// +// var_intr.h +// +// MCF5272 processor variant interrupt, exception and clock support +// +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: Wade Jensen +// Date: 2005-25-06 +// Purpose: Provide interrupt, exception and clock definitions specific +// to the MCF5272 processor. +// Usage: Included via "hal_intr.h". Do not use directly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// Include any platform specific interrupt definitions. +#include <cyg/hal/plf_intr.h> + +// Include for the device addresses (MCF5272_DEVS). +#include <cyg/hal/var_arch.h> + +// Include for HAL I/O macros +#include <cyg/hal/hal_io.h> + +// -------------------------------------------------------------------------- +// Interrupt controller management + +// This chip has a programmable interrupt vector base which is different +// from the vector base register (VBR). All interrupts from the interrupt +// controller are offset from the programmable interrupt vector register +// (PIVR). However, the only legal value is 64. + +#define HAL_PROG_INT_VEC_BASE 64 + +// Vector numbers defined by the interrupt controller. +// These are all relative to the interrupt vector base number. +#define CYGNUM_HAL_INTERRUPT_USR_SPURINT (0 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_EXTINT1 (1 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_EXTINT2 (2 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_EXTINT3 (3 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_EXTINT4 (4 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_TMR0 (5 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_TMR1 (6 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_TMR2 (7 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_TMR3 (8 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_UART1 (9 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_UART2 (10 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_PLIP (11 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_PLIA (12 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_USB0 (13 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_USB1 (14 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_USB2 (15 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_USB3 (16 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_USB4 (17 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_USB5 (18 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_USB6 (19 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_USB7 (20 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_DMA (21 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_ERX (22 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_ETX (23 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_ENTC (24 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_QSPI (25 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_EXTINT5 (26 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_EXTINT6 (27 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_SWTO (28 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_RES1 (29 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_RES2 (30 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_INTERRUPT_RES3 (31 + HAL_PROG_INT_VEC_BASE) + +// ------------------------------------------------------------------------- +// Interrupt and exception vector table definitions. We need to redifine +// CYGNUM_HAL_ISR_MIN because the first usable vector is 65 + +#define CYGNUM_HAL_ISR_RANGE_DEFINED +#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_EXTINT1 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_RES3 +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1) + +// ------------------------------------------------------------------------- +// Spurious interrupt definition. The MCF5272 returns vector number 64, +// instead of 24, for spurious interrupts + +#define CYGNUM_HAL_SPURIOUS_INTERRUPT CYGNUM_HAL_INTERRUPT_USR_SPURINT + +// -------------------------------------------------------------------------- +// Interrupt controller definitions. + +// Interrupt priority tables +externC volatile cyg_uint8 cyg_hal_ILVL_table[CYGNUM_HAL_ISR_COUNT]; +externC volatile cyg_uint8 cyg_hal_IMASK_table[CYGNUM_HAL_ISR_COUNT]; + +externC void hal_interrupt_set_level(int vector, int level); +externC void hal_interrupt_mask(int vector); +externC void hal_interrupt_unmask(int vector); + +// Mask the interrupt associated with the given vector. +#define HAL_INTERRUPT_MASK( _vector_ ) \ + hal_interrupt_mask(_vector_) + +// Unmask the interrupt associated with the given vector. +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ + hal_interrupt_unmask(_vector_) + +// Set the priority level of an interrupt. +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _prilevel_ ) \ + hal_interrupt_set_level(_vector_, _prilevel_) + +// Acknowledge the interrupt by writing a 1 to the corresponding +// interrupt pending bit. Write 0 to all other interrupt pending bits. Leave +// all priority levels unchanged. Disable all interrupts while we access the +// hardware registers. +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ +CYG_MACRO_START \ + cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \ + cyg_uint32 _icr = _vec_offset / 8; \ + cyg_uint32 _icr_msk = 0x80000000 >> ((_vec_offset % 8) * 4); \ + cyg_uint32 _icr_oldval; \ + CYG_INTERRUPT_STATE _intr_state; \ + \ + HAL_DISABLE_INTERRUPTS(_intr_state); \ + HAL_READ_UINT32(&MCF5272_DEVS->intc.icr[_icr], _icr_oldval); \ + HAL_WRITE_UINT32(&MCF5272_DEVS->intc.icr[_icr], \ + _icr_oldval & (_icr_msk | 0x77777777)); \ + HAL_RESTORE_INTERRUPTS(_intr_state); \ +CYG_MACRO_END + +// Set/clear the interrupt transition register bit. Disable all +// interrupts while we access the hardware registers. +#define HAL_INTERRUPT_CONFIGURE( _vector_, _leveltriggered_, _up_ ) \ +CYG_MACRO_START \ + if (!(_leveltriggered_)) \ + { \ + cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \ + cyg_uint32 _itr_bit = 0x80000000 >> _vec_offset; \ + cyg_uint32 _pitr_oldval; \ + CYG_INTERRUPT_STATE _intr_state; \ + \ + HAL_DISABLE_INTERRUPTS(_intr_state); \ + HAL_READ_UINT32(&MCF5272_DEVS->intc.pitr, _pitr_oldval); \ + if (_up_) \ + { \ + HAL_WRITE_UINT32(&MCF5272_DEVS->intc.pitr, _pitr_oldval | _itr_bit); \ + } \ + else \ + { \ + HAL_WRITE_UINT32(&MCF5272_DEVS->intc.pitr, _pitr_oldval & (~_itr_bit)); \ + } \ + HAL_RESTORE_INTERRUPTS(_intr_state); \ + } \ +CYG_MACRO_END + +// -------------------------------------------------------------------------- +// Clock control + +// The MCF5272 has 4 timers, numbered 0...3. Define the timer number that we +// want to use for the OS clock. +#define CYGNUM_HAL_RTC_TIMER_NUM (3) + +// The vector used by the real-time clock +#define CYGNUM_HAL_INTERRUPT_RTC (CYGNUM_HAL_INTERRUPT_TMR3) + +// Initialize the timer to generate an interrupt every 10 ms. Use the +// system clock divided by 16 as the source. Using 10 as the prescaler +// gives a 2.4 us counter. When this counter reaches _period_, generate +// an interrupt. +#define HAL_CLOCK_INITIALIZE(_period_) \ +CYG_MACRO_START \ +HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tmr, \ + 0x0000); \ +HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].trr, \ + (_period_)); \ +HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn, 0); \ +HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].ter, 0x0003); \ +HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tmr, \ + (((10)-1) << MCF5272_TIMER_TMR_PS_BIT) | \ + (0 << MCF5272_TIMER_TMR_CE_BIT) | \ + (0 << MCF5272_TIMER_TMR_OM_BIT) | \ + (1 << MCF5272_TIMER_TMR_ORI_BIT) | \ + (0 << MCF5272_TIMER_TMR_FRR_BIT) | \ + (2 << MCF5272_TIMER_TMR_CLK_BIT) | \ + (1 << MCF5272_TIMER_TMR_RST_BIT)); \ +CYG_MACRO_END + +// We must clear the bit in the timer event register before we can get +// another interrupt. +#define HAL_CLOCK_RESET( _vector_, _period_ ) \ +CYG_MACRO_START \ +HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn, 0); \ +HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].ter, 0x0002); \ +CYG_MACRO_END + +// Read the current counter from the timer +#define HAL_CLOCK_READ( _pvalue_ ) \ +CYG_MACRO_START \ +HAL_READ_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn, \ + *(_pvalue_)); \ +CYG_MACRO_END + +// Measure clock latency +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY +#define HAL_CLOCK_LATENCY( _pvalue_ ) \ +CYG_MACRO_START \ + register cyg_int32 result; \ + HAL_CLOCK_READ( &result ); \ + *_pvalue_ = result - CYGNUM_HAL_RTC_PERIOD; \ +CYG_MACRO_END +#endif + +// --------------------------------------------------------------------------- +// End of var_intr.h +#endif // ifndef CYGONCE_HAL_VAR_INTR_H diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/var_regs.h b/ecos/packages/hal/coldfire/mcf5272/current/include/var_regs.h new file mode 100644 index 0000000..41cb3be --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/var_regs.h @@ -0,0 +1,67 @@ +#ifndef CYGONCE_HAL_VAR_REGS_H +#define CYGONCE_HAL_VAR_REGS_H + +//========================================================================== +// +// var_regs.h +// +// ColdFire MCF5272 variant CPU definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Provide register definitions for the MCF5272. +// Description: +// Usage: Included via "coldfire_regs.h". Do not use directly. +// +//####DESCRIPTIONEND#### +//========================================================================== + +// CPU space registers definitions + +#define CYGARC_REG_CACR 0x002 +#define CYGARC_REG_ACR0 0x004 +#define CYGARC_REG_ACR1 0x005 +#define CYGARC_REG_VBR 0x801 +#define CYGARC_REG_ROMBAR0 0xC00 +#define CYGARC_REG_RAMBAR0 0xC04 +#define CYGARC_REG_MBAR 0xC0F + +// --------------------------------------------------------------------------- +// End of var_regs.h +#endif // ifdef CYGONCE_HAL_VAR_REGS_H diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/var_startup.h b/ecos/packages/hal/coldfire/mcf5272/current/include/var_startup.h new file mode 100644 index 0000000..51f4b4f --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/var_startup.h @@ -0,0 +1,68 @@ +#ifndef CYGONCE_VAR_STARTUP_H +#define CYGONCE_VAR_STARTUP_H + +//============================================================================= +// +// var_startup.h +// +// ColdFire MCF5272 CPU variant startup header +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: ColdFire MCF5272 CPU variant startup header. +// Description: +// Usage: Included via "hal_startup.h". Do not use directly. +// +//####DESCRIPTIONEND#### +//========================================================================== + +#include <cyg/infra/cyg_type.h> + +// Include the platform-specific startup header. +#include <cyg/hal/plf_startup.h> + +// Variant specific hardware initialization routine +externC void var_reset(void) __attribute__ ((section (".boot"))); + +// Variant specific data initialization routine +externC void var_init_data(void) __attribute__ ((section (".boot"))); + +// --------------------------------------------------------------------------- +// End of var_startup.h +#endif // CYGONCE_VAR_STARTUP_H diff --git a/ecos/packages/hal/coldfire/mcf5272/current/include/variant.inc b/ecos/packages/hal/coldfire/mcf5272/current/include/variant.inc new file mode 100644 index 0000000..9c5781e --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/include/variant.inc @@ -0,0 +1,100 @@ +#ifndef CYGONCE_HAL_VARIANT_INC +#define CYGONCE_HAL_VARIANT_INC + +|========================================================================== +| +| variant.inc +| +| MCF5272 variant assembler header file +| +|========================================================================== +| ####ECOSGPLCOPYRIGHTBEGIN#### +| ------------------------------------------- +| This file is part of eCos, the Embedded Configurable Operating System. +| Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +| +| eCos is free software; you can redistribute it and/or modify it under +| the terms of the GNU General Public License as published by the Free +| Software Foundation; either version 2 or (at your option) any later +| version. +| +| eCos is distributed in the hope that it will be useful, but WITHOUT +| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +| FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +| for more details. +| +| You should have received a copy of the GNU General Public License +| along with eCos; if not, write to the Free Software Foundation, Inc., +| 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +| +| As a special exception, if other files instantiate templates or use +| macros or inline functions from this file, or you compile this file +| and link it with other works to produce a work based on this file, +| this file does not by itself cause the resulting work to be covered by +| the GNU General Public License. However the source code for this file +| must still be made available in accordance with section (3) of the GNU +| General Public License v2. +| +| This exception does not invalidate any other reasons why a work based +| on this file might be covered by the GNU General Public License. +| ------------------------------------------- +| ####ECOSGPLCOPYRIGHTEND#### +|============================================================================= +|#####DESCRIPTIONBEGIN#### +| +| Author(s): Enrico Piria +| Contributors: +| Date: 2005-25-06 +| Purpose: MCF5272 variant definitions. +| Description: This file contains the definitions specific to the +| CPU variant, used in the architecture HAL assembler file. +| Usage: Included by "vectors.S". Do not use directly. +| +|####DESCRIPTIONEND#### +|========================================================================== + +#include <cyg/hal/platform.inc> + + +| ----------------------------------------------------------------------------- +| CPU specific macros. These provide a common assembler interface to +| operations that may have CPU specific implementations on different +| variants of the architecture. + +| CPU initialization macro + .macro hal_cpu_init + + | Invalidate and disable the cache and ACRs. + move.l #0x01000000,%d0 + movec %d0,%cacr + + move.l #0x0,%d0 + movec %d0,%acr0 + movec %d0,%acr1 + .endm + + +| ---------------------------------------------------------------------------- +| This macro retrieves the IPL of the current interrupt from the +| interrupt controller register. This is needed because on inetrrupt entry +| all interrupts are disabled by writing to the status register, and thus +| loosing the current IPL. +| Input: interrupt vector number in d0 +| Output: IPL associated to interrupt in d0 + + .macro hal_variant_retrieve_ipl + + | Subtract minimum interrupt vector number + sub.l #CYGNUM_HAL_ISR_MIN,%d0 + + | Load IPL table address in a0 + lea cyg_hal_ILVL_table,%a0 + + | Retrieve IPL level for current interrupt + move.b (%a0,%d0.l),%d0 + + .endm + +| ---------------------------------------------------------------------------- +| end of variant.inc +#endif // ifndef CYGONCE_HAL_VARIANT_INC diff --git a/ecos/packages/hal/coldfire/mcf5272/current/src/hal_diag.c b/ecos/packages/hal/coldfire/mcf5272/current/src/hal_diag.c new file mode 100644 index 0000000..3c04110 --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/src/hal_diag.c @@ -0,0 +1,417 @@ +//========================================================================== +// +// hal_diag.c +// +// HAL diagnostic I/O support routines for the MCF5272 +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Code to manage the serial ports for diagnostic output. +// Description: +// +//####DESCRIPTIONEND#### +//========================================================================== + + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_UART1 +#include <cyg/hal/hal_if.h> // __comm_control_cmd_t +#include <cyg/hal/hal_io.h> // HAL I/O macros +#include <cyg/hal/hal_misc.h> // cyg_hal_is_break +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +#include <cyg/hal/plf_serial.h> + + +typedef struct { + CYG_ADDRWORD base; // [Pointer] to Port base address + unsigned int vector; // UART interrupt vector + CYG_WORD msec_timeout; // Timeout in msec +} channel_data_t; + +static channel_data_t ports[] = { + { + (CYG_ADDRWORD) (&((mcf5272_devs_t *) 0)->uart[0]), + CYGNUM_HAL_INTERRUPT_UART1, + 1000 + }, + + { + (CYG_ADDRWORD) (&((mcf5272_devs_t *) 0)->uart[1]), + CYGNUM_HAL_INTERRUPT_UART2, + 1000 + } +}; + + +static cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data); + +static void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch); + +static void +cyg_hal_plf_serial_init_channel(channel_data_t *port); + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch); + +static cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch); + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len); +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len); + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data); +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...); + + +// ---------------------------------------------------------------------------- +// Early initialization of comm. channels. +void +cyg_hal_plf_comms_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + cyg_uint32 portcnt; + static int initialized = 0; + + if (initialized) + return; + initialized = 1; + +#if (defined(CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL) && \ + CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL == 0) || \ + (defined(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL) && \ + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0) + + // UART0 pins are multplexed with GPIO port B. Enable them in + // port B control register. + HAL_READ_UINT32(&MCF5272_DEVS->gpio.pbcnt, portcnt); + HAL_WRITE_UINT32(&MCF5272_DEVS->gpio.pbcnt, ((portcnt & + ~(MCF5272_GPIO_PBCNT_URT0_MSK)) | + (MCF5272_GPIO_PBCNT_URT0_EN))); + + // Init channel 0 + cyg_hal_plf_serial_init_channel(&ports[0]); + + // Setup procs in the vector table for channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); +#endif + +#if (defined(CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL) && \ + CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL == 1) || \ + (defined(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL) && \ + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1) + + // UART1 pins need to be enabled in port D control register. + HAL_READ_UINT32(&MCF5272_DEVS->gpio.pdcnt, portcnt); + HAL_WRITE_UINT32(&MCF5272_DEVS->gpio.pdcnt, ((portcnt & + ~(MCF5272_GPIO_PDCNT_URT1_MSK)) | + (MCF5272_GPIO_PDCNT_URT1_EN))); + + // Init channel 1 + cyg_hal_plf_serial_init_channel(&ports[1]); + + // Setup procs in the vector table for channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[1]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); +#endif + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + + +void cyg_hal_plf_serial_init_channel(channel_data_t *port) +{ + CYG_WORD16 clk_div; + volatile mcf5272_uart_t *base = + (volatile mcf5272_uart_t *)((char *)MCF5272_DEVS + port->base); + // Initialize variable to prevent compiler warnings + unsigned int baud_rate = 1200; + + +#ifdef CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + if( (port-&ports[0]) == CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL ) + baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD; +#endif +#ifdef CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + if( (port-&ports[0]) == CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL ) + baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD; +#endif + + // Before we do anything else, make sure we have enabled RTS in case + // the device we are using relies on hardware flow control. + // Note that this step is our only attempt at hardware flow control. + HAL_WRITE_UINT8(&base->uop1, MCF5272_UART_UOP1_RTS); + + // Initialize UART + + // Reset Transmitter + HAL_WRITE_UINT8(&base->ucr, MCF5272_UART_UCR_RTX); + + // Reset Receiver + HAL_WRITE_UINT8(&base->ucr, MCF5272_UART_UCR_RRX); + + // Reset Mode Register + HAL_WRITE_UINT8(&base->ucr, MCF5272_UART_UCR_RMR); + + HAL_WRITE_UINT8(&base->ucr, MCF5272_UART_UCR_RES); + HAL_WRITE_UINT8(&base->ucr, MCF5272_UART_UCR_RBC); + + // Mode register 1 sets the UART to 8 data bits with no parity, and + // mode register 2 forces 1 stop bit. Also, interrupt generation + // on RxRDY signal is enabled by default. + // Reading or write to the mode register switches it from umr1 to umr2. + // To set it to umr1, we must write a reset mode register command to the + // command register. + HAL_WRITE_UINT8(&base->umr, MCF5272_UART_UMR_8BNP); + HAL_WRITE_UINT8(&base->umr, MCF5272_UART_UMR_1S); + + // Select a prescaled (by 1/16) CLKIN for the clock source + HAL_WRITE_UINT8(&base->usr_ucsr, MCF5272_UART_UCSR_CLKIN); + + // Calculate baud settings + clk_div = (CYG_WORD16) + ((CYGHWR_HAL_SYSTEM_CLOCK_MHZ*1000000)/ + (baud_rate * 32)); + HAL_WRITE_UINT8(&base->udu, clk_div >> 8); + HAL_WRITE_UINT8(&base->udl, clk_div & 0x00ff); + + // Enable the transmitter and receiver + HAL_WRITE_UINT8(&base->ucr, MCF5272_UART_UCR_TXRXEN); + + // Set interrupt priority to highest maskable level + HAL_INTERRUPT_SET_LEVEL(port->vector, 6); +} + + +cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + return ch; +} + + +void cyg_hal_plf_serial_putc(void *__ch_data, cyg_uint8 ch) +{ + channel_data_t *port = (channel_data_t *) __ch_data; + volatile mcf5272_uart_t *base = + (volatile mcf5272_uart_t *)((char *)MCF5272_DEVS + port->base); + cyg_uint8 usr_ucsr, utf; + + + // Loop until the transmit data holding register is empty + do + { + HAL_READ_UINT8(&base->usr_ucsr, usr_ucsr); + } while (!(usr_ucsr & MCF5272_UART_USR_TXRDY)); + + // Write the character to the transmit buffer + HAL_WRITE_UINT8(&base->urb_utb, ch); + + // Loop until the transmit data FIFO and the shift register are empty + do + { + HAL_READ_UINT8(&base->utf, utf); + HAL_READ_UINT8(&base->usr_ucsr, usr_ucsr); + } while ((utf & MCF5272_UART_UTF_TXB) || + (!(usr_ucsr & MCF5272_UART_USR_TXEMP))); +} + +static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); +} + + +static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, + cyg_uint32 __len) +{ + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); +} + + +static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + channel_data_t *port = (channel_data_t *) __ch_data; + volatile mcf5272_uart_t *base = + (volatile mcf5272_uart_t *)((char *)MCF5272_DEVS + port->base); + cyg_uint8 usr_ucsr; + + + // Read status + HAL_READ_UINT8(&base->usr_ucsr, usr_ucsr); + + // Check if a character is present + if (usr_ucsr & MCF5272_UART_USR_RRDY) + { + // Read character + HAL_READ_UINT8(&base->urb_utb, *ch); + return true; + } + + return false; +} + + +static cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + cyg_bool res; + + + delay_count = ((channel_data_t *)__ch_data)->msec_timeout; + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + return res; +} + + +static int cyg_hal_plf_serial_control(void *__ch_data, + __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t *port = (channel_data_t *) __ch_data; + volatile mcf5272_uart_t *base = + (volatile mcf5272_uart_t *)((char *)MCF5272_DEVS + port->base); + int ret = 0; + + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + + HAL_WRITE_UINT8(&base->uisr_uimr, MCF5272_UART_UIMR_FFULL); + HAL_INTERRUPT_UNMASK(port->vector); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + + HAL_INTERRUPT_MASK(port->vector); + HAL_WRITE_UINT8(&base->uisr_uimr, 0); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = port->vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = port->msec_timeout; + port->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + default: + break; + } + + return ret; +} + + +static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + channel_data_t *port = (channel_data_t *) __ch_data; + volatile mcf5272_uart_t *base = + (volatile mcf5272_uart_t *)((char *)MCF5272_DEVS + port->base); + char c; + + + // Disable the interrupt temporarily + HAL_WRITE_UINT8(&base->uisr_uimr, 0); + + *__ctrlc = 0; + + // Read character + HAL_READ_UINT8(&base->urb_utb, c); + if( cyg_hal_is_break( &c , 1 ) ) + { + *__ctrlc = 1; + } + + // Re-enable RxRDY interrupt + HAL_WRITE_UINT8(&base->uisr_uimr, MCF5272_UART_UIMR_FFULL); + + return CYG_ISR_HANDLED; +} diff --git a/ecos/packages/hal/coldfire/mcf5272/current/src/var_misc.c b/ecos/packages/hal/coldfire/mcf5272/current/src/var_misc.c new file mode 100644 index 0000000..0d411ec --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/src/var_misc.c @@ -0,0 +1,162 @@ +//========================================================================== +// +// var_misc.c +// +// Miscellaneous functions specific to the processor variant +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Miscellaneous functions specific to the MCF5272 processor. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_io.h> + +#include CYGHWR_MEMORY_LAYOUT_H + +// ------------------------------------------------------------------------- +// VSR table + +// For the MCF5272, we can point the VBR directly to the VSR table. +// However, the table must be on a 1 MB boundary. Locate the VSR table where +// the linker tells us to. + +volatile CYG_ADDRESS cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT] + __attribute__ ((section (".ramvec"))); + +// ------------------------------------------------------------------------- +// Function prototypes + +static void hal_update_interrupt_controller(int vector); + +// ------------------------------------------------------------------------- +// Interrupt controller management +// +// With the MCF5272 interrupt controller, it is not possible to mask an +// interrupt while retaining its associated priority. Moreover, if we enabled +// the use of interrupts with different priorities, we don't have a means to +// retrieve the priority of the current interrupt, after having raised the +// IPL to the maximum, in the first instruction of the HAL ISR handler. +// So, we use an auxiliary table (cyg_hal_ILVL_table) that records all the +// priorities set for the various interrupts. +// The purpose of the cyg_hal_IMASK_table table is to record wether an +// interrupt is currently masked (0) or not (1). + +volatile cyg_uint8 cyg_hal_ILVL_table[CYGNUM_HAL_ISR_COUNT]; +volatile cyg_uint8 cyg_hal_IMASK_table[CYGNUM_HAL_ISR_COUNT]; + + +// Update priority table and interrupt controller +void hal_interrupt_set_level(int vector, int level) +{ + cyg_uint32 index; + + CYG_ASSERT((0 <= (level) && 7 >= (level)), "Illegal level"); + CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector) + && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector"); + + HAL_TRANSLATE_VECTOR(vector, index); + cyg_hal_ILVL_table[index] = (cyg_uint8) level; + + hal_update_interrupt_controller(vector); +} + +// Update mask table and interrupt controller +void hal_interrupt_mask(int vector) +{ + cyg_uint32 index; + + CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector) + && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector"); + + HAL_TRANSLATE_VECTOR(vector, index); + cyg_hal_IMASK_table[index] = 0; + + hal_update_interrupt_controller(vector); +} + +// Update mask table and interrupt controller +void hal_interrupt_unmask(int vector) +{ + cyg_uint32 index; + + CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector) + && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector"); + + HAL_TRANSLATE_VECTOR(vector, index); + cyg_hal_IMASK_table[index] = 1; + + hal_update_interrupt_controller(vector); +} + + +// Set the priority in the interrupt control register. +// Disable all interrupts while we access the hardware registers. +static void hal_update_interrupt_controller(int vector) +{ + cyg_uint32 index; + cyg_uint8 level; + cyg_uint32 vec_offset; + cyg_uint32 icr, icr_msk_offset, icr_msk, icr_val, icr_oldval; + CYG_INTERRUPT_STATE intr_state; + + HAL_TRANSLATE_VECTOR(vector, index); + level = cyg_hal_IMASK_table[index] ? cyg_hal_ILVL_table[index] : 0; + + vec_offset = (vector) - HAL_PROG_INT_VEC_BASE - 1; + icr = vec_offset / 8; + icr_msk_offset = ((8-1)*4) - (vec_offset % 8) * 4; + icr_msk = 0x0F << (icr_msk_offset); + icr_val = (0x08 | (level & 0x07)) << icr_msk_offset; + + HAL_DISABLE_INTERRUPTS(intr_state); + HAL_READ_UINT32(&MCF5272_DEVS->intc.icr[icr], icr_oldval); + icr_val |= icr_oldval & 0x77777777 & ~icr_msk; + HAL_WRITE_UINT32(&MCF5272_DEVS->intc.icr[icr], icr_val); + HAL_RESTORE_INTERRUPTS(intr_state); +} +// ------------------------------------------------------------------------- +// End of var_misc.c diff --git a/ecos/packages/hal/coldfire/mcf5272/current/src/var_startup.c b/ecos/packages/hal/coldfire/mcf5272/current/src/var_startup.c new file mode 100644 index 0000000..6ff0951 --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/src/var_startup.c @@ -0,0 +1,76 @@ +//========================================================================== +// +// var_startup.c +// +// Functions for the processor variant startup +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Enrico Piria +// Contributors: +// Date: 2005-25-06 +// Purpose: Functions needed for MCF5272 startup. +// Description: This module contains code that sets up the variant specific +// hardware and data. All the code must be contained in the +// section called ".boot", in order for the ROMRAM startup +// to work properly. +// +//####DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_startup.h> + + +// Variant specific initialization routine. +// This routine must be called with interrupts disabled. +void var_reset(void) +{ + // Nothing to do +} + +// Variant specific data initialization routine +void var_init_data(void) +{ + int i; + + // Initialize priority and mask tables + for(i = 0; i < CYGNUM_HAL_ISR_COUNT; i++) + { + cyg_hal_IMASK_table[i] = 0; + cyg_hal_ILVL_table[i] = 0; + } +} diff --git a/ecos/packages/hal/coldfire/mcf5272/current/src/variant.S b/ecos/packages/hal/coldfire/mcf5272/current/src/variant.S new file mode 100644 index 0000000..d35c0fa --- /dev/null +++ b/ecos/packages/hal/coldfire/mcf5272/current/src/variant.S @@ -0,0 +1,110 @@ +|========================================================================== +| +| variant.S +| +| MCF5272 variant code +| +|========================================================================== +| ####ECOSGPLCOPYRIGHTBEGIN#### +| ------------------------------------------- +| This file is part of eCos, the Embedded Configurable Operating System. +| Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. +| +| eCos is free software; you can redistribute it and/or modify it under +| the terms of the GNU General Public License as published by the Free +| Software Foundation; either version 2 or (at your option) any later +| version. +| +| eCos is distributed in the hope that it will be useful, but WITHOUT +| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +| FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +| for more details. +| +| You should have received a copy of the GNU General Public License +| along with eCos; if not, write to the Free Software Foundation, Inc., +| 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +| +| As a special exception, if other files instantiate templates or use +| macros or inline functions from this file, or you compile this file +| and link it with other works to produce a work based on this file, +| this file does not by itself cause the resulting work to be covered by +| the GNU General Public License. However the source code for this file +| must still be made available in accordance with section (3) of the GNU +| General Public License v2. +| +| This exception does not invalidate any other reasons why a work based +| on this file might be covered by the GNU General Public License. +| ------------------------------------------- +| ####ECOSGPLCOPYRIGHTEND#### +|============================================================================= +|#####DESCRIPTIONBEGIN#### +| +| Author(s): Enrico Piria +| Contributors: +| Date: 2005-25-06 +| Purpose: MCF5272 variant code. +| Description: This file contains the VSR table for the MCF5272, and +| other definitions used by the rest of the ColdFire HAL. +| +|####DESCRIPTIONEND#### +|========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/hal/cf_offsets.inc> + + +| ---------------------------------------------------------------------------- +| ROM vector table + + .section ".romvec","ax" + + .extern cyg_interrupt_stack + .extern cyg_hal_reset_vsr + .extern cyg_hal_default_exception_vsr + .extern cyg_hal_default_spurious_vsr + .extern cyg_hal_default_interrupt_vsr + + .globl rom_vsr_table +rom_vsr_table: + + | 0 - Initial SSP + .long cyg_interrupt_stack + + | 1 - Initial PC + .long cyg_hal_reset_vsr + + | 2-14 - Default exception handlers + .rept 14-2+1 + .long cyg_hal_default_exception_vsr + .endr + + | 15 - Uninitialized interrupt. It should never happen, because + | we configure interrupt controller at startup. + .long cyg_hal_default_spurious_vsr + + | 16-23 - Reserved, treat as exceptions + .rept 23-16+1 + .long cyg_hal_default_exception_vsr + .endr + + | 24 - Spurious interrupt + .long cyg_hal_default_spurious_vsr + + | 25-31 - Autovectored interrupts 1-7. Not used in MCF5272. + .rept 31-25+1 + .long cyg_hal_default_interrupt_vsr + .endr + + | 32-63 - Default exception handlers + .rept 63-32+1 + .long cyg_hal_default_exception_vsr + .endr + + | 64 - User spurious interrupt. The MCF5272 interrupt controller + | returns this vector number instead of vector 24 + .long cyg_hal_default_spurious_vsr + + | 65-255 - User interrupt vectors + .rept 255-65+1 + .long cyg_hal_default_interrupt_vsr + .endr |