Added the OS files

author: Michael Gielda <mgielda@antmicro.com> 2014-04-03 14:53:04 +0200
committer: Michael Gielda <mgielda@antmicro.com> 2014-04-03 14:53:04 +0200
commit: ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch)
tree: f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/cortexm
parent: f157da5337118d3c5cd464266796de4262ac9dbd (diff)
306 files changed, 53511 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/ChangeLog b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/ChangeLog
new file mode 100644
index 0000000..59ad9c7
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/ChangeLog
@@ -0,0 +1,45 @@
+2011-01-18  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/hal_cortexm_a2f200_eval.cdl:
+	* doc/a2f200e.sgml
+	* src/a2f200_eval_misc.c:
+	* src/platform_i2c.c:
+	* host/memory-map.xml:
+	* host/softconsole_flash_init.txt:
+	* host/softconsole_sram_init.txt:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_rom.h:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_a2f200_eval_sram.h:
+	New package -- Actel Smartfusion A2F200 EVAL board HAL.
+	[Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
+
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/cdl/hal_cortexm_a2f200_eval.cdl b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/cdl/hal_cortexm_a2f200_eval.cdl
new file mode 100644
index 0000000..3469aa6
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/cdl/hal_cortexm_a2f200_eval.cdl
@@ -0,0 +1,328 @@
+##==========================================================================
+##
+##      hal_cortexm_a2f200_eval.cdl
+##
+##      Actel Smartfusion A2F200 EVAL platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Date:         2011-02-13
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_A2F200_EVAL {
+    display       "Actel Smartfusion Development Board HAL"
+    doc           ref/hal-cortexm-a2fxxx-a2f200-eval.html
+    parent        CYGPKG_HAL_CORTEXM_A2FXXX
+    define_header hal_cortexm_a2f200_eval.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The Actel Smartfusion HAL package provides the support needed to run
+        eCos on the Actel Smartfusion A2F200 EVAL board."
+
+    compile       a2f200_eval_misc.c platform_i2c.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+                    (1 == CYGHWR_DEVS_ETH_PHY_DP8384X) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_a2fxxx.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_a2f200_eval.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Smartfusion A2F200 EVAL\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_option CYGNUM_DEVS_FLASH_SPI_AT25XXX_DEV0_MAP_ADDR {
+        display       "Base address of the SPI flash device"
+        flavor        data
+        default_value 0x10000000
+        description   "
+            Specifies the base address of the Atmel AT95DFxxx SPI flash."
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Architecture Startup type"
+        flavor        data
+        legal_values  { "SRAM" "ROM" }
+        calculated    { CYG_HAL_PLF_STARTUP == "SRAM" ? "SRAM" : "ROM" }
+        description   "
+            Mapping of CYG_HAL_PLF_STARTUP to CYG_HAL_STARTUP"
+        define -file system.h CYG_HAL_STARTUP
+    }
+
+    cdl_component CYG_HAL_PLF_STARTUP {
+        display       "Platform Startup type"
+        flavor        data
+        default_value {"ROM"}
+        legal_values  {"SRAM" "ROM" "ROM_SOFTCONSOLE"}
+        description   "
+            When targeting the Smartfusion A2F200 EVAL board it is possible 
+            to build the system for either SRAM bootstrap or ROM bootstrap.
+            Select 'SRAM' when building programs to load into SRAM using 
+            on-board debug software such as RedBoot or eCos GDB stubs or via 
+            a JTAG debugger.
+            Select 'ROM' when building a stand-alone application which will 
+            be put into ROM. The 'ROM_SOFTCONSOLE' type allows programs to be 
+            loaded (to 'ROM') and debug using the SoftConsole IDE."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated    { (CYG_HAL_PLF_STARTUP == "SRAM" ) ? "cortexm_a2f200_eval_sram"      :
+                        (CYG_HAL_PLF_STARTUP == "ROM" )  ? "cortexm_a2f200_eval_rom"       :
+                        (CYG_HAL_PLF_STARTUP == "ROM_SOFTCONSOLE" )  ? "cortexm_a2f200_eval_rom_sc" :
+                                                       "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+                display "Memory layout linker script fragment"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+                display "Memory layout header file"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_H
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    # Both UARTs 0 and 1 are available for diagnostic/debug use.
+    implements CYGINT_HAL_A2FXXX_UART0
+
+    implements      CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+    implements      CYGINT_IO_SERIAL_LINE_STATUS_HW
+    
+    
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The Actel Smartfusion EVAL board has two serial ports. This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    0
+         description      "
+            The Actel Smartfusion EVAL has two serial ports. This option
+            chooses which port will be used for diagnostic output."
+     }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port if the
+            console and GDB port are the same."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        requires { CYGNUM_REDBOOT_FLASH_BASE == 0x60000000 }
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary images"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to binary image formats suitable for ROM programming."
+
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_A2FXXX_EVAL_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O binary $< $@
+        }
+
+        description "This component causes the ELF image generated by the
+                     build process to be converted to S-Record and binary
+                     files."
+    }
+    
+}
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml
new file mode 100644
index 0000000..7175a04
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/doc/a2f200e.sgml
@@ -0,0 +1,814 @@
+<!-- DOCTYPE reference  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                         -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     a2f200e.sgml                                                -->
+<!--                                                                 -->
+<!--     Actel Smartfusion Board Support.                            -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2011 Free Software Foundation, Inc.               -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   ccoutand                                           -->
+<!-- Contact(s):                                                     -->
+<!-- Date:        2011/06/04                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+<part id="hal-cortexm-a2fxxx-a2f200-eval"><title>Actel Smartfusion Board Support</title>
+
+  <!-- {{{ Actel Smartfusion Board Support  -->
+  <chapter id="a2f200-eval-chapter">
+
+      <title>Actel Smartfusion Board Support</title>
+
+      <!-- {{{ Overview -->
+      <refentry id="a2f200-over">
+
+      <refmeta>
+          <refentrytitle>Overview</refentrytitle>
+      </refmeta>
+
+      <refnamediv>
+          <refname>Overview</refname>
+          <refpurpose>Actel Smartfusion Board Support</refpurpose>
+      </refnamediv>
+
+      <refsect1 id="a2f200-eval-overview"><title>Overview</title>
+
+      <para>
+        The Actel Smartfusion evaluation kit uses the A2F200 microcontroller from the 
+        Actel smartfusion family. The SmartFusion devices are a mix of programmable 
+        logic around a ARM cortex-M3 based processor. The SmartFusion has 3 variants: 
+        A2F060, A2F200, A2F500. The main difference between parts are the amount of 
+        RAM, FLASH as well as programmable logic. In addition, the A2F060 does not
+        include the Ethernet controller peripheral.
+        The A2F200 device includes 256KB of internal FLASH (also called Embedded 
+        Non-volatile Memory, ENVM) and 64KB of internal SRAM. 
+        The device has various peripherals such as UART, I2C, SPI, Ethernet MAC, ADC or 
+        DAC as well as the FPGA fabric. 
+        The kit features an OLED graphical display and UART0 is accessible via the 
+        on-board USB to UART converter. The kit also includes a serial flash, the Atmel 
+        AT25DF641 part (8MB memory). 
+        The FPGA fabric uses a non-volatile technology thus removing the 
+        need of additional flash memory for storing the FPGA programming matrix.
+      </para>
+
+      <para>
+        The eCos port targets standalone ROM application. The eCos device drivers include
+        support for the I2C and SPI buses as well as UART and Ethernet Controller. No 
+        device driver is currently available for the ADC/DAC or the In-Application 
+        Programming feature that allows the application to re-program the FLASH or the 
+        FPGA fabric.
+        The Smartfusion (A2Fxxx) HAL includes a timer test application and the A2F200 evaluation 
+        board flash device package includes a test application for the SPI serial flash.
+      </para>
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ Tools -->
+     <refsect1 id="a2f200-eval-tools"><title>Tools</title>
+
+     <para>
+        For compilation, the official eCos ARM toolchain is required (gcc version 4.3.2). 
+        For debugging, while the board offers a JTAG interface, the HAL was developed using 
+        the SoftConsole IDE supplied from Actel. SoftConsole is an Eclipse based IDE 
+        installed along with the CodeSourcery ARM compiler / debugger.  The ARM GDB and Sprite 
+        utilities from CodeSourcery are used to debug the target. The target includes an on-board 
+        debugger and is connected to the host via a USB cable. GDB interfaces the  
+        on-board debugger through the Actel flashpro driver. Detailed example of a debugging 
+        session is described later in this chapter.
+      </para>
+
+     </refsect1>
+     <!-- }}} -->
+     </refentry>
+     
+
+     <!-- {{{ HAL port -->
+       <refentry id="a2f200-eval-hal">
+      <refmeta>
+          <refentrytitle>HAL and Device Drivers</refentrytitle>
+      </refmeta>
+
+      <refnamediv>
+          <refname>HAL</refname>
+          <refpurpose>Actel HAL and Device Drivers</refpurpose>
+      </refnamediv>
+
+      <!-- {{{ Clocking -->
+     <refsect1 id="a2f200-eval-hal-clock"><title>Clocking</title>
+
+     <para>
+         The internal clock network of the Smarfusion devices includes a large amount of possible 
+         configuration combination. The network has 3 different input clocks (CLKA, CLKB and CLKC), 
+         each of them can be connected to a different clock source such as the main oscillator, the 
+         RC oscillator, the FPGA fabric or the dedicated single-ended or differential IO. The clock
+         network has an internal PLL and 3 global output clocks (CLKGA, CLKGB and CLKGC). The cortex-M3,
+         digital and analog peripherals clocks are derived either from CLKGA or CLKGC through the
+         NGMUX.
+         Due to the large amount of configuration parameters, it is recommended to use the Actel MSS
+         configuration tool to setup the clock network and let the system boot handle the configuration.
+         However, the eCos HAL includes all the required options to setup the clock network. Note that
+         only a limited subset of combinations have been tested.
+     </para>
+
+     </refsect1>
+     <!-- }}} -->
+
+     <!-- {{{ SPI Bus -->
+     <refsect1 id="a2f200-eval-hal-spi"><title>SPI bus</title>
+
+     <para>
+        The Actel AF2xxx microcontroller family has 2 SPI buses available. Each SPI bus has 
+        a certain number of slave select line (called SPI_x_SSx) that are directly driven by 
+        the SPI controller. 
+        The first SPI bus has 4 slave select lines available (SPI_0_SS0 to SPI_0_SS3) while the 
+        second bus has 8 of them (SPI_1_SS0 to SPI_1_SS7). In addition, the eCos SPI driver allows
+        using the GPIO of the microcontroller as slave select lines which is in some cases required. 
+        In the rest of this chapter, the former case is called SPI controlled slave select while 
+        the later is called GPIO controlled slave select
+     </para>
+
+     <para>
+        NOTE: The SPI_x_SSx microcontroller dedicated pins can be used as GPIO, thus, it is possible 
+        to use SPI_0_SS0 as slave select either in SPI or GPIO controlled mode. This is true for all 
+        SPI_x_SSx pins.
+     </para>
+
+     <para>
+        New SPI devices are instantiated using the following macro:
+     </para>
+     <programlisting width=80>
+        #include <filename class="headerfile">&lt;cyg/io/spi.h&gt;</filename>
+        #include <filename class="headerfile">&lt;cyg/io/spi_a2fxxx.h&gt;</filename>
+
+        #define CYG_DEVS_SPI_CORTEXM_A2FXXX_DEVICE(                    \
+                _name_, _bus_, _csnum_, _csgpio_, _proto_, _clpol_,    \
+                _clpha_, _brate_, _csup_dly_, _csdw_dly_, _trbt_dly_)
+
+
+        _name_     is the name of the SPI device. This will be used to 
+                   reference a data structure of type cyg_spi_device 
+                   which can be passed to the SPI driver API without 
+                   needing a cast.
+        _bus_      is the bus number to which this device is attached 
+                   (1 or 2).
+        _csgpio_   when set to false:
+                    - the device slave select line is controlled by the 
+                      SPI controller.
+                   when set to true:
+                    - the device slave select line is a GPIO of the 
+                      processor controlled by the SPI driver.
+        _csnum_    when _csgpio_ is set to false : 
+                    - is the slave select line used for this device, 
+                      numbered from 0.
+                   when _csgpio_ is set to true : 
+                    - is the GPIO number used to drive the device slave 
+                      select line.
+        _proto_    is the SPI bus protocol:
+                    0 -> Motorola SPI Mode (_clpol_ and _clpha_ are 
+                         valid in this mode)
+                    1 -> National Semiconductor MICROWIRE Mode
+                    2 -> Texas Instruments (TI) Synchronous Serial Mode
+        _clpol_    is the SPI bus clock polarity used by the device 
+                   (valid only for Motorola SPI Protocol).
+        _clpha_    is the SPI bus clock phase used by the device 
+                   (valid only for Motorola SPI Protocol).
+        _brate_    is the SPI bus clock baud rate used by the device, 
+                   measured in Hz.
+        _csup_dly_ is the minimum delay between slave select assert and 
+                   transfer start, measured in microseconds.
+        _csdw_dly_ is the minimum delay between transfer end and slave 
+                   select deassert, measured in microseconds.
+        _trbt_dly_ is the minimum delay between consecutive transfers.
+     </programlisting>
+
+     <para>
+        NOTE: _csup_dly_ and _csdw_dly_ are only valid when GPIOs are configured to drive the 
+        slave select line. When the SPI controller drives the slave select line itself, the user 
+        has no control over the exact timing.
+     </para>
+
+     <para>
+        The Actel Smartfusion board features a SPI serial flash (AT25DF641) attached 
+        to the first SPI bus. The SPI flash is connected to the SPI_0_SS0 line, however, to suit 
+        eCos SPI transaction, the line is configured as a general purpose IO and controlled by the 
+        SPI driver.
+     </para>
+
+     <para>
+        The following section describes how the SPI serial flash is declared. The code is located
+        in devs/fash/cortexm/a2fxxx/a2f200_eval/flash_a2f200_eval.c. The required includes are:
+     </para>
+
+     <programlisting width=80>
+        #include <filename class="headerfile">&lt;cyg/io/spi.h&gt;</filename>
+        #include <filename class="headerfile">&lt;cyg/io/at25dfxxx.h&gt;</filename>
+        #include <filename class="headerfile">&lt;cyg/io/spi_a2fxxx.h&gt;</filename>
+     </programlisting>
+
+     <para>
+        The device is defined to be connected on SPI bus 1, using GPIO 19 for slave select.
+        The Motorola protocol (mode 0) is selected with a bus clock speed of 25MHz.
+     </para>
+
+     <programlisting width=80>
+         CYG_DEVS_SPI_CORTEXM_A2FXXX_DEVICE (
+            at25dfxxx_spi_device, 1, 19, true, A2FXXX_SPI_MOTOROLA, 0, 0, 25000000, 1, 1, 1
+         );
+        
+         _bus_      = 1 
+         _csgpio_   = true -> use GPIO
+         _csgpio_   = 19   -> GPIO19 also SPI_0_SS0
+         _proto_    = Motorola Protocol
+         _clpol_    = 0
+         _clpha_    = 0
+         _brate_    = 25MHz
+         _csup_dly  = 1us
+         _csdw_dly_ = 1us
+         _trbt_dly_ = 1us
+     </programlisting>
+
+     <para>
+        From the default CDL, SPI bus 1 uses the DMA channel 0 for outbound and channel 1 for inbound 
+        transfer. SPI bus 2 uses DMA channel 2 and 3 respectively. The DMA channel number are selected 
+        with:
+     </para>
+
+     <programlisting width=80>
+        CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_TX_DMA
+        CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS1_RX_DMA 
+        and
+        CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_TX_DMA
+        CYGNUM_DEVS_SPI_CORTEXM_A2FXXX_BUS2_RX_DMA 
+     </programlisting>
+
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ I2C Bus -->
+     <refsect1 id="a2f200-eval-hal-i2c"><title>I2C bus</title>
+
+     <para>
+        The Actel microcontroller family has 2 I2C buses available and the Smartfusion evaluation kit
+        feature an OLED display connected to the first I2C bus with address 0x3C. 
+        The I2C driver is tested using the OLED display, however, the OLED driver is not part of the 
+        eCos HAL. A new I2C bus is instantiated using the following macro:
+     </para>
+
+     <programlisting width=80>
+        #define CYG_A2FXXX_I2C_BUS(                             \
+                _name_,                                         \
+                _init_fn_,                                      \
+                _base_,                                         \
+                _base_bb_,                                      \
+                _periph_,                                       \
+                _isr_vec_,                                      \
+                _isr_pri_)                                      \
+
+        _name_      is the name of the SPI device.
+        _init_fn_   is the I2C initialization function to be called by the C constructor.
+        _base_      is the base address of the I2C peripheral.
+        _base_bb_   is the Bit-Band base address of the I2C peripheral.
+        _periph_    is the peripheral bit identifier for reset/release operation.
+        _isr_vec_   is the peripheral interrupt vector number.
+        _isr_pri_   is the interrupt priority.
+     </programlisting>
+
+     <para>
+        The following section describes how the I2C bus 0 is declared. The code is located in
+        hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c. The required includes are:
+     </para>
+
+     <programlisting width=80>
+        #include <filename class="headerfile">&lt;cyg/io/i2c.h&gt;</filename>
+        #include <filename class="headerfile">&lt;cyg/io/i2c_a2fxxx.h&gt;</filename>
+     </programlisting>
+
+     <para>
+        The first part declares the I2C bus 0 and the second part attached a I2C device with address
+        0x3C to the bus.
+     </para>
+
+     <programlisting width=80>
+         CYG_A2FXXX_I2C_BUS(hal_a2fxxx_i2c0_bus,
+                 a2fxxx_i2c0_init,
+                 CYGHWR_HAL_A2FXXX_I2C0,
+                 CYGHWR_HAL_A2FXXX_I2C0_BB,
+                 CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0,
+                 CYGNUM_HAL_INTERRUPT_I2C0_0,
+                 0x60);
+
+         _name_     = hal_a2fxxx_i2c0_bus
+         _init_fn_  = a2fxxx_i2c0_init
+         _base_     = CYGHWR_HAL_A2FXXX_I2C0                    // Base address
+         _base_bb_  = CYGHWR_HAL_A2FXXX_I2C0_BB                 // for bit-band access
+         _periph_   = CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0
+         _isr_vec_  = CYGNUM_HAL_INTERRUPT_I2C0_0
+         _isr_pri_  = 0x60
+
+         CYG_I2C_DEVICE(i2c_a2fxxx_oled,
+                 &#38hal_a2fxxx_i2c0_bus,
+                 0x3c,
+                 0,
+                 CYG_I2C_DEFAULT_DELAY);
+     </programlisting>
+
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ Ethernet Controller -->
+     <refsect1 id="a2f200-eval-hal-eth"><title>Ethernet Controller</title>
+
+     <para>
+         The Ethernet MAC layer of the Actel device is compliant with the RMII 10/100Mbps specification.
+         The development kit interface the DP83848 PHY from National Semiconductor.
+     </para>
+     <para>
+         NOTE: To use the Ethernet interface of the evaluation kit, the FPGA fabric must be programmed.
+         The Ethernet PHY input clock (50MHz) is connected to an IO only accessible from the fabric. It 
+         is therefore required to route the MAC_CLK from the clock network to the IO (T6).
+     </para>
+     <para>
+         Some of the driver configuration parameters accessible from the CDL file are:
+     </para>
+
+     <variablelist>
+     <varlistentry>
+          <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_CHATTER</term>
+          <listitem>
+          <para>
+           Selecting this option will cause the Ethernet driver to print status
+           messages as various Ethernet operations are undertaken. This is option
+           is designed to help debugging the Ethernet driver.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_PROMISCUOUS</term>
+          <listitem>
+          <para>
+           Selecting this option will set the Ethernet MAC in promiscuous mode, all Ethernet
+           packets will be delivered to the application layer whether or not destinated to the
+           device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_TX</term>
+          <listitem>
+          <para>
+           This option specifies the size of the internal transmit buffers used
+           for the Ethernet device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_BUFSIZE_RX</term>
+          <listitem>
+          <para>
+           This option specifies the size of the internal receive buffers used
+           for the Ethernet device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_TxNUM</term>
+          <listitem>
+          <para>
+           This option specifies the number of output buffer packets
+           to be used for the Ethernet device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_RxNUM</term>
+          <listitem>
+          <para>
+           This option specifies the number of input buffer packets
+           to be used for the Ethernet device.
+          </para>
+          </listitem>
+     </varlistentry>
+
+     <varlistentry>
+          <term>CYGSEM_DEVS_ETH_CORTEXM_A2FXXX_STATS</term>
+          <listitem>
+          <para>
+           Selecting this option will cause the Ethernet driver to accumulate statistics 
+           provided from the MAC layer.
+          </para>
+          </listitem>
+     </varlistentry>
+     </variablelist>
+
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ Serial -->
+     <refsect1 id="a2f200-eval-hal-serial"><title>Serial</title>
+
+     <para>
+         The Actel A2Fxxx uses the 16x5x generic serial device driver. The driver is instantiaced through 
+         the CYGPKG_IO_SERIAL_CORTEXM_A2FXXX serial package.
+     </para>
+
+     </refsect1>
+     <!-- }}} -->
+
+      <!-- {{{ DMA -->
+     <refsect1 id="a2f200-eval-hal-dma"><title>DMA</title>
+
+     <para>
+         The eCos HAL offers some basics routines to configure and use the 8 DMA channels
+         available in the Smartfusion chips. It must be noted that all channels are sharing 
+         the same interrupt. The current implementation limits the transfer size to byte 
+         tranfer ( field TRANSFER_SIZE from the CHANNEL_x_CONTROL register ).
+         Currently only the SPI driver makes use of the DMA interface.
+     </para>
+
+     <para>
+         DMA channels are registered / released with <literal>a2fxxx_dma_ch_attach</literal> and 
+         <literal>a2fxxx_dma_ch_detach</literal> respectively:
+     </para>
+
+     <programlisting width=80>
+     cyg_uint32
+     a2fxxx_dma_ch_attach(cyg_uint8 ch, cyg_ISR_t *isr, cyg_DSR_t *dsr, cyg_addrword_t data)
+
+     ch         specify the DMA channel numbered from 0.
+     isr        specify the interrupt ISR to call for this channel.
+     dsr        specify the interrupt DSR to call for this channel.
+     data       data argument passed to the ISR and DSR routine.
+     </programlisting>
+
+     <programlisting width=80>
+     void
+     a2fxxx_dma_ch_detach (cyg_uint8 ch)
+
+     ch         specify the DMA channel number from 0 to 7
+     </programlisting>
+
+
+     <para>
+         DMA channels are configured with <literal>a2fxxx_dma_ch_setup</literal> :
+     </para>
+
+     <programlisting width=80>
+     cyg_uint32
+     a2fxxx_dma_ch_setup(cyg_uint8 ch, cyg_uint8 type, cyg_bool outbound, 
+           cyg_uint8 src_incr, cyg_uint8 dst_incr, cyg_bool pri, cyg_uint8 wr_adj)
+
+     ch         is the DMA channel numbered from 0.
+     type       is the transfer type to be performed. For valid
+                values, check CYGHWR_HAL_A2FXXX_DMA_XFER(_x) in var_io.h.
+     outbound   set to true for transfer out of memory, false for transfer 
+                to memory
+     src_incr   is the memory address increment step for the source. Valid
+                values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA
+                transfer from peripheral FIFO for instance.
+     dst_incr   is the memory address increment step for the destination.
+                Valid values are 0, 1, 2 and 4 byte(s). 0 can be used for 
+                DMA transfer to peripheral FIFO for instance.
+     pri        is the DMA channel priority (true = high , false = low)
+     wr_adj     indicates the number of FCLK periods which the PDMA must wait 
+                after completion of a read or write access to a peripheral
+                before evaluating the out-of-band status signals from that 
+                peripheral for another transfer.
+     </programlisting>
+
+     <para>
+         DMA transfer are initiated using <literal>a2fxxx_dma_xfer</literal> :
+     </para>
+
+     <programlisting width=80>
+     cyg_uint32
+     a2fxxx_dma_xfer (cyg_uint8 ch, cyg_bool polled, cyg_uint32 len, cyg_uint8 *src, 
+                          cyg_uint8 *dst)
+
+     ch         is the DMA channel numbered from 0.
+     polled     set to true to use the DMA channel in polling mode ( no
+                end of tranfer interrupt are raised ).
+     len        select the length of the transfer ( in number of byte
+                transfered ).
+     src        is the start address from which data is to be read during 
+                the next DMA transfer cycle.
+     dst        is the start address from which data is to be written during 
+                the next DMA transfer cycle.
+     </programlisting>
+
+     <para>
+         DMA interrupts are cleared with <literal>a2fxxx_dma_clear_interrupt</literal> and
+         status of the transaction is retreived with <literal>a2fxxx_dma_get_comp_flag</literal> :
+     </para>
+
+     <programlisting width=80>
+     void
+     a2fxxx_dma_clear_interrupt (cyg_uint8 ch)
+
+     cyg_uint8 
+     a2fxxx_dma_get_comp_flag (cyg_uint8 ch)
+
+     ch         is the DMA channel numbered from 0.
+     </programlisting>
+
+     </refsect1>
+     <!-- }}} -->
+
+     </refentry>
+     <!-- }}} -->
+
+
+     <!-- {{{ Configuration -->
+     <refentry id="a2f200-eval-conf">
+     <refmeta>
+         <refentrytitle>Configuration</refentrytitle>
+     </refmeta>
+     <refnamediv>
+         <refname>Configuration</refname>
+         <refpurpose>Configure, compile and debug the application</refpurpose>
+     </refnamediv>
+
+     <refsect1 id="a2f200-eval-conf-ov">
+     <title><!-- <index></index> -->Overview</title>
+     <para>
+        For compilation of the application, the official eCos ARM toolchain is required 
+        (gcc version 4.3.2). 
+        For debugging, it is needed to install the FlashPro utility from Actel as well 
+        as SoftConsole. SoftConsole is an Eclipse based IDE from Microsemi that installs  
+        along with the CodeSourcery ARM toolchain. Both are freely available and require 
+        a Windows OS based host workstation.
+        To use some peripherals such as the Ethernet controller, the FPGA fabric must be
+        configured to route the Ethernet PHY clock from the MAC_CLK. It is recommended to
+        restore the factory image provided from Actel as a starting point in case the user  
+        has already experimented with the fabric.
+     </para>
+     </refsect1>
+     <!-- }}} -->
+
+     <refsect1 id="a2f200-eval-conf-build">
+     <title><!-- <index></index> -->Building the application</title>
+
+     <para>
+         The steps needed to build the HAL library for the Smartfusion evaluation board are:
+     </para>
+     <screen>
+         $ mkdir a2f200_eval
+         $ cd a2f200_eval
+         $ ecosconfig new smartfusion kernel
+         $ ecosconfig resolve
+         $ ecosconfig tree
+         $ make
+     </screen>
+     <para>
+         At the end of the build the <filename
+         class="directory">install/lib</filename> subdirectory should contain the library and linker script and the <filename
+         class="directory">install/include</filename> subdirectory the necessary includes to compile the application.
+     </para>
+
+     <para>
+         The differents startup type available for this platforme are:
+     </para>
+
+     <informaltable frame="all">
+       <tgroup cols="2" colsep="1" rowsep="1" align="left">
+         <thead>
+           <row>
+             <entry>Configuration (HAL_PLF_STARTUP_TYPE)</entry>
+             <entry>Description</entry>
+           </row>
+         </thead>
+         <tbody>
+           <row>
+             <entry>ROM</entry>
+             <entry>Application running from the board's internal flash, LMA = 0x60000000 and VMA = 0x60000000</entry>
+           </row>
+           <row>
+             <entry>SRAM</entry>
+             <entry>Application running from the board's internal RAM, LMA = 0x20000000 and VMA = 0x20000000</entry>
+           </row>
+           <row>
+             <entry>ROM_SOFTCONSOLE</entry>
+             <entry>Application running from the board's internal flash, LMA = 0x60000000 and VMA = 0x00000000</entry>
+           </row>
+         </tbody>
+       </tgroup>
+     </informaltable>
+
+     </refsect1>
+     <!-- }}} -->
+
+     <refsect1 id="a2f200-eval-conf-sys">
+     <title><!-- <index></index> -->System Boot</title>
+
+     <para>
+         The Smartfusion devices boot process is not entirely controlled by the user. The 
+         Embedded Non-volatile Memory contains spare pages that are reserved to store 
+         specific data such as the factory boot code, the manufacturing parameters, the 
+         system boot code or other data such as the Analog block or MSS configuration.
+     </para>
+
+     <para>
+         As described in the device user manual, the device first boots from factory boot
+         code before jumping to the system boot and eventually giving the hand to the user 
+         code, in this case, the eCos ROM application.
+     </para>
+
+     <para>
+         The Actel MSS configuration tool can be used to alter the system boot and the 
+         configuration pages. The ENVM spare pages can then be re-programmed using the 
+         Actel FlashPro utility. The FlashPro utility can also be used to program the 
+         FPGA fabric if required.
+     </para>
+
+     <informaltable frame="all">
+       <tgroup cols="2" colsep="1" rowsep="1" align="left">
+         <thead>
+           <row>
+             <entry>Spare page content</entry>
+             <entry>Address</entry>
+           </row>
+         </thead>
+         <tbody>
+           <row>
+             <entry>Manufacturing parameters</entry>
+             <entry>0x60080000</entry>
+           </row>
+           <row>
+             <entry>Factory boot</entry>
+             <entry>0x60080400</entry>
+           </row>
+           <row>
+             <entry>System Boot</entry>
+             <entry>0x60080800</entry>
+           </row>
+           <row>
+             <entry>Analog block configuration</entry>
+             <entry>0x60081600</entry>
+           </row>
+           <row>
+             <entry>MSS configuration</entry>
+             <entry>0x60081E80</entry>
+           </row>
+         </tbody>
+       </tgroup>
+     </informaltable>
+
+     </refsect1>
+     <!-- }}} -->
+
+     <refsect1 id="a2f200-eval-conf-dbg">
+     <title><!-- <index></index> -->Debugging from console</title>
+
+     <para>
+         Loading of the application to internal FLASH or RAM of the target is done either 
+         using the SoftConsole IDE supplied from Actel or GDB from command line. The later
+         case is described in this paragraph.
+     </para>
+
+     <para>
+         To debug ROM based application, while configuring eCos, select the ROM_SOFTCONSOLE 
+         startup type. The ROM_SOFTCONSOLE startup type is equivalent to a ROM startup but 
+         while the application is loaded at address 0x60000000 (FLASH), it runs and is debugged 
+         from address 0x00000000. This is done by setting the load address (LMA) to 0x60000000 
+         and the virtual address (VMA) to 0x00000000 in the eCos memory layout file. In this 
+         example, the timers test application from the eCos Smartfusion HAL is compiled:
+     </para>
+
+     <screen>
+         $ mkdir a2f200_eval
+         $ cd a2f200_eval
+         $ ecosconfig new smartfusion kernel
+           -> Select ROM_SOFTCONSOLE statup type
+         $ ecosconfig resolve
+         $ ecosconfig tree
+         $ make
+         $ make -s tests IGNORE_LINK_ERRORS=y
+     </screen>
+ 
+     <para>
+        Once the application is compiled, from a Windows command interpreter, start the 
+        actel-keepalive utility:
+     </para>
+
+     <screen>
+         c:> start actel-keepalive actel-keepalive
+     </screen>
+
+     <para>
+        The GDB initialisation sequence located in a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt
+        is an example of initialisation sequence to use for debugging application located in
+        ROM. For RAM based application, the initialisation sequence from 
+        a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt shall be used.
+        Make sure to replace the path to the debugger toolchain and the eCos repository first. The GDB
+        initialisation sequence without in-line comments is:
+     </para>
+
+     <screen>
+        set arm fallback-mode thumb
+        target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/b-
+        in/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortex-
+        m/a2fxxx/a2f200_eval/current/host"
+        set mem inaccessible-by-default off
+        set *0x40006010 = 0x4C6E55FA
+        set *0xE0042000 = 0
+        set *0xE0042008 = 1
+        set *0xE0042040 = 0x00207FFD
+        set *0xE004203C = 0x00000001
+        set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7
+        set *0xE000ED08 = 0x00000000
+        load
+        set $sp = *0x60080000
+        set $pc = *0x60080004 - 1
+     </screen>
+
+     <para>
+         Start the GDB session to debug the timers test example:
+     </para>
+
+     <screen>
+         C:\root\a2f200_eval>arm-none-eabi-gdb install\tests\hal\cortexm\a2fxxx\var\curren-
+         t\tests\timers
+         GNU gdb (Sourcery G++ Lite Sourcery G++ Lite 2010q1-188 + Actel 1.2) 7.0.50.20100-
+         218-cvs
+         Copyright (C) 2010 Free Software Foundation, Inc.
+         License GPLv3+: GNU GPL version 3 or later &lt;http://gnu.org/licenses/gpl.html&gt;
+         This is free software: you are free to change and redistribute it.
+         There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
+         and "show warranty" for details.
+         This GDB was configured as "--host=i686-mingw32 --target=arm-none-eabi".
+         For bug reporting instructions, please see:
+         &lt;https://support.codesourcery.com/GNUToolchain/&gt;...
+         Reading symbols from c:\root\a2f200_eval\install\tests\hal\cortexm\a2fxxx\var\curren-
+         t\tests\timers...done.
+         (gdb)
+     </screen>
+
+     <para>
+        A typical log from the GDB initialisation sequence is shown here:
+     </para>
+
+     <screen>
+        Remote debugging using | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourc-
+        ery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/h-
+        al/cortexm/a2fxxx/a2f200_eval/current/host"
+        arm-none-eabi-sprite: Using memory map C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f-
+        200_eval/current/host/memory-map.xml
+        arm-none-eabi-sprite: Target reset
+        arm-none-eabi-sprite: Transferring memory map (may cause a delay)
+        0x6008051c in ?? ()
+        Loading section .rom_vectors, size 0x8 lma 0x60000000
+        Loading section .ARM.exidx, size 0x10 lma 0x60000008
+        Loading section .text, size 0x3340 lma 0x60000018
+        Loading section .rodata, size 0x4dc lma 0x60003358
+        Loading section .data, size 0x318 lma 0x6000383c
+        arm-none-eabi-sprite: Using host routines for flash programming
+        arm-none-eabi-sprite: Start of flash programming
+        arm-none-eabi-sprite: Comparing flash memory contents of actel-smartfusion-envm @-
+        0x60000000
+        arm-none-eabi-sprite: Program 0x60000000 sector [0x0,+0x80) unchanged
+        arm-none-eabi-sprite: Program 0x60000000 sector [0x80,+0x80) unchanged
+        arm-none-eabi-sprite: Program 0x60000000 sector [0x100,+0x80) unchanged
+        ....
+        arm-none-eabi-sprite: Program 0x60000000 sector [0x3b00,+0x80) unchanged
+        arm-none-eabi-sprite: End of programming
+        Start address 0x18, load size 15180
+        Transfer rate: 8 KB/sec, 62 bytes/write.
+     </screen>
+
+     </refsect1>
+     <!-- }}} -->
+
+   </refentry>
+   <!-- }}} -->
+     
+  </chapter>
+   <!-- }}} -->
+
+</part>
+
+  
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/memory-map.xml b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/memory-map.xml
new file mode 100644
index 0000000..fa2b302
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/memory-map.xml
@@ -0,0 +1,16 @@
+<board>
+ <properties>
+  <property name="system-v6-m"/>
+ </properties>
+ <memory-map>
+    <memory-device address="0x60000000" size="256k" type="flash" device="actel-smartfusion-envm">
+      <description>Flash</description>
+    </memory-device>
+    <memory-device address="0x00000000" size="256k" type="rom">
+      <description>ROM</description>
+    </memory-device>
+    <memory-device address="0x20000000" size="64k" type="ram">
+      <description>SRAM</description>
+    </memory-device>
+  </memory-map>
+</board>
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt
new file mode 100644
index 0000000..47097c8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_flash_init.txt
@@ -0,0 +1,53 @@
+
+# GDB initialization sequence provided from SoftConsole IDE with slight modification
+# for eCos
+
+# [1] Targeting SmartFusion embedded NVM (envm) @ 0x60000000.
+#     Loads at 0x60000000 but runs/debugs at 0x00000000 (i.e. ld LMA=0x60000000, VMA=0x00000000)
+
+# Make sure 16-bit Thumb mode breakpoint requests are always used.
+set arm fallback-mode thumb
+
+# Invoke debug sprite in Cortex-M3 mode
+#
+# PATH to the arm-none-eabi-sprite utility and eCos repository must be
+# updated according to a particular setup
+target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host"
+
+# Don't restrict memory access to just regions defined in linker script
+set mem inaccessible-by-default off
+
+# Disable the watchdog
+set *0x40006010 = 0x4C6E55FA
+
+# Ensure that eSRAM IS NOT mapped to 0x00000000
+# Clear ESRAM_CONFIG system register bit 0 (COM_ESRAMFWREMAP)
+set *0xE0042000 = 0
+# Ensure that eNVM @ 0x60000000 IS mapped to 0x00000000
+# Set ENVM_REMAP_BASE register COM_ENVMREMAPBASE field to 1
+set *0xE0042008 = 1
+
+# Configure external memory controller to access external RAM.
+
+# Program EMC_CONFIG_0_REG
+set *0xE0042040 = 0x00207FFD
+# Program EMC_MUX_CONFIG_REG
+set *0xE004203C = 0x00000001
+# Program SOFT_RESET_REG
+set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7
+
+#set *0xE0042004 = 0x00000001
+
+# Set temporary breakpoint on main (must be h/w BP for eNVM)
+thb cyg_usert_start
+
+# Specify user application vector table (remapped/mirrored address)
+set *0xE000ED08 = 0x00000000
+
+# Load the program
+load
+
+# Ensure chip boot code runs before transferring control to user application
+# Initialize SP & PC from chip boot vector table
+set $sp = *0x60080000
+set $pc = *0x60080004 - 1
+\ No newline at end of file
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt
new file mode 100644
index 0000000..3babba1
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host/softconsole_sram_init.txt
@@ -0,0 +1,42 @@
+
+# GDB initialization sequence provided from SoftConsole IDE with slight modification
+# for eCos
+
+# [1] Targeting SmartFusion embedded SRAM (esram) @ 0x20000000.
+#     Loads and debugs at 0x20000000 (i.e. ld LMA=VMA=0x20000000).
+
+# Make sure 16-bit Thumb mode breakpoint requests are always used.
+set arm fallback-mode thumb
+
+# PATH to the arm-none-eabi-sprite utility and eCos repository must be
+# updated according to a particular setup
+target remote | "C:/Program Files (x86)/Microsemi/SoftConsole v3.3/Sourcery-G++/bin/arm-none-eabi-sprite" flashpro:?cpu=Cortex-M3 "C:/wrk/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/host"
+
+# Don't restrict memory access to just regions defined in linker script
+set mem inaccessible-by-default off
+
+# Disable the watchdog
+set *0x40006010 = 0x4C6E55FA
+
+# Configure external memory controller to access external RAM.
+
+# Program EMC_CONFIG_0_REG
+set *0xE0042040 = 0x00207FFD
+# Program EMC_MUX_CONFIG_REG
+set *0xE004203C = 0x00000001
+# Program SOFT_RESET_REG
+set *0xE0042030 = *0xE0042030 & 0xFFFFFFF7
+
+# Set temporary breakpoint on main (must be s/w BP - Cortex-M3 h/w BPs only below 0x20000000)
+thb cyg_usert_start
+
+# Specify user application vector table
+set *0xE000ED08 = 0x20000400
+
+# Load the program
+load
+
+# Ensure chip boot code runs before transferring control to user application
+# Initialize SP & PC from chip boot vector table
+set $sp = *0x60080000
+set $pc = *0x60080004 - 1
+\ No newline at end of file
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.h b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.h
new file mode 100644
index 0000000..86d3872
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.h
@@ -0,0 +1,25 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+// Only to get Redboot to compile..
+#define CYGMEM_REGION_ram (CYGMEM_REGION_sram)
+#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR)
+
+#define CYGMEM_REGION_flash (0x60000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_SIZE+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi
new file mode 100644
index 0000000..b238a3d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x60000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x60000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000400, FOLLOWING (.got))
+    SECTION_data (sram, ALIGN (0x8), FOLLOWING (.sram))
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*64;
+
+
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h
new file mode 100644
index 0000000..86d3872
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.h
@@ -0,0 +1,25 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+// Only to get Redboot to compile..
+#define CYGMEM_REGION_ram (CYGMEM_REGION_sram)
+#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR)
+
+#define CYGMEM_REGION_flash (0x60000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_SIZE+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi
new file mode 100644
index 0000000..d02ce72
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_rom_sc.ldi
@@ -0,0 +1,39 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+#define PLF_FOLLOWING(_section_) FOLLOWING_ALIGNED(_section_, 8)
+
+MEMORY
+{
+    sram    : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash   : ORIGIN = 0x60000000, LENGTH = 0x00040000
+    /* flash mirrored to 0x00000000 */
+    flashm  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flashm, 0x00000000, AT (0x60000000))
+    SECTION_text (flashm, ALIGN (0x8), PLF_FOLLOWING (.rom_vectors))
+    SECTION_fini (flashm, ALIGN (0x8), PLF_FOLLOWING (.text))
+    SECTION_rodata (flashm, ALIGN (0x8), PLF_FOLLOWING (.fini))
+    SECTION_rodata1 (flashm, ALIGN (0x8), PLF_FOLLOWING (.rodata))
+    SECTION_fixup (flashm, ALIGN (0x8), PLF_FOLLOWING (.rodata1))
+    SECTION_gcc_except_table (flashm, ALIGN (0x8), PLF_FOLLOWING (.fixup))
+    SECTION_eh_frame (flashm, ALIGN (0x8), PLF_FOLLOWING (.gcc_except_table))
+    SECTION_got (flashm, ALIGN (0x8), PLF_FOLLOWING (.eh_frame))
+    SECTION_sram (sram, 0x20000400, PLF_FOLLOWING (.got))
+    SECTION_data (sram, ALIGN (0x8), PLF_FOLLOWING (.sram))
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*64;
+
+
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.h b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.h
new file mode 100644
index 0000000..d35bc20
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.h
@@ -0,0 +1,25 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGMEM_REGION_sram)
+#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR)
+
+#define CYGMEM_REGION_flash (0x60000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi
new file mode 100644
index 0000000..299c603
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/pkgconf/mlt_cortexm_a2f200_eval_sram.ldi
@@ -0,0 +1,34 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x60000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram, 0x20000400, LMA_EQ_VMA)
+    SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20010000;
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_arch.h b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_arch.h
new file mode 100644
index 0000000..6b4c822
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Purpose:     Actel Smartfusion A2F200 EVAL board specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_a2f200_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_intr.h b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_intr.h
new file mode 100644
index 0000000..24f09db
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_intr.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Purpose:     Actel Smartfusion A2F200 EVAL board specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_a2f200_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_io.h b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_io.h
new file mode 100644
index 0000000..e0c5272
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/include/plf_io.h
@@ -0,0 +1,74 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Purpose:     Actel Smartfusion A2F200 EVAL board specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_a2f200_eval.h>
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/a2f200_eval_misc.c b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/a2f200_eval_misc.c
new file mode 100644
index 0000000..a7df400
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/a2f200_eval_misc.c
@@ -0,0 +1,160 @@
+/*==========================================================================
+//
+//      a2f200_eval_misc.c
+//
+//      Cortex-M3 A2F200 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+#include <pkgconf/hal_cortexm_a2f200_eval.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+#define TEST_IO 0
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables. 
+
+
+__externC void
+hal_system_init( void )
+{
+}
+
+cyg_uint32 led[7] = {
+    CYGHWR_HAL_A2FXXX_GPIO( 24,  OUT, NONE, DISABLE ),
+    CYGHWR_HAL_A2FXXX_GPIO( 25,  OUT, NONE, DISABLE ),
+    CYGHWR_HAL_A2FXXX_GPIO( 26,  OUT, NONE, DISABLE ),
+    CYGHWR_HAL_A2FXXX_GPIO( 27,  OUT, NONE, DISABLE ),
+};
+
+
+//==========================================================================
+
+__externC void
+hal_platform_init( void )
+{
+#if TEST_IO
+   cyg_uint8 i;
+#endif
+
+#if TEST_IO
+   for(i = 0; i < 4; i++)
+   {
+      CYGHWR_HAL_A2FXXX_GPIO_SET( led[i] );
+      CYGHWR_HAL_A2FXXX_GPIO_OUT( led[i], 1);
+   }
+#endif
+
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct
+{
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+#ifdef CYGMEM_REGION_sram              // On-chip SRAM
+    {
+    CYGMEM_REGION_sram, CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_flash             // On-chip flash
+    {
+    CYGMEM_REGION_flash,
+            CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1},
+#endif
+    { 0xE0000000, 0x00000000-1 },      // Cortex-M peripherals
+    { 0x40000000, 0x60000000-1 },      // Smartfusion peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ )
+    {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+
+//==========================================================================
+// EOF a2f200_eval_misc.c
diff --git a/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c
new file mode 100644
index 0000000..3c9d515
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c
@@ -0,0 +1,179 @@
+//==========================================================================
+//
+//      platform_i2c.c
+//
+//      Optional I2C support for Cortex-M3 Actel Smartfusion
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-04-08
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+//=============================================================================
+//                               INCLUDES
+//=============================================================================
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/hal/hal_endian.h>
+#include <cyg/hal/hal_intr.h>
+
+#ifdef CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+
+#include <cyg/io/i2c.h>
+#include <cyg/io/i2c_a2fxxx.h>
+
+//=============================================================================
+// Setup I2C bus 0
+//
+static void
+a2fxxx_i2c0_init( struct cyg_i2c_bus *bus )
+{
+    cyg_uint32 scl_io = CYGHWR_HAL_A2FXXX_I2C0_SCL;
+    cyg_uint32 sda_io = CYGHWR_HAL_A2FXXX_I2C0_SDA;
+
+    //
+    // We only need to setup the pins here and
+    // leave the I2C driver to take care of the rest.
+    //
+    CYGHWR_HAL_A2FXXX_GPIO_SET( scl_io );
+    CYGHWR_HAL_A2FXXX_GPIO_SET( sda_io );
+
+    a2fxxx_i2c_init( bus );
+}
+
+
+//-----------------------------------------------------------------------------
+// I2C bus 0
+//
+CYG_A2FXXX_I2C_BUS(hal_a2fxxx_i2c0_bus,
+                 &a2fxxx_i2c0_init,
+                 CYGHWR_HAL_A2FXXX_I2C0,       // Base address
+                 CYGHWR_HAL_A2FXXX_I2C0_BB,    // Bit-band base address
+                 CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0,
+                 CYGNUM_HAL_INTERRUPT_I2C0_0,
+                 CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C0_ISR_PRIORITY);
+
+
+//-----------------------------------------------------------------------------
+// OLED
+//
+CYG_I2C_DEVICE(i2c_a2fxxx_oled,
+               &hal_a2fxxx_i2c0_bus,
+               0x3c,
+               0,
+               CYG_I2C_DEFAULT_DELAY);
+
+
+#define DELAY 1
+
+// Wrapper to OLED driver
+
+externC cyg_uint32
+a2fxxx_oled_write_first( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    cyg_i2c_transaction_begin( &i2c_a2fxxx_oled );
+
+    result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled,
+                                     true, ( cyg_uint8 * )&byte, 1, false );
+
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    return result;
+}
+
+externC cyg_uint32
+a2fxxx_oled_write_byte( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled,
+                                     false, ( cyg_uint8 * )&byte, 1, false );
+
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    return result;
+}
+
+
+externC cyg_uint32
+a2fxxx_oled_write_array( const cyg_uint8 *array, cyg_uint32 count )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled,
+                                     false, array, count, false );
+
+    return result;
+}
+
+
+externC cyg_uint32
+a2fxxx_oled_write_final( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_a2fxxx_oled,
+                                     false, ( cyg_uint8 * )&byte, 1, true );
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    cyg_i2c_transaction_end( &i2c_a2fxxx_oled );
+
+    return result;
+}
+
+#endif // #ifdef CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+
+//-----------------------------------------------------------------------------
+// EOF platform_i2c.c
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/ChangeLog b/ecos/packages/hal/cortexm/a2fxxx/var/current/ChangeLog
new file mode 100644
index 0000000..009d056
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/ChangeLog
@@ -0,0 +1,46 @@
+2012-01-04  Christophe Coutand  <ecos@hotmail.co.uk>
+	* src/hal_dma.c:
+	Fix compiler warning, unused variable in a2fxxx_dma_isr().
+
+2011-06-26  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* cdl/hal_cortexm_a2fxxx.cdl:
+	* cdl/hal_cortexm_a2fxxx_irq.cdl:
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/var_arch.h:
+	* include/variant.inc:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* src/hal_diag.c:
+	* src/hal_dma.c:
+	* src/a2fxxx_misc.c:
+	* tests/timers.c:
+	New package -- Actel SmartFusion Cortex-M3 variant HAL.
+	[Bugzilla 1001291]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
+
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx.cdl b/ecos/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx.cdl
new file mode 100644
index 0000000..4e11525
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx.cdl
@@ -0,0 +1,732 @@
+##==========================================================================
+##
+##      hal_cortexm_a2f.cdl
+##
+##      Cortex-M A2F variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Contributors: 
+## Date:         2011-02-03
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_A2FXXX {
+    display       "Actel Smartfusion A2Fxxx Variant (Cortex-M3)"
+    parent        CYGPKG_HAL_CORTEXM
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_a2fxxx.h
+    description   "
+        This package provides generic support for the Actel Smarfusiom Cortex-M3 
+        based microcontroller family. It is also necessary to select a platform 
+        HAL package."
+
+    compile       hal_diag.c a2fxxx_misc.c hal_dma.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M3" }
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+
+    cdl_option CYGHWR_HAL_CORTEXM_A2FXXX {
+        display          "Actel Smartfusion A2F variant in use"
+        flavor           data
+        default_value    { "A2F200" }
+        legal_values     { "A2F060" "A2F200" "A2F500" }
+        description      "The Smartfusion has several variants, the main differences
+                          being in the size of on-chip FLASH and SRAM and numbers of
+                          some analog peripherals. This option allows the platform HAL 
+                          to select the specific microcontroller fitted."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display         "CPU priority levels"
+        flavor          data
+        calculated      5
+        description     "This option defines the number of bits used to
+                         encode the exception priority levels that this
+                         variant of the Cortex-M CPU implements."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK {
+        display       "Clocking"
+        description   "Select this option to configure the internal 
+                 clock network of the device. Due to large amount of possible combination of 
+                 clock configuration, it is recommended to use the Actel MSS configuration tool
+                 and let the system boot handle the clock settings. Some of the requirement for
+                 setting the clock network of the device are : The On-chip Oscillator 
+                 clock frequency is fixed to 100 MHz and cannot be changed. The Main Crystal
+                 Oscillator clock frequency must be between 1.5 MHz and 20 MHz when the PLL is
+                 used or between 32 KHz and 20 MHz when the PLL is bypassed. The Main Crystal 
+                 Oscillator (RC network configuration) clock frequency must be between 1.5MHz 
+                 and 4 MHz when the PLL is used or between 32 KHz and 4 MHz when the PLL is 
+                 bypassed. For all other sources, the source clock frequency must be between 
+                 1.5 MHz and 176MHz when the PLL is used or between 32 KHz and 250 MHz when the 
+                 PLL is bypassed."
+        flavor         bool
+        default_value  0
+
+        cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKIN {
+            display       "Input clock selection"
+            flavor         none
+            description   "Configure the input clocks of the device."
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKA {
+                display       "Clock A configuration"
+                flavor         bool
+                default_value { CYGHWR_HAL_CORTEXM_A2FXXX_PLL }
+                description   "Configure the clock A input of the device."
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC {
+                    display        "Clock A source"
+                    flavor          data
+                    legal_values    { "AUIN" "AUIP" "ADIP" "GLAINT" "RCOSC" "MOSC" }
+                    default_value   { "RCOSC" }
+                    description   "
+                        Select the clock A source. Valid choices are the main oscillator,
+                        the RC oscillator, the FPGA fabric or the dedicated single-ended or 
+                        differential IOs."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ {
+                    display         "Clock A frequency in Hz"
+                    flavor           data
+                    legal_values     { 1500000 to 176000000 }
+                    default_value    { CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC == "RCOSC" ? 100000000 : 20000000 }
+                    description   "
+                        Select the clock A source frequency in Hz. Additional restrictions 
+                        of the frequency range apply giving the clock source. It is left to 
+                        the user to take care of not exceeding the limits provided by the 
+                        device user manual."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKB {
+                display       "Clock B configuration"
+                flavor         bool
+                description   "Configure the clock B input of the device."
+                default_value  0
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC {
+                    display       "Clock B source"
+                    flavor         data
+                    legal_values   { "BUIN" "BUIP" "BDIP" "GLBINT" "RCOSC" "MOSC" }
+                    default_value  { "MOSC" }
+                    description   "
+                        Select the clock B source. Valid choices are the main oscillator,
+                        the RC oscillator, the FPGA fabric or the dedicated single-ended or 
+                        differential IOs."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_FREQ {
+                    display         "Clock B frequency in Hz"
+                    flavor           data
+                    legal_values     { 32000 to 350000000 }
+                    default_value    { CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC == "RCOSC" ? 100000000 : 20000000 }
+                    description   "
+                        Select the clock B source frequency in Hz. Additional restrictions 
+                        of the frequency range apply giving the clock source. It is left to 
+                        the user to take care of not exceeding the limits provided by the 
+                        device user manual."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKC {
+                display       "Clock C configuration"
+                flavor         bool
+                description   "Configure the clock C input of the device."
+                default_value  0
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC {
+                    display       "Clock C source"
+                    flavor        data
+                    legal_values  { "CUIN" "CUIP" "CDIP" "GLCINT" "RCOSC" "32KOSC"}
+                    default_value { "RCOSC" }
+                    description   "
+                        Select the clock C source. Valid choices are the main oscillator,
+                        the RC oscillator, the FPGA fabric or the dedicated single-ended or 
+                        differential IOs."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_FREQ {
+                    display         "Clock C frequency in Hz"
+                    flavor          data
+                    legal_values    { 32000 to 350000000 }
+                    default_value   { CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC == "RCOSC" ? 100000000 : 20000000 }
+                    description   "
+                        Select the clock B source frequency in Hz. Additional restrictions 
+                        of the frequency range apply giving the clock source. It is left to 
+                        the user to take care of not exceeding the limits provided by the 
+                        device user manual."
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PLL {
+            display       "PLL configuration"
+            flavor         bool
+            requires       CYGHWR_HAL_CORTEXM_A2FXXX_CLKA
+            description   "Configure the device PLL."
+            default_value  1
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT {
+                display       "PLL Multiplier"
+                flavor         data
+                legal_values  { 1 to 128 }
+                default_value { 1 }
+                description   "
+                    Select the PLL multiplier coefficient (m)."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV {
+                display       "PLL Divider"
+                flavor         data
+                legal_values  { 1 to 128 }
+                default_value { 1 }
+                description   "
+                    Select the PLL divider coefficient (n)."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ {
+                display       "PLL output frequency"
+                flavor        data
+                calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_PLL ? ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ * CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT ) / CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV : 0 }
+                legal_values  { 22000000 to 350000000 }
+                description   "
+                    Computed PLL output frequency."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FB_DELAY {
+                display       "PLL Feedback delay"
+                flavor        data
+                legal_values  { 0 to 15 }
+                default_value { 0 }
+                description   "
+                    Select the PLL Feedback loop delay. Field FBDLY from user manual. 
+                    Value from 535 to 5560ns."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PLL_XDELAY {
+                display       "PLL Additional delay"
+                flavor        bool
+                default_value 0
+                description   "
+                    Add 2ns additional delay on PLL feedback loop."
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKOUT {
+            display       "Global clock output configuration"
+            flavor         none
+            description   "Configure the Global clocks of the device."
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA {
+                display       "Global clock A configuration"
+                flavor         bool
+                default_value { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" }
+                description   "Configure the Global clock A of the device."
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC {
+                    display         "Global clock A source"
+                    flavor           data
+                    legal_values    { "CLKA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" }
+                    default_value   { "PLL_VCO0" }
+                    requires        { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "CLKA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL }
+                    description   "
+                        Select the Global clock A source. Valid choices are the PLL output (with different phases)
+                        or the clock A input."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV {
+                    display        "Global clock A divider"
+                    flavor          data
+                    legal_values   { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 
+                                     10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 
+                                     20 21 22 23 24 25 26 27 28 29 30 31 32 }
+                    default_value  { 1 }
+                    description   "
+                        Select the Global clock A divider value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 {
+                    display        "Global clock A divider * 10"
+                    flavor          data
+                    calculated     { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV * 10 }
+                    description   "
+                        Computed Global clock A divider value multiplied by 10."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DELAY {
+                    display        "Global clock A delay line"
+                    flavor          data
+                    legal_values   { 0 to 15 }
+                    default_value  { 0 }
+                    description   "
+                        Select the Global clock A delay value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ {
+                    display        "Global clock A Frequency"
+                    flavor          data
+                    legal_values   { 1 to 100000000 }
+                    calculated     { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "PLL_VCO0_DL" ) ? ( ( CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC == "CLKA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10 ) : 0 }
+                    description   "
+                        Computed Global clock A frequency."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB {
+                display      "Global clock B configuration"
+                flavor        bool
+                description  "Configure the Global clock B of the device."
+                default_value { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC {
+                    display       "Global clock B source"
+                    flavor         data
+                    legal_values  { "CLKB" "CLKGA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" }
+                    default_value { "PLL_VCO0" }
+                    requires      { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKB" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKB : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL }
+                    description   "
+                        Select the Global clock B source. Valid choices are the PLL output (with different phases),
+                        the clock B input or the global clock A output."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV {
+                    display       "Global clock B divider"
+                    flavor         data
+                    legal_values   { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 
+                                     10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 
+                                     20 21 22 23 24 25 26 27 28 29 30 31 32 }
+                    default_value { 1 }
+                    description   "
+                        Select the Global clock B divider value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 {
+                    display        "Global clock B divider * 10"
+                    flavor          data
+                    calculated     { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV * 10 }
+                    description   "
+                        Computed Global clock B divider value multiplied by 10."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DELAY {
+                    display       "Global clock B delay line"
+                    flavor         data
+                    legal_values  { 0 to 15 }
+                    default_value { 0 }
+                    description   "
+                        Select the Global clock B delay value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ {
+                    display        "Global clock B Frequency"
+                    flavor          data
+                    calculated     { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "PLL_VCO0_DL" ) ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ*10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKB" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC == "CLKGA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10 ) : 0 }
+                    description   "
+                        Computed Global clock B frequency."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC {
+                display       "Global clock C configuration"
+                flavor        bool
+                description   "Configure the Global clock C of the device."
+                default_value { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGC" }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC {
+                    display       "Global clock C source"
+                    flavor         data
+                    legal_values  { "CLKC" "CLKGA" "PLL_VCO0" "PLL_VCO90" "PLL_VCO180" "PLL_VCO270" "PLL_VCO0_DL" }
+                    default_value { "PLL_VCO0" }
+                    requires      { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKC" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKC : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : CYGHWR_HAL_CORTEXM_A2FXXX_PLL }
+                    description   "
+                        Select the Global clock C source. Valid choices are the PLL output (with different phases),
+                        the clock C input or the global clock A output."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV {
+                    display       "Global clock C divider"
+                    flavor         data
+                    legal_values   { 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 
+                                     10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 16 17 18 19 
+                                     20 21 22 23 24 25 26 27 28 29 30 31 32 }
+                    default_value { 1 }
+                    description   "
+                        Select the Global clock C divider value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 {
+                    display        "Global clock C divider * 10"
+                    flavor          data
+                    calculated     { CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV * 10 }
+                    description    "
+                        Computed Global clock C divider value multiplied by 10."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DELAY {
+                    display       "Global clock C delay line"
+                    flavor         data
+                    legal_values  { 0 to 15 }
+                    default_value { 0 }
+                    description   "
+                        Select the Global clock C delay value."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_FREQ {
+                    display       "Global clock C Frequency"
+                    flavor         data
+                    calculated     { ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO0" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO90" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO180" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO270" || CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "PLL_VCO0_DL" ) ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ*10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKC" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC == "CLKGA" ? ( (CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ * 10) / CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10 ) : 0 }
+                    description   "
+                        Computed Global clock C frequency."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MSS_FPGA {
+                display      "MSS / FPGA Clock configuration"
+                flavor        none
+                description  "Configure the MSS and Fabric master clock."
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT {
+                    display       "NGMUX output clock"
+                    flavor         data
+                    legal_values  { "CLKGA" "CLKGC" }
+                    default_value { "CLKGA" }
+                    requires      { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA : ( CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC && CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC != "CLKGA" ) }
+                    description   "
+                        Select the NGMUX output clock. Valid choices are the Global Clock A or C."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ {
+                    display       "NGMUX output clock frequency"
+                    flavor        data
+                    legal_values  { 1 to 100000000 }
+                    calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT == "CLKGA" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_FREQ : CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_FREQ }
+                    description   "
+                        Computed NGMUX output clock frequency."
+                }
+
+                cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK {
+                    display       "Fabric clock configuration"
+                    flavor         bool
+                    default_value  0
+                    description   "Set the Fabric master clock. The Fabric frequency ration
+                        specifies which clock source to be used. For a ration of 1, the fabric 
+                        and MSS clock source are the same. For a ration of 2 of 4, the fabric 
+                        clock source is CLKGB and the ration between CLKGB and the MSS clock must 
+                        be configured by the user to be equal to 2 or 4."
+
+                    cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO {
+                        display       "Fabric to MSS clock ratio"
+                        flavor        data
+                        legal_values  { 1 2 4 }
+                        requires      { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB : 1 }
+                        requires      { CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ == CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO : 1 }
+                        default_value { 1 }
+                        description   "
+                            Select the Fabric to MSS clock ratio."
+                    }
+
+                    cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_FREQ {
+                        display       "Fabric clock Frequency"
+                        flavor         data
+                        calculated    { ( CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO != 1 ) ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_FREQ : ( CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK && CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_RATIO == 1 ) ?  CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ  : 0 }
+                        description   "
+                            Computed Fabric clock frequency."
+                    }
+                }
+
+                cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MSS_CLK {
+                    display       "MSS clock configuration"
+                    flavor         none
+                    description   "Configure the MSS master clock."
+
+                    cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_MSS_CLK_DELAY {
+                        display       "MSS clock delay"
+                        flavor         data
+                        legal_values  { 0 to 15 }
+                        default_value { 0 }
+                        description   "
+                            Select the MSS clock delay. Field FBDLY. Value from 535 to 5560ns."
+                    }
+
+                    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK {
+                        display       "ACE clock configuration"
+                        flavor         bool
+                        default_value  0
+                        description   "Configure the ACE master clock."
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV {
+                           display       "ACE clock divider"
+                            flavor        data
+                            legal_values  { 1 2 4 }
+                            default_value { 1 }
+                            description   "
+                                Select the ACE clock divider value."
+                        }
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_FREQ {
+                            display       "ACE clock Frequency"
+                            flavor         data
+                            calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV : 0 }
+                            description   "
+                                Computed ACE clock frequency."
+                        }
+                    }
+
+                    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_CLK {
+                        display      "PCLK0 clock configuration"
+                        flavor        none
+                        description  "Configure the PCLK0 clock."
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV {
+                            display       "PCLK0 clock divider"
+                            flavor        data
+                            legal_values  { 1 2 4 }
+                            default_value { 1 }
+                            description   "
+                                Select PCLK0 clock divider value."
+                        }
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_FREQ {
+                            display       "PCLK0 clock Frequency"
+                            flavor         data
+                            calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV : 0 }
+                            description   "
+                                Computed PCLK0 clock frequency."
+                        }
+                    }
+
+                    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_CLK {
+                        display       "PCLK1 clock configuration"
+                        flavor         none
+                        description   "Configure the PCLK1 clock."
+                        
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV {
+                            display       "PCLK1 clock divider"
+                            flavor         data
+                            legal_values  { 1 2 4 }
+                            default_value { 1 }
+                            description   "
+                                Select PCLK1 clock divider value."
+                        }
+
+                        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_FREQ {
+                            display       "PCLK1 clock Frequency"
+                            flavor         data
+                            calculated    { CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ ? CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ / CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV : 0 }
+                            description   "
+                                Computed PCLK1 clock frequency."
+                        }
+                    }
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK {
+                display       "Ethernet MAC clock configuration"
+                flavor         bool
+                default_value  0
+
+                cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC {
+                    display       "Ethernet MAC clock source"
+                    flavor         data
+                    legal_values  { "CLKGC" "EXTERNAL" }
+                    default_value { "CLKGC" }
+                    requires      { CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC == "CLKGC" ? CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC  : 1 }
+                    description   "
+                        Select the Ethernet MAC clock source."
+                }
+            }
+        }
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_A2FXXX_DMA {
+        display       "DMA"
+        flavor        none
+        description   "
+            DMA controller configuration."
+
+        cdl_option CYGDBG_HAL_CORTEXM_A2FXXX_DMA_TRACE {
+            display       "Display status messages during DMA operations"
+            flavor        bool
+            default_value 0
+            description   "
+               Selecting this option will cause the DMA driver to print status
+               messages as various DMA operations are undertaken."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_CORTEXM_A2FXXX_CLOCK_CHATTER {
+        display        "Trace clock network configuration."
+        default_value   1
+        flavor          bool
+        description     "
+            Enable debug tracing of the clock configuration."
+    }
+
+    cdl_option CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION {
+        display        "Override IDLE thread action"
+        default_value   1
+        flavor          bool
+        description     "
+            Override IDLE thread action defined by the architectural HAL.
+            The option must be active when running the application from a
+            debugger. The 'WFI' IDLE instruction defined in the architectural
+            HAL leads to software crash when application runs from a debugger."
+    }
+
+    cdl_component  CYGPKG_HAL_CORTEXM_A2FXXX_IO {
+        display         "IO configuration"
+        flavor          bool
+        default_value   0
+        description   "
+                Overwrite the default IO configuration
+        "
+
+        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK {
+            display       "IO west bank buffer type"
+            legal_values  { "LVCMOS_3V3" "LVCMOS_2V5" "LVCMOS_1V8" "LVCMOS_1V5" }
+            default_value { "LVCMOS_3V3" }
+            flavor        data
+            description   "
+                Select the device west bank IO buffer type to be used.
+            "
+        }
+        cdl_option CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK {
+            display       "IO east bank buffer type"
+            legal_values  { "LVCMOS_3V3" "LVCMOS_2V5" "LVCMOS_1V8" "LVCMOS_1V5" }
+            default_value { "LVCMOS_3V3" }
+            flavor        data
+            description   "
+                Select the device west bank IO buffer type to be used.
+            "
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+        display    "Variant IRQ priority defaults"
+        no_define
+        flavor     none
+        parent     CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+        description "
+            Interrupt priorities defined by the variant HAL"
+        script     hal_cortexm_a2fxxx_irq.cdl
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "The period defined here is something of a fake, it is expressed
+                           in terms of a notional 1MHz clock. The value actually installed
+                           in the hardware is calculated from the current settings of the
+                           clock generation hardware."
+        }
+    }
+
+    cdl_interface CYGINT_HAL_A2FXXX_UART0 {
+        display     "Platform has UART0 serial port"
+        description "The platform has a socket on UART0."
+    }
+
+    cdl_interface CYGINT_HAL_A2FXXX_UART1 {
+        display     "Platform has UART1 serial port"
+        description "The platform has a socket on UART1."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_A2FXXX_OPTIONS {
+        display "Build options"
+        flavor  none
+        description   "
+        Package specific build options including control over
+        compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the A2F variant HAL package. These flags are used
+                in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the A2F variant HAL package. These flags are removed from
+                the set of global flags if present."
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_A2FXXX_TESTS {
+        display "A2F tests"
+        active_if      CYGPKG_KERNEL
+        flavor  data
+        no_define
+        calculated { "tests/timers" }
+        description   "
+            This option specifies the set of tests for the A2F HAL."
+    }
+
+}
+\ No newline at end of file
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx_irq.cdl b/ecos/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx_irq.cdl
new file mode 100644
index 0000000..0e17a54
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/cdl/hal_cortexm_a2fxxx_irq.cdl
@@ -0,0 +1,150 @@
+##==========================================================================
+##
+##      hal_cortexm_a2fxxx_irq.cdl
+##
+##      Cortex-M A2F configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Date:         2012-02-20
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor         data
+        calculated     0xF0
+        description   "Set clock ISR priority to lowest priority."
+    }
+
+
+    cdl_option CYGNUM_HAL_CORTEXM_A2FXXX_DMA_ISR_PRIORITY {
+        display       "DMA peripheral interrupt ISR priority"
+        flavor         data
+        default_value  0x70
+             legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                0xF0 }
+        description   "
+          Set DMA controller ISR priority."
+     }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_I2C {
+        display "I2C IRQ priorities"
+        flavor none
+        no_define
+
+        cdl_option CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C0_ISR_PRIORITY {
+            display   "I2C bus 0 interrupt priority"
+            flavor     data
+            active_if  CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+            legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                0xF0 }
+            default_value 0x78
+        }
+
+        cdl_option CYGNUM_DEVS_I2C_CORTEXM_A2FXXX_I2C1_ISR_PRIORITY {
+            display   "I2C bus 1 interrupt priority"
+            flavor     data
+            active_if  CYGPKG_DEVS_I2C_CORTEXM_A2FXXX
+            legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                0xF0 }
+            default_value 0x78
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_ETH {
+        display   "Ethernet IRQ priorities"
+        flavor     none
+        no_define
+
+        cdl_option CYGNUM_DEVS_ETH_CORTEXM_A2FXXX_ISR_SP {
+            display       "Ethernet interrupt ISR priority"
+            active_if      CYGPKG_DEVS_ETH_CORTEXM_A2FXXX
+            flavor         data
+            no_define
+            default_value  0x78
+                legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                    0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                    0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                    0xF0 }
+            description   "
+                  Set the Ethernet controller ISR priority."
+       }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_SERIAL {
+        display   "Serial controller IRQ priorities"
+        flavor     none
+        no_define
+
+        cdl_option CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL0_ISR_SP {
+            display       "Serial port 0 driver ISR priority"
+            active_if      CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL0
+            flavor         data
+            no_define
+            default_value  0x78
+                legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                    0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                    0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                    0xF0 }
+            description   "
+                  Set the serial 0 controller ISR priority."
+       }
+
+        cdl_option CYGNUM_DEVS_SERIAL_CORTEXM_A2FXXX_SERIAL1_ISR_SP {
+            display       "Serial port 1 driver ISR priority"
+            active_if      CYGPKG_IO_SERIAL_CORTEXM_A2FXXX_SERIAL1
+            flavor         data
+            no_define
+            default_value  0x80
+                legal_values { 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48
+                    0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98
+                    0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8
+                    0xF0 }
+            description   "
+                  Set the serial 1 controller ISR priority."
+       }
+    }
+\ No newline at end of file
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/hal_cache.h
new file mode 100644
index 0000000..b12d50d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/hal_cache.h
@@ -0,0 +1,116 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: 
+// Date:         2011-00-03
+// Purpose:      Cache control API
+// Description:  The macros defined here provide the HAL APIs for handling
+//               cache control operations.
+//
+//               For the Atcel SmartFusion, these are empty macros as there
+//               is no cache.
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/hal_diag.h
new file mode 100644
index 0000000..13fdbdc
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/hal_diag.h
@@ -0,0 +1,91 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-02-03
+// Purpose:     HAL diagnostics
+// Description:
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#define HAL_DIAG_INIT()          hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void hal_a2fxxx_diag_init(void);
+__externC void hal_a2fxxx_diag_putc(char);
+__externC cyg_uint8 hal_a2fxxx_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_a2fxxx_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_a2fxxx_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_a2fxxx_diag_getc()
+# endif
+
+#endif
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/plf_stub.h
new file mode 100644
index 0000000..4d1a443
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/plf_stub.h
@@ -0,0 +1,89 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008
+// Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:jskov, gthomas, jlarmour
+// Date:        2008-07-30
+// Purpose:     Platform HAL stub support for STM32 variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/cortexm_stub.h>           // architecture stub support
+
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_arch.h
new file mode 100644
index 0000000..0302021
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_arch.h
@@ -0,0 +1,66 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      Actel SmartFusion  Cortex-M3 variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Purpose:      Actel SmartFusion Cortex-M3 variant architecture overrides
+// Description:
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION
+externC void hal_idle_thread_action( cyg_uint32 );
+
+# define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
+#endif
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_intr.h
new file mode 100644
index 0000000..dedd63d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_intr.h
@@ -0,0 +1,232 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for Smartfusion Cortex-M3 variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for Actel Smartfusion Cortex-M3
+//               are defined here.
+//
+// Usage:        #include <cyg/hal/var_intr.h>
+//               However applications should include using <cyg/hal/hal_intr.h>
+//               instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_WD               (0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_VR_PSM_5V        (1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_VR_PSM_3V        (2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RTC0_0           (3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RTC0_1           (4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MAC0             (5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_IAP              (6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ENVM0            (7+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ENVM1            (8+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA              (9+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART0            (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART1            (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SPI0             (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SPI1             (13+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0_0           (14+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0_1           (15+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0_2           (16+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1_0           (17+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1_1           (18+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1_2           (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM0_1           (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM0_2           (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MSS_CCC_0        (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MSS_CCC_1        (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AHB              (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED0        (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED1        (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED2        (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED3        (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED4        (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RESERVED5        (30+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_FAB              (31+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO0            (32+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO1            (33+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO2            (34+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO3            (35+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO4            (36+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO5            (37+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO6            (38+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO7            (39+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO8            (40+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO9            (41+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO10           (42+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO11           (43+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO12           (44+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO13           (45+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO14           (46+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO15           (47+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO16           (48+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO17           (49+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO18           (50+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO19           (51+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO20           (52+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO21           (53+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO22           (54+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO23           (55+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO24           (56+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO25           (57+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO26           (58+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO27           (59+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO28           (60+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO29           (61+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO30           (62+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIO31           (63+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG0    (64+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG1    (65+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG2    (66+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG3    (67+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG0    (68+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG1    (69+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG2    (70+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG3    (71+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG0    (72+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG1    (73+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG2    (74+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG3    (75+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_DV      (76+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_DV      (77+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_DV      (78+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_CD      (79+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_CD      (80+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_CD      (81+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_CS      (81+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_CS      (83+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_CS      (84+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP0_FALL   (85+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP1_FALL   (86+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP2_FALL   (87+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP3_FALL   (88+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP4_FALL   (89+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP5_FALL   (90+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP6_FALL   (91+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP7_FALL   (92+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP8_FALL   (93+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP9_FALL   (94+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP10_FALL  (95+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP11_FALL  (96+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP0_RISE   (97+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP1_RISE   (98+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP2_RISE   (99+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP3_RISE   (100+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP4_RISE   (101+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP5_RISE   (102+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP6_RISE   (103+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP7_RISE   (104+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP8_RISE   (105+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP9_RISE   (106+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP10_RISE  (107+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_COMP11_RISE  (108+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FF      (109+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FAF     (110+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FE      (111+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FF      (112+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FAF     (113+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FE      (114+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FF      (115+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FAF     (116+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FE      (117+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG0    (118+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG1    (119+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG2    (120+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG3    (121+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG4    (122+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG5    (123+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG6    (124+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG7    (125+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG8    (126+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG9    (127+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG10   (128+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG11   (129+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG12   (130+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG13   (131+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG14   (132+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG15   (133+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG16   (134+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG17   (135+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG18   (136+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG19   (137+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG20   (138+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG21   (139+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG22   (140+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG23   (141+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG24   (142+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG25   (143+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG26   (144+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG27   (145+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG28   (146+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG29   (147+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG30   (148+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG31   (149+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#ifndef CYGNUM_HAL_INTERRUPT_NVIC_MAX
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX       (CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG31)
+#endif
+
+#define CYGNUM_HAL_ISR_MIN     0
+#ifndef CYGNUM_HAL_ISR_MAX
+#define CYGNUM_HAL_ISR_MAX     CYGNUM_HAL_INTERRUPT_NVIC_MAX
+#endif
+#define CYGNUM_HAL_ISR_COUNT   (CYGNUM_HAL_ISR_MAX + 1)
+
+#define CYGNUM_HAL_VSR_MIN     0
+#ifndef CYGNUM_HAL_VSR_MAX
+#define CYGNUM_HAL_VSR_MAX     (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+#define CYGNUM_HAL_VSR_COUNT   (CYGNUM_HAL_VSR_MAX+1)
+
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_io.h b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_io.h
new file mode 100644
index 0000000..2e41303
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/var_io.h
@@ -0,0 +1,1196 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-02-03
+// Purpose:     Smartfusion Cortex-M3 variant specific registers
+// Description:
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Peripherals
+
+#define CYGHWR_HAL_A2FXXX_SC                               0xE0042000
+
+// Device peripherals
+#define CYGHWR_HAL_A2FXXX_UART0                            0x40000000
+#define CYGHWR_HAL_A2FXXX_SPI0                             0x40001000
+#define CYGHWR_HAL_A2FXXX_I2C0                             0x40002000
+#define CYGHWR_HAL_A2FXXX_MAC                              0x40003000
+#define CYGHWR_HAL_A2FXXX_DMA                              0x40004000
+#define CYGHWR_HAL_A2FXXX_TIMER                            0x40005000
+#define CYGHWR_HAL_A2FXXX_WD                               0x40006000
+#define CYGHWR_HAL_A2FXXX_FABRIC_IIC                       0x40007000
+#define CYGHWR_HAL_A2FXXX_UART1                            0x40010000
+#define CYGHWR_HAL_A2FXXX_SPI1                             0x40011000
+#define CYGHWR_HAL_A2FXXX_I2C1                             0x40012000
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO                         0x40013000
+#define CYGHWR_HAL_A2FXXX_RTC                              0x40014000
+#define CYGHWR_HAL_A2FXXX_EFROM                            0x40015000
+#define CYGHWR_HAL_A2FXXX_IAP                              0x40016000
+#define CYGHWR_HAL_A2FXXX_ANALOG_ENGINE                    0x40020000
+#define CYGHWR_HAL_A2FXXX_FPAG_ESRAM                       0x40040000
+#define CYGHWR_HAL_A2FXXX_FPGA                             0x40050000
+#define CYGHWR_HAL_A2FXXX_PERIPH                           0x42000000
+
+// Internal flash (Embedded Non-volatile Memory, ENVM)
+#define CYGHWR_HAL_A2FXXX_ENVM_ARRAY                       0x60000000
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES                 0x60080000
+#define CYGHWR_HAL_A2FXXX_ENVM_AUX_BLOCK_A                 0x60084000
+#define CYGHWR_HAL_A2FXXX_ENVM_AUX_BLOCK_SP                0x60088000
+#define CYGHWR_HAL_A2FXXX_ENVM                             0x60100000
+
+// External memory base address
+#define CYGHWR_HAL_A2FXXX_EMEM_TYPE0                       0x70000000
+#define CYGHWR_HAL_A2FXXX_EMEM_TYPE1                       0x74000000
+
+//=============================================================================
+// Bit-Band base address
+#define CYGHWR_HAL_A2FXXX_I2C0_BB                          ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00040000 )
+#define CYGHWR_HAL_A2FXXX_I2C1_BB                          ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00240000 )
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_BB                      ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00260000 )
+#define CYGHWR_HAL_A2FXXX_MAC_BB                           ( CYGHWR_HAL_A2FXXX_PERIPH + 0x00060000 )
+
+//=============================================================================
+// Device signature and ID registers
+
+#define CYGHWR_HAL_A2FXXX_MCU_ID                           (CYGHWR_HAL_A2FXXX_CORTEXM3 + 0xD00)
+#define CYGHWR_HAL_A2FXXX_MCU_ID_REV(__x)                  ((__x)&0xF)
+#define CYGHWR_HAL_A2FXXX_MCU_PART_NO(__x)                 (((__x)>>4)&0x0FFF)
+#define CYGHWR_HAL_A2FXXX_MCU_VAR_NO(__x)                  (((__x)>>20)&0xF)
+
+
+//=============================================================================
+// System Control
+//
+#define CYGHWR_HAL_A2FXXX_SC_ESRAM_CR                      0x000
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR                       0x004
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_SYS_CR             0x008
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_FAB_CR             0x00C
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_CR              0x010
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR              0x014
+#define CYGHWR_HAL_A2FXXX_SC_AHB_MATRIX_CR                 0x018
+#define CYGHWR_HAL_A2FXXX_SC_MSS_SR                        0x01C
+#define CYGHWR_HAL_A2FXXX_SC_CLR_MSS_SR                    0x020
+#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR                      0x024
+#define CYGHWR_HAL_A2FXXX_SC_IAP_CR                        0x028
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTIRQ_CR                0x02C
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR                0x030
+#define CYGHWR_HAL_A2FXXX_SC_DEVICE_SR                     0x034
+#define CYGHWR_HAL_A2FXXX_SC_SYSTICK_CR                    0x038
+#define CYGHWR_HAL_A2FXXX_SC_EMC_MUX_CR                    0x03C
+#define CYGHWR_HAL_A2FXXX_SC_EMC_CS0_CR                    0x040
+#define CYGHWR_HAL_A2FXXX_SC_EMC_CS1_CR                    0x044
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR                    0x048
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR                0x04C
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR                0x050
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR                0x054
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR                0x058
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR                    0x05C
+#define CYGHWR_HAL_A2FXXX_SC_VRPSM_CR                      0x064
+#define CYGHWR_HAL_A2FXXX_SC_FAB_APB_HW_DR                 0x070
+#define CYGHWR_HAL_A2FXXX_SC_LOOPBACK_CR                   0x074
+#define CYGHWR_HAL_A2FXXX_SC_MSS_IO_BANK_CR                0x078
+#define CYGHWR_HAL_A2FXXX_SC_GPIN_SOURCE_CR                0x07C
+#define CYGHWR_HAL_A2FXXX_SC_IOMUX(_x_)                    ( 0x100 + (_x_ << 0x2) )
+
+// Reset register
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_PAD            BIT_(19)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_F2M            BIT_(18)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_FPGA           BIT_(17)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_EXT            BIT_(16)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_IAP            BIT_(15)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_GPIO           BIT_(14)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ACE            BIT_(13)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C1           BIT_(12)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_I2C0           BIT_(11)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_SPI1           BIT_(10)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_SPI0           BIT_(9)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_UART1          BIT_(8)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_UART0          BIT_(7)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_TIMER          BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_PDMA           BIT_(5)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_MAC            BIT_(4)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_EMC            BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ESRAM1         BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ESRAM0         BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_ENVM           BIT_(0)
+
+#define CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(_periph)          CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR_##_periph
+
+void hal_a2fxxx_periph_reset( cyg_uint32 );
+void hal_a2fxxx_periph_release( cyg_uint32 );
+
+#define CYGHWR_HAL_A2FXXX_PERIPH_RESET           hal_a2fxxx_periph_reset
+#define CYGHWR_HAL_A2FXXX_PERIPH_RELEASE         hal_a2fxxx_periph_release
+
+#if 0
+#define CYGHWR_HAL_A2FXXX_PERIPH_START(_x)                 \
+{                                                          \
+    volatile int c = 0;                                    \
+    hal_a2fxxx_periph_reset(_x);                           \
+    while( c++ < 20 );                                     \
+    hal_a2fxxx_periph_release(_x);                         \
+}
+#endif
+
+// MSS CLK register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GLBDIV(_x)         VALUE_(12, ((_x)&0x3))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RTCIF(_x)          VALUE_( 8, ((_x)&0xf))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(_x)        VALUE_( 6, ((_x)&0x3))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(_x)       VALUE_( 4, ((_x)&0x3))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(_x)       VALUE_( 2, ((_x)&0x3))
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK0DIV(_x)   ((_x & 0x000C) >> 2)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK1DIV(_x)   ((_x & 0x0030) >> 4)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_GLBDIV(_x)     ((_x & 0x0C00) >> 12)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL         BIT_(0)
+
+// MSS CCC DIV register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVRST       BIT_(22)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF      BIT_(21)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(_x)      VALUE_(16, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVRST       BIT_(14)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF      BIT_(13)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(_x)      VALUE_( 8, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVRST       BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF      BIT_(5)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(_x)      VALUE_( 0, _x)
+
+// MSS CCC MUX register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_MAINOSCM(_x)   VALUE_(30, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_MAINOSCEN      BIT_(29)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(_x)   VALUE_(26, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(_x)   VALUE_(24, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC        BIT_(22)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(_x)      VALUE_(19, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNCSEL        BIT_(18)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXCSEL         BIT_(17)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATCSEL       BIT_(16)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB        BIT_(14)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(_x)      VALUE_(11, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNBSEL        BIT_(10)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXBSEL         BIT_(9)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATBSEL       BIT_(8)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA        BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(_x)      VALUE_( 3, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNASEL        BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXASEL         BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATASEL       BIT_(0)
+
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA             0
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC             1
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLINT           2
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GND             3
+
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKA_SEL(_x_)  \
+({                                                         \
+   cyg_uint32 _i = _x_;                                    \
+   _i;                                                     \
+})
+
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKB_SEL(_x_)  \
+({                                                         \
+   cyg_uint32 _i = _x_;                                    \
+   _i = _i << 8;                                           \
+   _i;                                                     \
+})
+
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKC_SEL(_x_)  \
+({                                                         \
+   cyg_uint32 _i = _x_;                                    \
+   _i = _i << 16;                                          \
+   _i;                                                     \
+})
+
+// MSS CCC PLL register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_PLLEN          BIT_(31)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL2_1(_x)  VALUE_(23, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL0        BIT_(22)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_XDLYSEL(_x)    VALUE_(21, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDLY(_x)      VALUE_(16, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBSEL(_x)      VALUE_(14, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDIV(_x)      VALUE_(7, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FINDIV(_x)     VALUE_(0, _x)
+
+// Delay Configuration Register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA1(_x)      VALUE_(20, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA0(_x)      VALUE_(15, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(_x)       VALUE_(10, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(_x)       VALUE_(5, _x)
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(_x)       VALUE_(0, _x)
+
+// CCC Status Register
+#define CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR_PLL_LOCK_SYNC      BIT_(0)
+
+// ESRAM control register
+#define CYGHWR_HAL_A2FXXX_SC_ESRAM_CR_REMAP                BIT_(0)
+
+// ENVM control register
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_SIX_CYCLE             BIT_(7)
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS           BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_CR_REMAP_SIZE(_s_)       VALUE_(0, _s_)
+
+// ENVM re-mapping in system or fabric master space register
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_BASE(_b_)          VALUE_(1, _b_)
+#define CYGHWR_HAL_A2FXXX_SC_ENVM_REMAP_EN                 BIT_(0)
+
+// Fabric protect size
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128B            VALUE_(0, 6)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_2KB             VALUE_(0, 10)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_16KB            VALUE_(0, 13)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_32KB            VALUE_(0, 14)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_64KB            VALUE_(0, 15)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128KB           VALUE_(0, 16)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_256KB           VALUE_(0, 17)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_512KB           VALUE_(0, 18)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_8MB             VALUE_(0, 22)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_128MB           VALUE_(0, 26)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_SIZE_2GB             VALUE_(0, 30)
+
+// Fabric protect control register
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR_VAL(_x)      VALUE_( 1, _x)
+#define CYGHWR_HAL_A2FXXX_SC_FAB_PROT_BASE_CR_EN           BIT_(0)
+
+// Embedded FlashROM control register
+#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR_SYS_TOPT3_1(_v_)     VALUE_(1, _v_)
+#define CYGHWR_HAL_A2FXXX_SC_EFROM_CR_SYS_TOPT0            BIT_(0)
+
+//=============================================================================
+// DMA
+//
+
+#define CYGHWR_HAL_A2FXXX_DMA_RATIO                         0x0
+#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS                 0x4
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(_x_)                (0x20 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(_x_)              (0x24 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_SRC(_x_)              (0x28 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_DST(_x_)              (0x2C + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT(_x_)            (0x30 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_SRC(_x_)              (0x34 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_DST(_x_)              (0x38 + (_x_ * 0x20))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT(_x_)            (0x3C + (_x_ * 0x20))
+
+// Ratio
+#define CYGHWR_HAL_A2FXXX_DMA_RATIO_HILO(_x_)              VALUE_(0, _x_)
+
+// Buffer status
+#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS_CHAxx(_x_)     VALUE_( (_x_ << 1), 1)
+#define CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS_CHAx(_x_)      VALUE_(((_x_ << 1)+1), 1)
+
+// Channel control
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH_SEL(_p_)     VALUE_(23, _p_)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_WR_ADJ(_v_)         VALUE_(14, _v_)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_4B         VALUE_(12, 0x3)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_2B         VALUE_(12, 0x2)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_1B         VALUE_(12, 0x1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_0B         VALUE_(12, 0x0)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR(_x_)       VALUE_(12, ((_x_) & 0x3))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_4B         VALUE_(10, 0x3)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_2B         VALUE_(10, 0x2)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_1B         VALUE_(10, 0x1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_0B         VALUE_(10, 0x0)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR(_x_)       VALUE_(10, ((_x_) & 0x3))
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_HI_PRI          BIT_(9)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB           BIT_(8)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA           BIT_(7)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN               BIT_(6)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_RESET               BIT_(5)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PAUSE               BIT_(4)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_WORD           VALUE_(2, 0x2)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_HWORD          VALUE_(2, 0x1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_BYTE           VALUE_(2, 0x0)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DIR                 BIT_(1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH              BIT_(0)
+
+// DMA transfer type
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_UART0              0x0
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_UART0                0x1
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_UART1              0x2
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_UART1                0x3
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_SPI0               0x4
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_SPI0                 0x5
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_SPI1               0x6
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_SPI1                 0x7
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_FPGA               0x8
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_FPGA                 0x9
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_FROM_ACE                0x10
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_TO_ACE                  0x11
+#define CYGHWR_HAL_A2FXXX_DMA_XFER_MEMORY                  0xff
+
+#define CYGHWR_HAL_A2FXXX_DMA_XFER(_x)                     CYGHWR_HAL_A2FXXX_DMA_XFER_##_x
+
+#define CYGHWR_HAL_A2FXXX_DMA_GET_SUB_ID(_x)               ((_x>>2) & 0x01)
+
+// Channel status
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_BUF_SEL           BIT_(2)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_COMPB             BIT_(1)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS_COMPA             BIT_(0)
+
+// Buffer count
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT_FIELD(_c)       VALUE_(0, _c)
+#define CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT_FIELD(_c)       VALUE_(0, _c)
+
+#define CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL                  8
+#define CYGHWR_HAL_A2FXXX_DMA_MAX_SUB_CHANNEL              2
+
+// DMA access prototypes
+void             hal_dma_init ( void );
+cyg_uint32       a2fxxx_dma_xfer (cyg_uint8 , cyg_bool , cyg_uint32 len, cyg_uint8* , cyg_uint8* );
+cyg_uint32       a2fxxx_dma_ch_setup (cyg_uint8 , cyg_uint8 , cyg_bool , cyg_uint8 , cyg_uint8 , cyg_bool, cyg_uint8);
+void             a2fxxx_dma_ch_detach (cyg_uint8 );
+void             a2fxxx_dma_update_incr (cyg_uint8 , cyg_bool , cyg_uint8 );
+void             a2fxxx_dma_clear_interrupt (cyg_uint8 );
+cyg_uint8        a2fxxx_dma_get_comp_flag (cyg_uint8 );
+
+#define CYGHWR_HAL_A2FXXX_DMA_OUTBOUND                     true
+#define CYGHWR_HAL_A2FXXX_DMA_INBOUND                      false
+
+//=============================================================================
+// ENVM
+//
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS                      0x00
+#define CYGHWR_HAL_A2FXXX_ENVM_CTRL                        0x04
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ                         0x08
+#define CYGHWR_HAL_A2FXXX_ENVM0_CR                         0x10
+#define CYGHWR_HAL_A2FXXX_ENVM1_CR                         0x14
+#define CYGHWR_HAL_A2FXXX_ENVM0_PAGE_STATUS                0x18
+#define CYGHWR_HAL_A2FXXX_ENVM1_PAGE_STATUS                0x1C
+
+// Status Register
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ILLEGAL_CMD_1        BIT_(31)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_1                    VALUE_(24, 0x3)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OP_DONE_1            BIT_(23)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC2_ERR_1           BIT_(22)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC1_ERR_1           BIT_(21)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OVER_THR_1           BIT_(20)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ERASE_ERR_1          BIT_(19)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROG_ERR_1           BIT_(18)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROT_ERR_1           BIT_(17)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_BSY_1                BIT_(16)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ILLEGAL_CMD_0        BIT_(15)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_0                    VALUE_( 8, 0x3)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OP_DONE_0            BIT_(7)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC2_ERR_0           BIT_(6)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ECC1_ERR_0           BIT_(5)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_OVER_THR_0           BIT_(4)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_ERASE_ERR_0          BIT_(3)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROG_ERR_0           BIT_(2)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_PROT_ERR_0           BIT_(1)
+#define CYGHWR_HAL_A2FXXX_ENVM_STATUS_BSY_0                BIT_(0)
+
+// Control Register
+#define CYGHWR_HAL_A2FXXX_ENVM_CTRL_COMMAND(_x_)           VALUE_(24, _x_)
+#define CYGHWR_HAL_A2FXXX_ENVM_CTRL_PAGE_ADDR(_x_)         VALUE_( 0, _x_)
+
+// Interrupt Enable
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ILLEGAL_CMD_1           BIT_(31)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OP_DONE_1               BIT_(23)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC2_ERR_1              BIT_(22)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC1_ERR_1              BIT_(21)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OVER_THR_1              BIT_(20)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ERASE_ERR_1             BIT_(19)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROG_ERR_1              BIT_(18)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROT_ERR_1              BIT_(17)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ILLEGAL_CMD_0           BIT_(15)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OP_DONE_0               BIT_(7)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC2_ERR_0              BIT_(6)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ECC1_ERR_0              BIT_(5)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_OVER_THR_0              BIT_(4)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_ERASE_ERR_0             BIT_(3)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROG_ERR_0              BIT_(2)
+#define CYGHWR_HAL_A2FXXX_ENVM_IRQ_PROT_ERR_0              BIT_(1)
+
+// Configuration Register
+#define CYGHWR_HAL_A2FXXX_ENVMx_CR_LOCK                    BIT_(2)
+#define CYGHWR_HAL_A2FXXX_ENVMx_CR_PAGE_LOSS               BIT_(1)
+#define CYGHWR_HAL_A2FXXX_ENVMx_CR_READ_NEXT               BIT_(0)
+
+// Page status
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_WCOUNT         VALUE_(8, 0x00ffffffff)
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_OVER_THR       BIT_(3)
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_RPROT          BIT_(2)
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_WPROT          BIT_(1)
+#define CYGHWR_HAL_A2FXXX_ENVMx_PAGE_STATUS_OPROT          BIT_(0)
+
+
+//=============================================================================
+// eSRAM
+//
+
+#define CYGHWR_HAL_A2FXXX_ESRAM_CR                         0xE0002000
+#define CYGHWR_HAL_A2FXXX_AHB_MATRIX_CR                    0xE0002018
+
+#define CYGHWR_HAL_A2FXXX_ESRAM_CR_REMAP                   BIT_(0)
+
+
+//=============================================================================
+// SPI
+//
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL                         0x00
+#define CYGHWR_HAL_A2FXXX_SPI_TXRXDF_SIZE                  0x04
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS                       0x08
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR                    0x0C
+#define CYGHWR_HAL_A2FXXX_SPI_RX                           0x10
+#define CYGHWR_HAL_A2FXXX_SPI_TX                           0x14
+#define CYGHWR_HAL_A2FXXX_SPI_CLK_GEN                      0x18
+#define CYGHWR_HAL_A2FXXX_SPI_SLAVE_SEL                    0x1C
+#define CYGHWR_HAL_A2FXXX_SPI_MIS                          0x20
+#define CYGHWR_HAL_A2FXXX_SPI_RIS                          0x24
+
+// Control Register
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_SPH                     BIT_(25)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_SPO                     BIT_(24)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_COUNT(_x)               VALUE_(8, _x)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_TX_UNRRUN           BIT_(7)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_RX_OVRFLO           BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_TX                  BIT_(5)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_IRQ_RX                  BIT_(4)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_NS                VALUE_(2, 0x2)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_TI                VALUE_(2, 0x1)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_PROTO_MOTOROLA          VALUE_(2, 0x0)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_MASTER                  BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_CTRL_EN                      BIT_(0)
+
+// Status Register
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_EMPTY_N       BIT_(11)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_EMPTY         BIT_(10)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_FULL_N        BIT_(9)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_FIFO_FULL          BIT_(8)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_EMPTY_N       BIT_(7)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_EMPTY         BIT_(6)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_FULL_N        BIT_(5)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_FIFO_FULL          BIT_(4)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_UNDERRUN           BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_OVERFLOW           BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_RX_RCED               BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_STATUS_TX_SENT               BIT_(0)
+
+// Interrupt Clear Register
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_TXUNDRUN           BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_RXOVRFLW           BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_RXRDY              BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_IRQ_CLEAR_TXDONE             BIT_(0)
+
+// Masked Interrupt
+#define CYGHWR_HAL_A2FXXX_SPI_MIS_TXUNDRUN                 BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SPI_MIS_RXOVRFLW                 BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SPI_MIS_RXRDY                    BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_MIS_TXDONE                   BIT_(0)
+
+// Raw Interrupt Status
+#define CYGHWR_HAL_A2FXXX_SPI_RIS_TXUNDRUN                 BIT_(3)
+#define CYGHWR_HAL_A2FXXX_SPI_RIS_RXOVRFLW                 BIT_(2)
+#define CYGHWR_HAL_A2FXXX_SPI_RIS_RXRDY                    BIT_(1)
+#define CYGHWR_HAL_A2FXXX_SPI_RIS_TXDONE                   BIT_(0)
+
+// Chip select selection
+#define CYGHWR_HAL_A2FXXX_SPI_CS_SEL(_dev)                 (0x1 << _dev)
+
+// Peripherals IOs mapping
+#define CYGHWR_HAL_A2FXXX_SPI0_DO  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_DO,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_DI  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_DI,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_CLK CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_CLK,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_SS0 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_0, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_SS1 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_1, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_SS2 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_2, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI0_SS3 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI0_SS_3, DISABLE )
+
+#define CYGHWR_HAL_A2FXXX_SPI1_DO  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_DO,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_DI  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_DI,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_CLK CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_CLK,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS0 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_0, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS1 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_1, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS2 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_2, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS3 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_3, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS4 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_4, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS5 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_5, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS6 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_6, DISABLE )
+#define CYGHWR_HAL_A2FXXX_SPI1_SS7 CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, SPI1_SS_7, DISABLE )
+
+// This is a special GPIO macro accommodated for SPI slave select
+#define CYGHWR_HAL_A2FXXX_CS_GPIO(                        \
+    __bit,                                                \
+    __mode,                                               \
+    __p_io,                                               \
+    __irq)                                                \
+(                                                         \
+      (__bit << 23) |                                     \
+      (CYGHWR_HAL_A2FXXX_GPIO_MODE_ ## __mode) |          \
+       CYGHWR_HAL_A2FXXX_GPIO_PERIPH_GPIO(__p_io) |       \
+      (CYGHWR_HAL_A2FXXX_GPIO_IRQ_ ## __irq)              \
+)
+
+__externC cyg_uint32 hal_a2fxxx_spi_clock( cyg_uint32 );
+
+//=============================================================================
+// I2C
+//
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL                         0x00
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS                       0x04
+#define CYGHWR_HAL_A2FXXX_I2C_DATA                         0x08
+#define CYGHWR_HAL_A2FXXX_I2C_ADDR                         0x0C
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS                        0x10
+#define CYGHWR_HAL_A2FXXX_I2C_FREQ                         0x14
+#define CYGHWR_HAL_A2FXXX_I2C_GLITCH                       0x18
+
+// Control Register
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR2                     BIT_(7)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_ENS1                    BIT_(6)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_STA                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_STO                     BIT_(4)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_SI                      BIT_(3)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_AA                      BIT_(2)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR1                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_I2C_CTRL_CR0                     BIT_(0)
+
+// I2C clock divider
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_8                        0x7
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_60                       0x6
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_120                      0x5
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_960                      0x4
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_160                      0x3
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_192                      0x2
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_224                      0x1
+#define CYGHWR_HAL_A2FXXX_I2C_DIV_256                      0x0
+
+// Status Registers
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_START             0x08
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_REPEAT_START      0x10
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ADDR_ACK          0x18
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ADDR_NACK         0x20
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_DATA_ACK          0x28
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_DATA_NACK         0x30
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MTX_ARBLOST           0x38
+
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_START             0x08
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_REPEAT_START      0x10
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ARBLOST           0x38
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ADDR_ACK          0x40
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_ADDR_NACK         0x48
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_DATA_ACK          0x50
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRX_DATA_NACK         0x58
+
+#define CYGHWR_HAL_A2FXXX_I2C_STATUS_MRESET                0xD0
+
+// SMB
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_RST                    BIT_(7)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_NO                     BIT_(6)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_NI                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBALERT_NO                  BIT_(4)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBALERT_NI                  BIT_(3)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_EN                     BIT_(2)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_IRQ_EN                 BIT_(1)
+#define CYGHWR_HAL_A2FXXX_I2C_SMBUS_ALERT_IRQ_EN           BIT_(0)
+
+// Peripherals IOs mapping
+#define CYGHWR_HAL_A2FXXX_I2C0_SDA CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C0_SDA, DISABLE )
+#define CYGHWR_HAL_A2FXXX_I2C0_SCL CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C0_SCL, DISABLE )
+
+#define CYGHWR_HAL_A2FXXX_I2C1_SDA CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C1_SDA, DISABLE )
+#define CYGHWR_HAL_A2FXXX_I2C1_SCL CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, I2C1_SCL, DISABLE )
+
+__externC cyg_uint32 hal_a2fxxx_i2c_clock( cyg_uint32 );
+
+//=============================================================================
+// GPIO
+//
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_CFG(_io)                (_io << 2)
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_INT                     0x080
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_DIN                     0x084
+#define CYGHWR_HAL_A2FXXX_MSS_GPIO_DOUT                    0x088
+
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR                   0xe0042078
+#define CYGHWR_HAL_A2FXXX_GPIN_SOURCE_CR                   0xe004207c
+#define CYGHWR_HAL_A2FXXX_IOMUX_CR                         0xe0042100
+
+// CFG
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(_t)              VALUE_(5, (_t & 0x7))
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINTEN                 BIT_(3)
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_OUTBUFEN                BIT_(2)
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINEN                  BIT_(1)
+#define CYGHWR_HAL_A2FXXX_GPIO_CFG_GPOUTEN                 BIT_(0)
+
+// MSS GPIO
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_3V3           0x0
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_2V5           0x1
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_1V8           0x2
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_LVCMOS_1V5           0x3
+
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(_t)        VALUE_(0, (CYGHWR_HAL_A2FXXX_MSS_IO_BANK_##_t & 0x3))
+#define CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(_t)        VALUE_(2, (CYGHWR_HAL_A2FXXX_MSS_IO_BANK_##_t & 0x3))
+
+// HAL definitions
+#define CYGHWR_HAL_A2FXXX_GPIO_MODE_IN                     VALUE_(0,0)     // Input mode
+#define CYGHWR_HAL_A2FXXX_GPIO_MODE_OUT                    VALUE_(0,1)     // Output mode
+#define CYGHWR_HAL_A2FXXX_GPIO_MODE_PERIPH                 VALUE_(0,2)     // Peripheral function mode
+
+#define CYGHWR_HAL_A2FXXX_GPIO_PERIPH_IO(_name_)           VALUE_(2, CYGHWR_HAL_A2FXXX_IOMUX_##_name_)
+#define CYGHWR_HAL_A2FXXX_GPIO_PERIPH_GPIO(_id_)           VALUE_(2, (CYGHWR_HAL_A2FXXX_IOMUX_GPIO_0+_id_))
+
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_DISABLE                 VALUE_(10,0)     // Interrupt disable
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_FALLING_EDGE            VALUE_(10,1)     // Interrupt on falling edge
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_RISING_EDGE             VALUE_(10,2)     // Interrupt on rising edge
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_BOTH_EDGES              VALUE_(10,3)     // Interrupt on both edges
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_LOW_LEVEL               VALUE_(10,4)     // Interrupt on low level
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ_HIGH_LEVEL              VALUE_(10,5)     // Interrupt on high level
+
+typedef struct
+{
+   cyg_uint32 val;
+} default_io_mux_type;
+
+// IOMUX index setting for peripherals
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_DO                    0
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_DI                    1
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_CLK                   2
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_0                  3
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_TX                   4
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RX                   5
+#define CYGHWR_HAL_A2FXXX_IOMUX_I2C0_SDA                   6
+#define CYGHWR_HAL_A2FXXX_IOMUX_I2C0_SCL                   7
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_DO                    8
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_DI                    9
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_CLK                   10
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_0                  11
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_TX                   12
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RX                   13
+#define CYGHWR_HAL_A2FXXX_IOMUX_I2C1_SDA                   14
+#define CYGHWR_HAL_A2FXXX_IOMUX_I2C1_SCL                   15
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXD0                  16
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXD1                  17
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXD0                  18
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXD1                  19
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_TXEN                  20
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_CRSDV                 21
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_RXER                  22
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_MDIO                  23
+#define CYGHWR_HAL_A2FXXX_IOMUX_MAC0_MDC                   24
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_0                     25
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_1                     26
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_2                     27
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_3                     28
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_4                     29
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_5                     30
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_6                     31
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_7                     32
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_8                     33
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_9                     34
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_10                    35
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_11                    36
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_12                    37
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_13                    38
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_14                    39
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_15                    40
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_16                    41
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_17                    42
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_18                    43
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_19                    44
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_20                    45
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_21                    46
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_22                    47
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_23                    48
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_24                    49
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_25                    50
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_26                    51
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_27                    52
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_28                    53
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_29                    54
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_30                    55
+#define CYGHWR_HAL_A2FXXX_IOMUX_GPIO_31                    56
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_1                  57
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_2                  58
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI0_SS_3                  59
+// 60 to 63 not used
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RTS                  64
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DTR                  65
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_CTS                  66
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DSR                  67
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_RI                   68
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART0_DCD                  69
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_1                  70
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_2                  71
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_3                  72
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_4                  73
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_5                  74
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_6                  75
+#define CYGHWR_HAL_A2FXXX_IOMUX_SPI1_SS_7                  76
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RTS                  77
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DTR                  78
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_CTS                  79
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DSR                  80
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_RI                   81
+#define CYGHWR_HAL_A2FXXX_IOMUX_UART1_DCD                  82
+#define CYGHWR_HAL_A2FXXX_IOMUX_NONE                       83
+
+// This macro packs the port, bit number, mode, buffer and irq
+// for a GPIO pin into a single word.
+// The packing puts:
+
+#define CYGHWR_HAL_A2FXXX_GPIO(                             \
+    __bit,                                                  \
+    __mode,                                                 \
+    __name,                                                 \
+    __irq)                                                  \
+(                                                           \
+         (__bit << 23) |                                    \
+         (CYGHWR_HAL_A2FXXX_GPIO_MODE_ ## __mode) |         \
+          CYGHWR_HAL_A2FXXX_GPIO_PERIPH_IO(__name) |        \
+         (CYGHWR_HAL_A2FXXX_GPIO_IRQ_ ## __irq)             \
+)
+
+
+// Macros to extract encoded values
+#define CYGHWR_HAL_A2FXXX_GPIO_BIT(__pin)                  (((__pin)>>23) & 0x1F)
+#define CYGHWR_HAL_A2FXXX_GPIO_MODE(__pin)                 ((__pin)&0x0003)
+#define CYGHWR_HAL_A2FXXX_GPIO_IOMUX_IDX(__pin)            ((__pin>>2)  & 0xff)
+#define CYGHWR_HAL_A2FXXX_GPIO_IRQ(__pin)                  ((__pin>>10) & 0x07)
+#define CYGHWR_HAL_A2FXXX_GPIO_NONE                        (0xFFFFFFFF)
+
+__externC void hal_a2fxxx_gpio_set( cyg_uint32 pin );
+__externC void hal_a2fxxx_gpio_out( cyg_uint32 pin, int val );
+__externC void hal_a2fxxx_gpio_in ( cyg_uint32 pin, int *val );
+
+#define CYGHWR_HAL_A2FXXX_GPIO_SET(__pin )        hal_a2fxxx_gpio_set( __pin )
+#define CYGHWR_HAL_A2FXXX_GPIO_OUT(__pin, __val ) hal_a2fxxx_gpio_out( __pin, __val )
+#define CYGHWR_HAL_A2FXXX_GPIO_IN(__pin,  __val ) hal_a2fxxx_gpio_in( __pin, __val )
+
+
+//=============================================================================
+// UART
+//
+#define CYGHWR_HAL_A2FXXX_UART16550_RBR                    0x00
+#define CYGHWR_HAL_A2FXXX_UART16550_THR                    0x00
+#define CYGHWR_HAL_A2FXXX_UART16550_DLR                    0x00
+#define CYGHWR_HAL_A2FXXX_UART16550_DMR                    0x04
+#define CYGHWR_HAL_A2FXXX_UART16550_IER                    0x04
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR                    0x08
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR                    0x08
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR                    0x0C
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR                    0x10
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR                    0x14
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR                    0x18
+#define CYGHWR_HAL_A2FXXX_UART16550_SR                     0x1C
+
+// IER
+#define CYGHWR_HAL_A2FXXX_UART16550_IER_EDSSI              BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_IER_ELSI               BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_IER_ETBEI              BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI              BIT_(0)
+
+// IIR (by priority)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_MODEM_STATUS       VALUE_(0, 0x0)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_THRE               VALUE_(0, 0x2)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_CTI                VALUE_(0, 0xC)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_RXD                VALUE_(0, 0x4)
+#define CYGHWR_HAL_A2FXXX_UART16550_IIR_RLS                VALUE_(0, 0x6)
+
+// Fifo control
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_1BYTE      VALUE_(6, 0x0)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_4BYTE      VALUE_(6, 0x1)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_8BYTE      VALUE_(6, 0x2)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RX_TRIG_14BYTE     VALUE_(6, 0x3)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_EN_TXRX_DY         BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_TX_FIFO      BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_RX_FIFO      BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_FCR_RESERVED           BIT_(0)
+
+// Line control
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_DLAB               BIT_(7)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_SB                 BIT_(6)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_SP                 BIT_(5)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_EPS                BIT_(4)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_PEN                BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_1             VALUE_(2,0)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_2             VALUE_(2,1)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_5BITS          VALUE_(0, 0x0)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_6BITS          VALUE_(0, 0x1)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_7BITS          VALUE_(0, 0x2)
+#define CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_8BITS          VALUE_(0, 0x3)
+
+// MCR register
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_LOOP               BIT_(4)
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_OUT2               BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_OUT1               BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_RTS                BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_MCR_DTR                BIT_(0)
+
+// LSR register
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_FIER               BIT_(6)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_TEMT               BIT_(6)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_THRE               BIT_(5)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_BI                 BIT_(4)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_FE                 BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_PE                 BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_OE                 BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_LSR_DR                 BIT_(0)
+
+// MSR
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DCD                BIT_(7)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_RI                 BIT_(6)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DSR                BIT_(5)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_CTS                BIT_(4)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DDCD               BIT_(3)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_TERI               BIT_(2)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DDSR               BIT_(1)
+#define CYGHWR_HAL_A2FXXX_UART16550_MSR_DCTS               BIT_(0)
+
+__externC cyg_uint32 hal_a2fxxx_pclk0;
+__externC cyg_uint32 hal_a2fxxx_pclk1;
+
+__externC void hal_a2fxxx_uart_setbaud(cyg_uint32 , cyg_uint32 );
+
+// Consider adding rounding ?
+#define CYG_HAL_CORTEXM_A2FXXX_BAUD_GENERATOR( id, baud )  \
+({                                                         \
+   cyg_uint16 _divider;                                    \
+   if( id == 0 )                                           \
+     _divider = (hal_a2fxxx_pclk0/(baud << 4));            \
+   else                                                    \
+     _divider = (hal_a2fxxx_pclk1/(baud << 4));            \
+   _divider;                                               \
+})
+
+// Peripherals IOs mapping
+#define CYGHWR_HAL_A2FXXX_UART0_TX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART0_TX, DISABLE )
+#define CYGHWR_HAL_A2FXXX_UART0_RX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART0_RX, DISABLE )
+
+#define CYGHWR_HAL_A2FXXX_UART1_TX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART1_TX, DISABLE )
+#define CYGHWR_HAL_A2FXXX_UART1_RX CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, UART1_RX, DISABLE )
+
+
+//=============================================================================
+// Watchdog
+//
+#define CYGHWR_HAL_A2FXXX_WD_VALUE                         0x00
+#define CYGHWR_HAL_A2FXXX_WD_LOAD                          0x04
+#define CYGHWR_HAL_A2FXXX_WD_MVRP                          0x08
+#define CYGHWR_HAL_A2FXXX_WD_REFRESH                       0x0C
+#define CYGHWR_HAL_A2FXXX_WD_ENABLE                        0x10
+#define CYGHWR_HAL_A2FXXX_WD_CTRL                          0x14
+#define CYGHWR_HAL_A2FXXX_WD_STATUS                        0x18
+#define CYGHWR_HAL_A2FXXX_WD_RIS                           0x1C
+#define CYGHWR_HAL_A2FXXX_WD_MIS                           0x20
+
+// Keys
+#define CYGHWR_HAL_A2FXXX_WD_REFRESH_KEY                   0xAC15DE42
+#define CYGHWR_HAL_A2FXXX_WD_DISABLE_KEY                   0x4C6E55FA
+
+
+//=============================================================================
+// Timer
+//
+#define CYGHWR_HAL_A2FXXX_TIMER1   CYGHWR_HAL_A2FXXX_TIMER
+#define CYGHWR_HAL_A2FXXX_TIMER2   (CYGHWR_HAL_A2FXXX_TIMER + 0x18)
+
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_VAL                   0x00
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_LOADVAL               0x04
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_BGLOADVAL             0x08
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL                  0x0c
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_RIS                   0x10
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_MIS                   0x14
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_VAL_U                0x30
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_VAL_L                0x34
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_LOADVAL_U            0x38
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_LOADVAL_L            0x3C
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_BGLOADVAL_U          0x40
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_BGLOADVAL_L          0x44
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_CTRL                 0x48
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_RIS                  0x4C
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MIS                  0x50
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MODE                 0x54
+
+// Timer control
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_INTEN            BIT_(2)
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_ONESHOT          BIT_(1)
+#define CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_EN               BIT_(0)
+
+// Timer control 64 bits
+#define CYGHWR_HAL_A2FXXX_TIMER_TIM64_MODE_64BITS          BIT_(0)
+
+
+//=============================================================================
+// MAC
+//
+#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_A2F200) || \
+           defined(CYGHWR_HAL_CORTEXM_A2FXXX_A2F500)
+
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0                         0x00
+#define CYGHWR_HAL_A2FXXX_MAC_CSR1                         0x08
+#define CYGHWR_HAL_A2FXXX_MAC_CSR2                         0x10
+#define CYGHWR_HAL_A2FXXX_MAC_CSR3                         0x18
+#define CYGHWR_HAL_A2FXXX_MAC_CSR4                         0x20
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5                         0x28
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6                         0x30
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7                         0x38
+#define CYGHWR_HAL_A2FXXX_MAC_CSR8                         0x40
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9                         0x48
+#define CYGHWR_HAL_A2FXXX_MAC_CSR10                        0x50
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11                        0x58
+
+// Bus Mode Register (CSR0)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_CLEAR                   0xFE000000
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_SPD                     BIT_(21)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_DBO                     BIT_(20)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_TAP(_x)                 VALUE_(17, (_x & 0x7))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_PBL(_x)                 VALUE_(8, (_x & 0x2f))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_BLE                     BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_DSL(_x)                 VALUE_(2, (_x & 0x1f))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_BAR                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR0_SWR                     BIT_(0)
+
+// Transmit Poll Demand Register (CSR1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR1_TPD(_x)                 VALUE_(0, _x)
+
+// Receive Poll Demand Register (CSR2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR2_RPD(_x)                 VALUE_(0, _x)
+
+// Receive Descriptor List Base Address Register (CSR3)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR3_RLA(_x)                 VALUE_(0, _x)
+
+// Transmit Descriptor List Base Address Register (CSR4)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR4_TLA(_x)                 VALUE_(0, _x)
+
+// Status and Control Register (CSR5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_CLOSE_TXD            VALUE_(20, 0x7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_SUSPEND              VALUE_(20, 0x6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_SETUP_PACKET         VALUE_(20, 0x5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_XFER                 VALUE_(20, 0x3)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_WAIT_EOT             VALUE_(20, 0x2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_FETCH_TXD            VALUE_(20, 0x1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_STOP                 VALUE_(20, 0x0)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_MASK                 VALUE_(20, 0x7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_XFER                 VALUE_(17, 0x7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_CLOSE_RXD            VALUE_(17, 0x5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_SUSPEND              VALUE_(17, 0x4)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_WAIT_PACKET          VALUE_(17, 0x3)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_WAIT_EOR             VALUE_(17, 0x2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_FETCH_RXD            VALUE_(17, 0x1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_STOP                 VALUE_(17, 0x0)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_MASK                 VALUE_(17, 0x7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_NIS                     BIT_(16)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_AIS                     BIT_(15)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_ERI                     BIT_(14)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_GTE                     BIT_(11)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_ETI                     BIT_(10)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RPS                     BIT_(8)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RU                      BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_RI                      BIT_(6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_UNF                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TU                      BIT_(2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TPS                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR5_TI                      BIT_(0)
+
+// Define MAC state
+#define A2FXXX_MAC_TX_STATE(_x_)   CYGHWR_HAL_A2FXXX_MAC_CSR5_TS_##_x_
+#define A2FXXX_MAC_RX_STATE(_x_)   CYGHWR_HAL_A2FXXX_MAC_CSR5_RS_##_x_
+#define A2FXXX_MAC_TX_STATE_MASK                           VALUE_(20, 0x7)
+#define A2FXXX_MAC_RX_STATE_MASK                           VALUE_(17, 0x7)
+
+// Operation Mode Register (CSR6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_CLEAR                   0xBF9F1D20
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_RA                      BIT_(30)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_TTM                     BIT_(22)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_SF                      BIT_(21)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_TR(_x)                  VALUE_(14, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_ST                      BIT_(13)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_FD                      BIT_(9)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PM                      BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PR                      BIT_(6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_IF                      BIT_(4)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_PB                      BIT_(3)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_HO                      BIT_(2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_SR                      BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR6_HP                      BIT_(0)
+
+// Interrupt Enable Register (CSR7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_NIE                     BIT_(16)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_AIE                     BIT_(15)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_ERE                     BIT_(14)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_GTE                     BIT_(11)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_ETE                     BIT_(10)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RSE                     BIT_(8)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RUE                     BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_RIE                     BIT_(6)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_UNE                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TUE                     BIT_(2)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TSE                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR7_TIE                     BIT_(0)
+
+// Missed Frames and Overflow Counter Register (CSR8)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR8_OCO                     BIT_(28)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR8_MFO                     BIT_(16)
+
+// RMII Management Interface Register (CSR9)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDI                     BIT_(19)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDEN                    BIT_(18)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDO                     BIT_(17)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR9_MDC                     BIT_(16)
+
+// General-Purpose Timer and Interrupt Mitigation Control Register (CSR11)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_CS                     BIT_(31)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_TT(_x)                 VALUE_(27, (_x & 0xf))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_NTP(_x)                VALUE_(24, (_x & 0x7))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_RT(_x)                 VALUE_(20, (_x & 0xf))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_NRP(_x)                VALUE_(17, (_x & 0x7))
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_CON                    BIT_(16)
+#define CYGHWR_HAL_A2FXXX_MAC_CSR11_TIM(_x)                VALUE_(0, _x)
+
+// Receive Descriptors (RDESx)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_OWN                    BIT_(31)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FF                     BIT_(30)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FL(_x)                 VALUE_(16, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_ES                     BIT_(15)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_DE                     BIT_(14)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_RF                     BIT_(11)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_MF                     BIT_(10)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FS                     BIT_(9)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_LS                     BIT_(8)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_TL                     BIT_(7)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_CS                     BIT_(6)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_FT                     BIT_(5)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_RE                     BIT_(3)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_DB                     BIT_(2)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_CE                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES0_ZERO                   BIT_(0)
+
+#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RER                    BIT_(25)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RCH                    BIT_(24)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RBS2(_x)               VALUE_(11, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_RDES1_RBS1(_x)               VALUE_(0, _x)
+
+// Receive Descriptors (TDESx)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_OWN                    BIT_(31)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_ES                     BIT_(15)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_LO                     BIT_(11)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_NC                     BIT_(10)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_LC                     BIT_(9)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_EC                     BIT_(8)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_CC(_x)                 VALUE_(3, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_UF                     BIT_(1)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES0_DE                     BIT_(0)
+
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_IC                     BIT_(31)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_LS                     BIT_(30)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FS                     BIT_(29)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FT1                    BIT_(28)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_SET                    BIT_(27)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_AC                     BIT_(26)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TER                    BIT_(25)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TCH                    BIT_(24)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_DPD                    BIT_(23)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_FT0                    BIT_(22)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TBS2(_x)               VALUE_(11, _x)
+#define CYGHWR_HAL_A2FXXX_MAC_TDES1_TBS1(_x)               VALUE_(0, _x)
+
+#define CYGHWR_HAL_A2FXXX_MAC0_MDIO   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_MDIO,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_MDC    CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_MDC,   DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_TXD0   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXD0,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_TXD1   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXD1,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_RXD0   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXD0,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_RXD1   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXD1,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_TXEN   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_TXEN,  DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_CRSDV  CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_CRSDV, DISABLE )
+#define CYGHWR_HAL_A2FXXX_MAC0_RXER   CYGHWR_HAL_A2FXXX_GPIO( 0, PERIPH, MAC0_RXER,  DISABLE )
+
+#endif
+
+//=============================================================================
+// Spare page
+
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY       0x081C
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_VERSION   0x0840
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_1_3_FCLK  0x162C
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_2_x_FCLK  0x1EAC
+
+// System boot key value
+#define CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY_VALUE 0x4C544341
+
+// System boot version
+#define CYGHWR_HAL_A2FXXX_SYSBOOT_VERSION(_x, _y, _z)        ((_x << 16) | (_y << 8) | (_z))
+
+#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_VERSION()                                      \
+({                                                                                   \
+   cyg_uint32 _i;                                                                    \
+   cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES;                             \
+   HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_VERSION, _i);  \
+   _i;                                                                               \
+})
+
+#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_KEY()                                          \
+({                                                                                   \
+   cyg_uint32 _i;                                                                    \
+   cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES;                             \
+   HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY, _i);      \
+   _i;                                                                               \
+})
+
+#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_1_3_FCLK()                                     \
+({                                                                                   \
+   cyg_uint32 _i;                                                                    \
+   cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES;                             \
+   HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_1_3_FCLK, _i); \
+   _i;                                                                               \
+})
+
+#define CYGHWR_HAL_A2FXXX_GET_SYSBOOT_2_0_FCLK()                                     \
+({                                                                                   \
+   cyg_uint32 _i;                                                                    \
+   cyg_uint32 base = CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES;                             \
+   HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_2_x_FCLK, _i); \
+   _i;                                                                               \
+})
+
+#define CYGHWR_HAL_A2FXXX_BITSET                           0x1
+#define CYGHWR_HAL_A2FXXX_BITCLEAR                         0x0
+//
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_HAL_VAR_IO_H
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/include/variant.inc b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/variant.inc
new file mode 100644
index 0000000..e215184
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/include/variant.inc
@@ -0,0 +1,54 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+
+//==========================================================================
+// EOF variant.inc
+
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/src/a2fxxx_misc.c b/ecos/packages/hal/cortexm/a2fxxx/var/current/src/a2fxxx_misc.c
new file mode 100644
index 0000000..49d4e73
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/src/a2fxxx_misc.c
@@ -0,0 +1,1214 @@
+/*==========================================================================
+//
+//      a2f_misc.c
+//
+//      Cortex-M Actel A2F HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-02-03
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+
+//==========================================================================
+// Clock Initialization values
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+
+#define CLKx_SRC_CLKA    0
+#define CLKx_SRC_CLKB    1
+#define CLKx_SRC_CLKC    2
+#define CLKx_SRC_CLKGA   3
+#define CLKx_SRC_CLKGB   4
+#define CLKx_SRC_CLKGC   5
+#define CLKx_SRC_CLKGINT 6
+
+#define CLKx_SRC_UIN     0
+#define CLKx_SRC_DIP     1
+#define CLKx_SRC_UIP     4
+#define CLKx_SRC_GLxINT  5
+#define CLKx_SRC_RCOSC   2
+#define CLKx_SRC_MOSC    6
+#define CLKx_SRC_32KOSC  6
+
+// Select source of CLKA
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_AUIN
+# define CLKA_SRC_SEL CLKx_SRC_UIN
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_AUIP)
+# define CLKA_SRC_SEL CLKx_SRC_UIP
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_ADIP)
+# define CLKA_SRC_SEL CLKx_SRC_DIP
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_GLAINT)
+# define CLKA_SRC_SEL CLKx_SRC_GLxINT
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKA_SRC_RCOSC)
+# define CLKA_SRC_SEL CLKx_SRC_RCOSC
+#else
+# define CLKA_SRC_SEL CLKx_SRC_MOSC
+#endif
+
+// Select source of CLKB
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BUIN
+#  define CLKB_SRC_SEL CLKx_SRC_UIN
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BUIP)
+#  define CLKB_SRC_SEL CLKx_SRC_UIP
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_BDIP)
+#  define CLKB_SRC_SEL CLKx_SRC_DIP
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_GLBINT)
+#  define CLKB_SRC_SEL CLKx_SRC_GLxINT
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKB_SRC_RCOSC)
+#  define CLKB_SRC_SEL CLKx_SRC_RCOSC
+# else
+#  define CLKB_SRC_SEL CLKx_SRC_MOSC
+# endif
+#endif
+
+// Select source of CLKC
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CUIN
+#  define CLKC_SRC_SEL CLKx_SRC_UIN
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CUIP)
+#  define CLKC_SRC_SEL CLKx_SRC_UIP
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_CDIP)
+#  define CLKC_SRC_SEL CLKx_SRC_DIP
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_GLCINT)
+#  define CLKC_SRC_SEL CLKx_SRC_GLxINT
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKC_SRC_RCOSC)
+#  define CLKC_SRC_SEL CLKx_SRC_RCOSC
+# else
+#  define CLKC_SRC_SEL CLKx_SRC_32KOSC
+# endif
+#endif
+
+// Select source of CLKGA
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_CLKA
+#  define CLKGA_SRC_SEL 1
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO0)
+#  define CLKGA_SRC_SEL 4
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO90)
+#  define CLKGA_SRC_SEL 5
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO180)
+#  define CLKGA_SRC_SEL 6
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_SRC_PLL_VCO270)
+#  define CLKGA_SRC_SEL 7
+# else
+#  define CLKGA_SRC_SEL 2
+# endif
+#endif
+
+// Select source of CLKGB
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_CLKB
+#  define CLKGB_SRC_SEL 1
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_CLKGA
+#  define CLKGB_SRC_SEL 3
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO0)
+#  define CLKGB_SRC_SEL 4
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO90)
+#  define CLKGB_SRC_SEL 5
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO180)
+#  define CLKGB_SRC_SEL 6
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_SRC_PLL_VCO270)
+#  define CLKGB_SRC_SEL 7
+# else
+#  define CLKGB_SRC_SEL 2
+# endif
+#endif
+
+// Select source of CLKGC
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC
+#  define CLKGC_SRC_SEL 1
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKGA)
+#  define CLKGC_SRC_SEL 3
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO0)
+#  define CLKGC_SRC_SEL 4
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO90)
+#  define CLKGC_SRC_SEL 5
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO180)
+#  define CLKGC_SRC_SEL 6
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_PLL_VCO270)
+#  define CLKGC_SRC_SEL 7
+# else
+#  define CLKGC_SRC_SEL 2
+# endif
+#endif
+
+#if CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV   == 1
+# define PCLK0DIV 0
+#elif CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_DIV == 2
+# define PCLK0DIV 1
+#else
+# define PCLK0DIV 2
+#endif
+
+#if CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV   == 1
+# define PCLK1DIV 0
+#elif CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_DIV == 2
+# define PCLK1DIV 1
+#else
+# define PCLK1DIV 2
+#endif
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK
+# if CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV   == 1
+#  define ACLKDIV 0
+# elif CYGHWR_HAL_CORTEXM_A2FXXX_ACLK_DIV == 2
+#  define ACLKDIV 1
+# else
+#  define ACLKDIV 2
+# endif
+#endif
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL
+# if CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ   < 43750000
+#  define PLL_RANGE 0
+# elif CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ < 87500000
+#  define PLL_RANGE 1
+# elif CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FREQ < 175000000
+#  define PLL_RANGE 2
+# else
+#  define PLL_RANGE 3
+# endif
+#endif
+
+#define OXDIV_CLEAR 0x1F
+#define OXMUX_CLEAR 0x07
+#define DLYX_CLEAR  0x1F
+#define DIV_CLEAR   0x03
+
+#endif // CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+
+//==========================================================================
+// IO settings
+
+#ifdef CYGPKG_HAL_CORTEXM_A2FXXX_IO
+
+# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_3V3)
+# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_3V3)
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_2V5)
+# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_2V5)
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_WEST_BANK_LVCMOS_1V8)
+# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_1V8)
+# else
+# define IO_WEST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTWEST(LVCMOS_1V5)
+# endif
+
+# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_3V3)
+# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_3V3)
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_2V5)
+# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_2V5)
+# elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_IO_EAST_BANK_LVCMOS_1V8)
+# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_1V8)
+# else
+# define IO_EAST_BANK CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR_BTEAST(LVCMOS_1V5)
+# endif
+
+#endif // CYGPKG_HAL_CORTEXM_A2FXXX_IO
+
+
+#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_CLOCK_CHATTER
+# define A2FXXX_CLOCK_TRACE(args...)   diag_printf(args)
+#else
+# define A2FXXX_CLOCK_TRACE(args...)    /* NOOP */
+#endif
+
+
+//==========================================================================
+// Clock frequencies
+//
+// These are set to the frequencies of the various system clocks.
+
+cyg_uint32 hal_a2fxxx_pclk0;           // Peripheral clock (connected to APB_0)
+cyg_uint32 hal_a2fxxx_pclk1;           // Peripheral clock (connected to APB_1)
+cyg_uint32 hal_a2fxxx_aclk;            // Analog Peripheral clock (ADC /DAC etc..)
+cyg_uint32 hal_a2fxxx_pclk_fpga;       // FPGA clock
+
+cyg_uint32 hal_a2fxxx_glb;             // Global Clock B
+cyg_uint32 hal_a2fxxx_glc;             // Global Clock C
+
+cyg_uint32 hal_cortexm_systick_clock;  // NGMUx output or FCLK or SysTick clock
+cyg_uint32 hal_a2fxxx_fclk;            // FCLK
+
+
+//==========================================================================
+// Local prototypes
+
+static void hal_a2fxxx_clk_network_chatter( cyg_uint8 );
+
+static cyg_uint8 hal_start_clocks( void );
+static cyg_uint8 hal_a2fxxx_get_system_boot_clk( void );
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+static void hal_a2fxxx_set_clk_network( void );
+static void hal_a2fxxx_set_envm_timing( void );
+static void hal_a2fxxx_set_clkx( cyg_uint8 x, cyg_uint8 src );
+static void hal_a2fxxx_set_clkgx( cyg_uint8 x );
+static void hal_a2fxxx_set_clkgx_default( cyg_uint8 x );
+static void hal_a2fxxx_set_ngmux( cyg_uint8 );
+static cyg_uint8 hal_a2fxxx_get_ngmux( void );
+
+# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+static inline void hal_a2fxxx_set_pll( void );
+# endif
+#endif
+
+
+//==========================================================================
+
+void
+hal_variant_init( void )
+{
+#if !defined(CYG_HAL_STARTUP_RAM)
+    cyg_uint8 sysboot_miss;
+#endif
+    cyg_uint32 base = CYGHWR_HAL_A2FXXX_WD;
+
+    // Disable Watch-dog
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_WD_ENABLE,
+                                           CYGHWR_HAL_A2FXXX_WD_DISABLE_KEY);
+
+#if !defined(CYG_HAL_STARTUP_RAM)
+    sysboot_miss = hal_start_clocks();
+#endif
+
+    // Release GPIO
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(GPIO) );
+
+    // Setup IO banks
+#ifdef CYGPKG_HAL_CORTEXM_A2FXXX_IO
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MSS_IO_BANK_CR, (IO_WEST_BANK | IO_EAST_BANK) );
+#endif
+
+    // Reset UART0
+#if CYGINT_HAL_A2FXXX_UART0>0
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(UART0) );
+#endif
+
+    // Reset UART1
+#if CYGINT_HAL_A2FXXX_UART1>0
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(UART1) );
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+
+#if !defined(CYG_HAL_STARTUP_RAM)
+    hal_a2fxxx_clk_network_chatter( sysboot_miss );
+#endif
+}
+
+//==========================================================================
+// Setup up system clocks
+//
+// Set up clocks from configuration. In the future this should be extended so
+// that clock rates can be changed at runtime.
+
+static cyg_uint8
+hal_start_clocks( void )
+{
+    if( ! hal_a2fxxx_get_system_boot_clk( ) )
+        return 0;
+
+    //
+    // User has chosen to re-configure the clock network and
+    // overwrite the settings provided by the system boot
+    //
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+    hal_a2fxxx_set_clk_network( );
+
+    // Adjust the ENVM timing according to the core clock
+    // frequency
+    hal_a2fxxx_set_envm_timing( );
+#endif
+
+    return 1;
+}
+
+
+//==========================================================================
+// Read clock configuration as setup by the system boot
+
+static cyg_uint8
+hal_a2fxxx_get_system_boot_clk( void )
+{
+    cyg_uint32 sysboot_key, sysboot_ver, clk_cr, clkga0;
+
+    sysboot_ver = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_VERSION();
+    sysboot_key = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_KEY();
+
+    // Verify that the system boot is present, if not we must give up?
+    if( CYGHWR_HAL_A2FXXX_ENVM_SPARE_PAGES_SYSBOOT_KEY_VALUE
+             != sysboot_key )
+       return 0;
+
+    // Read the MSS CLGA0 frequency value. Address varies with system boot
+    // version
+    if ( sysboot_ver < CYGHWR_HAL_A2FXXX_SYSBOOT_VERSION(2, 0, 0) ) {
+       clkga0 = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_1_3_FCLK();
+    }
+    else {
+       clkga0 = CYGHWR_HAL_A2FXXX_GET_SYSBOOT_2_0_FCLK();
+    }
+
+    // Compute the BUS and fabric clock frequency
+    hal_cortexm_systick_clock = clkga0;
+
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR, clk_cr);
+
+    hal_a2fxxx_pclk0     =
+          clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK0DIV( clk_cr );
+    hal_a2fxxx_pclk1     =
+          clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_PCLK1DIV( clk_cr );
+    hal_a2fxxx_pclk_fpga =
+          clkga0 >> CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_GET_GLBDIV( clk_cr );
+
+    return 1;
+}
+
+
+//==========================================================================
+// Chatter function
+
+static void
+hal_a2fxxx_clk_network_chatter( cyg_uint8 hal_clk_network_chatter )
+{
+    if ( hal_clk_network_chatter == 0 )
+        diag_printf("Actel System Boot Missing\n Clock network configuration failed!!\n");
+
+    A2FXXX_CLOCK_TRACE("Device clock network configuration:\n");
+    A2FXXX_CLOCK_TRACE("Global Clock A (Systick): %d [Hz]\n",
+                                                  hal_cortexm_systick_clock);
+    A2FXXX_CLOCK_TRACE("PCLK0: %d [Hz]\n", hal_a2fxxx_pclk0);
+    A2FXXX_CLOCK_TRACE("PCLK1: %d [Hz]\n", hal_a2fxxx_pclk1);
+}
+
+
+//==========================================================================
+// Setup device clock network
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+
+static void
+hal_a2fxxx_set_clk_network( void )
+{
+    cyg_uint32 mss_ccc_mux;
+    cyg_uint32 mss_clk_cr;
+    cyg_uint8  ngmux;
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL
+    cyg_bool   pll = false;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA
+    cyg_bool  clka = false;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC
+    cyg_bool  clkc = false;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA
+    cyg_bool  clkga = false;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC
+    cyg_bool  clkgc = false;
+#endif
+
+    // Find out which CLKGx is currently used as FLCK
+    ngmux = hal_a2fxxx_get_ngmux( );
+
+    //
+    // Start by configuring NGMUX. In the following case, if
+    // the current NGMUX output is already CLKGA, first move
+    // to CLKGC to keep a stable ground otherwise go ahead and
+    // configure CLKGA.
+    //
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGA
+    if( ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA )
+    {
+        // Setup CLKGC to use the On-Chip RC oscillator and move
+        // the MSS clock to CLKGC. No division factor is applied
+        // therefore FCLK = 100MHz
+
+        // CLKC = RCOSC
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC );
+
+        // CLKGC = CLKC
+        hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC );
+
+        // FCLK = CLKGC
+        hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC );
+    }
+    else {
+        HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                         CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+        mss_ccc_mux &= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR);
+        mss_ccc_mux = mss_ccc_mux >> 19;
+
+        // Make sure PLL is bypassed.
+        if ( mss_ccc_mux != 1 ){
+            hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC );
+            hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC );
+        }
+    }
+
+    // Now we can configure CLKGA as specified by the
+    // user. Check is PLL should be configured.
+    hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL );
+
+# if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+    hal_a2fxxx_set_pll( );
+    pll = true;
+# endif
+
+    // Move to CLKGA
+    hal_a2fxxx_set_clkgx( CLKx_SRC_CLKGA );
+    clka = clkga = true;
+    hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGA );
+
+#endif  // CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGA
+
+
+    //
+    // In the following case, NGMUX is configured to use CLKGC.
+    // This can be tricky as CLKGC can be routed from CLKGA...
+    //
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGC
+
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                           CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    mss_ccc_mux &= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR);
+    mss_ccc_mux = mss_ccc_mux >> 19;
+
+    // If CLKGC is not routed form CLKC or if CLKGC is not used
+    // as NGMUX output, proceed to configure CLKGC = CLKC
+    if( ((ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC) && (mss_ccc_mux != 1)) ||
+                (ngmux == CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA) )
+    {
+
+        // Set CLKC source, use on-chip oscillator as default
+        // value
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL );
+        clkc = true;
+# else
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKx_SRC_RCOSC );
+# endif
+
+        // Set CLKGC = CLKC
+        hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGC );
+
+        // Set NGMUX = CLKGC
+        hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC );
+
+        // Configure PLL input if in use
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL );
+        clka = true;
+# endif
+
+    }
+    else {
+
+        // Set CLKA source, use on-chip oscillator as default
+        // value
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL );
+        clka = true;
+# else
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKx_SRC_RCOSC );
+# endif
+
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_SRC_CLKC
+        // CLKGA = CLKA
+        hal_a2fxxx_set_clkgx_default( CLKx_SRC_CLKGA );
+
+        // Move NGMUX = CLKGA
+        hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGA );
+
+        // Now we can Configure CLKC
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL );
+# endif
+
+    }
+
+# ifdef CYGHWR_HAL_CORTEXM_A2FXXX_PLL
+    hal_a2fxxx_set_pll( );
+    pll = true;
+# endif
+
+    clkgc = true;
+    hal_a2fxxx_set_clkgx( CLKx_SRC_CLKGC );
+    hal_a2fxxx_set_ngmux( CLKx_SRC_CLKGC );
+
+#endif // CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_CLKGC
+
+
+    // Configure CLKA
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKA
+    if ( clka == false ){
+       hal_a2fxxx_set_clkx( CLKx_SRC_CLKA, CLKA_SRC_SEL );
+    }
+#endif
+
+    // Configure the PLL
+#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+    if ( pll == false ){
+        hal_a2fxxx_set_pll( );
+    }
+#endif
+
+    // Configure CLKB
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKB
+    hal_a2fxxx_set_clkx( CLKx_SRC_CLKB, CLKB_SRC_SEL );
+#endif
+
+    // Configure CLKC
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKC
+    if ( clkc == false ){
+        hal_a2fxxx_set_clkx( CLKx_SRC_CLKC, CLKC_SRC_SEL );
+    }
+#endif
+
+    // Configure CLKGA
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA
+    if ( clkga == false ){
+        hal_a2fxxx_set_clkgx( CLKx_SRC_CLKA );
+    }
+#endif
+
+    // Configure CLKGB
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB
+    hal_a2fxxx_set_clkgx( CLKx_SRC_CLKB );
+#endif
+
+    // Configure CLKGC
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC
+    if ( clkgc == false ){
+        hal_a2fxxx_set_clkgx( CLKx_SRC_CLKC );
+    }
+#endif
+
+    // Now, configure all MSS clock dividers
+    //
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                           CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                           CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR, mss_clk_cr);
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_ACE_CLK
+    mss_clk_cr &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(DIV_CLEAR) );
+    mss_clk_cr |=  ( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_ACLKDIV(ACLKDIV) );
+#endif
+
+    mss_clk_cr &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(DIV_CLEAR) |
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(DIV_CLEAR) );
+
+    mss_clk_cr |=  ( CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK1DIV(PCLK1DIV) |
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_PCLK0DIV(PCLK0DIV) );
+
+    // Record the different clock frequencies
+    hal_cortexm_systick_clock = CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ;
+    hal_a2fxxx_fclk  = CYGHWR_HAL_CORTEXM_A2FXXX_NGMUX_CLKOUT_FREQ;
+    hal_a2fxxx_pclk0 = CYGHWR_HAL_CORTEXM_A2FXXX_PCLK0_FREQ;
+    hal_a2fxxx_pclk1 = CYGHWR_HAL_CORTEXM_A2FXXX_PCLK1_FREQ;
+
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK
+    hal_a2fxxx_pclk_fpga = CYGHWR_HAL_CORTEXM_A2FXXX_FAB_CLK_FREQ;
+#endif
+
+    // Configure the MAC clock
+#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK) && \
+          defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC_CLKGC)
+
+    mss_clk_cr |= CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL;
+
+#elif defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_CLK) && \
+          defined(CYGHWR_HAL_CORTEXM_A2FXXX_MAC_SRC_EXTERNAL)
+
+    mss_clk_cr &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR_RMIICLKSEL;
+
+#endif
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CLK_CR,
+                      mss_clk_cr);
+
+    // PLL is disable if not in used
+#if !defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR, 0x0);
+#endif
+}
+
+
+//==========================================================================
+// Get / Set NGMUX settings
+
+static cyg_uint8
+hal_a2fxxx_get_ngmux( void )
+{
+    cyg_uint32 mss_ccc_mux;
+    cyg_uint8  ngmux_setting;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+
+    mss_ccc_mux = mss_ccc_mux >> 24;
+    switch( mss_ccc_mux & 0xf ){
+    case  0:
+    case  2:
+    case  4:
+    case  6:
+    case 12:
+        ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLA;
+        break;
+    case  1:
+    case  3:
+    case  8:
+    case 10:
+    case 13:
+        ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLC;
+        break;
+    case  5:
+    case  7:
+    case  9:
+    case 11:
+    case 14:
+        ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GLINT;
+        break;
+    default:
+        ngmux_setting = CYGHWR_HAL_A2FXXX_SC_MSS_CCC_GLMUX_GND;
+        break;
+    }
+
+    return ngmux_setting;
+}
+
+
+static void
+hal_a2fxxx_set_ngmux( cyg_uint8 x )
+{
+    cyg_uint32 mss_ccc_mux;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+
+    // Clear bits
+    mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(0x3) |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0x3) );
+
+    if( x == CLKx_SRC_CLKGA ){
+        mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(0) |
+                         CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0) );
+    }
+    else if (x == CLKx_SRC_CLKGC ){
+        mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(1) |
+                         CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(0) );
+    }
+    else{
+        mss_ccc_mux |= ( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXSEL(2) |
+                         CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_GLMUXCFG(3) );
+    }
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+}
+
+
+//==========================================================================
+// Setup PLL
+
+#if defined(CYGHWR_HAL_CORTEXM_A2FXXX_PLL)
+static inline void
+hal_a2fxxx_set_pll( void )
+{
+    cyg_uint32 x =
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FINDIV((CYGHWR_HAL_CORTEXM_A2FXXX_PLL_DIV-1)) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDIV((CYGHWR_HAL_CORTEXM_A2FXXX_PLL_MULT-1)) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBSEL(1) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_FBDLY(CYGHWR_HAL_CORTEXM_A2FXXX_PLL_FB_DELAY) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL0 |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_VCOSEL2_1(PLL_RANGE) |
+    CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR_PLLEN;
+
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_PLL_CR, x);
+
+    // Wait PLL lock
+    do {
+        HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR, x);
+    } while( (x & CYGHWR_HAL_A2FXXX_SC_MSS_CCC_SR_PLL_LOCK_SYNC) == 0);
+}
+#endif
+
+
+//==========================================================================
+// Setup CLKA, CLKB or CLKC input clock
+
+static void
+hal_a2fxxx_set_clkx( cyg_uint8 x, cyg_uint8 src )
+{
+    cyg_uint32 mss_ccc_mux;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    if( x == CLKx_SRC_CLKA ){
+        mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNASEL |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXASEL  |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATASEL );
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKA_SEL (src);
+    }
+    else if (x == CLKx_SRC_CLKB ){
+        mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNBSEL |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXBSEL  |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATBSEL );
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKB_SEL (src);
+    }
+    else{
+        mss_ccc_mux &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_DYNCSEL |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_RXCSEL  |
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_STATCSEL );
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_CLKC_SEL (src);
+    }
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+}
+
+
+//==========================================================================
+// Setup CLKGA, CLKGB or CLKGC output clock
+
+static void
+hal_a2fxxx_set_clkgx( cyg_uint8 x )
+{
+    cyg_uint32 mss_ccc_mux;
+    cyg_uint32 mss_ccc_dly;
+    cyg_uint32 mss_ccc_div;
+    cyg_uint8  div10;
+    cyg_uint8  div;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div);
+
+    if( x == CLKx_SRC_CLKGA ){
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF );
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(DLYX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(OXMUX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA;
+        // Compute divider
+        div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV10;
+        div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DIV;
+        if( div10 % 10 ){
+            div += 1;
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF;
+        }
+        else {
+           div -= 1;
+        }
+        // CLKA = CLGA, bypass MUX
+        if (div == 0 && CLKGA_SRC_SEL == 1) {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA;
+        }
+        else {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(CLKGA_SRC_SEL);
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(div);
+        }
+        mss_ccc_dly |=
+        CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGA_DELAY);
+#endif
+    }
+    if ( x == CLKx_SRC_CLKGB ){
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF );
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(OXMUX_CLEAR);
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(DLYX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB;
+        // Compute divider
+        div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV10;
+        div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DIV;
+        if( div10 % 10 ){
+            div += 1;
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIVHALF;
+        }
+        else {
+           div -= 1;
+        }
+        // CLKB = CLGB, bypass MUX
+        if (div == 0 && CLKGB_SRC_SEL == 1) {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSB;
+        }
+        else {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OBMUX(CLKGB_SRC_SEL);
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OBDIV(div);
+            mss_ccc_dly |=
+            CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYB(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGB_DELAY);
+        }
+#endif
+    }
+    if ( x == CLKx_SRC_CLKGC ){
+#ifdef CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF );
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR);
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(DLYX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC;
+        // Compute divider
+        div10 = CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV10;
+        div = (cyg_uint8) CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DIV;
+        if( div10 % 10 ){
+            div += 1;
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF;
+        }
+        else {
+           div -= 1;
+        }
+        // CLKC = CLGC, bypass MUX
+        if (div == 0 && CLKGC_SRC_SEL == 1) {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC;
+        }
+        else {
+            mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(CLKGC_SRC_SEL);
+            mss_ccc_div |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(div);
+        }
+        mss_ccc_dly |=
+        CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(CYGHWR_HAL_CORTEXM_A2FXXX_CLKGC_DELAY);
+#endif
+    }
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+}
+
+//==========================================================================
+// Setup CLKGA CLKGC output clock
+
+static void
+hal_a2fxxx_set_clkgx_default( cyg_uint8 x )
+{
+    cyg_uint32 mss_ccc_mux;
+    cyg_uint32 mss_ccc_dly;
+    cyg_uint32 mss_ccc_div;
+
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly);
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                     CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div);
+
+    if( x == CLKx_SRC_CLKGA ){
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OADIVHALF );
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(DLYX_CLEAR);
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OAMUX(OXMUX_CLEAR);
+        // CLKGA = CLKA, Division factor = 1 and minimum delay of 535ps
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSA;
+        mss_ccc_dly |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYA(0);
+    }
+    if ( x == CLKx_SRC_CLKGC ){
+        // Clear bits
+        mss_ccc_div &= ~( CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIV(OXDIV_CLEAR) |
+                          CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR_OCDIVHALF );
+        mss_ccc_mux &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_OCMUX(OXMUX_CLEAR);
+        mss_ccc_dly &= ~CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(DLYX_CLEAR);
+        // CLKGC = CLKC, Division factor = 1 and minimum delay of 535ps
+        mss_ccc_mux |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR_BYPASSC;
+        mss_ccc_dly |= CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR_DLYC(0);
+    }
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DIV_CR, mss_ccc_div);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_DLY_CR, mss_ccc_dly);
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                      CYGHWR_HAL_A2FXXX_SC_MSS_CCC_MUX_CR, mss_ccc_mux);
+}
+
+
+//==========================================================================
+// Adjust ENVM timing
+
+static void
+hal_a2fxxx_set_envm_timing( void ) {
+    cyg_uint32 x;
+    HAL_READ_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_ENVM_CR, x);
+    x &= ~CYGHWR_HAL_A2FXXX_SC_ENVM_CR_SIX_CYCLE;
+    if( hal_a2fxxx_fclk <= 80e6 ){
+        x |= CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS;
+    } else {
+        x &= ~CYGHWR_HAL_A2FXXX_SC_ENVM_CR_PIPE_BYPASS;
+    }
+    HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC + CYGHWR_HAL_A2FXXX_SC_ENVM_CR, x);
+}
+
+#endif // CYGHWR_HAL_CORTEXM_A2FXXX_CLOCK
+
+
+//==========================================================================
+// Reset modules
+
+__externC void
+hal_a2fxxx_periph_release( cyg_uint32 bit )
+{
+    cyg_uint32 sc, base = CYGHWR_HAL_A2FXXX_SC;
+    HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR, sc );
+    sc &= ~( bit );
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR, sc );
+}
+
+
+__externC void
+hal_a2fxxx_periph_reset( cyg_uint32 bit )
+{
+    cyg_uint32 sc, base = CYGHWR_HAL_A2FXXX_SC;
+    HAL_READ_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR , sc );
+    sc |= ( bit );
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_SC_CLR_SOFTRST_CR , sc );
+}
+
+
+//==========================================================================
+// GPIO support
+//
+
+const default_io_mux_type default_io_mux[] = {
+   // SPI0
+   {0x00}, {0x0a}, {0x00}, {0x00},
+   // UART0
+   {0x18}, {0x00},
+   // I2C0
+   {0x00}, {0x00},
+   // SPI1
+   {0x00}, {0x0a}, {0x00}, {0x00},
+   // UART1
+   {0x18}, {0x00},
+   // I2C1
+   {0x00}, {0x00},
+   // MAC0
+   {0x18}, {0x18}, {0x0a}, {0x0a}, {0x18}, {0x0a}, {0x0a}, {0x00}, {0x18},
+   // GPIO
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   // SPI0 CS
+   {0x00}, {0x00}, {0x00},
+   // Unused
+   {0x00}, {0x00}, {0x00}, {0x00},
+   // UART0 misc
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   // SPI1 CS
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   // UART1 misc
+   {0x00}, {0x00}, {0x00}, {0x00}, {0x00}, {0x00},
+   {0x0}
+};
+
+// These functions provide configuration and IO for GPIO pins.
+
+__externC void
+hal_a2fxxx_gpio_set( cyg_uint32 pin )
+{
+    cyg_uint32 bit  = CYGHWR_HAL_A2FXXX_GPIO_BIT( pin );
+    cyg_uint32 mode = CYGHWR_HAL_A2FXXX_GPIO_MODE( pin );
+    cyg_uint32 mux  = CYGHWR_HAL_A2FXXX_GPIO_IOMUX_IDX( pin );
+    cyg_uint32 irq  = CYGHWR_HAL_A2FXXX_GPIO_IRQ( pin );
+    cyg_uint32 reg    = 0;
+    cyg_uint32 io_mux = 0;
+
+    if (pin == CYGHWR_HAL_A2FXXX_GPIO_NONE)
+        return;
+
+    if(mode == CYGHWR_HAL_A2FXXX_GPIO_MODE_PERIPH){
+       // Set IOMUX default value for peripheral use
+       io_mux = default_io_mux[mux].val;
+       HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                         CYGHWR_HAL_A2FXXX_SC_IOMUX( mux ), io_mux );
+    } else {
+       // Set GPIO input/ output mode
+       if (mode == CYGHWR_HAL_A2FXXX_GPIO_MODE_OUT) {
+           reg = CYGHWR_HAL_A2FXXX_GPIO_CFG_GPOUTEN |
+                 CYGHWR_HAL_A2FXXX_GPIO_CFG_OUTBUFEN;
+       }
+
+       // Configure IO as interrupt
+       if (irq != CYGHWR_HAL_A2FXXX_GPIO_IRQ_DISABLE) {
+           reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_GPINTEN;
+           if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_FALLING_EDGE)
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(0);
+           else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_RISING_EDGE)
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(1);
+           else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_BOTH_EDGES)
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(2);
+           else if(irq & CYGHWR_HAL_A2FXXX_GPIO_IRQ_LOW_LEVEL)
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(3);
+           else
+              reg |= CYGHWR_HAL_A2FXXX_GPIO_CFG_INTYPE(4);
+       }
+
+       // Write down result
+       HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_MSS_GPIO +
+                       ( CYGHWR_HAL_A2FXXX_MSS_GPIO_CFG( bit ) ), reg );
+
+       // For GPIO 16 to 31, we must setup the IOMUX
+       // TODO, this is for output only?
+       if( bit > 15 ){
+          bit = bit - 16;
+          io_mux = 0x35;
+          HAL_WRITE_UINT32( CYGHWR_HAL_A2FXXX_SC +
+                            CYGHWR_HAL_A2FXXX_SC_IOMUX( bit ), io_mux );
+       }
+
+    }
+}
+
+
+__externC void
+hal_a2fxxx_gpio_out( cyg_uint32 pin, int val )
+{
+    cyg_uint32 bit = ( CYGHWR_HAL_A2FXXX_GPIO_BIT(pin) << 2 );
+    cyg_uint32 port =  CYGHWR_HAL_A2FXXX_MSS_GPIO_BB +
+                     ( CYGHWR_HAL_A2FXXX_MSS_GPIO_DOUT << 5 );
+
+    port += bit;
+
+    HAL_WRITE_UINT32( port, val );
+}
+
+
+__externC void
+hal_a2fxxx_gpio_in ( cyg_uint32 pin, int *val )
+{
+    cyg_uint32 bit = ( CYGHWR_HAL_A2FXXX_GPIO_BIT(pin) << 2 );
+    cyg_uint32 port =  CYGHWR_HAL_A2FXXX_MSS_GPIO_BB +
+                     ( CYGHWR_HAL_A2FXXX_MSS_GPIO_DIN << 5 );
+    cyg_uint32 pd;
+
+    port += bit;
+
+    HAL_READ_UINT32( port, pd );
+    *val = 1 ? (bit & pd) : 0;
+}
+
+
+//==========================================================================
+// I2C clock rate
+//
+__externC cyg_uint32
+hal_a2fxxx_i2c_clock( cyg_uint32 base )
+{
+    return ( (base == CYGHWR_HAL_A2FXXX_I2C0) ? hal_a2fxxx_pclk0 : hal_a2fxxx_pclk1 );
+}
+
+
+//==========================================================================
+// SPI clock rate
+//
+__externC cyg_uint32
+hal_a2fxxx_spi_clock( cyg_uint32 base )
+{
+    return ( (base == CYGHWR_HAL_A2FXXX_SPI0) ? hal_a2fxxx_pclk0 : hal_a2fxxx_pclk1 );
+}
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current APB clock settings.
+
+__externC void
+hal_a2fxxx_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)
+{
+    cyg_uint16 divider =
+         CYG_HAL_CORTEXM_A2FXXX_BAUD_GENERATOR( ((base == CYGHWR_HAL_A2FXXX_UART0)? 0 : 1) , baud );
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LCR,
+                                  CYGHWR_HAL_A2FXXX_UART16550_LCR_DLAB);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_DMR, divider >> 8);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_DLR, divider & 0xFF);
+}
+
+
+//==========================================================================
+// Idle thread
+//
+#ifdef CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION
+__externC void
+hal_idle_thread_action( cyg_uint32 count )
+{
+    while(1);
+}
+#endif
+
+//==========================================================================
+// EOF a2fxxx_misc.c
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/a2fxxx/var/current/src/hal_diag.c
new file mode 100644
index 0000000..5659696
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/src/hal_diag.c
@@ -0,0 +1,399 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2011
+// Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Original:    nickg (STM32 HAL)
+// Date:        2011-04-03
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing
+
+#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+
+#include <cyg/hal/var_io.h>             // USART registers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32          uart;
+    CYG_ADDRESS         base;
+    cyg_int32           msec_timeout;
+    int                 isr_vector;
+    cyg_uint32          rxpin;
+    cyg_uint32          txpin;
+    cyg_uint32          baud_rate;
+    int                 irq_state;
+
+} channel_data_t;
+
+
+static channel_data_t a2fxxx_ser_channels[] = {
+#if CYGINT_HAL_A2FXXX_UART0>0
+    { 0,
+      CYGHWR_HAL_A2FXXX_UART0,
+      1000,
+      CYGNUM_HAL_INTERRUPT_UART0,
+      CYGHWR_HAL_A2FXXX_UART0_RX,
+      CYGHWR_HAL_A2FXXX_UART0_TX,
+      CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGINT_HAL_A2FXXX_UART1>0
+    { 1,
+      CYGHWR_HAL_A2FXXX_UART1,
+      1000,
+      CYGNUM_HAL_INTERRUPT_UART1,
+      CYGHWR_HAL_A2FXXX_UART1_RX,
+      CYGHWR_HAL_A2FXXX_UART1_TX,
+      CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void
+hal_a2fxxx_serial_init_channel(void* __ch_data)
+{
+    channel_data_t *chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS base = chan->base;
+    cyg_uint32 lcr = CYGHWR_HAL_A2FXXX_UART16550_LCR_WLS_8BITS |
+                     CYGHWR_HAL_A2FXXX_UART16550_LCR_STOP_1;
+
+    // Enable the PIO lines for the serial channel
+    CYGHWR_HAL_A2FXXX_GPIO_SET( chan->rxpin );
+    CYGHWR_HAL_A2FXXX_GPIO_SET( chan->txpin );
+
+    // Set baud rate
+    hal_a2fxxx_uart_setbaud( base, chan->baud_rate );
+
+    // 8-1-no parity
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_UART16550_LCR, lcr );
+
+    // Reset and clear TX/RX FIFO
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_A2FXXX_UART16550_FCR,
+                     CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_TX_FIFO |
+                     CYGHWR_HAL_A2FXXX_UART16550_FCR_CLEAR_RX_FIFO );
+
+}
+
+void
+hal_a2fxxx_serial_putc(void *__ch_data, char c)
+{
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint32 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+     do
+     {
+         HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LSR, lsr );
+     } while ((lsr & CYGHWR_HAL_A2FXXX_UART16550_LSR_THRE) == 0);
+
+     HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_THR, c );
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+hal_a2fxxx_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint32 lsr;
+    cyg_uint32 c;
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LSR, lsr );
+
+    if( (lsr & CYGHWR_HAL_A2FXXX_UART16550_LSR_DR) == 0 )
+        return false;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_RBR, c );
+
+    *ch = (cyg_uint8)c;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return true;
+}
+
+cyg_uint8
+hal_a2fxxx_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!hal_a2fxxx_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+hal_a2fxxx_serial_write(void* __ch_data, const cyg_uint8* __buf,
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        hal_a2fxxx_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+hal_a2fxxx_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = hal_a2fxxx_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+hal_a2fxxx_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 100; // delay in 10 us steps
+
+    for(;;) {
+        res = hal_a2fxxx_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(10);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+hal_a2fxxx_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    int ret = 0;
+    cyg_uint32 ier;
+
+    va_list ap;
+
+    CYGARC_HAL_SAVE_GP();
+
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE( chan->isr_vector );
+        HAL_INTERRUPT_UNMASK( chan->isr_vector );
+        HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier );
+        ier |= CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier );
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK( chan->isr_vector );
+        HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier );
+        ier &= ~CYGHWR_HAL_A2FXXX_UART16550_IER_ERBFI;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_IER, ier );
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+
+        va_start(ap, __func);
+
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        hal_a2fxxx_uart_setbaud( base, chan->baud_rate );
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+hal_a2fxxx_serial_isr(void *__ch_data, int* __ctrlc,
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8 ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+     *__ctrlc = 0;
+
+     if( hal_a2fxxx_serial_getc_nonblock(__ch_data, &ch) )
+     {
+         if( cyg_hal_is_break( (char *)&ch , 1 ) )
+             *__ctrlc = 1;
+     }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+    return 1;
+}
+
+static void
+hal_a2fxxx_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur;
+    int i;
+
+    cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    for( i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS ; i++ )
+    {
+        hal_a2fxxx_serial_init_channel(&a2fxxx_ser_channels[i]);
+
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &a2fxxx_ser_channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, hal_a2fxxx_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, hal_a2fxxx_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, hal_a2fxxx_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, hal_a2fxxx_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, hal_a2fxxx_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_a2fxxx_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_a2fxxx_serial_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+
+    // set debug channel baud rate if different
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate( &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] );
+#endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    hal_a2fxxx_serial_init();
+}
+
+#endif
+
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void
+hal_a2fxxx_diag_init(void)
+{
+    hal_a2fxxx_serial_init(
+            &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+void
+hal_a2fxxx_diag_putc(char c)
+{
+    hal_a2fxxx_serial_putc(
+            &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8
+hal_a2fxxx_diag_getc(void)
+{
+    return hal_a2fxxx_serial_getc(
+            &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+
+#endif
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c b/ecos/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c
new file mode 100644
index 0000000..8d360a0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c
@@ -0,0 +1,427 @@
+/*==========================================================================
+//
+//      hal_dma.c
+//
+//      Cortex-M Actel A2F DMA channels configuration
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors:
+// Date:         2011-02-03
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_a2fxxx.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+#include <cyg/hal/drv_api.h>
+
+#ifdef CYGDBG_HAL_CORTEXM_A2FXXX_DMA_TRACE
+# define DMA_TRACE(args...) diag_printf(args)
+#else
+# define DMA_TRACE(args...)
+#endif
+
+//-----------------------------------------------------------------------------
+// DMA channel ISR/DSR handling
+
+typedef struct a2fxxx_dma_ch {
+    cyg_ISR_t*      isr;
+    cyg_DSR_t*      dsr;
+    cyg_uint32      isr_ret;
+    cyg_addrword_t  data;
+} a2fxxx_dma_ch;
+
+typedef struct a2fxxx_dma_info {
+    cyg_uint32      init;
+    cyg_uint32      base;
+    cyg_handle_t    interrupt_handle;
+    cyg_interrupt   interrupt_data;
+    a2fxxx_dma_ch   ch[CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL];
+    cyg_uint32      dma_cr[CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL];
+    cyg_uint32      dma_sr;
+} a2fxxx_dma_info;
+
+static a2fxxx_dma_info a2fxxx_dma = {
+    .base = CYGHWR_HAL_A2FXXX_DMA,
+    .init =0,
+};
+
+
+//-----------------------------------------------------------------------------
+// DMA ISR handler
+
+static cyg_uint32
+a2fxxx_dma_isr (cyg_vector_t vector, cyg_addrword_t data)
+{
+    a2fxxx_dma_info *dma = (a2fxxx_dma_info *) data;
+    cyg_uint32 sr = 0;
+    cyg_uint8 i = 0, j = 0;
+
+    HAL_READ_UINT32(dma->base + CYGHWR_HAL_A2FXXX_DMA_BUFFER_STATUS, sr);
+    dma->dma_sr |= sr;
+
+    DMA_TRACE("DMA interrupt, sr 0x%x\n", dma->dma_sr);
+
+    while(i < 16){
+        if( sr & 0x1 ){
+            j = i >> 1;
+            if(dma->ch[j].isr != NULL){
+              dma->ch[j].isr_ret = dma->ch[j].isr(i, dma->ch[j].data);
+            }
+        }
+        sr = sr >> 1; i++;
+    }
+    cyg_drv_interrupt_acknowledge (CYGNUM_HAL_INTERRUPT_DMA);
+    cyg_drv_interrupt_mask (CYGNUM_HAL_INTERRUPT_DMA);
+    return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
+}
+
+
+//-----------------------------------------------------------------------------
+// DMA DSR handler
+
+static void
+a2fxxx_dma_dsr (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
+{
+    a2fxxx_dma_info *dma = (a2fxxx_dma_info *) data;
+    cyg_uint8 i = 0, j = 0;
+    cyg_uint32 sr;
+
+    cyg_drv_isr_lock ();
+    sr = dma->dma_sr;
+    dma->dma_sr = 0;
+    cyg_drv_isr_unlock ();
+
+    while(i < 16){
+        if( sr & 0x1 ){
+            j = i >> 1;
+            if( (dma->ch[j].dsr != NULL) &&
+                           (dma->ch[j].isr_ret & CYG_ISR_CALL_DSR) ){
+                dma->ch[j].dsr(i, 0, dma->ch[j].data);
+            }
+        }
+        sr = sr >> 1; i++;
+    }
+
+    cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_DMA);
+}
+
+
+//-----------------------------------------------------------------------------
+// DMA Initialization
+
+void
+hal_dma_init( void )
+{
+    cyg_uint8 i = 0;
+
+    // Avoid multiple initialization
+    if(a2fxxx_dma.init)
+        return;
+
+    a2fxxx_dma.init = 1;
+
+    // Reset DMA
+    CYGHWR_HAL_A2FXXX_PERIPH_RESET( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(PDMA) );
+
+    // Clear channel ISR / DSR
+    while( i < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL ) {
+        a2fxxx_dma.ch[i].isr    = NULL;
+        a2fxxx_dma.ch[i].dsr    = NULL;
+        a2fxxx_dma.dma_cr[i]    = 0;
+        a2fxxx_dma.ch[i++].data = 0;
+    }
+    a2fxxx_dma.dma_sr = 0;
+
+    // Register DMA interrupt
+    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_DMA,
+                           CYGNUM_HAL_CORTEXM_A2FXXX_DMA_ISR_PRIORITY,
+                           (cyg_addrword_t)&a2fxxx_dma,
+                           &a2fxxx_dma_isr,
+                           &a2fxxx_dma_dsr,
+                           &(a2fxxx_dma.interrupt_handle),
+                           &(a2fxxx_dma.interrupt_data));
+    cyg_drv_interrupt_attach(a2fxxx_dma.interrupt_handle);
+    cyg_drv_interrupt_acknowledge (CYGNUM_HAL_INTERRUPT_DMA);
+    cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_DMA);
+
+    // Release DMA
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(PDMA) );
+
+    // HW initialization
+    i=0;
+    while( i < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL ) {
+        HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(i++),
+                         CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_RESET);
+    }
+}
+
+
+//-----------------------------------------------------------------------------
+// Register the DMA sub-channel ISR / DSR
+
+__externC cyg_uint32
+a2fxxx_dma_ch_attach(cyg_uint8 ch, cyg_ISR_t *isr, cyg_DSR_t *dsr,
+                     cyg_addrword_t data)
+{
+    cyg_uint32 res = 1;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                         "DMA : Channel number out of range (Attach).");
+
+#ifdef CYGPKG_KERNEL
+    cyg_interrupt_disable();
+#endif
+    if( a2fxxx_dma.ch[ch].isr != NULL ||
+        a2fxxx_dma.ch[ch].dsr != NULL || a2fxxx_dma.ch[ch].data != 0 ) {
+        res = 0;
+    } else {
+        a2fxxx_dma.ch[ch].isr  = isr;
+        a2fxxx_dma.ch[ch].dsr  = dsr;
+        a2fxxx_dma.ch[ch].data = data;
+    }
+#ifdef CYGPKG_KERNEL
+    cyg_interrupt_enable();
+#endif
+
+    return res;
+}
+
+
+//-----------------------------------------------------------------------------
+// Update DMA source / destination address increment
+
+__externC void
+a2fxxx_dma_update_incr(cyg_uint8 ch, cyg_bool dst, cyg_uint8 incr)
+{
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                          "DMA : Channel number out of range (Update).");
+
+    if(dst==false){
+        // Clear bits
+        a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR_4B;
+        a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_SRC_INCR(incr);
+    }
+    else {
+        // Clear bits
+        a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR_4B;
+        a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DST_INCR(incr);
+    }
+}
+
+
+//-----------------------------------------------------------------------------
+// Setup DMA channel
+//
+// channel      select the DMA channel ID.
+// type         select the transfer type to be performed. For valid
+//              values, check CYGHWR_HAL_A2FXXX_DMA_XFER(_x) in var_io.h.
+// outbound     set to true for transfer out of memory, false for transfer to
+//              memory
+// src_incr     select the memory address increment step for the source. Valid
+//              values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA
+//              transfer from peripheral FIFO for instance.
+// dst_incr     select the memory address increment step for the destination.
+//              Valid values are 0, 1, 2 and 4 byte(s). 0 can be used for DMA
+//              transfer to peripheral FIFO for instance.
+// pri          select the DMA channel priority (true = high , false = low)
+// wr_adj       indicates the number of FCLK periods which the PDMA must wait
+//              after completion of a read or write access to a peripheral before
+//              evaluating the out-of-band status signals from that peripheral
+//              for another transfer
+
+__externC cyg_uint32
+a2fxxx_dma_ch_setup(cyg_uint8 ch, cyg_uint8 type, cyg_bool outbound,
+      cyg_uint8 src_incr, cyg_uint8 dst_incr, cyg_bool pri, cyg_uint8 wr_adj)
+{
+    cyg_uint32 res = 1;
+    cyg_uint32 xfer_type = 0, xfer_dir = 0, xfer_incr =
+                                    CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_XFER_BYTE;
+    a2fxxx_dma.dma_cr[ch] = 0;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                               "DMA : Channel number out of range (Setup).");
+
+    DMA_TRACE("DMA setup channel %d, direction: %s, type %x, step %d-%d byte(s)\n", ch ,
+             ((outbound==true) ? "outbound" : "inbound"), type, src_incr, dst_incr );
+
+    if( type != CYGHWR_HAL_A2FXXX_DMA_XFER_MEMORY ){
+        xfer_type = CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH_SEL(type) |
+                CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_PERIPH;
+    }
+
+    if( outbound == true ){
+        xfer_dir = CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_DIR;
+    }
+
+    a2fxxx_dma_update_incr(ch, true, dst_incr);
+    a2fxxx_dma_update_incr(ch, false, src_incr);
+
+    a2fxxx_dma.dma_cr[ch] |= ( xfer_type | xfer_dir |
+          ((pri == true) ? CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_HI_PRI : 0) |
+          CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA |
+          CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB |
+          CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_WR_ADJ(wr_adj) |
+          xfer_incr);
+
+    HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch),
+                                    a2fxxx_dma.dma_cr[ch]);
+
+    return res;
+}
+
+
+//-----------------------------------------------------------------------------
+// Remove DMA channel handler
+
+__externC void
+a2fxxx_dma_ch_detach (cyg_uint8 ch)
+{
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                              "DMA : Channel number out of range (Detach).");
+
+#ifdef CYGPKG_KERNEL
+    cyg_interrupt_disable();
+#endif
+    a2fxxx_dma.ch[ch].isr  = NULL;
+    a2fxxx_dma.ch[ch].dsr  = NULL;
+    a2fxxx_dma.ch[ch].data = 0;
+#ifdef CYGPKG_KERNEL
+    cyg_interrupt_enable();
+#endif
+}
+
+
+//-----------------------------------------------------------------------------
+// Start DMA transfer
+
+__externC cyg_uint32
+a2fxxx_dma_xfer (cyg_uint8 ch, cyg_bool polled, cyg_uint32 len, cyg_uint8 *src,
+                     cyg_uint8 *dst)
+{
+    cyg_uint32 res = 1;
+    cyg_uint32 src_reg, dst_reg, cnt_reg;
+    cyg_uint32 sub = 0;
+    cyg_haladdress dma_src = (cyg_haladdress) src;
+    cyg_haladdress dma_dst = (cyg_haladdress) dst;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                           "DMA : Channel number out of range (Transfer).");
+
+    if( polled == true )
+        a2fxxx_dma.dma_cr[ch] &= ~CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN;
+    else
+        a2fxxx_dma.dma_cr[ch] |= CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_INTEN;
+
+    HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch),
+                                 a2fxxx_dma.dma_cr[ch]);
+
+    HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(ch), sub);
+    sub = CYGHWR_HAL_A2FXXX_DMA_GET_SUB_ID( sub );
+
+    src_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_SRC(ch) :
+                            CYGHWR_HAL_A2FXXX_DMA_CHx_BB_SRC(ch));
+    dst_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_DST(ch) :
+                            CYGHWR_HAL_A2FXXX_DMA_CHx_BB_DST(ch));
+    cnt_reg = ((sub == 0) ? CYGHWR_HAL_A2FXXX_DMA_CHx_BA_COUNT(ch) :
+                            CYGHWR_HAL_A2FXXX_DMA_CHx_BB_COUNT(ch));
+
+    DMA_TRACE("DMA transfer of length %d on channel %d(%s) - SRC: 0x%x / DST: 0x%x\n",
+                          len, ch, ((sub==0) ? "A" : "B"), dma_src, dma_dst);
+    DMA_TRACE("DMA register address 0x%x / 0x%x\n", src_reg , dst_reg);
+
+    HAL_WRITE_UINT32(a2fxxx_dma.base + src_reg, dma_src);
+    HAL_WRITE_UINT32(a2fxxx_dma.base + dst_reg, dma_dst);
+    HAL_WRITE_UINT32(a2fxxx_dma.base + cnt_reg, len);
+
+    return res;
+}
+
+
+//-----------------------------------------------------------------------------
+// Clear DMA interrupt
+
+void a2fxxx_dma_clear_interrupt (cyg_uint8 ch)
+{
+    cyg_uint32 reg;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                           "DMA : Channel number out of range (Clear IRQ).");
+
+    DMA_TRACE("DMA status register 0x%x\n",
+                     (a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch)));
+
+    HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch), reg);
+    reg |= (CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPA |
+            CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL_CLR_COMPB);
+    HAL_WRITE_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_CTRL(ch), reg);
+}
+
+
+//-----------------------------------------------------------------------------
+// Clear DMA interrupt
+
+cyg_uint8 a2fxxx_dma_get_comp_flag (cyg_uint8 ch)
+{
+    cyg_uint32 reg;
+
+    CYG_ASSERT (ch < CYGHWR_HAL_A2FXXX_DMA_MAX_CHANNEL,
+                                  "DMA : Channel number out of range (Get).");
+
+    HAL_READ_UINT32(a2fxxx_dma.base + CYGHWR_HAL_A2FXXX_DMA_CHx_STATUS(ch), reg);
+
+    return (reg&0x3);
+}
+
+//-----------------------------------------------------------------------------
+// End of hal_dma.c
diff --git a/ecos/packages/hal/cortexm/a2fxxx/var/current/tests/timers.c b/ecos/packages/hal/cortexm/a2fxxx/var/current/tests/timers.c
new file mode 100644
index 0000000..a82ca52
--- /dev/null
+++ b/ecos/packages/hal/cortexm/a2fxxx/var/current/tests/timers.c
@@ -0,0 +1,336 @@
+/*=============================================================================
+//
+//      timers.c
+//
+//      Test for Cortex-M3 Actel Smartfusion Timers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg for STM32
+//               ccoutand updated for Cortex-M3 Actel Smartfusion Devices
+// Date:         2011-03-06
+//              
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#if defined(CYGPKG_KERNEL)
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/testcase.h>
+
+//=============================================================================
+// Check all required packages and components are present
+
+#if !defined(CYGPKG_KERNEL) || !defined(CYGPKG_KERNEL_API)
+
+#define NA_MSG  "Configuration insufficient"
+
+#endif
+
+//=============================================================================
+// If everything is present, compile the full test.
+
+#ifndef NA_MSG
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+
+#include <cyg/kernel/kapi.h>
+#include <cyg/infra/diag.h>
+#include <string.h>
+
+//=============================================================================
+
+#define LOOPS      24           // == 2 minutes
+
+#define STACK_SIZE 8000
+
+static int test_stack[(STACK_SIZE/sizeof(int))];
+static cyg_thread test_thread;
+static cyg_handle_t main_thread;
+
+//=============================================================================
+
+struct timer
+{
+    cyg_uint32          timer;
+    cyg_uint32          base;
+    cyg_uint32          vector;
+    cyg_uint32          priority;
+    cyg_uint32          interval;
+
+    cyg_uint32          ticks;
+
+    cyg_uint32          preempt[10];
+
+    cyg_uint32          preempt_dsr[10];
+    cyg_uint32          dsr_count[10];
+
+    cyg_interrupt       interrupt_object;
+    cyg_handle_t        interrupt_handle;
+};
+
+struct timer timers[] =
+{
+    { 1, CYGHWR_HAL_A2FXXX_TIMER1, CYGNUM_HAL_INTERRUPT_TIM0_1, 0x20,     127 },
+    { 2, CYGHWR_HAL_A2FXXX_TIMER2, CYGNUM_HAL_INTERRUPT_TIM0_2, 0x30,     355 },
+    { 0, 0, 0, 0 }
+};
+
+//=============================================================================
+
+volatile cyg_uint32 ticks = 0;
+volatile cyg_uint32 nesting = 0;
+volatile cyg_uint32 max_nesting = 0;
+volatile cyg_uint32 max_nesting_seen = 0;
+volatile cyg_uint32 current = 0;
+volatile cyg_uint32 in_dsr = 0;
+
+//=============================================================================
+
+__externC cyg_uint32 hal_a2fxxx_pclk0;
+
+void init_timer( cyg_uint32 base, cyg_uint32 interval )
+{
+    cyg_uint32 period = hal_a2fxxx_pclk0;
+
+    period = period / 1000000;
+    period = period * interval;
+
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_BGLOADVAL, period-1 );
+
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL, \
+            CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_EN | CYGHWR_HAL_A2FXXX_TIMER_TIMx_CTRL_INTEN);
+}
+
+//=============================================================================
+
+cyg_uint32 timer_isr( cyg_uint32 vector, CYG_ADDRWORD data )
+{
+    struct timer *t = (struct timer *)data;
+    cyg_uint32 preempt = current;
+    CYG_ADDRWORD base = t->base;
+    cyg_uint32 cnt;
+
+    current = t->timer;
+    t->ticks++;
+    ticks++;
+    t->preempt[preempt]++;
+    nesting++;
+
+    // Count only first ISR to preempt a DSR
+    if( preempt == 0 )
+        t->preempt_dsr[in_dsr]++;
+
+    HAL_WRITE_UINT32(t->base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_RIS, 1 );
+
+    if( nesting > max_nesting )
+        max_nesting = nesting;
+
+    // Loiter here for a proportion of the timer interval to give
+    // other timers the chance to preempt us.
+    do
+    {
+        HAL_READ_UINT32( base+CYGHWR_HAL_A2FXXX_TIMER_TIMx_VAL, cnt );
+    } while( cnt < t->interval/10 );
+
+    nesting--;
+    current = preempt;
+
+    if( (t->ticks % 10) == 0 )
+        return 3;
+    else
+        return 1;
+}
+
+//=============================================================================
+
+void timer_dsr( cyg_uint32 vector, cyg_uint32 count, CYG_ADDRWORD data )
+{
+    struct timer *t = (struct timer *)data;
+    int i;
+
+    in_dsr = t->timer;
+
+    if( count >= 8 )
+        count = 8;
+
+    t->dsr_count[count]++;
+
+    // Loiter for a while
+    for( i = 0; i < t->interval/10; i++)
+        continue;
+
+    in_dsr = 0;
+}
+
+//=============================================================================
+
+void
+timers_test(cyg_addrword_t data)
+{
+    int loops = LOOPS;
+    int i;
+    CYG_INTERRUPT_STATE istate;
+
+    CYG_TEST_INIT();
+
+    CYG_TEST_INFO("Start Timers test");
+
+    CYGHWR_HAL_A2FXXX_PERIPH_RELEASE( CYGHWR_HAL_A2FXXX_PERIPH_SOFTRST(TIMER) );
+
+    for( i = 0; timers[i].timer != 0; i++ )
+    {
+        struct timer *t = &timers[i];
+
+        init_timer( t->base, t->interval );
+
+        cyg_interrupt_create( t->vector,
+                              t->priority,
+                              (cyg_addrword_t)t,
+                              timer_isr,
+                              timer_dsr,
+                              &t->interrupt_handle,
+                              &t->interrupt_object
+            );
+
+        cyg_interrupt_attach( t->interrupt_handle );
+        cyg_interrupt_unmask( t->vector );
+
+    }
+
+    while( loops-- )
+    {
+        int j;
+
+        // 5 second delay
+        cyg_thread_delay( 5*100 );
+
+        // Disable interrupts while we print details, otherwise it
+        // comes out very slowly.
+        HAL_DISABLE_INTERRUPTS( istate );
+
+        if( max_nesting > max_nesting_seen )
+            max_nesting_seen = max_nesting;
+
+        diag_printf("\nISRs max_nesting %d max_nesting_seen %d\n", max_nesting, max_nesting_seen );
+        max_nesting = 0;
+
+        diag_printf(" T      Ticks ");
+
+        for( j = 0; j < 9; j++ )
+            diag_printf("%9d ", j );
+        diag_printf("\n");
+
+        for( i = 0; timers[i].timer != 0; i++ )
+        {
+            struct timer *t = &timers[i];
+
+            diag_printf("%2d: %9d ", t->timer, t->ticks );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->preempt[j] );
+            diag_printf("\n");
+
+        }
+
+        diag_printf("DSRs\n");
+
+        diag_printf(" T:           ");
+
+        for( j = 0; j < 9; j++ )
+            diag_printf("%9d ", j );
+        diag_printf("\n");
+
+        for( i = 0; timers[i].timer != 0; i++ )
+        {
+            struct timer *t = &timers[i];
+
+            diag_printf("%2d:  preempt: ", t->timer);
+
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->preempt_dsr[j] );
+            diag_printf("\n");
+
+            diag_printf("       count: ");
+
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->dsr_count[j] );
+            diag_printf("\n");
+        }
+
+        HAL_RESTORE_INTERRUPTS( istate );
+    }
+
+    CYG_TEST_PASS_FINISH("Timers test");
+}
+
+//=============================================================================
+
+void cyg_user_start(void)
+{
+    cyg_thread_create(0,                // Priority
+                      timers_test,
+                      0,
+                      "timers test",    // Name
+                      test_stack,       // Stack
+                      STACK_SIZE,       // Size
+                      &main_thread,     // Handle
+                      &test_thread // Thread data structure
+        );
+    cyg_thread_resume( main_thread);
+}
+
+//=============================================================================
+// Print a message if we cannot run
+
+#else // NA_MSG
+
+void cyg_user_start(void)
+{
+    CYG_TEST_NA(NA_MSG);
+}
+
+#endif // NA_MSG
+
+//=============================================================================
+/* EOF timers.c */
diff --git a/ecos/packages/hal/cortexm/arch/current/ChangeLog b/ecos/packages/hal/cortexm/arch/current/ChangeLog
new file mode 100644
index 0000000..7aee9ff
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/ChangeLog
@@ -0,0 +1,214 @@
+2014-02-28  John Dallaway  <john@dallaway.org.uk>
+
+	* src/mcount.S: Add mcount functions for call-graph profiling.
+	* cdl/hal_cortexm.cdl: Add option to build mcount functions.
+	[ Bugzilla 1001954 ]
+
+2013-08-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_fpu.cdl, include/fpv4_sp_d16_libm.h: Define Cortex-M4F
+	architecture specific builtin mathematical functions.  [ Bugzilla 1001539 ]
+
+2013-04-29  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/cortexm_stub.h: Remove unwanted diag_printf().
+
+2013-02-10  Ilija Kocho  <ilijak@siva.com.mk>
+            Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm.cdl:
+	* cdl/hal_cortexm_fpu.cdl:   New
+	* include/cortexm_core.h:    New
+	* include/cortexm_fpu.h:     New
+	* include/cortexm_regs.h:
+	* include/cortexm_stub.h:
+	* include/fpv4_sp_d16.h:     New
+	* include/hal_arch.h:
+	* include/hal_arch.inc:      New
+	* include/hal_io.h:
+	* src/context.S:
+	* src/cortexm_fpu.c:         New
+	* src/cortexm_stub.c:
+	* src/fpv4_sp_d16.c:         New
+	* src/hal_misc.c:
+	* src/vectors.S:
+	Add: hardware floating point support for Cortex-M4F [ Bugzilla 1001607 ]
+
+2012-04-23  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * cdl/hal_cortexm.cdl:
+    * include/basetype.h:
+    * include/cortexm_stub.h:
+    * include/hal_arch.h:
+    * include/hal_intr.h:
+    * include/hal_io.h:
+    * src/context.S:
+    * src/cortexm_stub.c:
+    * src/hal_misc.c:
+    * src/vectors.S:
+    Whitespace cleanup [Bugzilla 1001569]
+
+2012-03-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * include/hal_intr.h: Fix compiler warning about unused variables.
+    [Bugzilla 1001520]
+
+2012-02-05  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/hal_misc.c (hal_reset_vsr): Ensure we only init intr vectors
+	up to top of VSR table.
+
+2011-08-23  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm.cdl: New CDL option CYGIMP_HAL_ARCH_ENDIAN
+	* include/cortexm_endian.h: New file
+	* include/cortexm_regs.h: New file
+	[ Bugzilla 1001275 ]
+
+2011-04-06  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/cortexm.cdl: Remove M1 CPU family from architecture config
+	file (as not supported for now). [Bugzilla 1001186]
+
+2011-04-02  Ilija Kocho  <ilijak@siva.com.mk>
+	* cdl/cortexm.cdl: Add M4 CPU family to CYGHWR_HAL_CORTEXM. Add
+	FPU (Floating Point Unit) interface.
+	* include/hal_io.h: Add CYGHWR_HAL_CORTEXM_M4 to some preprocessor
+	conditions. [Bugzilla 1001186]
+
+2011-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/hal_intr.h: Remove double inclusion of var_intr.h
+	header and include it at proper place. [ Bugzilla 1001184 ]
+
+2011-02-17  John Dallaway  <john@dallaway.org.uk>
+
+	* include/hal_intr.h (HAL_DISABLE_INTERRUPTS): Mark operand as
+	an earlyclobber operand to ensure correct register usage. Issue
+	reported by both Ulrich Holeschak and Stanislav Meduna.
+	[ Bugzilla 1001154 ]
+
+2011-02-16  Ilija Kocho <ilijak@siva.com.mk>
+
+	* src/cortexm.ld: Added USER_SECTION() macro. [Bugzilla 1001142 ]
+
+2011-01-20  Christophe Coutand  <ccoutand@stmi.com>
+
+	* include/hal_intr.h:
+	* cdl/hal_cortexm.cdl:
+	Allow variant or platform to define their own RTC clock. Add
+	CDL entry to select SysTick clock source. [ Bugzilla 1001090 ]
+
+2010-12-28  Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/hal_io.h: conditional VTOR setting.
+
+2011-01-13  John Dallaway  <john@dallaway.org.uk>
+
+	* src/vectors.S (hal_default_interrupt_vsr): Save interrupt state
+	if CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED is implemented.
+	[ Bugzilla 1001111 ]
+
+2011-01-02  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/hal_cortexm.cdl: Eliminate some warnings. [ Bugzilla
+	1001083 ]
+
+2010-05-17  Spencer Oliver <spen@spen-soft.co.uk>
+
+	* include/hal_intr.h (HAL_INTERRUPT_STACK_CALL_PENDING_DSRS):
+	* src/hal_misc.c (hal_reset_vsr): Add 0 argument to SWI.
+
+	* src/vectors.S (hal_switch_state_vsr): Eliminate "msr psp,sp",
+	which is now deprecated.
+	(hal_pendable_svc_vsr): Add 0 argument to SWI.
+
+2009-02-27  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* include/hal_io.h: Added system control register definitions 
+
+2009-02-13  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/hal_arch.h: Add include for var_arch.h.
+	(HAL_IDLE_THREAD_ACTION): Tidy up debug code left in by mistake.
+
+2009-02-07  Chris Holgate  <chris@zynaptic.com>
+
+	* src/hal_misc.c:
+	* src/cortexm.ld: 
+	Modified SRAM linker section to support initialisation from ROM.
+
+2008-12-03  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/hal_misc.c (hal_deliver_interrupt): Fix instrumentation call
+	to allow it to compile properly.
+
+2008-11-24  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* include/hal_io.c: Fixed MASK_ macro.
+
+2008-11-04  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* include/hal_intr.h:
+	Fixed load value of SysTick counter.
+	* src/hal_misc.c:
+	Fixed wrap-around in hal_delay_us().
+
+2008-11-04  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* include/hal_intr.h:
+	Fixed base address in reset function.
+
+2008-10-16  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/vectors.S: 
+	* src/hal_misc.c: Tidy some comments and code.
+
+2008-10-10  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/hal_misc.c (hal_deliver_interrupt): Add support for chained
+	interrupts.
+	(hal_interrupt_end): Only increment scheduler lock when the kernel
+	is present.
+
+	* include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Add end-stop to
+	new thread states to terminate GDB backtraces.
+
+2008-10-06  Nick Garnett  <nickg@ecoscentric.com>
+
+	* hal_cortexm.cdl:
+	* include/basetype.h:
+	* include/hal_arch.h:
+	* include/hal_intr.h:
+	* include/hal_io.h:
+	* include/cortex_stub.h:
+	* src/vectors.S:
+	* src/context.S:
+	* src/cortexm.ld:
+	* src/cortexm_stub.c:
+	* src/hal_misc.c:
+	New package -- Cortex-M architecture HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011, 2014 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl b/ecos/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
new file mode 100644
index 0000000..cab81bc
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/cdl/hal_cortexm.cdl
@@ -0,0 +1,275 @@
+##==========================================================================
+##
+##      hal_cortexm.cdl
+##
+##      Cortex-M architectural HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2008, 2011, 2014 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):       nickg
+## Contributor(s):  jld
+## Date:            2008-07-30
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM {
+    display       "Cortex-M Architecture"
+    parent        CYGPKG_HAL
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm.h
+    description   "
+        This package provides generic support for the ARM Cortex-M architecture.
+        It is also necessary to select a variant and platform HAL package."
+
+    implements    CYGINT_PROFILE_HAL_MCOUNT
+
+    compile       hal_misc.c context.S cortexm_stub.c
+
+    requires { CYGHWR_HAL_CORTEXM_BIGENDIAN implies
+        is_substr(CYGBLD_GLOBAL_CFLAGS,   " -mbig-endian ") &&
+        is_substr(CYGBLD_GLOBAL_LDFLAGS,  " -mbig-endian ") }
+    requires { !CYGHWR_HAL_CORTEXM_BIGENDIAN implies
+        !is_substr(CYGBLD_GLOBAL_CFLAGS,  " -mbig-endian ") &&
+        !is_substr(CYGBLD_GLOBAL_LDFLAGS, " -mbig-endian ") }
+
+    make {
+        <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S
+        $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
+        @echo $@ ": \\" > $(notdir $@).deps
+        @tail -n +2 vectors.tmp >> $(notdir $@).deps
+        @echo >> $(notdir $@).deps
+        @rm vectors.tmp
+    }
+
+    make {
+        <PREFIX>/lib/target.ld: <PACKAGE>/src/cortexm.ld
+        $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<
+        @echo $@ ": \\" > $(notdir $@).deps
+        @tail -n +2 target.tmp >> $(notdir $@).deps
+        @echo >> $(notdir $@).deps
+        @rm target.tmp
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_BIGENDIAN {
+        display "The platform and architecture supports Big Endian operation"
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_BIGENDIAN {
+        display          "Use big-endian mode"
+        active_if        { CYGINT_HAL_CORTEXM_BIGENDIAN != 0 }
+        default_value    0
+        description      "
+            Use the CPU in big-endian mode."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM {
+        display          "Cortex-M CPU family"
+        flavor           data
+        legal_values     { "M3" "M4" }
+        default_value    { "M3" }
+        description      "
+            The Cortex-M architecture has two variants at present. The
+            M3 and M4 are based on the ARMV7 architecture specification
+            and execute the Thumb2 instruction set. The M4 in addition
+            to M3 instruction set has SIMD and optional single precision
+            floating point instructions."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE {
+        display          "System tick timer clock"
+        flavor           data
+        legal_values     { "EXTERNAL" "INTERNAL" }
+        default_value    { "EXTERNAL" }
+        description      "Select the Cortex-M system tick timer clock source."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_FPU {
+        display        "Floating Point Support"
+        flavor         data
+        calculated     { !CYGHWR_HAL_CORTEXM_FPU ? "SOFT" :
+                          "HARD: " . CYGHWR_HAL_CORTEXM_FPU_SWITCH }
+        no_define
+        active_if      { CYGHWR_HAL_CORTEXM == "M4" }
+        description    "
+            Floating point arithmetics can be executed in software or,
+            on devices with floating point unit - FPU, in hardware.
+            FPU is optional on Cortex-M4 architecture, and is present
+            on Cortex-M4F cores."
+
+        script         hal_cortexm_fpu.cdl
+    }
+
+    cdl_option CYGIMP_HAL_ARCH_ENDIAN {
+        display       "Architecture optimized endian functions"
+        flavor        bool
+        default_value 1
+        description   "
+            Cortex-M architecture implements instructions for endian
+            manipulation (byte swapping).  If enabled, this feature
+            can produce shorter and faster code for that."
+
+        define_proc {
+            puts $::cdl_system_header "#define CYGBLD_HAL_ENDIAN_H <cyg/hal/cortexm_endian.h>"
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_MAX {
+         display         "Maximum usable priority"
+         flavor          data
+         calculated      1<<(8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
+         description     "
+             Calculate the maximum exception priority that can be set by interrupts.
+             Higher priorities are reserved for the DEBUG and SVC traps."
+    }
+
+    cdl_option CYGBLD_HAL_CORTEXM_MCOUNT {
+        display           "Support call-graph profiling"
+        flavor            bool
+        no_define
+        active_if         CYGPKG_PROFILE_GPROF
+        calculated        CYGPKG_PROFILE_CALLGRAPH
+        compile           mcount.S
+        description       "
+            Calculate whether mcount functions should be built
+            to support call-graph profiling."
+    }
+
+    cdl_option CYGBLD_LINKER_SCRIPT {
+        display "Linker script"
+        flavor data
+        no_define
+        calculated  { "src/cortexm.ld" }
+    }
+
+    cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {
+            display       "Number of breakpoints supported by the HAL."
+            flavor        data
+            default_value 8
+            description   "
+                This option determines the number of breakpoints supported by the HAL."
+    }
+
+    cdl_component CYGBLD_ARCH_CPUFLAGS {
+        display      "Architecture related build flags"
+        flavor data
+        no_define
+
+        calculated { CYGHWR_HAL_CORTEXM == "M3" ? " -mcpu=cortex-m3" :
+                     CYGHWR_HAL_CORTEXM_FPU     ? " -mcpu=cortex-m4" : " " }
+
+        description "This component defines flags that code generation dependent on specific
+            CPU type or CPU features."
+
+        cdl_option CYGBLD_ARCH_CPUFLAGX_M3 {
+            display    "Exclude Cortex-M3 build flag"
+            flavor     data
+            no_define
+
+            calculated { CYGHWR_HAL_CORTEXM_FPU ? "-mcpu=cortex-m3" : "no_exclude" }
+        }
+
+        cdl_option CYGBLD_ARCH_CPUFLAGX_M4 {
+            display    "Exclude Cortex-M4 build flag"
+            flavor     data
+            no_define
+
+            calculated { (CYGHWR_HAL_CORTEXM != "M4") ? "-mcpu=cortex-m4" : "no_exclude" }
+        }
+
+        cdl_component CYGBLD_ARCH_CPUFLAG_FLOAT_ABI {
+            display    "Float ABI build flags"
+            flavor     data
+            no_define
+            calculated { CYGHWR_HAL_CORTEXM_FPU ? " -mfloat-abi=hard" : "" }
+
+            cdl_option CYGBLD_ARCH_CPUFLAGX_FLOAT_ABI {
+                display    "Float ABI flag to exclude"
+                flavor     data
+                no_define
+                calculated { CYGHWR_HAL_CORTEXM_FPU ? "-mfloat-abi=soft" : "-mfloat-abi=hard" }
+            }
+
+            cdl_option CYGBLD_ARCH_CPUFLAGX_HARDSOFT_FLOAT {
+                display    "Alt. float flag to exclude"
+                flavor     data
+                no_define
+                calculated { CYGHWR_HAL_CORTEXM_FPU ? "-msoft-float" : "-mhard-float" }
+            }
+
+            cdl_component CYGBLD_ARCH_CPUFLAG_FPV4SPD16 {
+                display    "FPv4-SP-D16 flags"
+                flavor     data
+                no_define
+                calculated { CYGHWR_HAL_FPV4_SP_D16 ? " -mfpu=fpv4-sp-d16" : "" }
+
+                cdl_option CYGBLD_ARCH_CPUFLAGX_FPV4SPD16 {
+                    display    "Exclude FPv4-SP-D16 flag"
+                    flavor     data
+                    no_define
+                    calculated { CYGHWR_HAL_FPV4_SP_D16 ? "do_not_exclude" : "-mfpu=fpv4-sp-d16" }
+                }
+            }
+        }
+
+        requires {
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_M3)             &&
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_M4)             &&
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_FLOAT_ABI)      &&
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_HARDSOFT_FLOAT) &&
+            !is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGX_FPV4SPD16)      &&
+
+            is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAGS)                 &&
+            is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAG_FLOAT_ABI)        &&
+            is_substr(CYGBLD_GLOBAL_CFLAGS, CYGBLD_ARCH_CPUFLAG_FPV4SPD16)
+        }
+        requires {
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_M3)             &&
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_M4)             &&
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_FLOAT_ABI)      &&
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_HARDSOFT_FLOAT) &&
+            !is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGX_FPV4SPD16)      &&
+
+            is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAGS)                 &&
+            is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAG_FLOAT_ABI)        &&
+            is_substr(CYGBLD_GLOBAL_LDFLAGS, CYGBLD_ARCH_CPUFLAG_FPV4SPD16)
+        }
+    }
+}
+
+# EOF hal_cortexm.cdl
diff --git a/ecos/packages/hal/cortexm/arch/current/cdl/hal_cortexm_fpu.cdl b/ecos/packages/hal/cortexm/arch/current/cdl/hal_cortexm_fpu.cdl
new file mode 100644
index 0000000..69b3bf7
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/cdl/hal_cortexm_fpu.cdl
@@ -0,0 +1,136 @@
+##==========================================================================
+##
+##      hal_cortexm_fpu.cdl
+##
+##      Cortex-M HAL Floating Point configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ilijak
+## Date:         2012-03-03
+## Usage:        script hal_cortexm_fpu.cdl
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+    #cdl_component CYGPKG_HAL_CORTEXM_FPU {
+        #display          "Floating Point Unit"
+        #flavor           none
+        #no_define
+
+        cdl_interface CYGINT_HAL_FPV4_SP_D16 {
+            display   "FPU is FPv4-SP-D16"
+            flavor     bool
+            implements CYGINT_HAL_CORTEXM_FPU
+        }
+
+        cdl_interface CYGINT_HAL_CORTEXM_FPU {
+            display  "FPU present."
+            flavor   data
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_FPU {
+            display        "Use hardware FPU"
+            flavor         bool
+            active_if      { CYGINT_HAL_CORTEXM_FPU }
+            default_value  0
+            compile        cortexm_fpu.c
+
+            description "
+                Cortex-M4F cores have a single precision floating point unit.
+                This option enables FPU usage and provides related FPU control
+                options.
+                Hardware FPU enable, implies Cortex-M4 code generation, and
+                build flags shall be set accordingly, including -mcpu=cortex-m4.
+                As a side effect, the Cortex_M4 build flag will remain \(sticky\)
+                even if hardware FPU is subsequently disabled.
+                "
+
+            cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH {
+                display       "FPU context switch"
+                flavor data
+                legal_values  { "ALL" "LAZY" "NONE" }
+                default_value { "LAZY" }
+
+                requires { is_active (CYGPKG_KERNEL) implies
+                    CYGTST_KERNEL_SKIP_MULTI_THREAD_FP_TEST ==
+                    (CYGHWR_HAL_CORTEXM_FPU_SWITCH == "NONE") }
+
+                description   "
+                    This option selects the FPU context switching scheme.
+                    Straight-forward behaviour is to save and
+                    restore FPU state on every CPU context save/restore.
+                    While simple, robust and deterministic, this
+                    approach can be expensive if the FPU is used by
+                    few threads. The alternative schemes, available by this
+                    option, are to use hardware features that allow either:
+                    - LAZY: Save FPU context only if the thread makes use of
+                    the FPU. Where only few threads use FPU this should give
+                    shorter average context switching delay compared to ALL
+                    scheme. If more than one threads use FPU, the worst context
+                    switching time is typically worse than the one for ALL
+                    scheme.
+                    - ALL: Save FPU context for all threads. This is a simple
+                    scheme, which if all, or majority of threads use FPU may
+                    give better average context switching time than LAZY.
+                    This scheme also includes Lazy Stacking of FPU state
+                    for exceptions/interrupts.
+                    - NONE: No FPU state saving, this scheme adds no additional
+                    delay for saving of FPU state to context switching, but is
+                    only suitable if maximum one thread uses floating point."
+            }
+
+        cdl_option CYGHWR_HAL_FPV4_SP_D16 {
+            flavor bool
+            active_if { CYGINT_HAL_FPV4_SP_D16 }
+            calculated { CYGINT_HAL_FPV4_SP_D16 && CYGHWR_HAL_CORTEXM_FPU }
+            display     "FPv4-SP-D16"
+            no_define
+            compile     fpv4_sp_d16.c
+
+            define_proc {
+                puts $::cdl_system_header "#define CYGBLD_HAL_LIBM_H <cyg/hal/fpv4_sp_d16_libm.h>"
+            }
+
+            description "
+                FPv4-SP-D16 is ARMv7 architecture single precision floating
+                point unit with 16 double precision / 32 single precision
+                registers. It is found on Cortex-M4F and Cortex-R5 cores."
+        }
+    #}
+
+# EOF hal_cortexm_fpu.cdl
diff --git a/ecos/packages/hal/cortexm/arch/current/include/basetype.h b/ecos/packages/hal/cortexm/arch/current/include/basetype.h
new file mode 100644
index 0000000..6ed8532
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/basetype.h
@@ -0,0 +1,71 @@
+#ifndef CYGONCE_HAL_BASETYPE_H
+#define CYGONCE_HAL_BASETYPE_H
+/*==========================================================================
+//
+//      hal_intr.h
+//
+//      Cortex-M standard types
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Description:  Define architecture base types
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#define CYG_BYTEORDER           CYG_LSBFIRST    // Little endian
+#define CYG_DOUBLE_BYTEORDER    CYG_LSBFIRST
+
+//-----------------------------------------------------------------------------
+// Cortex-M does not usually use labels with underscores.
+
+#define CYG_LABEL_NAME(_name_) _name_
+#define CYG_LABEL_DEFN(_name_) _name_
+
+//-----------------------------------------------------------------------------
+// Define the standard variable sizes
+
+// The ARM architecture uses the default definitions of the base
+// types, so we do not need to define any here.
+
+
+//==========================================================================
+#endif // CYGONCE_HAL_BASETYPE_H
+// End of basetype.h
diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_core.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_core.h
new file mode 100644
index 0000000..cf64721
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_core.h
@@ -0,0 +1,77 @@
+#ifndef CYGONCE_CORTEXM_CORE_H
+#define CYGONCE_CORTEXM_CORE_H
+//==========================================================================
+//
+//      cortexm_core.h
+//
+//      Cortex-M some core registers
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-06-26
+// Description:    Some Cortex-M core register definitions
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+// Coprocessor Access Control Register
+#define CYGARC_REG_FPU_CPACR 0xE000ED88
+
+#define CYGARC_REG_FPU_CPACR_ACCESS_DENIED     0
+#define CYGARC_REG_FPU_CPACR_ACCESS_PRIVILEGED 1
+#define CYGARC_REG_FPU_CPACR_ACCESS_RESERVED   2
+#define CYGARC_REG_FPU_CPACR_ACCESS_FULL       (CYGARC_REG_FPU_CPACR_ACCESS_PRIVILEGED | \
+                                               CYGARC_REG_FPU_CPACR_ACCESS_RESERVED)
+
+#define CYGARC_REG_FPU_CPACR_CP10(_access) ((_access) << 20)
+#define CYGARC_REG_FPU_CPACR_CP11(_access) ((_access) << 22)
+
+#define CYGARC_REG_FPU_CPACR_ENABLE                                       \
+           (CYGARC_REG_FPU_CPACR_CP10(CYGARC_REG_FPU_CPACR_ACCESS_FULL) | \
+            CYGARC_REG_FPU_CPACR_CP11(CYGARC_REG_FPU_CPACR_ACCESS_FULL))
+
+// CONTROL register
+// The CONTROL register is not memory mapped. Use CYGARC_MSR() and CYGARC_MRS().
+#define CYGARC_REG_CONTROL_PRIV_M       0x1
+#define CYGARC_REG_CONTROL_SPSEL_M      0x2
+#define CYGARC_REG_CONTROL_FPCA_M       0x4
+
+//==========================================================================
+#endif //CYGONCE_CORTEXM_CORE_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_endian.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_endian.h
new file mode 100644
index 0000000..67b3801
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_endian.h
@@ -0,0 +1,77 @@
+#ifndef CYGONCE_CORTEXM_ENDIAN_H
+#define CYGONCE_CORTEXM_ENDIAN_H
+//==========================================================================
+//
+//      cortexm_endian.h
+//
+//      Cortex-M architecture endian conversion macros/functions.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+//               Sergei Gavrikov
+// Date:         2011-08-20
+// Description:  Endian conversion macros/functions optimized for Cortex-M
+// Usage:        #include <cyg/hal/cortexm_endian.h>
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/cortexm_regs.h>
+
+//===========================================================================
+// Endian operations optimized for Cortex-M architecture.
+
+static __inline__ cyg_uint32 cyg_hal_swap32(cyg_uint32 original)
+{
+    cyg_uint32 swapped;
+    CYGARC_REV(swapped, original);
+    return swapped;
+}
+
+static __inline__ cyg_uint16 cyg_hal_swap16(cyg_uint16 original)
+{
+    cyg_uint16 swapped;
+    CYGARC_REV16(swapped, original);
+    return swapped;
+}
+
+#define CYG_SWAP32(__val) cyg_hal_swap32(__val)
+#define CYG_SWAP16(__val) cyg_hal_swap16(__val)
+
+//==========================================================================
+#endif //CYGONCE_CORTEXM_ENDIAN_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_fpu.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_fpu.h
new file mode 100644
index 0000000..ccc1687
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_fpu.h
@@ -0,0 +1,98 @@
+#ifndef CYGONCE_CORTEXM_FPU_H
+#define CYGONCE_CORTEXM_FPU_H
+//==========================================================================
+//
+//      cortexm_fpu.h
+//
+//      Cortex-M General Floating Point Unit definitions 
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-04-25
+// Description:    Cortex-M4F General Floating Point Unit definitions and macros
+// Usage:          include <cyg/hal/cortexm_fpu.h>
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+//===========================================================================
+// Floating Point Unit
+//
+// FPU is optional unit of Cortex-M4
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <cyg/hal/cortexm_core.h>
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+
+# if defined CYGSEM_HAL_ROM_MONITOR || defined CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#  define CYGSEM_HAL_DEBUG_FPU
+# endif
+
+# ifdef CYGINT_HAL_FPV4_SP_D16
+#  include <cyg/hal/fpv4_sp_d16.h>
+# else
+#  error "Unknown FPU unit!"
+# endif
+
+#else // CYGHWR_HAL_CORTEXM_FPU
+
+# define CYGARC_CORTEXM_GDB_REG_FPA
+
+# define GDB_STUB_SAVEDREG_FRAME_TYPE(__type) (__type->u.type)
+
+# define HAL_SAVEDREG_AUTO_FRAME_SIZE (8*4)
+
+# define HAL_SAVEDREG_FPU_THREAD_S
+# define HAL_SAVEDREG_MAN_FPU_EXCEPTION_S
+# define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S
+# define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT
+
+# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+# define GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+# define GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+
+#endif// CYGHWR_HAL_CORTEXM_FPU
+
+
+//==========================================================================
+#endif //CYGONCE_CORTEXM_FPU_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_regs.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_regs.h
new file mode 100644
index 0000000..4bb4c86
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_regs.h
@@ -0,0 +1,118 @@
+#ifndef CYGONCE_CORTEXM_REGS_H
+#define CYGONCE_CORTEXM_REGS_H
+//==========================================================================
+//
+//      cortexm_regs.h
+//
+//      Cortex-M architecture, special machine instruction wrappers
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+//               Sergei Gavrikov
+// Date:         2011-06-18
+// Description:  C wrappers for some special architecture instructions.
+//
+//####DESCRIPTIONEND####
+//
+//=========================================================================
+
+#ifndef __ASSEMBLER__
+
+//--------------------------------------------------------------------------
+// No operation
+#define CYGARC_NOP() { __asm__ volatile( "nop" ); }
+
+
+//---------------------------------------------------------------------------
+// Change processor state instructions
+
+// Disable / enable interrupts
+#define CYGARC_CPSID( _flags_ ) __asm__ volatile ("cpsid " #_flags_ "\n")
+
+// Enable interrupts and fault handlers (clear FAULTMASK)
+#define CYGARC_CPSIE( _flags_ ) __asm__ volatile ("cpsie " #_flags_ "\n")
+
+//---------------------------------------------------------------------------
+// Byte swapping instructions
+
+// Reverse word
+#define CYGARC_REV( _swapped_, _origin_ ) \
+        __asm__ volatile ("rev %0, %1\n" : "=r"(_swapped_) : "r"(_origin_))
+
+// Reverse halfwords
+#define CYGARC_REV16( _swapped_, _origin_ ) \
+        __asm__ volatile ("rev16 %0, %1\n" : "=r"(_swapped_) : "r"(_origin_))
+
+// Reverse signed halfword
+#define CYGARC_REVSH( _swapped_, _origin_ ) \
+        __asm__ volatile ("revsh %0, %1\n" : "=r"(_swapped_) : "r"(_origin_))
+
+//------------------------------------------------------------------------
+// Barrier instructions
+// Data Synchronization Barrier
+#define CYGARC_DSB() __asm__ volatile( "dsb" )
+// Instruction Synchronization Barrier
+#define CYGARC_ISB() __asm__ volatile( "isb" )
+
+#define HAL_MEMORY_BARRIER() \
+CYG_MACRO_START              \
+    CYGARC_DSB();            \
+    CYGARC_ISB();            \
+CYG_MACRO_END
+
+//----------------------------------------------------------------------------
+// MSR instuctions
+// Special register instructions
+#define CYGARC_MSR(_reg_, _val_) \
+        __asm__ volatile ("msr " #_reg_", %0\n" : : "r"(_val_))
+
+#define CYGARC_MRS(_val_, _reg_) \
+        __asm__ volatile ("mrs %0," #_reg_ "\n" : "=r"(_val_) : )
+
+//----------------------------------------------------------------------------
+// VFP instuctions
+// Special floating point unit register instructions
+#define CYGARC_VMSR(_reg_, _val_) \
+        __asm__ volatile ("vmsr " #_reg_", %0\n" : : "r"(_val_))
+
+#define CYGARC_VMRS(_val_, _reg_) \
+        __asm__ volatile ("vmrs %0," #_reg_ "\n" : "=r"(_val_) : )
+
+#endif // __ASSEMBLER__
+
+//==========================================================================
+#endif // CYGONCE_CORTEXM_REGS_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_stub.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_stub.h
new file mode 100644
index 0000000..9ec3b6a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_stub.h
@@ -0,0 +1,161 @@
+#ifndef CYGONCE_HAL_CORTEXM_STUB_H
+#define CYGONCE_HAL_CORTEXM_STUB_H
+/*==========================================================================
+//
+//      cortexm_stub.h
+//
+//      Cortex-M GDB stub support
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:         2008-07-30
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+#include <cyg/hal/cortexm_fpu.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifndef CYGHWR_HAL_CORTEXM_FPU
+// The ARM has float (and possibly other coprocessor) registers that are
+// larger than it can hold in a target_register_t.
+# define TARGET_HAS_LARGE_REGISTERS
+
+// ARM stub has special needs for register handling (not all regs are the
+// the same size), so special put_register and get_register are provided.
+# define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1
+
+# define NUMREGS    (16+8+2)  // 16 GPR, 8 FPR (unused), 2 PS
+
+# define REGSIZE( _x_ ) (((_x_) < F0 || (_x_) >= FPS) ? 4 : 12)
+
+# ifndef TARGET_REGISTER_T_DEFINED
+#  define TARGET_REGISTER_T_DEFINED
+typedef unsigned long target_register_t;
+# endif
+
+enum regnames {
+    R0, R1, R2, R3, R4, R5, R6, R7,
+    R8, R9, R10, FP, IP, SP, LR, PC,
+    F0, F1, F2, F3, F4, F5, F6, F7,
+    FPS, PS
+};
+
+#endif // CYGHWR_HAL_CORTEXM_FPU
+
+# define HAL_STUB_REGISTERS_SIZE \
+   ((sizeof(HAL_CORTEXM_GDB_Registers) + sizeof(target_register_t) - 1) / sizeof(target_register_t))
+
+# define PS_N 0x80000000
+# define PS_Z 0x40000000
+# define PS_C 0x20000000
+# define PS_V 0x10000000
+
+typedef enum regnames regnames_t;
+
+//------------------------------------------------------------------------
+
+/* Given a trap value TRAP, return the corresponding signal. */
+extern int __computeSignal (unsigned int trap_number);
+
+/* Return the trap number corresponding to the last-taken trap. */
+extern int __get_trap_number (void);
+
+/* Return the currently-saved value corresponding to register REG. */
+extern target_register_t get_register (regnames_t reg);
+
+/* Store VALUE in the register corresponding to WHICH. */
+extern void put_register (regnames_t which, target_register_t value);
+
+/* Set the currently-saved pc register value to PC. This also updates NPC
+   as needed. */
+extern void set_pc (target_register_t pc);
+
+/* Set things up so that the next user resume will execute one instruction.
+   This may be done by setting breakpoints or setting a single step flag
+   in the saved user registers, for example. */
+void __single_step (void);
+
+/* Clear the single-step state. */
+void __clear_single_step (void);
+
+/* If the breakpoint we hit is in the breakpoint() instruction, return a
+   non-zero value. */
+extern int __is_breakpoint_function (void);
+
+/* Skip the current instruction. */
+extern void __skipinst (void);
+
+extern void __install_breakpoints (void);
+
+extern void __clear_breakpoints (void);
+
+extern int __is_bsp_syscall(void);
+
+//------------------------------------------------------------------------
+// Special definition of CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+// we can only do this at all if break support is enabled:
+
+// If this macro is used from Thumb code, we need to pass this information
+// along to the place_break function so it can do the right thing.
+#define CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION( _old_ )                         \
+do {                                                                          \
+    HAL_DISABLE_INTERRUPTS(_old_);                                            \
+    cyg_hal_gdb_place_break((target_register_t)((unsigned long)&&cyg_hal_gdb_break_place));\
+} while ( 0 )
+
+#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+//==========================================================================
+#endif // ifndef CYGONCE_HAL_CORTEXM_STUB_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h b/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h
new file mode 100644
index 0000000..d11cf07
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h
@@ -0,0 +1,285 @@
+#ifndef CYGONCE_FPV4_SP_D16_H
+#define CYGONCE_FPV4_SP_D16_H
+//==========================================================================
+//
+//      fpv4_sp_d16.h
+//
+//      FPv4spD16 Floating Point Unit definitions 
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-04-25
+// Description:    FPv4spD16 Floating Point Unit definitions and macros
+// Usage:          include <cyg/hal/fpv4_sp_d16.h>
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+#define CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+#endif
+
+//===========================================================================
+// Floating-point Context Control Register
+#define CYGARC_REG_FPU_FPCCR 0xE000EF34
+
+#define CYGARC_REG_FPU_FPCCR_LSPACT   0x1
+#define CYGARC_REG_FPU_FPCCR_USER     0x2
+#define CYGARC_REG_FPU_FPCCR_THREAD   0x8
+#define CYGARC_REG_FPU_FPCCR_HFRDY    0x10
+#define CYGARC_REG_FPU_FPCCR_MMRDY    0x20
+#define CYGARC_REG_FPU_FPCCR_BFRDY    0x40
+#define CYGARC_REG_FPU_FPCCR_MONRDY   0x100
+#define CYGARC_REG_FPU_FPCCR_LSPEN    0x40000000
+#define CYGARC_REG_FPU_FPCCR_ASPEN    0x80000000
+
+#define HAL_CORTEXM_FPU_ENABLE()                      \
+CYG_MACRO_START                                       \
+    cyg_uint32 regval;                                \
+    HAL_READ_UINT32(CYGARC_REG_FPU_CPACR, regval);    \
+    regval |= CYGARC_REG_FPU_CPACR_ENABLE;            \
+    HAL_WRITE_UINT32(CYGARC_REG_FPU_CPACR, regval);   \
+    HAL_MEMORY_BARRIER();                             \
+CYG_MACRO_END
+
+#define HAL_CORTEXM_FPU_DISABLE()                     \
+CYG_MACRO_START                                       \
+    cyg_uint32 regval;                                \
+    HAL_READ_UINT32(CYGARC_REG_FPU_CPACR, regval);    \
+    regval &= ~CYGARC_REG_FPU_CPACR_ENABLE;           \
+    HAL_WRITE_UINT32(CYGARC_REG_FPU_CPACR, regval);   \
+    HAL_MEMORY_BARRIER();                             \
+CYG_MACRO_END
+
+#ifndef __ASSEMBLER__
+__externC void hal_init_fpu(void);
+#endif
+
+// Floating-point Context Address Register
+#define CYGARC_REG_FPU_FPCAR 0xE000EF38
+
+// Floating-point Default Status Control Register
+#define CYGARC_REG_FPU_FPDSCR 0xE000EF3C
+
+#define CYGARC_REG_FPU_FPDSCR_FZ            BIT_(24)
+#define CYGARC_REG_FPU_FPDSCR_DN            BIT_(25)
+#define CYGARC_REG_FPU_FPDSCR_AHP           BIT_(26)
+
+#define CYGARC_REG_FPU_FPDSCR_ROUND(__mode) VALUE_(22, (__mode))
+// where __mode is:
+#define CYGARC_REG_FPU_FPDSCR_ROUND_RN      0
+#define CYGARC_REG_FPU_FPDSCR_ROUND_RP      1
+#define CYGARC_REG_FPU_FPDSCR_ROUND_RM      2
+#define CYGARC_REG_FPU_FPDSCR_ROUND_RZ      3
+
+//==========================================================================
+// FPU Context
+#define HAL_SAVEDREGISTERS_WITH_FPU        0x80
+
+#define HAL_SAVEDREGISTERS_THREAD_FPU      (HAL_SAVEDREGISTERS_THREAD | \
+                                            HAL_SAVEDREGISTERS_WITH_FPU)
+
+#define HAL_SAVEDREGISTERS_EXCEPTION_FPU   (HAL_SAVEDREGISTERS_EXCEPTION | \
+                                            HAL_SAVEDREGISTERS_WITH_FPU)
+
+#ifndef CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+
+// Without automatic contex saving during exception or interrupt
+# define HAL_SAVEDREGISTERS_FPU_THREAD_CONTEXT_SIZE   (HAL_SAVEDREG_THREAD_FPU_N*4+4)
+# define HAL_SAVEDREG_AUTO_FRAME_SIZE                 (8*4)
+
+# define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S
+
+#else //  !CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+
+// With automatic contex saving during exception or interrupt enabled
+# if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+
+#  define HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N    16
+#  define HAL_SAVEDREG_AUTO_FRAME_SIZE         (8*4 + 16*4 + 4 + 4)
+
+// HAL_SavedRegisters entries for floating point registers
+//     see hal_arch.h for HAL_SavedRegisters definition.
+
+#  define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S                        \
+            cyg_uint32  s_auto[HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N]; \
+            cyg_uint32  fpscr_auto;                                \
+            cyg_uint32  aligner
+
+# else // defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+#  error  "Automatic FPU context saving is not supported in LAZY and NONE modes."
+# endif // defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+#endif //  !CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+
+// Common for AUTOSAVE and non AUTOSAVE
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+// HAL_SavedRegisters entries for floating point registers
+//     see hal_arch.h for HAL_SavedRegisters definition.
+
+# define HAL_SAVEDREG_THREAD_FPU_N         32
+# define HAL_SAVEDREG_EXCEPTION_FPU_N      32
+
+# define HAL_SAVEDREG_FPU_THREAD_S                      \
+           cyg_uint32  fpscr;                           \
+           cyg_uint32  s[HAL_SAVEDREG_THREAD_FPU_N]
+
+# define HAL_SAVEDREG_FPU_EXCEPTION_S                   \
+           cyg_uint32  s[HAL_SAVEDREG_EXCEPTION_FPU_N]; \
+           cyg_uint32  fpscr;                           \
+           cyg_uint32  cpacr
+
+// Thread FP context initialization
+# define HAL_THREAD_INIT_FPU_REGS(__regs_p)                                 \
+CYG_MACRO_START                                                             \
+    int __reg_i;                                                            \
+    for(__reg_i = 0; __reg_i < HAL_SAVEDREG_THREAD_FPU_N; __reg_i++)    \
+        (__regs_p)->u.thread.s[__reg_i] = 0;                                \
+CYG_MACRO_END
+
+# define HAL_THREAD_INIT_FPU_CONTEXT(__regs_p)                              \
+CYG_MACRO_START                                                             \
+    HAL_THREAD_INIT_FPU_REGS(__regs_p);                                     \
+    (__regs_p)->u.thread.fpscr = 0;                                         \
+CYG_MACRO_END
+#else //defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+#  define HAL_SAVEDREG_FPU_THREAD_S
+#  define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT
+
+#endif //defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+//==========================================================================
+// hal_arch.h GDB stub support
+
+// Register layout expected by GDB VFP
+#ifndef __ASSEMBLER__
+typedef struct {
+    cyg_uint32 gpr[16];
+    cyg_uint32 xpsr;
+    cyg_uint32 s[32];
+    cyg_uint32 fpscr;
+} HAL_CORTEXM_GDB_Registers;
+#endif
+
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+# define GDB_STUB_SAVEDREG_FRAME_TYPE(__regs)                        \
+         ((__regs)->u.type & ~HAL_SAVEDREGISTERS_WITH_FPU)
+
+# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs)           \
+CYG_MACRO_START                                                      \
+    cyg_uint32 reg_i;                                                \
+    for( reg_i = 0; reg_i < HAL_SAVEDREG_THREAD_FPU_N; reg_i++ ) \
+        (__gdbreg)->s[reg_i] = (__regs)->u.thread.s[reg_i];          \
+    (__gdbreg)->fpscr = (__regs)->u.thread.fpscr;                    \
+CYG_MACRO_END
+
+# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs)           \
+CYG_MACRO_START                                                      \
+    cyg_uint32 reg_i;                                                \
+    for( reg_i = 0; reg_i < HAL_SAVEDREG_THREAD_FPU_N; reg_i++ ) \
+        (__regs)->u.thread.s[reg_i] = (__gdbreg)->s[reg_i];          \
+    (__regs)->u.thread.fpscr = (__gdbreg)->fpscr;                    \
+CYG_MACRO_END
+
+#else //  defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+# define GDB_STUB_SAVEDREG_FRAME_TYPE(__regs)              ((__regs)->u.type)
+# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT
+
+#endif //  defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+#define GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(__gdbreg,__regs)        \
+CYG_MACRO_START                                                     \
+    cyg_uint32 reg_i;                                               \
+    for( reg_i = 0; reg_i < HAL_SAVEDREG_EXCEPTION_FPU_N; reg_i++ ) \
+        (__gdbreg)->s[reg_i] = (__regs)->u.exception.s[reg_i];      \
+    (__gdbreg)->fpscr = (__regs)->u.exception.fpscr;                \
+CYG_MACRO_END
+
+#define GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(__gdbreg,__regs)                      \
+CYG_MACRO_START                                                                   \
+    cyg_uint32 reg_i;                                                             \
+    for( reg_i = 0; reg_i < HAL_SAVEDREG_EXCEPTION_FPU_N; reg_i++ )               \
+        (__regs)->u.exception.s[reg_i] = (__gdbreg)->s[reg_i];                    \
+    (__regs)->u.exception.fpscr = (__gdbreg)->fpscr;                              \
+    if(*(cyg_uint32 *)CYGARC_REG_FPU_FPCCR & CYGARC_REG_FPU_FPCCR_ASPEN) {        \
+        for( reg_i = 0; reg_i < HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N; reg_i++ )      \
+            (__regs)->u.exception.s_auto[reg_i] = (__regs)->u.exception.s[reg_i]; \
+        (__regs)->u.exception.fpscr_auto = (__regs)->u.exception.fpscr;           \
+    }                                                                             \
+CYG_MACRO_END
+
+//==========================================================================
+// hal_arch.h Minimal and sensible stack sizes:
+// Override value in hal_arch.h
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * (20+32+4+4))
+
+// GDB stub ==================================================================
+// cortexm_stub.h definitions for FPV4-SP-D16
+
+// The Cortex-M4F double registers are larger then target_register_t.
+#define TARGET_HAS_LARGE_REGISTERS
+
+// Cortex-M4F stub register handling macros
+#define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1
+#define NUMREGS    (FPSCR+1)  // 16 GPR, XPSR, 10 non existent, 16 VFP, FPSCR
+#define REGSIZE( _x_ ) (_x_ <= PC ? 4 :                         \
+                        (_x_ < XPSR ? 0 :                        \
+                         (_x_ == XPSR ? 4 :                      \
+                          (((_x_ >= VD0) && (_x_ <= VD15)) ? 8 : \
+                           (_x_ == FPSCR ? 4 : 0 )))))
+#ifndef __ASSEMBLER__
+# ifndef TARGET_REGISTER_T_DEFINED
+#  define TARGET_REGISTER_T_DEFINED
+typedef unsigned long target_register_t;
+# endif
+
+enum regnames {
+    R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, SP, LR, PC,
+    XPSR = 25,
+    VD0 = 26, VD1, VD2, VD3, VD4, VD5, VD6, VD7,
+    VD8, VD9, VD10, VD11, VD12, VD13, VD14, VD15,
+    FPSCR
+};
+#endif // __ASSEMBLER__
+
+//==========================================================================
+#endif //CYGONCE_FPV4_SP_D16_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h b/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h
new file mode 100644
index 0000000..57e70b8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_FPV4_SP_D16_LIBM_H
+#define CYGONCE_FPV4_SP_D16_LIBM_H
+//==========================================================================
+//
+//      fpv4_sp_d16_libm.h
+//
+//      FPv4spD16 Floating Point Unit mathematical functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2013-06-10
+// Description:    FPv4spD16 Floating Point Unit builtin mathematical functions.
+// Usage:          include <cyg/hal/fpv4_sp_d16_libm.h>
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#ifdef CYGSEM_LIBM_IEEE_API_INLINE
+
+// Builtin mathematical functions
+#define __ieee754_sqrtf(__x) __builtin_sqrtf(__x)
+
+#endif // CYGSEM_LIBM_IEEE_API_INLINE
+
+//==========================================================================
+#endif //CYGONCE_FPV4_SP_D16_LIBM_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/hal_arch.h b/ecos/packages/hal/cortexm/arch/current/include/hal_arch.h
new file mode 100644
index 0000000..f8e73e3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/hal_arch.h
@@ -0,0 +1,390 @@
+#ifndef CYGONCE_HAL_ARCH_H
+#define CYGONCE_HAL_ARCH_H
+/*==========================================================================
+//
+//      hal_arch.h
+//
+//      Cortex-M architecture abstractions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2008-07-30
+// Description:    Define architecture abstractions
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#ifndef __ASSEMBLER__
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/var_arch.h>
+#include <cyg/hal/cortexm_regs.h>
+
+#include <cyg/hal/cortexm_fpu.h>
+
+#endif //__ASSEMBLER__
+
+//==========================================================================
+// CPU save state
+//
+// This is a discriminated union of different save states for threads,
+// exceptions and interrupts. State is saved in the most efficient way
+// for each context. This makes the GDB state get/put slightly more
+// complex, but that is a suitable compromise.
+
+#define HAL_SAVEDREGISTERS_EXCEPTION    1
+#define HAL_SAVEDREGISTERS_THREAD       2
+#define HAL_SAVEDREGISTERS_INTERRUPT    3
+
+#ifndef __ASSEMBLER__
+
+typedef struct
+{
+    union
+    {
+        cyg_uint32              type;           // State type
+
+        // Thread
+        struct
+        {
+            cyg_uint32          type;           // State type
+            cyg_uint32          basepri;        // BASEPRI
+            cyg_uint32          sp;             // SP (R13)
+
+            HAL_SAVEDREG_FPU_THREAD_S;          // Floating Point Unit context
+
+            cyg_uint32          r[13];          // R0..R12
+            cyg_uint32          pc;             // PC/LR
+        } thread;
+
+        // Exception
+        struct
+        {
+            cyg_uint32          type;           // State type
+            cyg_uint32          vector;         // Exception vector number
+            cyg_uint32          basepri;        // BASEPRI
+
+            cyg_uint32          r4_11[8];       // Remaining CPU registers
+            cyg_uint32          xlr;            // Exception return LR
+#ifdef CYGSEM_HAL_DEBUG_FPU
+            HAL_SAVEDREG_FPU_EXCEPTION_S;   // Floating Point Unit context
+#endif
+            // The following are saved and restored automatically by the CPU
+            // for exceptions or interrupts.
+
+            cyg_uint32          r0;
+            cyg_uint32          r1;
+            cyg_uint32          r2;
+            cyg_uint32          r3;
+            cyg_uint32          r12;
+            cyg_uint32          lr;
+            cyg_uint32          pc;
+            cyg_uint32          psr;
+
+            HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S; // Floating Point Unit context
+        } exception;
+
+        // Interrupt
+        struct
+        {
+            cyg_uint32          type;           // State type
+
+            // The following are saved and restored automatically by the CPU
+            // for exceptions or interrupts.
+
+            cyg_uint32          r0;
+            cyg_uint32          r1;
+            cyg_uint32          r2;
+            cyg_uint32          r3;
+            cyg_uint32          r12;
+            cyg_uint32          lr;
+            cyg_uint32          pc;
+            cyg_uint32          psr;
+
+            HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S; // Floating Point Unit context
+        } interrupt;
+    } u;
+
+} HAL_SavedRegisters;
+
+//==========================================================================
+// Thread context initialization
+
+#ifndef HAL_THREAD_INIT_FPU_CONTEXT
+#define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT
+#endif
+
+#define HAL_THREAD_INIT_CONTEXT( __sparg, __thread, __entry, __id )     \
+CYG_MACRO_START                                                         \
+    register CYG_WORD __sp = ((CYG_WORD)__sparg) & ~7;                  \
+    register CYG_WORD *__ep = (CYG_WORD *)(__sp -= sizeof(CYG_WORD));   \
+    register HAL_SavedRegisters *__regs;                                \
+    int __i;                                                            \
+    __sp = ((CYG_WORD)__sp) &~15;                                       \
+    __regs = (HAL_SavedRegisters *)((__sp) - sizeof(__regs->u.thread)); \
+    __regs->u.type = HAL_SAVEDREGISTERS_THREAD;                         \
+    for( __i = 1; __i < 13; __i++ )                                     \
+        __regs->u.thread.r[__i] = 0;                                    \
+    HAL_THREAD_INIT_FPU_CONTEXT(__regs);                                \
+    *__ep = (CYG_WORD)(__entry);                                        \
+    __regs->u.thread.sp       = (CYG_WORD)(__sp);                       \
+    __regs->u.thread.r[0]     = (CYG_WORD)(__thread);                   \
+    __regs->u.thread.r[1]     = (CYG_WORD)(__id);                       \
+    __regs->u.thread.r[11]    = (CYG_WORD)(__ep);                       \
+    __regs->u.thread.pc       = (CYG_WORD)__entry;                      \
+    __regs->u.thread.basepri  = 0;                                      \
+    __sparg = (CYG_ADDRESS)__regs;                                      \
+CYG_MACRO_END
+
+//==========================================================================
+// Context switch macros.
+// The arguments are pointers to locations where the stack pointer
+// of the current thread is to be stored, and from where the SP of the
+// next thread is to be fetched.
+
+__externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
+__externC void hal_thread_load_context( CYG_ADDRESS to ) __attribute__ ((noreturn));
+
+#define HAL_THREAD_SWITCH_CONTEXT(__fspptr,__tspptr)                    \
+        hal_thread_switch_context((CYG_ADDRESS)__tspptr,                \
+                                  (CYG_ADDRESS)__fspptr);
+
+#define HAL_THREAD_LOAD_CONTEXT(__tspptr)                               \
+        hal_thread_load_context( (CYG_ADDRESS)__tspptr );
+
+
+//==========================================================================
+// Fetch PC from saved state
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || \
+    defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+#define CYGARC_HAL_GET_PC_REG(__regs,__val)                                       \
+{                                                                                 \
+    switch(GDB_STUB_SAVEDREG_FRAME_TYPE(__regs))                                                    \
+    {                                                                             \
+    case HAL_SAVEDREGISTERS_THREAD:    (__val) = (__regs)->u.thread.pc; break;    \
+    case HAL_SAVEDREGISTERS_EXCEPTION: (__val) = (__regs)->u.exception.pc; break; \
+    case HAL_SAVEDREGISTERS_INTERRUPT: (__val) = (__regs)->u.interrupt.pc; break; \
+    default: (__val) = 0;                                                         \
+    }                                                                             \
+}
+#else
+#define CYGARC_HAL_GET_PC_REG(__regs,__val)                                       \
+{                                                                                 \
+    switch( (__regs)->u.type )                                                    \
+    {                                                                             \
+    case HAL_SAVEDREGISTERS_THREAD   : (__val) = (__regs)->u.thread.pc; break;    \
+    case HAL_SAVEDREGISTERS_EXCEPTION: (__val) = (__regs)->u.exception.pc; break; \
+    case HAL_SAVEDREGISTERS_INTERRUPT: (__val) = (__regs)->u.interrupt.pc; break; \
+    default: (__val) = 0;                                                         \
+    }                                                                             \
+}
+#endif
+//==========================================================================
+// Exception handling function
+// This function is defined by the kernel according to this prototype. It is
+// invoked from the HAL to deal with any CPU exceptions that the HAL does
+// not want to deal with itself. It usually invokes the kernel's exception
+// delivery mechanism.
+
+externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
+
+//==========================================================================
+// Bit manipulation macros
+
+#define HAL_LSBIT_INDEX(__index, __mask)                                \
+{                                                                       \
+    register cyg_uint32 __bit = (__mask);                               \
+    register int __count;                                               \
+    __bit = __bit & -__bit;                                             \
+    __asm__ volatile ("clz %0,%1" : "=r"(__count) : "r"(__bit) );       \
+    (__index) = 31-__count;                                             \
+}
+
+#define HAL_MSBIT_INDEX(__index, __mask)                                \
+{                                                                       \
+    register cyg_uint32 __bit = (__mask);                               \
+    register int __count;                                               \
+    __asm__ volatile ("clz %0,%1" : "=r"(__count) : "r"(__bit) );       \
+    (__index) = 31-__count;                                             \
+}
+
+//==========================================================================
+// Execution reorder barrier.
+// When optimizing the compiler can reorder code. In multithreaded systems
+// where the order of actions is vital, this can sometimes cause problems.
+// This macro may be inserted into places where reordering should not happen.
+
+#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
+
+//==========================================================================
+// Breakpoint support
+// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
+// if executed.
+// HAL_BREAKINST is the value of the breakpoint instruction and
+// HAL_BREAKINST_SIZE is its size in bytes.
+
+#define HAL_BREAKINST           0xbebe         // BKPT
+
+# define HAL_BREAKINST_SIZE      2
+# define HAL_BREAKINST_TYPE      cyg_uint16
+
+#define _stringify1(__arg) #__arg
+#define _stringify(__arg) _stringify1(__arg)
+
+# define HAL_BREAKPOINT(_label_)                        \
+__asm__ volatile (" .globl  " #_label_ ";"              \
+              #_label_":"                               \
+              " .short  " _stringify(HAL_BREAKINST)     \
+    );
+
+//==========================================================================
+// GDB support
+
+#ifdef CYGARC_CORTEXM_GDB_REG_FPA
+// Register layout expected by GDB FPA
+typedef struct
+{
+    cyg_uint32  gpr[16];
+    cyg_uint32  f0[3];
+    cyg_uint32  f1[3];
+    cyg_uint32  f2[3];
+    cyg_uint32  f3[3];
+    cyg_uint32  f4[3];
+    cyg_uint32  f5[3];
+    cyg_uint32  f6[3];
+    cyg_uint32  f7[3];
+    cyg_uint32  fps;
+    cyg_uint32  xpsr;
+} HAL_CORTEXM_GDB_Registers;
+#endif
+
+// Translate a stack pointer as saved by the thread context macros
+// into a pointer to a HAL_SavedRegisters structure. On the Cortex-M
+// these are equivalent.
+
+#define HAL_THREAD_GET_SAVED_REGISTERS(__stack, __regs) \
+    CYG_MACRO_START                                     \
+    (__regs)    = (HAL_SavedRegisters*)(__stack);       \
+    CYG_MACRO_END
+
+
+__externC void hal_get_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs );
+__externC void hal_set_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs );
+
+#define HAL_GET_GDB_REGISTERS(__regval, __regs) hal_get_gdb_registers( (HAL_CORTEXM_GDB_Registers *)(__regval), (HAL_SavedRegisters *)(__regs) )
+#define HAL_SET_GDB_REGISTERS(__regs, __regval) hal_set_gdb_registers( (HAL_CORTEXM_GDB_Registers *)(__regval), (HAL_SavedRegisters *)(__regs) )
+
+//==========================================================================
+// HAL setjmp
+
+#define CYGARC_JMP_BUF_SIZE     16
+
+typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
+
+__externC int hal_setjmp(hal_jmp_buf env);
+__externC void hal_longjmp(hal_jmp_buf env, int val);
+
+
+//==========================================================================
+// Idle thread code.
+//
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. Here we only supply a default fallback if the variant/platform
+// doesn't define anything.
+
+#ifndef HAL_IDLE_THREAD_ACTION
+#define HAL_IDLE_THREAD_ACTION(__count) __asm__ volatile ( "wfi\n" )
+#endif
+
+//==========================================================================
+// Minimal and sensible stack sizes: the intention is that applications
+// will use these to provide a stack size in the first instance prior to
+// proper analysis.  Idle thread stack should be this big.
+
+//    THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
+//           THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
+// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
+
+// This is not a config option because it should not be adjusted except
+// under "enough rope" sort of disclaimers.
+
+// A minimal, optimized stack frame - space for return link plus four
+// arguments or local variables.
+#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 20)
+
+// Stack needed for a context switch
+#if !defined CYGNUM_HAL_STACK_CONTEXT_SIZE
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 20)
+#endif
+
+// Interrupt + call to ISR, interrupt_end() and the DSR
+#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
+    (CYGNUM_HAL_STACK_CONTEXT_SIZE + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+// Space for the maximum number of nested interrupts, plus room to call functions
+#define CYGNUM_HAL_MAX_INTERRUPT_NESTING 4
+
+// Minimum stack size. Space for the given number of nested
+// interrupts, plus a thread context switch plus a couple of function
+// calls.
+#define CYGNUM_HAL_STACK_SIZE_MINIMUM \
+        ((CYGNUM_HAL_MAX_INTERRUPT_NESTING+1) * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \
+         2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+// Typical stack size -- used mainly for test programs. The minimum
+// stack size plus enough space for some function calls.
+#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
+        (CYGNUM_HAL_STACK_SIZE_MINIMUM + 32 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+//==========================================================================
+// Macros for switching context between two eCos instances (jump from
+// code in ROM to code in RAM or vice versa).
+
+#define CYGARC_HAL_SAVE_GP()
+#define CYGARC_HAL_RESTORE_GP()
+
+#endif // __ASSEMBLER__
+
+//==========================================================================
+#endif //CYGONCE_HAL_ARCH_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/hal_arch.inc b/ecos/packages/hal/cortexm/arch/current/include/hal_arch.inc
new file mode 100644
index 0000000..bef2e52
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/hal_arch.inc
@@ -0,0 +1,115 @@
+/*==========================================================================
+//
+//      hal_arch.inc
+//
+//      Cortex-M exception vector macros
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       ilijak
+// Contributors(s):
+// Date:            2012-07-08
+// Description:     This file defines some GAS macros exception VSRs.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+
+# ifdef CYGINT_HAL_FPV4_SP_D16
+
+//============================================================================
+// LAZY context switching scheme keeps FPU disabled for the threads that
+// don't use floating point. We need to enable it before we save FPU context
+// in order to avoid Usage Fault exception.
+
+        .macro hal_fpu_enable
+        ldr    r1,=CYGARC_REG_FPU_CPACR
+        ldr    r2,[r1]
+        stmdb  r0!,{r2}           // Save thread's CPACR state
+        orr    r2,#CYGARC_REG_FPU_CPACR_ENABLE
+        str    r2,[r1]
+        .endm
+
+//============================================================================
+// Restore thread's FPU usage state.
+// undo hal_fpu_enable
+
+        .macro hal_fpu_undo_enable
+        ldmia  r0!,{r2}           // Retrieve previous thread's CPACR state
+        ldr    r1,=CYGARC_REG_FPU_CPACR
+        str    r2,[r1]
+        .endm
+
+//============================================================================
+// Store FPU context during exception if FPU was disabled then enamble it.
+
+        .macro hal_fpu_exc_push
+        hal_fpu_enable
+        vmrs         r1,fpscr
+        stmdb        r0!,{r1}
+        vstmdb.f64   r0!,{d0-d15}
+        .endm
+
+//============================================================================
+// Restore FPU context during exception and undo FPU enable.
+
+        .macro hal_fpu_exc_pop
+        vldmia.f64   r0!,{d0-d15}
+        ldmia        r0!,{r1}
+        vmsr         fpscr,r1
+        hal_fpu_undo_enable
+        .endm
+
+//============================================================================
+// Make fake fpu frame for hal_pendable_svc_vsr
+
+        .macro hal_fpu_isr_fake_frame_push
+        sub        r12,#4
+        vmrs       r1,fpscr
+        stmdb      r12!,{r1}
+        vstmdb.f32 r12!,{s0-s15}
+        .endm
+
+# else // CYGINT_HAL_FPV4_SP_D16
+#  error Unknown Floating Point Unit!
+# endif // CYGINT_HAL_FPV4_SP_D16
+
+#endif //CYGHWR_HAL_CORTEXM_FPU
+
+// end of hal_arch.inc
diff --git a/ecos/packages/hal/cortexm/arch/current/include/hal_intr.h b/ecos/packages/hal/cortexm/arch/current/include/hal_intr.h
new file mode 100644
index 0000000..21745bd
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/hal_intr.h
@@ -0,0 +1,409 @@
+#ifndef CYGONCE_HAL_INTR_H
+#define CYGONCE_HAL_INTR_H
+/*==========================================================================
+//
+//      hal_intr.h
+//
+//      Cortex-M interrupt and clock abstractions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Description:  Define interrupt and clock abstractions
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_io.h>
+
+//==========================================================================
+// Exception vectors
+//
+// These are the common vectors defined by all Cortex-M CPUs.  The
+// exact number of vectors is variant specific, so the limits will be
+// defined in var_intr.h.
+
+
+#define CYGNUM_HAL_VECTOR_STACK          0      // Reset stack pointer
+#define CYGNUM_HAL_VECTOR_RESET          1      // Reset entry point
+#define CYGNUM_HAL_VECTOR_NMI            2      // Non-Maskable Interrupt
+#define CYGNUM_HAL_VECTOR_HARD_FAULT     3      // Hard fault
+#define CYGNUM_HAL_VECTOR_MEMORY_MAN     4      // Memory management (M3)
+#define CYGNUM_HAL_VECTOR_BUS_FAULT      5      // Bus Fault
+#define CYGNUM_HAL_VECTOR_USAGE_FAULT    6      // Usage Fault
+#define CYGNUM_HAL_VECTOR_RESERVED_07    7
+#define CYGNUM_HAL_VECTOR_RESERVED_08    8
+#define CYGNUM_HAL_VECTOR_RESERVED_09    9
+#define CYGNUM_HAL_VECTOR_RESERVED_10   10
+#define CYGNUM_HAL_VECTOR_SERVICE       11      // System service call
+#define CYGNUM_HAL_VECTOR_DEBUG         12      // Debug monitor (M3)
+#define CYGNUM_HAL_VECTOR_RESERVED_13   13
+#define CYGNUM_HAL_VECTOR_PENDSV        14      // Pendable svc request
+#define CYGNUM_HAL_VECTOR_SYS_TICK      15      // System timer tick
+#define CYGNUM_HAL_VECTOR_EXTERNAL      16      // Base of external interrupts
+
+
+//==========================================================================
+// Interrupt vectors
+//
+// The system tick interrupt is mapped to vector 0 and all external
+// interrupts are mapped from vector 1 up.
+
+#define CYGNUM_HAL_INTERRUPT_SYS_TICK    0
+#define CYGNUM_HAL_INTERRUPT_EXTERNAL    1
+
+
+//==========================================================================
+// Include variant definitions here.
+
+#include <cyg/hal/var_intr.h>
+
+// Variant or platform allowed to override these definitions to use
+// a different RTC
+#ifndef CYGNUM_HAL_INTERRUPT_RTC
+#define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_SYS_TICK
+#endif
+
+//==========================================================================
+// Exception vectors.
+//
+// These are the values used when passed out to an external exception
+// handler using cyg_hal_deliver_exception()
+
+#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS        CYGNUM_HAL_VECTOR_MEMORY_MAN
+#define CYGNUM_HAL_EXCEPTION_CODE_TLBMISS_ACCESS        CYGNUM_HAL_VECTOR_MEMORY_MAN
+#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS                CYGNUM_HAL_VECTOR_BUS_FAULT
+#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS                CYGNUM_HAL_VECTOR_BUS_FAULT
+#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION        CYGNUM_HAL_VECTOR_USAGE_FAULT
+#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS      CYGNUM_HAL_VECTOR_USAGE_FAULT
+#define CYGNUM_HAL_EXCEPTION_INTERRUPT                  CYGNUM_HAL_VECTOR_SERVICE
+
+
+#define CYGNUM_HAL_EXCEPTION_MIN     CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS
+#define CYGNUM_HAL_EXCEPTION_MAX     CYGNUM_HAL_EXCEPTION_INTERRUPT
+#define CYGNUM_HAL_EXCEPTION_COUNT   (CYGNUM_HAL_EXCEPTION_MAX - \
+                                      CYGNUM_HAL_EXCEPTION_MIN + 1)
+
+
+//==========================================================================
+// VSR handling
+
+__externC volatile CYG_ADDRESS   hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
+
+#ifndef HAL_VSR_GET
+#define HAL_VSR_GET( __vector, __pvsr )                         \
+    *(CYG_ADDRESS *)(__pvsr) = hal_vsr_table[__vector];
+#endif
+
+#ifndef HAL_VSR_SET
+#define HAL_VSR_SET( __vector, __vsr, __poldvsr )               \
+CYG_MACRO_START                                                 \
+    if( __poldvsr != NULL )                                     \
+        *(CYG_ADDRESS *)__poldvsr = hal_vsr_table[__vector];    \
+    hal_vsr_table[__vector] = (CYG_ADDRESS)__vsr;               \
+CYG_MACRO_END
+#endif
+
+#ifndef HAL_VSR_SET_TO_ECOS_HANDLER
+__externC void hal_default_interrupt_vsr( void );
+__externC void hal_default_exception_vsr( void );
+# define HAL_VSR_SET_TO_ECOS_HANDLER( __vector, __poldvsr )             \
+CYG_MACRO_START                                                         \
+    cyg_uint32  __vector2    = (cyg_uint32) (__vector);                 \
+    CYG_ADDRESS* __poldvsr2  = (CYG_ADDRESS*)(__poldvsr);               \
+    if( __vector2 < CYGNUM_HAL_VECTOR_SYS_TICK )                        \
+        HAL_VSR_SET(__vector2, &hal_default_exception_vsr, __poldvsr2); \
+    else                                                                \
+        HAL_VSR_SET(__vector2, &hal_default_interrupt_vsr, __poldvsr2); \
+CYG_MACRO_END
+#endif
+
+// Default definition of HAL_TRANSLATE_VECTOR(), a no-op
+#ifndef HAL_TRANSLATE_VECTOR
+# define HAL_TRANSLATE_VECTOR(__vector, __index) ((__index) = (__vector))
+#endif
+
+//==========================================================================
+// ISR handling
+//
+// Interrupt handler/data/object tables plus functions and macros to
+// manipulate them.
+
+__externC volatile CYG_ADDRESS   hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
+__externC volatile CYG_ADDRWORD  hal_interrupt_data    [CYGNUM_HAL_ISR_COUNT];
+__externC volatile CYG_ADDRESS   hal_interrupt_objects [CYGNUM_HAL_ISR_COUNT];
+
+//--------------------------------------------------------------------------
+// Interrupt delivery
+//
+// This function is used by the HAL to deliver an interrupt, and post
+// a DSR if required. It may also be used to deliver secondary
+// interrupts from springboard ISRs.
+
+__externC void hal_deliver_interrupt( cyg_uint32 vector );
+
+//--------------------------------------------------------------------------
+// Default ISR The #define is used to test whether this routine
+// exists, and to allow code outside the HAL to call it.
+
+externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
+#define HAL_DEFAULT_ISR hal_default_isr
+
+//--------------------------------------------------------------------------
+
+#define HAL_INTERRUPT_IN_USE( _vector_, _state_)                        \
+{                                                                       \
+    cyg_uint32 _index_;                                                 \
+    HAL_TRANSLATE_VECTOR ((_vector_), _index_);                         \
+                                                                        \
+    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
+        (_state_) = 0;                                                  \
+    else                                                                \
+        (_state_) = 1;                                                  \
+}
+
+#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ )       \
+{                                                                       \
+    if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \
+    {                                                                   \
+        hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_;          \
+        hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_;           \
+        hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_;        \
+    }                                                                   \
+}
+
+#define HAL_INTERRUPT_DETACH( _vector_, _isr_ )                         \
+{                                                                       \
+    if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ )        \
+    {                                                                   \
+        hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \
+        hal_interrupt_data[_vector_] = 0;                               \
+        hal_interrupt_objects[_vector_] = 0;                            \
+    }                                                                   \
+}
+
+//--------------------------------------------------------------------------
+// CPU interrupt control.
+//
+// We use the BASEPRI register to control delivery of interrupts. The
+// register is set to the second highest implemented priority for this
+// Cortex-M implementation to mask interrupts. It is set to zero to
+// enable interrupts, which will disable the BASEPRI mechanism.
+
+#ifndef __ASSEMBLER__
+typedef cyg_uint32  CYG_INTERRUPT_STATE;
+#endif
+
+#ifndef HAL_DISABLE_INTERRUPTS
+# define HAL_DISABLE_INTERRUPTS(__old)          \
+    __asm__ volatile (                          \
+        "mrs    %0, basepri             \n"     \
+        "mov    r1,%1                   \n"     \
+        "msr    basepri,r1              \n"     \
+        : "=&r" (__old)                         \
+        :  "r" (CYGNUM_HAL_CORTEXM_PRIORITY_MAX)\
+        : "r1"                                  \
+        );
+#endif
+
+#ifndef HAL_RESTORE_INTERRUPTS
+# define HAL_RESTORE_INTERRUPTS(__old)          \
+    __asm__ volatile (                          \
+        "msr    basepri, %0             \n"     \
+        :                                       \
+        : "r" (__old)                           \
+        );
+#endif
+
+#ifndef HAL_ENABLE_INTERRUPTS
+# define HAL_ENABLE_INTERRUPTS()                \
+    __asm__ volatile (                          \
+        "mov    r1,#0                   \n"     \
+        "msr    basepri,r1              \n"     \
+        :                                       \
+        :                                       \
+        : "r1"                                  \
+        );
+#endif
+
+#ifndef HAL_QUERY_INTERRUPTS
+#define HAL_QUERY_INTERRUPTS(__state)           \
+    __asm__ volatile (                          \
+        "mrs    %0, basepri             \n"     \
+        : "=r" (__state)                        \
+        );
+#endif
+
+//--------------------------------------------------------------------------
+// Interrupt masking and unmasking
+//
+// This is mostly done via the architecture defined NVIC. The
+// HAL_VAR_*() macros allow the variant HAL to provide extended
+// support for additional interrupt sources supported by supplementary
+// interrupt controllers.
+
+__externC void hal_interrupt_mask( cyg_uint32 vector );
+__externC void hal_interrupt_unmask( cyg_uint32 vector );
+__externC void hal_interrupt_set_level( cyg_uint32 vector, cyg_uint32 level );
+__externC void hal_interrupt_acknowledge( cyg_uint32 vector );
+__externC void hal_interrupt_configure( cyg_uint32 vector, cyg_uint32 level, cyg_uint32 up );
+
+
+#define HAL_INTERRUPT_MASK( __vector ) hal_interrupt_mask( __vector )
+#define HAL_INTERRUPT_UNMASK( __vector ) hal_interrupt_unmask( __vector )
+#define HAL_INTERRUPT_SET_LEVEL( __vector, __level ) hal_interrupt_set_level( __vector, __level )
+#define HAL_INTERRUPT_ACKNOWLEDGE( __vector ) hal_interrupt_acknowledge( __vector )
+#define HAL_INTERRUPT_CONFIGURE( __vector, __level, __up ) hal_interrupt_configure( __vector, __level, __up )
+
+//--------------------------------------------------------------------------
+// Routine to execute DSRs using separate interrupt stack
+
+__externC void hal_call_dsrs_vsr(void);
+#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS()         \
+{                                                       \
+    __asm__ volatile (                                  \
+        "ldr     r3,=hal_call_dsrs_vsr          \n"     \
+        "swi 0                                  \n"     \
+        :                                               \
+        :                                               \
+        : "r3"                                          \
+        );                                              \
+}
+
+//--------------------------------------------------------------------------
+
+#if 0
+// these are offered solely for stack usage testing
+// if they are not defined, then there is no interrupt stack.
+#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
+#define HAL_INTERRUPT_STACK_TOP  cyg_interrupt_stack
+// use them to declare these extern however you want:
+//       extern char HAL_INTERRUPT_STACK_BASE[];
+//       extern char HAL_INTERRUPT_STACK_TOP[];
+// is recommended
+#endif
+
+//==========================================================================
+// Clock control
+//
+// This uses the CPU SysTick timer. Variant or platform allowed to override
+// these definitions
+
+#ifndef CYGHWR_HAL_CLOCK_DEFINED
+
+__externC cyg_uint32 hal_cortexm_systick_clock;
+
+// Select the clock source of the system tick timer
+#ifdef CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_EXTERNAL
+ #define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_EXT
+#elif defined(CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_INTERNAL)
+ #define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_INT
+#endif
+
+#define HAL_CLOCK_INITIALIZE( __period )                                \
+{                                                                       \
+    cyg_uint32 __p = __period;                                          \
+    __p = hal_cortexm_systick_clock / ( 1000000 / __p ) - 1;            \
+    HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_RELOAD, \
+                     __p );                                             \
+    HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR,    \
+                     CYGARC_REG_SYSTICK_CSR_ENABLE      |               \
+                     CYGARC_REG_SYSTICK_CSR_CLK_SRC     );              \
+}
+
+#define HAL_CLOCK_RESET( __vector, __period )                           \
+{                                                                       \
+    cyg_uint32 __csr CYGBLD_ATTRIB_UNUSED;                              \
+    HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, __csr ); \
+}
+
+#define HAL_CLOCK_READ( __pvalue )                                      \
+{                                                                       \
+    cyg_uint32 __period, __value;                                       \
+    HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_RELOAD, __period ); \
+    HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_VALUE, __value ); \
+    __value = ( __period + 1 ) - __value;                               \
+    __value /= (hal_cortexm_systick_clock / 1000000 );                  \
+    *(__pvalue) = __value;                                              \
+}
+
+#define HAL_CLOCK_READ_NS( __pvalue )                                              \
+CYG_MACRO_START                                                                                  \
+    cyg_uint32 __period, __value;                                                  \
+    HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_RELOAD, __period ); \
+    HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_VALUE, __value );   \
+    __value = (( __period + 1 ) - __value) * 1000;                                          \
+    __value /= (hal_cortexm_systick_clock / 1000000 );                  \
+    *(__pvalue) = __value;                                                         \
+CYG_MACRO_END
+
+#define HAL_CLOCK_LATENCY( __pvalue ) HAL_CLOCK_READ( __pvalue )
+
+#endif // CYGHWR_HAL_CLOCK_DEFINED
+
+//==========================================================================
+// HAL_DELAY_US().
+//
+
+__externC void hal_delay_us( cyg_int32 us );
+#define HAL_DELAY_US( __us ) hal_delay_us( __us )
+
+//==========================================================================
+// Reset.
+//
+// This uses the SYSRESETREQ bit in the Cortex-M3 NVIC.
+
+#define HAL_PLATFORM_RESET()                                            \
+{                                                                       \
+    HAL_WRITE_UINT32(CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_AIRCR,        \
+                     CYGARC_REG_NVIC_AIRCR_KEY|                         \
+                     CYGARC_REG_NVIC_AIRCR_SYSRESETREQ );               \
+    for(;;);                                                            \
+}
+
+__externC void hal_reset_vsr( void );
+#define HAL_PLATFORM_RESET_ENTRY &hal_reset_vsr
+
+//==========================================================================
+#endif //CYGONCE_HAL_INTR_H
diff --git a/ecos/packages/hal/cortexm/arch/current/include/hal_io.h b/ecos/packages/hal/cortexm/arch/current/include/hal_io.h
new file mode 100644
index 0000000..c5df099
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/include/hal_io.h
@@ -0,0 +1,417 @@
+#ifndef CYGONCE_HAL_IO_H
+#define CYGONCE_HAL_IO_H
+/*==========================================================================
+//
+//      hal_io.h
+//
+//      Cortex-M architecture IO register definitions 
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Description:  Define IO registers
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/var_io.h>
+
+//==========================================================================
+// Handy macros for defining register bits and fields:
+//
+
+#define BIT_(__n)       (1<<(__n))
+#define MASK_(__n,__s)  (((1<<(__s))-1)<<(__n))
+#define VALUE_(__n,__v) ((__v)<<(__n))
+
+//==========================================================================
+// SysTick timer
+//
+// This is really part of the NVIC, but we break it out into a
+// separate definition for convenience.
+
+#define CYGARC_REG_SYSTICK_BASE                 0xE000E010
+
+#define CYGARC_REG_SYSTICK_CSR                  0
+#define CYGARC_REG_SYSTICK_RELOAD               4
+#define CYGARC_REG_SYSTICK_VALUE                8
+#define CYGARC_REG_SYSTICK_CAL                  12
+
+#define CYGARC_REG_SYSTICK_CSR_COUNTFLAG        BIT_(16)
+#define CYGARC_REG_SYSTICK_CSR_CLK_EXT          VALUE_(2,0)
+#define CYGARC_REG_SYSTICK_CSR_CLK_INT          VALUE_(2,1)
+#define CYGARC_REG_SYSTICK_CSR_TICKINT          BIT_(1)
+#define CYGARC_REG_SYSTICK_CSR_ENABLE           BIT_(0)
+
+#define CYGARC_REG_SYSTICK_CAL_NOREF            BIT_(31)
+#define CYGARC_REG_SYSTICK_CAL_SKEW             BIT_(30)
+#define CYGARC_REG_SYSTICK_CAL_TENMS            MASK_(0,23)
+
+//==========================================================================
+// NVIC registers
+
+#define CYGARC_REG_NVIC_BASE                    0xE000E000
+
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
+#define CYGARC_REG_NVIC_TYPE                    0x004
+#endif
+
+#define CYGARC_REG_NVIC_SER0                    0x100
+#define CYGARC_REG_NVIC_CER0                    0x180
+#define CYGARC_REG_NVIC_SPR0                    0x200
+#define CYGARC_REG_NVIC_CPR0                    0x280
+#define CYGARC_REG_NVIC_ABR0                    0x300
+#define CYGARC_REG_NVIC_PR0                     0x400
+
+// Generate address of 32 bit control register for interrupt
+#define CYGARC_REG_NVIC_SER(__intr)             (CYGARC_REG_NVIC_SER0+4*((__intr)>>5))
+#define CYGARC_REG_NVIC_CER(__intr)             (CYGARC_REG_NVIC_CER0+4*((__intr)>>5))
+#define CYGARC_REG_NVIC_SPR(__intr)             (CYGARC_REG_NVIC_SPR0+4*((__intr)>>5))
+#define CYGARC_REG_NVIC_CPR(__intr)             (CYGARC_REG_NVIC_CPR0+4*((__intr)>>5))
+#define CYGARC_REG_NVIC_ABR(__intr)             (CYGARC_REG_NVIC_ABR0+4*((__intr)>>5))
+
+// Generate bit in register for interrupt
+#define CYGARC_REG_NVIC_IBIT(__intr)            BIT_((__intr)&0x1F)
+
+// Generate byte address of interrupt's priority register.
+#define CYGARC_REG_NVIC_PR(__intr)              (CYGARC_REG_NVIC_PR0+(__intr))
+
+
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
+
+#define CYGARC_REG_NVIC_CPUID                   0xD00
+#define CYGARC_REG_NVIC_ICSR                    0xD04
+#define CYGARC_REG_NVIC_VTOR                    0xD08
+#define CYGARC_REG_NVIC_AIRCR                   0xD0C
+#define CYGARC_REG_NVIC_SCR                     0xD10
+#define CYGARC_REG_NVIC_CCR                     0xD14
+#define CYGARC_REG_NVIC_SHPR0                   0xD18
+#define CYGARC_REG_NVIC_SHPR1                   0xD1C
+#define CYGARC_REG_NVIC_SHPR2                   0xD20
+#define CYGARC_REG_NVIC_SHCSR                   0xD24
+#define CYGARC_REG_NVIC_CFSR                    0xD28
+#define CYGARC_REG_NVIC_HFSR                    0xD2C
+#define CYGARC_REG_NVIC_DFSR                    0xD30
+#define CYGARC_REG_NVIC_MMAR                    0xD34
+#define CYGARC_REG_NVIC_BFAR                    0xD38
+#define CYGARC_REG_NVIC_AFSR                    0xD3C
+#define CYGARC_REG_NVIC_PFR0                    0xD40
+#define CYGARC_REG_NVIC_PFR1                    0xD44
+#define CYGARC_REG_NVIC_DFR0                    0xD48
+#define CYGARC_REG_NVIC_AFR0                    0xD4C
+#define CYGARC_REG_NVIC_MMFR0                   0xD50
+#define CYGARC_REG_NVIC_MMFR1                   0xD54
+#define CYGARC_REG_NVIC_MMFR2                   0xD58
+#define CYGARC_REG_NVIC_MMFR3                   0xD5C
+#define CYGARC_REG_NVIC_ISAR0                   0xD60
+#define CYGARC_REG_NVIC_ISAR1                   0xD64
+#define CYGARC_REG_NVIC_ISAR2                   0xD68
+#define CYGARC_REG_NVIC_ISAR3                   0xD6C
+#define CYGARC_REG_NVIC_ISAR4                   0xD70
+#define CYGARC_REG_NVIC_STIR                    0xF00
+#define CYGARC_REG_NVIC_PID4                    0xFD0
+#define CYGARC_REG_NVIC_PID5                    0xFD4
+#define CYGARC_REG_NVIC_PID6                    0xFD8
+#define CYGARC_REG_NVIC_PID7                    0xFDC
+#define CYGARC_REG_NVIC_PID0                    0xFE0
+#define CYGARC_REG_NVIC_PID1                    0xFE4
+#define CYGARC_REG_NVIC_PID2                    0xFE8
+#define CYGARC_REG_NVIC_PID3                    0xFEC
+#define CYGARC_REG_NVIC_CID0                    0xFF0
+#define CYGARC_REG_NVIC_CID1                    0xFF4
+#define CYGARC_REG_NVIC_CID2                    0xFF8
+#define CYGARC_REG_NVIC_CID3                    0xFFC
+
+// ICSR
+
+#define CYGARC_REG_NVIC_ICSR_NMIPENDSET         BIT_(31)
+#define CYGARC_REG_NVIC_ICSR_PENDSVSET          BIT_(28)
+#define CYGARC_REG_NVIC_ICSR_PENDSVCLR          BIT_(27)
+#define CYGARC_REG_NVIC_ICSR_PENDSTSET          BIT_(26)
+#define CYGARC_REG_NVIC_ICSR_PENDSTCLR          BIT_(25)
+#define CYGARC_REG_NVIC_ICSR_ISRPREEMPT         BIT_(23)
+#define CYGARC_REG_NVIC_ICSR_ISRPENDING         BIT_(22)
+#define CYGARC_REG_NVIC_ICSR_VECTPENDING        MASK_(12,9)
+#define CYGARC_REG_NVIC_ICSR_RETTOBASE          BIT_(11)
+#define CYGARC_REG_NVIC_ICSR_VECTACTIVE         MASK_(0,9)
+
+// VTOR
+
+#define CYGARC_REG_NVIC_VTOR_TBLOFF(__o)        VALUE_(7,__o)
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_CODE       0
+#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM       BIT_(29)
+#endif
+
+// AI/RCR
+
+#define CYGARC_REG_NVIC_AIRCR_KEY               VALUE_(16,0x5FA)
+#define CYGARC_REG_NVIC_AIRCR_BIGENDIAN         BIT_(15)
+#define CYGARC_REG_NVIC_AIRCR_PRIGROUP(__p)     VALUE_(8,__p)
+#define CYGARC_REG_NVIC_AIRCR_SYSRESETREQ       BIT_(2)
+#define CYGARC_REG_NVIC_AIRCR_VECTCLRACTIVE     BIT_(1)
+#define CYGARC_REG_NVIC_AIRCR_VECTRESET         BIT_(0)
+
+// SCR
+
+#define CYGARC_REG_NVIC_SCR_SLEEPONEXIT         BIT_(1)
+#define CYGARC_REG_NVIC_SCR_DEEPSLEEP           BIT_(2)
+#define CYGARC_REG_NVIC_SCR_SEVONPEND           BIT_(4)
+
+// SHCSR
+
+#define CYGARC_REG_NVIC_SHCSR_USGFAULTENA       BIT_(18)
+#define CYGARC_REG_NVIC_SHCSR_BUSFAULTENA       BIT_(17)
+#define CYGARC_REG_NVIC_SHCSR_MEMFAULTENA       BIT_(16)
+#define CYGARC_REG_NVIC_SHCSR_SVCALLPENDED      BIT_(15)
+#define CYGARC_REG_NVIC_SHCSR_BUSFAULTPENDED    BIT_(14)
+#define CYGARC_REG_NVIC_SHCSR_MEMFAULTPENDED    BIT_(13)
+#define CYGARC_REG_NVIC_SHCSR_USGFAULTPENDED    BIT_(12)
+#define CYGARC_REG_NVIC_SHCSR_SYSTICKACT        BIT_(11)
+#define CYGARC_REG_NVIC_SHCSR_PENDSVACT         BIT_(10)
+#define CYGARC_REG_NVIC_SHCSR_MONITORACT        BIT_(8)
+#define CYGARC_REG_NVIC_SHCSR_SVCALLACT         BIT_(7)
+#define CYGARC_REG_NVIC_SHCSR_USGFAULTACT       BIT_(3)
+#define CYGARC_REG_NVIC_SHCSR_BUSFAULTACT       BIT_(1)
+#define CYGARC_REG_NVIC_SHCSR_MEMFAULTACT       BIT_(0)
+
+// Usage Fault register
+
+#define CYGARC_REG_UFSR                         0xE000ED2A
+#define CYGARC_REG_UFSR_DIVBYZERO               BIT_(9)
+#define CYGARC_REG_UFSR_UNALIGNED               BIT_(8)
+#define CYGARC_REG_UFSR_NOCP                    BIT_(3)
+#define CYGARC_REG_UFSR_INVPC                   BIT_(2)
+#define CYGARC_REG_UFSR_INVSTATE                BIT_(1)
+#define CYGARC_REG_UFSR_UNDEFINSTR              BIT_(0)
+
+#endif
+
+//==========================================================================
+// Debug registers
+
+#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
+
+#define CYGARC_REG_DEBUG_BASE                   0xE000EDF0
+
+#define CYGARC_REG_DEBUG_DHSR                   0x00
+#define CYGARC_REG_DEBUG_DCRSR                  0x04
+#define CYGARC_REG_DEBUG_DCRDR                  0x08
+#define CYGARC_REG_DEBUG_DEMCR                  0x0C
+
+
+#define CYGARC_REG_DEBUG_DHSR_DBGKEY            VALUE_(16,0xA05F)
+#define CYGARC_REG_DEBUG_DHSR_S_RESET           BIT_(25)
+#define CYGARC_REG_DEBUG_DHSR_S_RETIRE          BIT_(24)
+#define CYGARC_REG_DEBUG_DHSR_S_LOCKUP          BIT_(19)
+#define CYGARC_REG_DEBUG_DHSR_S_SLEEP           BIT_(18)
+#define CYGARC_REG_DEBUG_DHSR_S_HALT            BIT_(17)
+#define CYGARC_REG_DEBUG_DHSR_S_REGRDY          BIT_(16)
+#define CYGARC_REG_DEBUG_DHSR_C_SNAPSTALL       BIT_(5)
+#define CYGARC_REG_DEBUG_DHSR_C_MASKINTS        BIT_(3)
+#define CYGARC_REG_DEBUG_DHSR_C_STEP            BIT_(2)
+#define CYGARC_REG_DEBUG_DHSR_C_HALT            BIT_(1)
+#define CYGARC_REG_DEBUG_DHSR_C_DEBUGEN         BIT_(0)
+
+
+#define CYGARC_REG_DEBUG_DCRSR_REG_WRITE        BIT_(16)
+#define CYGARC_REG_DEBUG_DCRSR_REG_READ         0
+#define CYGARC_REG_DEBUG_DCRSR_REG(__x)         VALUE_(0,__x)
+
+
+#define CYGARC_REG_DEBUG_DEMCR_TRCENA           BIT_(24)
+#define CYGARC_REG_DEBUG_DEMCR_MON_REQ          BIT_(19)
+#define CYGARC_REG_DEBUG_DEMCR_MON_STEP         BIT_(18)
+#define CYGARC_REG_DEBUG_DEMCR_MON_PEND         BIT_(17)
+#define CYGARC_REG_DEBUG_DEMCR_MON_EN           BIT_(16)
+#define CYGARC_REG_DEBUG_DEMCR_VC_HARDERR       BIT_(10)
+#define CYGARC_REG_DEBUG_DEMCR_VC_INTERR        BIT_(9)
+#define CYGARC_REG_DEBUG_DEMCR_VC_BUSERR        BIT_(8)
+#define CYGARC_REG_DEBUG_DEMCR_VC_STATERR       BIT_(7)
+#define CYGARC_REG_DEBUG_DEMCR_VC_CHKERR        BIT_(6)
+#define CYGARC_REG_DEBUG_DEMCR_VC_NOCPERR       BIT_(5)
+#define CYGARC_REG_DEBUG_DEMCR_VC_MMERR         BIT_(4)
+#define CYGARC_REG_DEBUG_DEMCR_VC_CORERESET     BIT_(0)
+
+#endif
+
+//==========================================================================
+// IO Register address.
+// This type is for recording the address of an IO register.
+
+typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
+
+//-----------------------------------------------------------------------------
+// HAL IO macros.
+
+#ifndef HAL_IO_MACROS_DEFINED
+
+//-----------------------------------------------------------------------------
+// BYTE Register access.
+// Individual and vectorized access to 8 bit registers.
+
+
+#define HAL_READ_UINT8( _register_, _value_ ) \
+        ((_value_) = *((volatile CYG_BYTE *)(_register_)))
+
+#define HAL_WRITE_UINT8( _register_, _value_ ) \
+        (*((volatile CYG_BYTE *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_];        \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_];        \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ )             \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_i_];        \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ )            \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        ((volatile CYG_BYTE *)(_register_)) = (_buf_)[_i_];             \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// 16 bit access.
+// Individual and vectorized access to 16 bit registers.
+
+
+#define HAL_READ_UINT16( _register_, _value_ ) \
+        ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
+
+#define HAL_WRITE_UINT16( _register_, _value_ ) \
+        (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_];      \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_];      \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_)             \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_i_];      \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_)            \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        ((volatile CYG_WORD16 *)(_register_))[_i_] = (_buf_)[_i_];      \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// 32 bit access.
+// Individual and vectorized access to 32 bit registers.
+
+#define HAL_READ_UINT32( _register_, _value_ ) \
+        ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
+
+#define HAL_WRITE_UINT32( _register_, _value_ ) \
+        (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_];      \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )   \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_];      \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT32_STRING( _register_, _buf_, _count_)             \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_i_];      \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_)            \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        ((volatile CYG_WORD32 *)(_register_))[_i_] = (_buf_)[_i_];      \
+    CYG_MACRO_END
+
+
+#define HAL_IO_MACROS_DEFINED
+
+#endif // !HAL_IO_MACROS_DEFINED
+
+// Enforce a flow "barrier" to prevent optimizing compiler from reordering
+// operations.
+#define HAL_IO_BARRIER()
+
+
+//==========================================================================
+#endif //CYGONCE_HAL_IO_H
diff --git a/ecos/packages/hal/cortexm/arch/current/src/context.S b/ecos/packages/hal/cortexm/arch/current/src/context.S
new file mode 100644
index 0000000..0ebe186
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/src/context.S
@@ -0,0 +1,267 @@
+/*==========================================================================
+//
+//      context.S
+//
+//      Cortex-M context switch code
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg, ilijak (FPU support)
+// Contributor(s):
+// Date:           2008-07-30
+// Description:    This file contains thread context switch code.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/cortexm_fpu.h>        // Optional Floating Point Unit
+
+#endif
+
+//==========================================================================
+
+        .syntax unified
+        .thumb
+        .text
+
+//==========================================================================
+// Context switch
+//
+// R0 contains a pointer to the SP of the thread to load, R1 contains
+// a pointer to the SP of the current thread.
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+//==========================================================================
+// LAZY Context switch
+//
+// Save the FPU registers only for threads that use FPU.
+//
+
+        .globl  hal_thread_switch_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_switch_context, %function
+hal_thread_switch_context:
+
+        push      {r0-r12,lr}                       // Push all savable register
+        ldr       r7,=CYGARC_REG_FPU_CPACR          //
+        ldr       r6,[r7]
+        tst       r6,#CYGARC_REG_FPU_CPACR_ENABLE   // Is FPU enabled?
+        beq       lazy_float_push                   // N: Be lazy.
+        vmrs      r5,fpscr                          // Y: Save FPU context
+        vpush.f64 {d0-d15}                          //   Push FPU registers
+        push      {r5}                              //   together with FPSCR
+        mov       r2,#HAL_SAVEDREGISTERS_THREAD_FPU // Set state type: thread with FPU
+        b         float_push_join
+   lazy_float_push:
+        mov       r2,#HAL_SAVEDREGISTERS_THREAD
+        sub       sp,#HAL_SAVEDREGISTERS_FPU_THREAD_CONTEXT_SIZE
+   float_push_join:
+        mrs       r3,basepri                        // Get priority base register
+        mov       r4,sp                             // Get SP (for info only)
+        push      {r2-r4}                           // Push them
+        str       sp,[r1]                           // Save SP
+        // Fall through
+
+//--------------------------------------------------------------------------
+// Load context
+//
+// This is used to load a thread context, abandoning the current one. Following
+// function part is the second half of hal_thread_switch_context.
+
+
+        .globl  hal_thread_load_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_load_context, %function
+hal_thread_load_context_common:
+
+        ldr      sp,[r0]                // Load SP
+        pop      {r2-r4}                // Pop type, basepri, SP(discarded) and FPSCR
+        msr      basepri,r3             // Set BASEPRI
+        cmp      r2,#HAL_SAVEDREGISTERS_THREAD_FPU // Is state type a FP thread?
+        beq      real_float_pop // Y:
+                                // N: Be lazy
+        and      r6,#~CYGARC_REG_FPU_CPACR_ENABLE
+        add      sp,#HAL_SAVEDREGISTERS_FPU_THREAD_CONTEXT_SIZE
+        str      r6,[r7]
+        pop      {r0-r12,pc} // Pop all registers and return to an non-FP thread
+
+   real_float_pop: // Restore floating point context for FP thread.
+        orr      r6,#CYGARC_REG_FPU_CPACR_ENABLE
+        pop      {r5}           // Retrieve FPU status register
+        str      r6,[r7]
+        dsb
+        isb
+        vpop.f64 {d0-d15}       // Pestore FPU registers
+        vmsr     fpscr,r5       // Restore FPU status register
+        pop      {r0-r12,pc}    // Pop all registers and return to a FP thread.
+
+// Load context entry point
+// Load context initially needs CPACR register, so it is provided here.
+hal_thread_load_context:
+        ldr      r7,=CYGARC_REG_FPU_CPACR
+        ldr      r6,[r7]
+        b        hal_thread_load_context_common
+
+#elif defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+
+//==========================================================================
+// ALL Context switch
+//
+// Save the FPU registers for all threads.
+//
+
+        .globl  hal_thread_switch_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_switch_context, %function
+hal_thread_switch_context:
+
+        push      {r0-r12,lr}                       // Push all savable register
+        vmrs      r5,fpscr
+        mov       r2,#HAL_SAVEDREGISTERS_THREAD_FPU // Set state type == thread
+        vpush.f64 {d0-d15}                          // Push FPU registers
+        sub       r4,sp,#4                          // Get SP (for info only)
+        mrs       r3,basepri                        // Get priority base register
+        push      {r2-r5}                           // Push them
+        str       sp,[r1]                           // Save SP
+        // Fall through
+
+//--------------------------------------------------------------------------
+// Load context
+//
+// This is used to load a thread context, abandoning the current one. This
+// function is also the second half of hal_thread_switch_context.
+
+
+        .globl  hal_thread_load_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_load_context, %function
+hal_thread_load_context:
+
+        ldr      sp,[r0]                // Load SP
+        pop      {r2-r5}                // Pop type, basepri,SP(discarded) and FPSCR
+        msr      basepri,r3             // Set BASEPRI
+        vpop.f64 {d0-d15}               // Pop FPU registers
+        vmsr     fpscr,r5               // and FPU status register
+        pop      {r0-r12,pc}            // Pop all register and return
+
+#else
+
+//==========================================================================
+// NONE Context switch
+//
+// No FPU or NONE context saving scheme. Do not save FPU registers.
+//
+
+        .globl  hal_thread_switch_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_switch_context, %function
+hal_thread_switch_context:
+
+        push    {r0-r12,lr}             // Push all savable register
+        mov     r2,#2                   // Set state type == thread
+        mrs     r3,basepri              // Get priority base register
+        mov     r4,sp                   // Get SP (for info only)
+        push    {r2-r4}                 // Push them
+
+        str     sp,[r1]                 // Save SP
+
+        // Fall through
+
+//--------------------------------------------------------------------------
+// Load context
+//
+// This is used to load a thread context, abandoning the current one. This
+// function is also the second half of hal_thread_switch_context.
+
+        .globl  hal_thread_load_context
+        .thumb
+        .thumb_func
+        .type   hal_thread_load_context, %function
+hal_thread_load_context:
+
+        ldr     sp,[r0]                 // Load SP
+        pop     {r2-r4}                 // Pop type, basepri and SP (discarded)
+        msr     basepri,r3              // Set BASEPRI
+        pop     {r0-r12,pc}             // Pop all register and return
+
+#endif
+
+//==========================================================================
+//  HAL longjmp, setjmp implementations
+//
+//  hal_setjmp saves only to callee save registers R4-14
+//  and LR into buffer supplied in r0[arg0].
+
+        .globl  hal_setjmp
+        .thumb
+        .thumb_func
+        .type   hal_setjmp, %function
+hal_setjmp:
+        mov     r3,sp
+        stmea   r0,{r3-r12,r14}
+        mov     r0,#0
+        bx      lr
+
+//  hal_longjmp loads state from r0[arg0] and returns
+
+        .globl  hal_longjmp
+        .thumb
+        .thumb_func
+        .type   hal_longjmp, %function
+hal_longjmp:
+        ldmfd   r0,{r3-r12,r14}
+        mov     sp,r3
+        mov     r0,r1           // return [arg1]
+        bx      lr
+
+//==========================================================================
+// EOF context.S
diff --git a/ecos/packages/hal/cortexm/arch/current/src/cortexm.ld b/ecos/packages/hal/cortexm/arch/current/src/cortexm.ld
new file mode 100644
index 0000000..9b6c65c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/src/cortexm.ld
@@ -0,0 +1,279 @@
+//=============================================================================
+//
+// MLT linker script for Cortex-M
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+STARTUP(vectors.o)
+ENTRY(reset_vector)
+INPUT(extras.o)
+GROUP(libtarget.a libgcc.a libsupc++.a)
+
+#if defined(__ARMEB__)
+OUTPUT_FORMAT(elf32-bigarm)
+#endif
+
+// ALIGN_LMA is 4, but the AAPCS now requires that double word types
+// be aligned to 8, which means some input sections can be marked as needing
+// 8-byte alignment, even text ones (consider literal data).
+
+#define ALIGN_LMA 4
+#define AAPCS_ALIGN 8
+#define FOLLOWING_ALIGNED(_section_, _align_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + (_align_) - 1) & ~ ((_align_) - 1))
+#define FOLLOWING(_section_) FOLLOWING_ALIGNED(_section_, ALIGN_LMA)
+
+#define LMA_EQ_VMA
+#define FORCE_OUTPUT . = .
+
+// Some versions of gcc define "arm" which causes problems with .note.arm.ident
+#undef arm
+#define SECTIONS_BEGIN                          \
+  /* Debug information */                       \
+  .debug_aranges  0 : { *(.debug_aranges) }     \
+  .debug_pubnames 0 : { *(.debug_pubnames) }    \
+  .debug_info     0 : { *(.debug_info) }        \
+  .debug_abbrev   0 : { *(.debug_abbrev) }      \
+  .debug_line     0 : { *(.debug_line) }        \
+  .debug_frame    0 : { *(.debug_frame) }       \
+  .debug_str      0 : { *(.debug_str) }         \
+  .debug_loc      0 : { *(.debug_loc) }         \
+  .debug_macinfo  0 : { *(.debug_macinfo) }     \
+  .note.arm.ident 0 : { KEEP (*(.note.arm.ident)) } \
+  /DISCARD/       0 : { *(.fini_array*) }
+
+
+// Following not used unless CYGHWR_HAL_ARM_SEPARATE_VSR_TABLE
+// defined in hal_platform_setup.h. Otherwise vsr table
+// goes in .fixed_vectors.
+#define SECTION_hal_vsr_table(_region_, _vma_, _lma_) \
+    .hal_vsr_table _vma_ : _lma_ \
+    { FORCE_OUTPUT; KEEP (*(.hal_vsr_table)) } \
+    > _region_
+
+#define SECTION_fixed_vectors(_region_, _vma_, _lma_) \
+    .fixed_vectors _vma_ : _lma_ \
+    { FORCE_OUTPUT; KEEP (*(.fixed_vectors)) } \
+    > _region_
+
+#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
+    .rom_vectors _vma_ : _lma_ \
+    { __rom_vectors_vma = ABSOLUTE(.); \
+      FORCE_OUTPUT; KEEP (*(.vectors)) } \
+    > _region_ \
+    __rom_vectors_lma = LOADADDR(.rom_vectors);
+
+// We slot in the .ARM.extab and .ARM.exidx sections first. They
+// need to be close to .text due to their relocations which may
+// want small offsets - .rodata may be somewhere very different.
+// This approach also allows forward compatibility with targets
+// which haven't used the EABI before (no new SECTION_xxx definition
+// to use).
+// One glitch is that the AAPCS can require up to 8-byte alignment
+// for double word types. For sections after the first (for which we
+// "trust" the MLT files (probably a mistake)), we need to
+// ensure the subsequent sections' VMA and LMA move in sync, which
+// means keeping the same alignment, and thus since for example literal
+// data in .text can require up to 8 byte alignment, the LMA must also
+// be 8 byte aligned.
+#define SECTION_text(_region_, _vma_, _lma_) \
+    .ARM.extab _vma_ : _lma_ \
+    { PROVIDE (__stext = ABSOLUTE(.));_stext = ABSOLUTE(.) ; \
+    FORCE_OUTPUT; \
+    *(.ARM.extab* .gnu.linkonce.armextab.*) } > _region_ \
+    . = ALIGN(AAPCS_ALIGN); \
+    __exidx_start = ABSOLUTE(.); \
+    .ARM.exidx ALIGN(AAPCS_ALIGN) : FOLLOWING_ALIGNED(.ARM.extab, AAPCS_ALIGN) { \
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*) \
+    FORCE_OUTPUT; \
+    } > _region_ \
+    __exidx_end = ABSOLUTE(.);\
+    .text ALIGN(AAPCS_ALIGN) : FOLLOWING_ALIGNED(.ARM.exidx, AAPCS_ALIGN) \
+    { \
+    *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \
+    *(.glue_7) *(.glue_7t)  \
+    __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \
+    __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \
+    } > _region_ \
+    _etext = .; PROVIDE (__etext = .);
+
+#define SECTION_fini(_region_, _vma_, _lma_) \
+    .fini _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.fini) } \
+    > _region_
+
+#define SECTION_rodata(_region_, _vma_, _lma_) \
+    .rodata _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.rodata*) *(.gnu.linkonce.r.*) } \
+    > _region_
+
+#define SECTION_rodata1(_region_, _vma_, _lma_) \
+    .rodata1 _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.rodata1) } \
+    > _region_
+
+#define SECTION_fixup(_region_, _vma_, _lma_) \
+    .fixup _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.fixup) } \
+    > _region_
+
+#define SECTION_gcc_except_table(_region_, _vma_, _lma_)      \
+    .gcc_except_table _vma_ : _lma_                           \
+    { FORCE_OUTPUT;                                           \
+      KEEP(*(.gcc_except_table))                              \
+      *(.gcc_except_table.*)                                  \
+    } > _region_
+
+#define SECTION_eh_frame(_region_, _vma_, _lma_)      \
+  .eh_frame _vma_ : _lma_                             \
+    {                                                 \
+       FORCE_OUTPUT;  __EH_FRAME_BEGIN__ = .;         \
+       KEEP(*(.eh_frame))                             \
+       __FRAME_END__ = .;                             \
+       . = . + 8;                                     \
+    } > _region_ = 0
+
+#define SECTION_RELOCS(_region_, _vma_, _lma_)                              \
+  .rel.text      :                                                          \
+    {                                                                       \
+      *(.rel.text)                                                          \
+      *(.rel.text.*)                                                        \
+      *(.rel.gnu.linkonce.t*)                                               \
+    } > _region_                                                            \
+  .rela.text     :                                                          \
+    {                                                                       \
+      *(.rela.text)                                                         \
+      *(.rela.text.*)                                                       \
+      *(.rela.gnu.linkonce.t*)                                              \
+    } > _region_                                                            \
+  .rel.data      :                                                          \
+    {                                                                       \
+      *(.rel.data)                                                          \
+      *(.rel.data.*)                                                        \
+      *(.rel.gnu.linkonce.d*)                                               \
+    } > _region_                                                            \
+  .rela.data     :                                                          \
+    {                                                                       \
+      *(.rela.data)                                                         \
+      *(.rela.data.*)                                                       \
+      *(.rela.gnu.linkonce.d*)                                              \
+    } > _region_                                                            \
+  .rel.rodata    :                                                          \
+    {                                                                       \
+      *(.rel.rodata)                                                        \
+      *(.rel.rodata.*)                                                      \
+      *(.rel.gnu.linkonce.r*)                                               \
+    } > _region_                                                            \
+  .rela.rodata   :                                                          \
+    {                                                                       \
+      *(.rela.rodata)                                                       \
+      *(.rela.rodata.*)                                                     \
+      *(.rela.gnu.linkonce.r*)                                              \
+    } > _region_                                                            \
+  .rel.got       :   { *(.rel.got)    } > _region_                          \
+  .rela.got      :   { *(.rela.got)   } > _region_                          \
+  .rel.ctors     :   { *(.rel.ctors)  } > _region_                          \
+  .rela.ctors    :   { *(.rela.ctors) } > _region_                          \
+  .rel.dtors     :   { *(.rel.dtors)  } > _region_                          \
+  .rela.dtors    :   { *(.rela.dtors) } > _region_                          \
+  .rel.init      :   { *(.rel.init)   } > _region_                          \
+  .rela.init     :   { *(.rela.init)  } > _region_                          \
+  .rel.fini      :   { *(.rel.fini)   } > _region_                          \
+  .rela.fini     :   { *(.rela.fini)  } > _region_                          \
+  .rel.bss       :   { *(.rel.bss)    } > _region_                          \
+  .rela.bss      :   { *(.rela.bss)   } > _region_                          \
+  .rel.plt       :   { *(.rel.plt)    } > _region_                          \
+  .rela.plt      :   { *(.rela.plt)   } > _region_                          \
+  .rel.dyn       :   { *(.rel.dyn)    } > _region_
+
+#define SECTION_got(_region_, _vma_, _lma_)                                 \
+  .got _vma_ : _lma_                                                        \
+    {                                                                       \
+      FORCE_OUTPUT; *(.got.plt) *(.got)                                     \
+      _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.);      \
+      _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.);      \
+    } > _region_
+
+#define SECTION_mmu_tables(_region_, _vma_, _lma_) \
+    .mmu_tables _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.mmu_tables) } \
+    > _region_
+
+#define SECTION_sram(_region_, _vma_, _lma_) \
+    .sram _vma_ : _lma_ \
+    { __sram_data_start = ABSOLUTE (.); \
+    *(.sram*) . = ALIGN (4); } \
+    > _region_ \
+    __srom_data_start = LOADADDR (.sram); \
+    __sram_data_end = .; PROVIDE (__sram_data_end = .); \
+    PROVIDE (__srom_data_end = LOADADDR (.sram) + SIZEOF(.sram));
+
+#define SECTION_data(_region_,  _vma_, _lma_) \
+    .data _vma_ : _lma_ \
+    { __ram_data_start = ABSOLUTE (.); \
+    *(.data*) *(.data1) *(.gnu.linkonce.d.*) \
+    . = ALIGN (4); \
+    KEEP(*( SORT (.ecos.table.*))) ;            \
+    . = ALIGN (4); \
+    __init_array_start__ = ABSOLUTE (.); KEEP (*(SORT (.init_array.*))) \
+    KEEP (*(SORT (.init_array))) __init_array_end__ = ABSOLUTE (.); \
+    *(.dynamic) *(.sdata*) *(.gnu.linkonce.s.*) \
+    . = ALIGN (4); *(.2ram.*) } \
+    > _region_ \
+    __rom_data_start = LOADADDR (.data); \
+    __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); \
+    PROVIDE (__rom_data_end = LOADADDR (.data) + SIZEOF(.data));
+
+#define SECTION_bss(_region_,  _vma_, _lma_) \
+    .bss _vma_ : _lma_ \
+    { __bss_start = ABSOLUTE (.); \
+    *(.scommon) *(.dynsbss) *(.sbss*) *(.gnu.linkonce.sb.*) \
+    *(.dynbss) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON) \
+    __bss_end = ABSOLUTE (.); } \
+    > _region_
+
+#define USER_SECTION(_name_, _region_,  _vma_, _lma_) \
+    ._name_ _vma_ : _lma_ \
+    { __ ## _name_ ## _start = ABSOLUTE (.); \
+     *(._name_*) \
+    __ ## _name_ ## _end = ABSOLUTE (.); } \
+    > _region_
+
+#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .);
+
+#include <pkgconf/hal_cortexm.h>
+#include CYGHWR_MEMORY_LAYOUT_LDI
diff --git a/ecos/packages/hal/cortexm/arch/current/src/cortexm_fpu.c b/ecos/packages/hal/cortexm/arch/current/src/cortexm_fpu.c
new file mode 100644
index 0000000..dd0975e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/src/cortexm_fpu.c
@@ -0,0 +1,97 @@
+/*==========================================================================
+//
+//      cortexm_fpu.c
+//
+//      Cortex-M exception vectors
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-05-30
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/cortexm_regs.h>       // Special Cortex-M asm instructions
+
+#include <cyg/hal/cortexm_fpu.h>        // Optional Floating Point Unit
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+//============================================================================
+// FPU Usage Fault VSR handler
+// Execution of Floating Point instruction when FPU is disabled
+// generates usage fault exception. In LAZY context switching scheme
+// it is used for detection of FPU usage by threads.
+//
+cyg_uint32 hal_deliver_usagefault_fpu_exception(void) {
+    cyg_uint32 regval;
+
+    HAL_READ_UINT32(CYGARC_REG_FPU_CPACR, regval);
+    if(!((regval & CYGARC_REG_FPU_CPACR_ENABLE) ^ CYGARC_REG_FPU_CPACR_ENABLE)){
+        CYG_FAIL("Usage fault exception other than FPU!!!");
+    } else {
+        HAL_READ_UINT32(CYGARC_REG_UFSR, regval);
+        if(regval & CYGARC_REG_UFSR_NOCP){
+            // Floating point instruction has occured
+            // Enable FPU
+            HAL_CORTEXM_FPU_ENABLE();
+            CYGARC_VMSR(fpscr, 0);
+            HAL_MEMORY_BARRIER();
+            HAL_WRITE_UINT32(CYGARC_REG_UFSR, CYGARC_REG_UFSR_NOCP);
+        } else {
+            CYG_FAIL("Usage fault exception other than FPU/NOCP!!!");
+        }
+    }
+    HAL_READ_UINT32(CYGARC_REG_UFSR, regval);
+    return regval;
+}
+#endif // CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+//==========================================================================
+// EOF cortexm_fpu.c
diff --git a/ecos/packages/hal/cortexm/arch/current/src/cortexm_stub.c b/ecos/packages/hal/cortexm/arch/current/src/cortexm_stub.c
new file mode 100644
index 0000000..e232c9e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/src/cortexm_stub.c
@@ -0,0 +1,290 @@
+/*==========================================================================
+//
+//      cortexm_stub.c
+//
+//      Cortex-M GDB stub support
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak, jifl
+// Date:           2008-07-30
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <stddef.h>
+
+#include <pkgconf/hal.h>
+
+#ifdef CYGPKG_REDBOOT
+#include <pkgconf/redboot.h>
+#endif
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_stub.h>
+
+//==========================================================================
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE  1
+#endif
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+#include <cyg/hal/dbg-threads-api.h>    // dbg_currthread_id
+#endif
+
+//==========================================================================
+/* Given a trap value TRAP, return the corresponding signal. */
+
+int __computeSignal (unsigned int trap_number)
+{
+    switch (trap_number)
+    {
+    case CYGNUM_HAL_VECTOR_BUS_FAULT:      // Fall through
+    case CYGNUM_HAL_VECTOR_MEMORY_MAN:     // Fall through
+        return SIGBUS;
+    case CYGNUM_HAL_VECTOR_NMI:
+    case CYGNUM_HAL_VECTOR_SYS_TICK:
+        return SIGINT;
+    case CYGNUM_HAL_VECTOR_USAGE_FAULT:
+        return SIGFPE;
+    default:
+        return SIGTRAP;
+    }
+}
+
+
+//==========================================================================
+/* Return the trap number corresponding to the last-taken trap. */
+
+int __get_trap_number (void)
+{
+    // The vector is not not part of the GDB register set so get it
+    // directly from the save context.
+    return _hal_registers->u.exception.vector;
+}
+
+
+//==========================================================================
+// Set the currently-saved pc register value to PC.
+
+void set_pc (target_register_t pc)
+{
+    put_register (PC, pc);
+}
+
+//==========================================================================
+// Calculate byte offset a given register from start of register save area.
+
+static int
+reg_offset(regnames_t reg)
+{
+    int reg_i, offset = 0;
+
+    for(reg_i = 0; reg_i < NUMREGS; reg_i++) {
+        if(reg_i == reg)
+            break;
+        offset += REGSIZE(reg_i);
+    }
+    return (NUMREGS == reg_i || 0 == REGSIZE(reg_i)) ? -1 : offset;
+}
+
+//==========================================================================
+// Return the currently-saved value corresponding to register REG of
+// the exception context.
+
+target_register_t
+get_register (regnames_t reg)
+{
+    target_register_t val;
+    int offset = reg_offset(reg);
+
+    if (REGSIZE(reg) > sizeof(target_register_t) || offset == -1)
+        return -1;
+
+    val = _registers[offset/sizeof(target_register_t)];
+
+    return val;
+}
+
+//==========================================================================
+// Store VALUE in the register corresponding to WHICH in the exception
+// context.
+
+void
+put_register (regnames_t which, target_register_t value)
+{
+    int offset = reg_offset(which);
+
+    if (REGSIZE(which) > sizeof(target_register_t) || offset == -1)
+        return;
+
+    _registers[offset/sizeof(target_register_t)] = value;
+}
+
+//==========================================================================
+// Write the contents of register WHICH into VALUE as raw bytes. This
+// is only used for registers larger than sizeof(target_register_t).
+// Return non-zero if it is a valid register.
+
+int
+get_register_as_bytes (regnames_t which, char *value)
+{
+    int offset = reg_offset(which);
+
+    if (offset != -1) {
+        memcpy (value, (char *)_registers + offset, REGSIZE(which));
+        return 1;
+    }
+    return 0;
+}
+
+//==========================================================================
+// Alter the contents of saved register WHICH to contain VALUE. This
+// is only used for registers larger than sizeof(target_register_t).
+// Return non-zero if it is a valid register.
+
+int
+put_register_as_bytes (regnames_t which, char *value)
+{
+    int offset = reg_offset(which);
+
+    if (offset != -1) {
+        memcpy ((char *)_registers + offset, value, REGSIZE(which));
+        return 1;
+    }
+    return 0;
+}
+
+//==========================================================================
+// Single step the processor.
+//
+// We do this by setting the MON_STEP bit in the DEMCR. So long as we
+// are in a DebugMonitor exception this will single step the CPU on
+// return.
+// We also need to block all pending interrupts by setting basepri
+// before doing the step. Otherwise an interrupt may be delivered
+// before the step happens, and may cause unpleasant things to happen.
+
+cyg_uint32 __single_step_basepri = 0;
+
+void __single_step (void)
+{
+    CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE;
+    cyg_uint32 demcr;
+
+    // Save basepri and set it to mask all interrupts.
+    __single_step_basepri = _hal_registers->u.exception.basepri;
+    _hal_registers->u.exception.basepri = CYGNUM_HAL_CORTEXM_PRIORITY_MAX;
+
+    // Set MON_STEP
+    HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
+    demcr |= CYGARC_REG_DEBUG_DEMCR_MON_STEP;
+    HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
+
+    // Clear any bits set in DFSR
+    base = CYGARC_REG_NVIC_BASE;
+    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );
+
+}
+
+//==========================================================================
+// Clear the single-step state.
+
+void __clear_single_step (void)
+{
+    CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE;
+    cyg_uint32 demcr;
+
+    // Restore basepri
+    _hal_registers->u.exception.basepri = __single_step_basepri;
+
+    // Clear MON_STEP
+    HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
+    demcr &= ~CYGARC_REG_DEBUG_DEMCR_MON_STEP;
+    HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
+
+    // Clear any bits set in DFSR
+    base = CYGARC_REG_NVIC_BASE;
+    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );
+}
+
+//==========================================================================
+
+void __install_breakpoints (void)
+{
+    __install_breakpoint_list();
+}
+
+//--------------------------------------------------------------------------
+
+void __clear_breakpoints (void)
+{
+    __clear_breakpoint_list();
+}
+
+//--------------------------------------------------------------------------
+/* If the breakpoint we hit is in the breakpoint() instruction, return a
+   non-zero value. */
+
+int
+__is_breakpoint_function ()
+{
+    return get_register (PC) == (target_register_t)&_breakinst;
+}
+
+
+//--------------------------------------------------------------------------
+/* Skip the current instruction.  Since this is only called by the
+   stub when the PC points to a breakpoint or trap instruction,
+   we can safely just skip 2. */
+
+void __skipinst (void)
+{
+    unsigned long pc = get_register(PC);
+    pc += 2;
+    put_register(PC, pc);
+}
+
+//==========================================================================
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
diff --git a/ecos/packages/hal/cortexm/arch/current/src/fpv4_sp_d16.c b/ecos/packages/hal/cortexm/arch/current/src/fpv4_sp_d16.c
new file mode 100644
index 0000000..6348590
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/src/fpv4_sp_d16.c
@@ -0,0 +1,105 @@
+//==========================================================================
+//
+//      fpv4_sp_d16.c
+//
+//      FPv4-SP-D16 support
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-05-30
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/cortexm_regs.h>       // Special Cortex-M asm instructions
+
+#include <cyg/hal/cortexm_fpu.h>        // Optional Floating Point Unit
+
+
+#define CYGARC_REG_NVIC_ACTLR                   (CYGARC_REG_NVIC_BASE + 0x008)
+#define CYGARC_REG_NVIC_ACTLR_DISFCA            BIT_(8)
+//==========================================================================
+// FPU is disbled upon reset. Dependent on FPU context switching model it
+// may be enabled.
+
+void hal_init_fpu(void)
+{
+    cyg_uint32 regval;
+
+    // Initialize FPU according to context switch model.
+    // Disable FPU so we could access FPCCR
+    HAL_CORTEXM_FPU_DISABLE();
+
+#if defined CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+    // Enable automatic exception FPU context saving.
+    HAL_READ_UINT32(CYGARC_REG_FPU_FPCCR, regval);
+    regval |= CYGARC_REG_FPU_FPCCR_LSPEN | CYGARC_REG_FPU_FPCCR_ASPEN;
+    HAL_WRITE_UINT32(CYGARC_REG_FPU_FPCCR, regval);
+    HAL_MEMORY_BARRIER();
+#else
+    // Disable automatic exception FPU context saving.
+    CYGARC_MRS(regval, control);
+    regval &= ~CYGARC_REG_CONTROL_FPCA_M;
+    CYGARC_MSR(control, regval);
+    HAL_READ_UINT32(CYGARC_REG_FPU_FPCCR, regval);
+    regval &= ~(CYGARC_REG_FPU_FPCCR_LSPEN | CYGARC_REG_FPU_FPCCR_ASPEN);
+    HAL_WRITE_UINT32(CYGARC_REG_FPU_FPCCR, regval);
+    HAL_MEMORY_BARRIER();
+#endif
+
+#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_NONE || \
+    defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL
+    // Enable FPU
+    HAL_CORTEXM_FPU_ENABLE();
+    CYGARC_VMSR(fpscr, 0);
+#endif
+}
+
+//==========================================================================
+// EOF fpv4_sp_d16.c
diff --git a/ecos/packages/hal/cortexm/arch/current/src/hal_misc.c b/ecos/packages/hal/cortexm/arch/current/src/hal_misc.c
new file mode 100644
index 0000000..6e74852
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/src/hal_misc.c
@@ -0,0 +1,720 @@
+/*==========================================================================
+//
+//      hal_misc.c
+//
+//      Cortex-M exception vectors
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2008-07-30
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/cortexm_regs.h>       // Special Cortex-M asm instructions
+#include <cyg/hal/drv_api.h>
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+#include <cyg/hal/cortexm_fpu.h>        // Optional Floating Point Unit
+#endif
+
+#if defined(CYGPKG_KERNEL_INSTRUMENT) &&        \
+    defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
+#include <cyg/kernel/instrmnt.h>
+#endif
+
+//==========================================================================
+
+typedef cyg_uint32 cyg_isr(cyg_uint32 vector, CYG_ADDRWORD data);
+
+//==========================================================================
+// External references
+
+// VSRs in vectors.S
+__externC void hal_default_exception_vsr( void );
+__externC void hal_default_interrupt_vsr( void );
+__externC void hal_default_svc_vsr( void );
+__externC void hal_pendable_svc_vsr( void );
+__externC void hal_switch_state_vsr( void );
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+__externC void hal_usagefault_exception_vsr( void );
+#endif
+
+// HAL and eCos functions
+__externC void hal_system_init( void );
+__externC void hal_variant_init( void );
+__externC void hal_platform_init( void );
+__externC void hal_ctrlc_isr_init( void );
+__externC void initialize_stub( void );
+__externC void cyg_hal_invoke_constructors( void );
+__externC void cyg_start( void );
+__externC void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
+__externC void interrupt_end(cyg_uint32 isr_ret, CYG_ADDRWORD intr, HAL_SavedRegisters *regs );
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+// Scheduler lock
+__externC volatile cyg_uint32 cyg_scheduler_sched_lock;
+
+//==========================================================================
+// Interrupt tables
+
+volatile CYG_ADDRESS   hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
+volatile CYG_ADDRWORD  hal_interrupt_data    [CYGNUM_HAL_ISR_COUNT];
+volatile CYG_ADDRESS   hal_interrupt_objects [CYGNUM_HAL_ISR_COUNT];
+
+//==========================================================================
+// Main entry point
+//
+// Enter here from reset via slot 1 of VSR table. The stack pointer is
+// already set to the value in VSR slot 0, usually the top of internal
+// SRAM.
+
+void hal_reset_vsr( void )
+{
+    // Call system init routine. This should do the minimum necessary
+    // for the rest of the initialization to complete. For example set
+    // up GPIO, the SRAM, power management etc. This routine is
+    // usually supplied by the platform HAL. Calls to
+    // hal_variant_init() and hal_platform_init() later will perform
+    // the main initialization.
+
+    hal_system_init();
+#if defined CYGHWR_HAL_CORTEXM_FPU
+    // Floating Point Unit is disabled after reset.
+    // Enable it unless for LAZY context switching scheme.
+    hal_init_fpu();
+#endif
+
+    // Initialize vector table in base of SRAM.
+    {
+        register int i;
+
+#if !defined(CYG_HAL_STARTUP_RAM)
+
+        // Only install the exception vectors for non-RAM startup. For
+        // RAM startup we want these to continue to point to the original
+        // VSRs, which will belong to RedBoot or GDB stubs.
+
+        for( i = 2; i < 15; i++ )
+            hal_vsr_table[i] = (CYG_ADDRESS)hal_default_exception_vsr;
+#endif // !defined(CYG_HAL_STARTUP_RAM)
+        // Always point SVC and PENDSVC vectors to our local versions
+
+        hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
+        hal_vsr_table[CYGNUM_HAL_VECTOR_PENDSV] = (CYG_ADDRESS)hal_pendable_svc_vsr;
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+        // Install UsageFault and HardFault to trap the FPU usage exceptions.
+        HAL_VSR_SET(CYGNUM_HAL_VECTOR_USAGE_FAULT, hal_usagefault_exception_vsr, NULL);
+        HAL_VSR_SET(CYGNUM_HAL_VECTOR_HARD_FAULT, hal_usagefault_exception_vsr, NULL);
+#endif // CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+        // For all startup type, redirect interrupt vectors to our VSR.
+        for( i = CYGNUM_HAL_VECTOR_SYS_TICK ;
+             i < CYGNUM_HAL_VSR_MAX;
+             i++ )
+            hal_vsr_table[i] = (CYG_ADDRESS)hal_default_interrupt_vsr;
+    }
+
+#if !defined(CYG_HAL_STARTUP_RAM)
+
+    // Ensure that the CPU will use the vector table we have just set
+    // up.
+
+# if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4)
+
+    // On M3 and M4 parts, the NVIC contains a vector table base register.
+    // We program this to relocate the vector table base to the base of SRAM.
+
+    HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR,
+                      CYGARC_REG_NVIC_VTOR_TBLOFF(0)|
+                      CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM );
+
+# else
+
+#  error Unknown SRAM/VECTAB remap mechanism
+
+# endif
+
+    // Use SVC to switch our state to thread mode running on the PSP.
+    // We don't need to do this for RAM startup since the ROM code
+    // will have already done it.
+
+    hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;
+
+    __asm__ volatile( "swi 0" );
+
+    hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
+
+#endif // !defined(CYG_HAL_STARTUP_RAM)
+
+#if defined(CYG_HAL_STARTUP_ROM)
+    // Relocate data from ROM to RAM
+    {
+        register cyg_uint32 *p, *q;
+        for( p = &__ram_data_start, q = &__rom_data_start;
+             p < &__ram_data_end;
+             p++, q++ )
+            *p = *q;
+    }
+
+    // Relocate data from ROM to SRAM
+    {
+        register cyg_uint32 *p, *q;
+        for( p = &__sram_data_start, q = &__srom_data_start;
+             p < &__sram_data_end;
+             p++, q++ )
+            *p = *q;
+    }
+#endif
+
+    // Clear BSS
+    {
+        register cyg_uint32 *p;
+        for( p = &__bss_start; p < &__bss_end; p++ )
+            *p = 0;
+    }
+
+    // Initialize interrupt vectors. Set the levels for all interrupts
+    // to default values. Also set the default priorities of the
+    // system handlers: all exceptions maximum priority except SVC and
+    // PendSVC which are lowest priority.
+    {
+        register int i;
+
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR0, 0x00000000 );
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR1, 0xFF000000 );
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, 0x00FF0000 );
+
+        hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SYS_TICK] = (CYG_ADDRESS)hal_default_isr;
+
+        for( i = 1; i < CYGNUM_HAL_ISR_COUNT; i++ )
+        {
+            hal_interrupt_handlers[i] = (CYG_ADDRESS)hal_default_isr;
+            HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(i-CYGNUM_HAL_INTERRUPT_EXTERNAL), 0x80 );
+        }
+    }
+
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+    // Enable DebugMonitor exceptions. This is needed to enable single
+    // step. This only has an effect if no external JTAG device is
+    // attached.
+    {
+        CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE;
+        cyg_uint32 demcr;
+
+        HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
+        demcr |= CYGARC_REG_DEBUG_DEMCR_MON_EN;
+        HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
+    }
+#endif
+
+#if !defined(CYG_HAL_STARTUP_RAM)
+    // Enable Usage, Bus and Mem fault handlers. Do this for ROM and
+    // JTAG startups. For RAM startups, this will have already been
+    // done by the ROM monitor.
+    {
+        CYG_ADDRESS base = CYGARC_REG_NVIC_BASE;
+        cyg_uint32 shcsr;
+
+        HAL_READ_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
+        shcsr |= CYGARC_REG_NVIC_SHCSR_USGFAULTENA;
+        shcsr |= CYGARC_REG_NVIC_SHCSR_BUSFAULTENA;
+        shcsr |= CYGARC_REG_NVIC_SHCSR_MEMFAULTENA;
+        HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
+    }
+#endif
+
+    // Call variant and platform init routines
+    hal_variant_init();
+    hal_platform_init();
+
+    // Start up the system clock
+    HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+    initialize_stub();
+
+#endif
+
+#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \
+    defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
+
+    hal_ctrlc_isr_init();
+
+#endif
+
+    // Run through static constructors
+    cyg_hal_invoke_constructors();
+
+    // Finally call into application
+    cyg_start();
+    for(;;);
+}
+
+//==========================================================================
+// Handle Exceptions
+//
+// Exceptions are passed here from the initial VSR. We pass the
+// exception on to GDB stubs or the kernel as appropriate.
+
+__externC void __handle_exception (void);
+
+__externC HAL_SavedRegisters *_hal_registers;
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+__externC void* volatile __mem_fault_handler;
+#endif
+
+void hal_deliver_exception( HAL_SavedRegisters *regs )
+{
+    // Special case handler for code which has chosen to take care
+    // of data exceptions (i.e. code which expects them to happen)
+    // This is common in discovery code, e.g. checking for a particular
+    // device which may generate an exception when probing if the
+    // device is not present
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+    if (__mem_fault_handler )
+    {
+        regs->u.exception.pc = (unsigned long)__mem_fault_handler;
+        return; // Caught an exception inside stubs
+    }
+#endif
+
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+
+    _hal_registers = regs;
+    __handle_exception();
+
+#elif defined(CYGPKG_KERNEL_EXCEPTIONS)
+
+    cyg_hal_deliver_exception( regs->u.exception.vector, (CYG_ADDRWORD)regs );
+
+#else
+
+    CYG_FAIL("Exception!!!");
+
+#endif
+}
+
+//==========================================================================
+// Handle Interrupts
+//
+// Interrupts are passed here from the low-level VSR in vectors.S. We
+// look up the ISR in the interrupt table, call it and if it requests
+// it, post a DSR. If necessary we also then cause the pendable SVC to
+// be requested.
+//
+// This function is also callable from ISR springboards that decode
+// additional interrupts via external controllers to deliver an
+// interrupt to a secondary vector.
+
+void hal_deliver_interrupt( cyg_uint32 vector )
+{
+    register cyg_uint32 isr_result;
+    register cyg_isr *isr;
+    cyg_bool pendsvc = false;
+
+#if defined(CYGPKG_KERNEL_INSTRUMENT) && \
+    defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
+    CYG_INSTRUMENT_INTR(RAISE, vector, 0);
+#endif
+    isr = (cyg_isr *)hal_interrupt_handlers[vector];
+
+    // Call the ISR
+    isr_result = isr( vector, hal_interrupt_data[vector] );
+
+
+#if !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
+    // If the ISR has returned the CALL_DSR bit, post the DSR and set
+    // the pendable SVC exception pending.
+    if( isr_result & CYG_ISR_CALL_DSR )
+    {
+        cyg_interrupt_post_dsr( hal_interrupt_objects[vector] );
+
+        // Post the pendable SVC to call interrupt_end(). But only if
+        // the scheduler lock is currently zero. If it is non zero
+        // then interrupt_end will do nothing useful, so avoid calling
+        // it.
+        if( cyg_scheduler_sched_lock == 0 )
+            pendsvc = true;
+    }
+#else
+    // When chaining we don't know here whether the nested interrupt
+    // has posted a DSR, so we have to run interrupt_end() regardless.
+    // However, the same considerations as above regarding the
+    // scheduler lock still apply.
+    if( cyg_scheduler_sched_lock == 0 )
+        pendsvc = true;
+#endif
+
+    // Post the pendable SVC if required.
+    if( pendsvc )
+    {
+        cyg_uint32 icsr;
+        HAL_READ_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_ICSR, icsr );
+        icsr |= CYGARC_REG_NVIC_ICSR_PENDSVSET;
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_ICSR, icsr );
+    }
+}
+
+//==========================================================================
+// Call interrupt_end()
+//
+// This is called on the thread stack as a result of the pendable
+// SVC. interrupt_end() decrements the scheduler lock, calls DSRs and
+// optionally switches thread context. So before calling, we must
+// increment the lock. The actual interrupt end processing has already
+// been done above in hal_default_interrupt_vsr1(), so the arguments
+// are zero.
+
+__externC void hal_interrupt_end( void )
+{
+#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
+    cyg_scheduler_sched_lock++;
+#endif
+
+   interrupt_end(0,0,0);
+}
+
+//==========================================================================
+// Interrupt masking and configuration
+
+#ifndef HAL_VAR_INTERRUPT_MASK
+#define HAL_VAR_INTERRUPT_MASK( __vector ) CYG_EMPTY_STATEMENT
+#define HAL_VAR_INTERRUPT_UNMASK( __vector ) CYG_EMPTY_STATEMENT
+#define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) CYG_EMPTY_STATEMENT
+#define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) CYG_EMPTY_STATEMENT
+#define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up ) CYG_EMPTY_STATEMENT
+#endif
+
+//--------------------------------------------------------------------------
+
+__externC void hal_interrupt_mask( cyg_uint32 vector )
+{
+    if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
+        vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_CER(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
+                          CYGARC_REG_NVIC_IBIT(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL) );
+    else if( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
+    {
+        cyg_uint32 csr;
+        HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
+        csr &= ~CYGARC_REG_SYSTICK_CSR_TICKINT;
+        HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
+    }
+    HAL_VAR_INTERRUPT_MASK( vector );
+}
+
+//--------------------------------------------------------------------------
+
+__externC void hal_interrupt_unmask( cyg_uint32 vector )
+{
+    if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
+        vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
+                          CYGARC_REG_NVIC_IBIT(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL) );
+    else if( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
+    {
+        cyg_uint32 csr;
+        HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
+        csr |= CYGARC_REG_SYSTICK_CSR_TICKINT;
+        HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
+    }
+    HAL_VAR_INTERRUPT_UNMASK( vector );
+}
+
+//--------------------------------------------------------------------------
+
+__externC void hal_interrupt_acknowledge( cyg_uint32 vector )
+{
+    HAL_VAR_INTERRUPT_ACKNOWLEDGE( vector );
+}
+
+//--------------------------------------------------------------------------
+
+__externC void hal_interrupt_configure( cyg_uint32 vector, cyg_uint32 level, cyg_uint32 up )
+{
+    HAL_VAR_INTERRUPT_CONFIGURE( vector, level, up );
+}
+
+//--------------------------------------------------------------------------
+
+__externC void hal_interrupt_set_level( cyg_uint32 vector, cyg_uint32 level )
+{
+    cyg_uint32 l = (level)+CYGNUM_HAL_CORTEXM_PRIORITY_MAX;
+    if( l > 0xFF ) l = 0xFF; /* clamp to 0xFF */
+    if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
+        vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
+    {
+        HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
+                         l );
+    }
+    else if ( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
+    {
+        cyg_uint32 shpr2;
+        HAL_READ_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, shpr2 );
+        shpr2 &= ~0xFF000000;
+        shpr2 |= (l)<<24;
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, shpr2 );
+    }
+    HAL_VAR_INTERRUPT_SET_LEVEL( vector, level );
+}
+
+//==========================================================================
+// Microsecond delay
+//
+// The system RTC is set up to tick at 1MHz so all we need to do here
+// is count ticks.
+
+__externC void hal_delay_us( cyg_int32 us )
+{
+    cyg_uint32 t0, t1;
+
+    HAL_CLOCK_READ( &t0 );
+    while ( us > 0 )
+    {
+        HAL_CLOCK_READ( &t1 );
+        if( t1 < t0 )
+            us -= (t1 + CYGNUM_HAL_RTC_PERIOD - t0);
+        else
+            us -= t1 - t0;
+        t0 = t1;
+    }
+}
+
+//==========================================================================
+// C++ support - run initial constructors
+
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+cyg_bool cyg_hal_stop_constructors;
+#endif
+
+typedef void (*pfunc) (void);
+
+extern pfunc __init_array_start__[];
+extern pfunc __init_array_end__[];
+#define CONSTRUCTORS_START  (__init_array_start__[0])
+#define CONSTRUCTORS_END    (__init_array_end__)
+#define NEXT_CONSTRUCTOR(c) ((c)++)
+
+void
+cyg_hal_invoke_constructors (void)
+{
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+    static pfunc *p = &CONSTRUCTORS_START;
+
+    cyg_hal_stop_constructors = 0;
+    for (; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p)) {
+        (*p)();
+        if (cyg_hal_stop_constructors) {
+            NEXT_CONSTRUCTOR(p);
+            break;
+        }
+    }
+#else
+    pfunc *p;
+
+    for (p = &CONSTRUCTORS_START; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p))
+        (*p)();
+#endif
+}
+
+//==========================================================================
+// Architecture default ISR
+
+__externC cyg_uint32
+hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
+{
+    CYG_TRACE1(true, "Interrupt: %d", vector);
+
+    CYG_FAIL("Spurious Interrupt!!!");
+
+    return 0;
+}
+
+//==========================================================================
+// GDB support
+//
+// These functions translate between HAL saved contexts and GDB
+// register dumps.
+
+__externC void hal_get_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
+{
+    int i;
+
+    switch(GDB_STUB_SAVEDREG_FRAME_TYPE(regs))
+    {
+    case HAL_SAVEDREGISTERS_THREAD:
+        for( i = 0; i < 13; i++ )
+            gdbreg->gpr[i] = regs->u.thread.r[i];
+        gdbreg->gpr[13] = regs->u.thread.sp;
+        gdbreg->gpr[14] = regs->u.thread.pc;
+        gdbreg->gpr[15] = regs->u.thread.pc;
+        gdbreg->xpsr = 0x01000000;
+
+        GDB_STUB_SAVEDREG_FPU_THREAD_GET(gdbreg, regs);
+        break;
+
+    case HAL_SAVEDREGISTERS_EXCEPTION:
+        gdbreg->gpr[0] = regs->u.exception.r0;
+        gdbreg->gpr[1] = regs->u.exception.r1;
+        gdbreg->gpr[2] = regs->u.exception.r2;
+        gdbreg->gpr[3] = regs->u.exception.r3;
+        for( i = 0; i < 8; i++ )
+            gdbreg->gpr[i+4] = regs->u.exception.r4_11[i];
+        gdbreg->gpr[12] = regs->u.exception.r12;
+        gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.exception);
+        gdbreg->gpr[14] = regs->u.exception.lr;
+        gdbreg->gpr[15] = regs->u.exception.pc;
+        gdbreg->xpsr = regs->u.exception.psr;
+#ifdef  CYGSEM_HAL_DEBUG_FPU
+        GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(gdbreg, regs);
+#endif
+        break;
+
+    case HAL_SAVEDREGISTERS_INTERRUPT:
+        gdbreg->gpr[0] = regs->u.interrupt.r0;
+        gdbreg->gpr[1] = regs->u.interrupt.r1;
+        gdbreg->gpr[2] = regs->u.interrupt.r2;
+        gdbreg->gpr[3] = regs->u.interrupt.r3;
+        gdbreg->gpr[12] = regs->u.interrupt.r12;
+        gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.interrupt);
+        gdbreg->gpr[14] = regs->u.interrupt.lr;
+        gdbreg->gpr[15] = regs->u.interrupt.pc;
+        gdbreg->xpsr = regs->u.interrupt.psr;
+        break;
+    }
+#ifdef CYGARC_CORTEXM_GDB_REG_FPA
+    // Clear FP state, which we don't use
+    {
+        cyg_uint32 *p = gdbreg->f0;
+        for( i = 0; i < (8*3+1); i++ )
+            p[i] = 0;
+    }
+#endif
+}
+
+__externC void hal_set_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
+{
+    int i;
+
+    switch(GDB_STUB_SAVEDREG_FRAME_TYPE(regs))
+    {
+    case HAL_SAVEDREGISTERS_THREAD:
+        for( i = 0; i < 13; i++ )
+            regs->u.thread.r[i] = gdbreg->gpr[i];
+        regs->u.thread.sp = gdbreg->gpr[13];
+        regs->u.thread.pc = gdbreg->gpr[14];
+        regs->u.thread.pc = gdbreg->gpr[15];
+
+        GDB_STUB_SAVEDREG_FPU_THREAD_SET(gdbreg, regs);
+        break;
+
+    case HAL_SAVEDREGISTERS_EXCEPTION:
+        regs->u.exception.r0 = gdbreg->gpr[0];
+        regs->u.exception.r1 = gdbreg->gpr[1];
+        regs->u.exception.r2 = gdbreg->gpr[2];
+        regs->u.exception.r3 = gdbreg->gpr[3];
+        for( i = 0; i < 8; i++ )
+            regs->u.exception.r4_11[i] = gdbreg->gpr[i+4];
+        regs->u.exception.r12 = gdbreg->gpr[12];
+        regs->u.exception.lr = gdbreg->gpr[14];
+        regs->u.exception.pc = gdbreg->gpr[15];
+        regs->u.exception.psr = gdbreg->xpsr;
+#ifdef  CYGSEM_HAL_DEBUG_FPU
+        GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(gdbreg, regs);
+#endif
+        break;
+
+    case HAL_SAVEDREGISTERS_INTERRUPT:
+        regs->u.interrupt.r0 = gdbreg->gpr[0];
+        regs->u.interrupt.r1 = gdbreg->gpr[1];
+        regs->u.interrupt.r2 = gdbreg->gpr[2];
+        regs->u.interrupt.r3 = gdbreg->gpr[3];
+        regs->u.interrupt.r12 = gdbreg->gpr[12];
+        regs->u.interrupt.lr = gdbreg->gpr[14];
+        regs->u.interrupt.pc = gdbreg->gpr[15];
+        regs->u.interrupt.psr = gdbreg->xpsr;
+        break;
+    }
+}
+
+//==========================================================================
+// When compiling C++ code with static objects the compiler
+// inserts a call to __cxa_atexit() with __dso_handle as one of the
+// arguments. __cxa_atexit() would normally be provided by glibc, and
+// __dso_handle is part of crtstuff.c. eCos applications
+// are linked rather differently, so either a differently-configured
+// compiler is needed or dummy versions of these symbols should be
+// provided. If these symbols are not actually used then providing
+// them is still harmless, linker garbage collection will remove them.
+
+void
+__cxa_atexit(void (*arg1)(void*), void* arg2, void* arg3)
+{
+}
+
+void*   __dso_handle = (void*) &__dso_handle;
+
+//==========================================================================
+// EOF hal_misc.c
diff --git a/ecos/packages/hal/cortexm/arch/current/src/mcount.S b/ecos/packages/hal/cortexm/arch/current/src/mcount.S
new file mode 100644
index 0000000..33e4539
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/src/mcount.S
@@ -0,0 +1,138 @@
+/*==========================================================================
+//
+//      mcount.S
+//
+//      Cortex-M mcount implementation
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2014 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       jld
+// Contributor(s):  
+// Date:            2014-02-28
+// Description:     This file provides mcount functions used for
+//                  call-graph profiling.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/hal_cortexm.h>
+
+/*
+// GCC inserts mcount code at the start of every function when compiling
+// with "-pg". For GCC prior to version 4.4 targeting Cortex-M,
+// the following code is inserted:
+// 
+//   mov r12, lr
+//   bl mcount
+//   .word <data pointer>
+//
+// For GCC version 4.4 and later targeting Cortex-M, the following code is
+// inserted:
+//
+//   push { lr }
+//   bl __gnu_mcount_nc
+//
+// We provide implementations of both mcount() and __gnu_mcount_nc() to
+// call the eCos __profile_mcount() function.
+*/
+
+        .syntax unified
+        .globl mcount
+        .section .text.mcount
+        .thumb_func
+mcount:
+        // resume execution beyond the data pointer on return to caller
+        add lr, lr, #4
+
+        // caller assumes r0-r3 will be preserved (non-AAPCS), we use
+        // r6 and must preserve lr across our __profile_mcount() call
+        push { r0, r1, r2, r3, r6, lr }
+
+        // set up parameters for __profile_mcount()
+        sub r0, r12, #2
+        bic r0, r0, #1
+        bic r1, lr, #1
+
+        // disable interrupts
+        mov r2, #CYGNUM_HAL_CORTEXM_PRIORITY_MAX
+        mrs r6, basepri
+        msr basepri, r2
+
+        // call eCos __profile_mcount()
+        // r6 is preserved across the call per AAPCS
+        bl __profile_mcount
+
+        // restore interrupts
+        msr basepri, r6
+
+        // restore registers and return
+        pop { r0, r1, r2, r3, r6, pc }
+
+
+        .globl __gnu_mcount_nc
+        .section .text.__gnu_mcount_nc
+        .thumb_func
+__gnu_mcount_nc:
+        // caller assumes r0-r3 will be preserved (non-AAPCS), we use
+        // r6 and must preserve lr across our __profile_mcount() call
+        push { r0, r1, r2, r3, r6, lr }
+
+        // set up parameters for __profile_mcount()
+        ldr r0, [ sp, #24 ]
+        sub r0, r0, #2
+        bic r0, r0, #1
+        bic r1, lr, #1
+
+        // disable interrupts
+        mov r2, #CYGNUM_HAL_CORTEXM_PRIORITY_MAX
+        mrs r6, basepri
+        msr basepri, r2
+
+        // call eCos __profile_mcount()
+        // r6 is preserved across the call per AAPCS
+        bl __profile_mcount
+
+        // restore interrupts
+        msr basepri, r6
+
+        // restore registers and return
+        pop { r0, r1, r2, r3, r6, r12, lr }
+        bx r12
+
+//==========================================================================
+// end of mcount.S
diff --git a/ecos/packages/hal/cortexm/arch/current/src/vectors.S b/ecos/packages/hal/cortexm/arch/current/src/vectors.S
new file mode 100644
index 0000000..8564bdb
--- /dev/null
+++ b/ecos/packages/hal/cortexm/arch/current/src/vectors.S
@@ -0,0 +1,393 @@
+/*==========================================================================
+//
+//      vectors.S
+//
+//      Cortex-M exception vectors
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011, 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Contributors(s): ilijak
+// Date:         2008-07-30
+// Description:  This file defines the code placed into the exception
+//               vectors. It also contains the first level default VSRs
+//               that save and restore state for both exceptions and
+//               interrupts.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/hal/cortexm_fpu.h>
+#ifdef CYGHWR_HAL_CORTEXM_FPU
+# include <cyg/hal/hal_arch.inc>
+#endif
+
+#include <cyg/hal/variant.inc>
+
+//==========================================================================
+
+        .syntax unified
+        .thumb
+
+//==========================================================================
+// Initial exception vector table
+//
+// This only contains the stack and entry point for reset. The table
+// to be used at runtime is constructed by code in hal_reset_vsr().
+
+        .section        ".vectors","ax"
+
+        .global         hal_vsr_table
+hal_vsr_table_init:
+
+        .long           hal_startup_stack               //  0 Reset stack
+        .long           hal_reset_vsr                   //  1 Reset entry
+
+//==========================================================================
+
+        .text
+        .thumb
+
+//==========================================================================
+// Fake entry point.
+//
+// The ELF file entry point points here. When loading an executable
+// via RedBoot/Stubs or via JTAG the PC will be set to this address.
+// The code here sets up the SP and branches to the reset VSR in
+// emulation of the hardware reset behaviour.
+
+        .align  2
+        .global reset_vector
+        .thumb
+        .thumb_func
+        .type   reset_vector, %function
+reset_vector:
+
+        ldr     sp,=hal_startup_stack
+        b       hal_reset_vsr
+
+        .pool
+
+#if !defined(CYG_HAL_STARTUP_RAM)
+//==========================================================================
+// State switch VSR
+//
+// This is called from the init code to switch execution from the main
+// stack to the process stack. We also take the opportunity to do some
+// other things that are best done in asm code such as disabling interrupts
+// and setting the control register.
+//
+// The adjustment to MSP by 1/2 interrupt stack size allows code to
+// throw exceptions without corrupting the execution stack. This is
+// only necessary for non-kernel configurations (e.g. RedBoot, Stubs)
+// since kernel configurations will switch to a thread stack before
+// they should throw an exception.
+
+        .global hal_switch_state_vsr
+        .thumb
+        .thumb_func
+        .type   hal_switch_state_vsr, %function
+hal_switch_state_vsr:
+
+        mov     r0,#CYGNUM_HAL_CORTEXM_PRIORITY_MAX
+        msr     basepri,r0
+
+        mov     r0,#2                   // Set CONTROL register to 2
+        msr     control,r0
+        isb                             // Insert a barrier
+
+        mov     r0,sp
+        msr     psp,r0                  // Copy SP to PSP
+
+#if !defined(CYGPKG_KERNEL)
+        sub     sp,#(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE/2)
+#endif
+
+        orr     lr,#0xD                 // Adjust return link
+        bx      lr                      // Return to init code on PSP now
+
+#endif
+
+//==========================================================================
+// Default exception VSR
+//
+// This is attached to all exception vectors. It saves the entire
+// machine state and calls into the eCos exception handling code.
+//
+// NOTE: At present this implementation does not permit an exception
+// handler to suspend the faulting thread and enter the scheduler to
+// switch elsewhere. However, I know of no code that does anything
+// like this. If there is then this may need treating in the same way
+// as the interrupt end code.
+
+        .global hal_default_exception_vsr
+        .thumb
+        .thumb_func
+        .type   hal_default_exception_vsr, %function
+hal_default_exception_vsr:
+
+        mrs     r0,psp                  // Get process stack
+
+#ifdef  CYGSEM_HAL_DEBUG_FPU
+        hal_fpu_exc_push                // Save Floating Point Unit context
+#endif
+        sub     r1,r0,#(4*12)           // Make space for saved state
+        msr     psp,r1                  // Ensure PSP is up to date
+
+        mov     r1,#1                   // R1 = exception state type
+        mrs     r2,ipsr                 // R2 = vector number
+        mrs     r3,basepri              // R3 = basepri
+        stmfd   r0!,{r1-r11,lr}         // Push type, vector, basepri, r4-11
+        mov     r4,r0                   // R4 = saved state pointer
+
+        bl      hal_deliver_exception
+
+        mov     r0,r4                   // R0 = state saved across call
+        ldmfd   r0!,{r1-r11,lr}         // Pop type, vec, basepri, registers and LR
+
+#ifdef  CYGSEM_HAL_DEBUG_FPU
+        hal_fpu_exc_pop                 // Update Floating Point Unit context
+#endif
+        msr     psp,r0                  // Restore PSP
+        msr     basepri,r3              // Restore basepri
+
+        bx      lr                      // Return
+
+        .pool
+
+//==========================================================================
+// Default interrupt VSR
+//
+// This is a trampoline that translates from the hardware defined entry point
+// to the ISR defined by eCos. The CPU will switch automatically to the main
+// (interrupt) stack with the process state saved on the process stack. Apart
+// from saving a pointer to the interrupt state for Ctrl-C support, and fetching
+// the vector number, most of the work is actually done in hal_deliver_interrupt().
+
+
+        .global hal_default_interrupt_vsr
+        .thumb
+        .thumb_func
+        .type   hal_default_interrupt_vsr, %function
+hal_default_interrupt_vsr:
+
+        push    {lr}                    // Save return link
+        sub     sp,#4                   // Realign SP to 8 bytes
+
+#if CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED > 0
+        // If we are supporting Ctrl-C interrupts from GDB, we must squirrel
+        // away a pointer to the saved interrupt state here so that we can
+        // plant a breakpoint at some later time.
+
+       .extern  hal_saved_interrupt_state
+        mrs     r1,psp                  // Get PSP
+        mov     r0,#3                   // Interrupt state type
+        stmfd   r1!,{r0}                // Push interrupt type
+        ldr     r12,=hal_saved_interrupt_state
+        str     r1,[r12]
+#endif
+
+        mrs     r0,ipsr                 // R0 = arg0 = vector number
+        sub     r0,#15                  // Adjust to interrupt range
+
+        bl      hal_deliver_interrupt
+
+        add     sp,#4                   // pop alignment padding
+        pop     {pc}                    // Pop LR and return
+
+        .pool
+
+//==========================================================================
+// Pendable SVC VSR
+//
+// This is invoked if an interrupt posts a DSR. It calls the DSR
+// and finalizes interrupt processing by calling interrupt_end(). We want
+// to run interrupt_end() on the PSP of the current thread. So we push
+// a fake exception frame onto the PSP which will take us to hal_interrupt_end(),
+// which will make the call. The return link loaded by that frame takes us
+// back to hal_interrupt_end_done which will unwind the real exception
+// frame that is still on the PSP.
+
+
+        .global hal_pendable_svc_vsr
+        .thumb
+        .thumb_func
+        .type   hal_pendable_svc_vsr, %function
+hal_pendable_svc_vsr:
+
+        mrs     r12,psp                 // R12 = thread's PSP
+        sub     r0,r12,#HAL_SAVEDREG_AUTO_FRAME_SIZE            // Make space for frame
+        msr     psp,r0                  // Put it back
+
+#ifdef CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+        hal_fpu_isr_fake_frame_push
+#endif // CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
+        ldr     r3,=0x01000000          // R3 = PSR = thumb bit set
+        ldr     r2,=hal_interrupt_end   // R2 = PC = interrupt end entry point
+        ldr     r1,=hal_interrupt_end_done // R1 = LR = restore code
+        stmfd   r12!,{r0-r3}            // Save fake R12, LR, PC, PSR
+        stmfd   r12!,{r0-r3}            // Save fake R0-R3
+
+        bx      lr                      // Return to hal_interrupt_end
+
+        .pool
+
+//==========================================================================
+// Interrupt end done
+//
+// After calling interrupt end a thread returns here to unstack the
+// exception frame used to enter hal_pendable_svc_vsr. We can only
+// successfully unstack a frame by doing a proper exception return
+// from handler mode, so we use a SWI which will discard its own
+// frame and restore the saved one.
+
+
+        .global hal_interrupt_end_done
+        .thumb
+        .thumb_func
+        .type   hal_interrupt_end_done, %function
+hal_interrupt_end_done:
+
+        ldr  r3,=hal_interrupt_end_vsr
+        swi  0
+
+//==========================================================================
+// Interrupt end VSR
+//
+// This is the SVC VSR invoked by hal_interrupt_end_done to restore the
+// original exception frame from a pendable SVC entry. It does this
+// by discarding its own frame and using the one below it on the
+// stack to return.
+
+        .global hal_interrupt_end_vsr
+        .thumb
+        .thumb_func
+        .type   hal_interrupt_end_vsr, %function
+hal_interrupt_end_vsr:
+
+        mrs     r12,psp                 // R12 = thread's PSP
+        add     r12,#HAL_SAVEDREG_AUTO_FRAME_SIZE                 // Skip our saved state
+        msr     psp,r12                 // Restore thread's PSP
+
+        bx      lr                      // And return
+
+//==========================================================================
+// Run DSRs VSR
+//
+// This is invoked from the kernel via a SWI to run DSRs on the
+// interrupt/main stack. It merely branches to
+// cyg_interrupt_call_pending_DSRs() which will then directly return
+// from the SVC exception.
+
+        .global hal_call_dsrs_vsr
+        .thumb
+        .thumb_func
+        .type   hal_call_dsrs_vsr, %function
+
+hal_call_dsrs_vsr:
+
+        .extern cyg_interrupt_call_pending_DSRs
+        b       cyg_interrupt_call_pending_DSRs
+
+//==========================================================================
+// SVC VSR
+//
+// The SVC VSR is used as a general-purpose mechanism for running code
+// in handler mode. R3 contains the address of a piece of code to run,
+// R0-R2 contain any arguments. Once entered the code is responsible for
+// handling the system state and returning to thread mode.
+//
+// Note that R0-R3 must be explicitly restored from their stacked
+// copies since a late arriving interrupt can preempt the SVC entry
+// and corrupt these registers before we get here.
+
+        .global hal_default_svc_vsr
+        .thumb
+        .thumb_func
+        .type   hal_default_svc_vsr, %function
+hal_default_svc_vsr:
+
+        mrs     r12,psp
+        ldmfd   r12,{r0-r3}
+        bx      r3                      // Jump to routine in R3
+
+        .pool
+
+#ifdef CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+//==========================================================================
+// Usage Fault VSR
+// Note: This VSR is also attached to HardFault vector.
+// At present this VSR is used to detect FPU usage for Lazy context switch.
+// after saving processor context on the process stack call
+// hal_deliver_usagefault_fpu_exception() to do the job and retun result in r0.
+// If result indicates no FPU activity then jump in hal_default_exception_vsr.
+        .global hal_usagefault_exception_vsr
+        .thumb
+        .thumb_func
+        .type   hal_usagefault_exception_vsr, %function
+hal_usagefault_exception_vsr:
+
+        mrs     r0,psp                  // Get process stack
+        sub     r1,r0,#(2*4)            // Make space for saved state
+        msr     psp,r1                  // Ensure PSP is up to date
+        stmfd   r0!,{r4,lr}             // save registers
+        mov     r4,r0                   // R4 = saved state pointer
+
+        bl      hal_deliver_usagefault_fpu_exception
+
+        mov     r1,r4                   // R0 = state saved across call
+        ldmfd   r1!,{r4,lr}             // Restore registers
+        msr     psp,r1                  // Restore PSP
+
+        cmp     r0,#0                   // Exception other than FPU?
+        bne     hal_default_exception_vsr // Y: - process it
+
+        bx      lr                      // N: Return
+
+        .pool
+
+#endif // CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
+
+//==========================================================================
+// end of vectors.S
diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
new file mode 100644
index 0000000..910b14e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/ChangeLog
@@ -0,0 +1,49 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/kwikstik_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
+	Sync with variant changes due to hardware floating point support.
+	Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM.    [Bugzilla 1001607]
+
+2011-12-15  Tomas Frydrych  <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_kwikstik.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/kwikstik_misc.c:
+	New package -- Freescale Kwikstik board, based on twr_k40x256 board.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011, 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
new file mode 100644
index 0000000..8c16ffe
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/cdl/hal_cortexm_kinetis_kwikstik.cdl
@@ -0,0 +1,297 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_kwikstik.cdl
+##
+##      Cortex-M Freescale KwikStik platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2011, 2012 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Tomas Frydrych <tomas@sleepfive.com>
+## Contributor(s): jld
+## Date:         2011-12-15
+## Original:     hal_cortexm_kinetis_twr_k40x256.cdl by Ilija Kocho
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_KWIKSTIK {
+    display       "Freescale Kinetis KwikStik Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_kwikstik.h
+    include_dir   cyg/hal
+    hardware
+
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" }
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X"
+                    implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART5
+    implements    CYGINT_IO_FREESCALE_I2C1
+    implements    CYGINT_HAL_FREESCALE_UART5
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+
+    description   "
+        The Freescale KwikStik Platform HAL package provides
+        the support needed to run eCos on the KwikStik development
+        system. This package can also be used for other boards that
+        employ a controller from Kinetis families."
+
+    compile       kwikstik_misc.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_kwikstik.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale KwikStik\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platform Reference Clock Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 4000000
+        legal_values { 32768 4000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 0 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This optionchooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console
+            port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        no_define
+        parent  CYGPKG_NONE
+        description   "
+        Global build options including control over
+        compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+            This option controls the global compiler flags which are used to
+            compile all packages by default. Individual packages may define
+            options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+            This option controls the global linker flags. Individual
+            packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on the
+            board, and this ROM monitor may process exceptions or interrupts
+            generated from the application. This enables features such as
+            utilizing a separate interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_KWIKSTIK_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h
new file mode 100644
index 0000000..f14c402
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Tomas Frydrych <tomas@sleepfive.com>
+// Original:    Cloned from plf_arch.h for twr-k40x256 board by Ilija Kocho
+// Date:        2011-12-15
+// Purpose:     Kwikstick platform specific architecture overrides
+// Description:
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_kwikstik.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h
new file mode 100644
index 0000000..6c083a9
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_intr.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Tomas Frydrych <tomas@sleepfive.com>
+// Original:       Cloned from plf_intr.h for twr-k40x256 board by Ilija Kocho
+// Date:           2011-12-15
+// Purpose:        Kwikstik platform specific interrupt overrides
+// Description:
+// Usage:          #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_kwikstik.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h
new file mode 100644
index 0000000..feb6fae
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/include/plf_io.h
@@ -0,0 +1,110 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Tomas Frydrych <tomas@sleepfive.com>
+// Original:       Based on plf_io.h for twr-k40x256 board by Ilija Kocho
+// Date:           2011-12-15
+// Purpose:        Kwikstik platform specific registers
+// Description:
+// Usage:          #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_kwikstik.h>
+
+
+// UART PINs
+
+#ifndef CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 9, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 8, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_FREESCALE_UART5_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_FREESCALE_UART5_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_FREESCALE_UART5_PIN_CTS
+#endif
+
+// LCD
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_M            0x40000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_S            30
+
+#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M             \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M | \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M |     \
+             CYGHWR_HAL_KINETIS_SIM_SCGC3_SLCD_M)
+#endif
+
+// I2C pins
+# define CYGHWR_HAL_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 0, 6, 0)
+# define CYGHWR_HAL_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 1, 6, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/ecos/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c
new file mode 100644
index 0000000..e43fcd6
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/kwikstik/current/src/kwikstik_misc.c
@@ -0,0 +1,255 @@
+//==========================================================================
+//
+//      kwikstik_misc.c
+//
+//      Cortex-M4 Kwikstik HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Tomas Frydrych <tomas@sleepfive.com>
+// Original:       Cloned from twr_k40x256_misc.c by Ilija Kocho
+// Date:           2011-12-15
+// Description:    Miscellaneous code for platform hal.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_kwikstik.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
+    hal_wdog_disable();
+    hal_misc_init();
+    hal_start_clocks();
+#endif
+#if defined(CYG_HAL_STARTUP_SRAM) && !defined(CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED)
+    // Note: For CYG_HAL_STARTUP_SRAM, the SRAM_L bank simulates ROM
+    // Relocate data from ROM to RAM
+    {
+        register cyg_uint32 *ram_p, *rom_p;
+        for( ram_p = &__ram_data_start, rom_p = &__rom_data_start;
+             ram_p < &__ram_data_end;
+             ram_p++, rom_p++ )
+            *ram_p = *rom_p;
+    }
+
+    // Relocate data from ROM to SRAM
+    {
+        register cyg_uint32 *ram_p, *sram_p;
+        for( ram_p = &__sram_data_start, sram_p = &__srom_data_start;
+             ram_p < &__sram_data_end;
+             ram_p++, sram_p++ )
+            *ram_p = *sram_p;
+    }
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // Main RAM
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1      },      // External flash
+#endif
+#ifdef CYGMEM_REGION_flexnvm
+    { CYGMEM_REGION_flexnvm,    CYGMEM_REGION_flexnvm+CYGMEM_REGION_flexnvm_SIZE-1  },  // On-chip flexnvm (DFlash)
+#endif
+#ifdef CYGMEM_REGION_flexram
+    { CYGMEM_REGION_flexram,    CYGMEM_REGION_flexram+CYGMEM_REGION_flexram_SIZE-1  },  // On-chip flexram
+#endif
+#ifdef CYGMEM_REGION_eeeprom0
+    { CYGMEM_REGION_eeeprom0,    CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom0_SIZE-1  },  // On-chip Enhanced EEPROM
+#endif
+#ifdef CYGMEM_REGION_eeeprom1
+    { CYGMEM_REGION_eeeprom1,    CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom1_SIZE-1  },  // On-chip Enhanced EEPROM
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+#define CASE_CYGMEM_REGION_SRAM 1
+    case CASE_CYGMEM_REGION_SRAM:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#else
+#define CASE_CYGMEM_REGION_SRAM 0
+#endif
+#ifdef CYGMEM_REGION_flexram
+#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM + 1)
+    case CASE_CYGMEM_REGION_FLEXRAM:
+        *start = (unsigned char *)CYGMEM_REGION_flexram;
+        *end = (unsigned char *)(CYGMEM_REGION_flexram +
+                                 CYGMEM_REGION_flexram_SIZE);
+        break;
+#else
+#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM)
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+
+//==========================================================================
+// EOF kwikstik_misc.c
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
new file mode 100644
index 0000000..21c726c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog
@@ -0,0 +1,72 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k40x256_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	Sync with variant changes due to hardware floating point support.
+	Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM.    [Bugzilla 1001607]
+
+2012-10-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k40x256_misc.c: Initialization for separate SRAM regions
+	synchronized with variant.                  [Bugzilla 1001606]
+
+2012-05-19  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl: Reference per-package
+	documentation.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* doc/twr_k40x512.sgml:
+	New file -- TWR-K40X512 platform documentation. [Bug 1001580]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	* include/plf_io.h:
+	* src/twr_k40x256_misc.c:
+	Add entry for DMA, Add CYG_HAL_STARTUP_ENV. Add DSPI pins for SPI1 bus.
+	Updated for early clock start. [Bugzilla 1001450]
+
+2011-08-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k40x256.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/twr_k40x256_misc.c:
+	New package -- Freescale TWR-K40X256 board.
+	
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
new file mode 100644
index 0000000..2455088
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl
@@ -0,0 +1,316 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k40x256.cdl
+##
+##      Cortex-M Freescale TWR-K40X256 platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011, 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-07-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256 {
+    display       "Freescale Kinetis TWR-K40X256 Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k40x256.h
+    include_dir   cyg/hal
+    doc           ref/kinetis-twr-k40x256.html
+    hardware
+
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" }
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X"
+                    implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART3
+    implements    CYGINT_IO_FREESCALE_I2C0
+    implements    CYGINT_IO_FREESCALE_I2C1
+    
+    implements    CYGINT_HAL_FREESCALE_UART3
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+
+    description   "
+        The Freescale TWR K40X256 Platform HAL package provides
+        the support needed to run eCos on the TWR K40X256 development
+        system. This package can also be used for other boards that
+        employ a controller from Kinetis families."
+
+    compile       twr_k40x256_misc.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K40X256\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platform Reference Clock Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 8000000
+        legal_values { 32768 8000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 0 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This optionchooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console
+            port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        no_define
+        parent  CYGPKG_NONE
+        description   "
+        Global build options including control over
+        compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+            This option controls the global compiler flags which are used to
+            compile all packages by default. Individual packages may define
+            options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+            This option controls the global linker flags. Individual
+            packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on the
+            board, and this ROM monitor may process exceptions or interrupts
+            generated from the application. This enables features such as
+            utilizing a separate interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK40X256_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml
new file mode 100644
index 0000000..e521bca
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml
@@ -0,0 +1,75 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     twr_k40x256.sgml                                             -->
+<!--                                                                 -->
+<!--     TWR-K40X256 board documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>-->
+
+<refentry id="kinetis-twr-k40x256">
+  <refmeta>
+    <refentrytitle>TWR-K40X256-KIT Development kit</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256</refname>
+    <refpurpose>eCos Support for the Freescale TWR-K40X256 development kit</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="kinetis-twr-k40x256-description"><title>Description</title>
+    <para>
+    The Freescale TWR-K40X256-KIT is a development kit for <link linkend="hal-cortexm-kinetis-var">
+    Freescale Kinetis</link>  Cortex-M4 based micro-controllers. It covers K40 and K30 microcontroller
+    subfamilies. K40X256 is a high end member comprising 256 KiB FLASH, 256 KiB FlexMemory and  64 KiB SRAM,
+    as well as rich set of communication interfaces including USB, UARTs CAN, SPI and I2C.
+    K40 controllers also feature a Segment LCD controller, a DMA controller and a FlexBus
+    external memory interface. They are mixed signal devices featuring 16 bit ADC and 12 bit DAC. 
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-twr-k40x256-config"><title>Configuration</title>
+    <refsect2 id="kinetis-twr-k40x256-config-hardware"><title>Hardware Setup</title>
+      <para>
+      No changes to the factory default setup are necessary.
+    </para>
+  <refsect3 id="twr-k40x256-clocking"><title>Clocking</title>
+    <para>
+    The TWR-K40X256 uses an 8MHz crystal as a clock reference which is stated as a requirement in the platform package.
+    </para>
+  </refsect3>  
+  <refsect3 id="twr-k40x256-memory"><title>Memory</title>
+    <para> K40X245 has two 32KiB SRAM banks giving a total of 64KiB on chip SRAM. </para>
+  </refsect3>
+ </refsect2>
+  </refsect1>
+</refentry>
+
+<!-- </part> -->
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h
new file mode 100644
index 0000000..6d35948
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributor(s):
+// Date:        2011-02-05
+// Purpose:     TWR-K40X256 platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h
new file mode 100644
index 0000000..f23f2e3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K40X256 platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h
new file mode 100644
index 0000000..fe85537
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h
@@ -0,0 +1,113 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K40X256 platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>
+
+
+// UART PINs
+
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+#endif
+
+
+// DSPI
+// DSPI Pins
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(B, 2, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(B, 3, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c
new file mode 100644
index 0000000..b895c36
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c
@@ -0,0 +1,233 @@
+//==========================================================================
+//
+//      twr_k40x256_misc.c
+//
+//      Cortex-M4 TWR-K40X256 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
+    hal_wdog_disable();
+    hal_misc_init();
+    hal_start_clocks();
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // Main RAM
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1      },      // External flash
+#endif
+#ifdef CYGMEM_REGION_flexnvm
+    { CYGMEM_REGION_flexnvm,    CYGMEM_REGION_flexnvm+CYGMEM_REGION_flexnvm_SIZE-1  },  // On-chip flexnvm (DFlash)
+#endif
+#ifdef CYGMEM_REGION_flexram
+    { CYGMEM_REGION_flexram,    CYGMEM_REGION_flexram+CYGMEM_REGION_flexram_SIZE-1  },  // On-chip flexram
+#endif
+#ifdef CYGMEM_REGION_eeeprom0
+    { CYGMEM_REGION_eeeprom0,    CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom0_SIZE-1  },  // On-chip Enhanced EEPROM
+#endif
+#ifdef CYGMEM_REGION_eeeprom1
+    { CYGMEM_REGION_eeeprom1,    CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom1_SIZE-1  },  // On-chip Enhanced EEPROM
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+#define CASE_CYGMEM_REGION_SRAM 1
+    case CASE_CYGMEM_REGION_SRAM:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#else
+#define CASE_CYGMEM_REGION_SRAM 0
+#endif
+#ifdef CYGMEM_REGION_flexram
+#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM + 1)
+    case CASE_CYGMEM_REGION_FLEXRAM:
+        *start = (unsigned char *)CYGMEM_REGION_flexram;
+        *end = (unsigned char *)(CYGMEM_REGION_flexram +
+                                 CYGMEM_REGION_flexram_SIZE);
+        break;
+#else
+#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM)
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k40x256_misc.c
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog
new file mode 100644
index 0000000..84b0c4e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/ChangeLog
@@ -0,0 +1,39 @@
+2013-07-02  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/twr_k60f120m.sgml: Fix missing </para>.
+
+2013-06-02  Mike Jones <mjones@proclivis.com.>
+
+	* cdl/hal_cortexm_kinetis_twr_k60f120m.cdl: New
+	* doc/twr_k60f120m.sgml: New
+	* include/plf_intr.h: New
+	* include/plf_io.h: New
+	* include/plf_arch.h: New
+	* misc/redboot_K60_ROM_FPU.ecm: New
+	* src/twr_k60f120m_misc.c: New
+
+	Add support for K60F120M [ Bugzilla 1001861 ]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl
new file mode 100644
index 0000000..14d9e19
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/cdl/hal_cortexm_kinetis_twr_k60f120m.cdl
@@ -0,0 +1,399 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k60f120m.cdl
+##
+##      Cortex-M Freescale TWR-K60F120M platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2013 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Contrib(s):   Mike Jones <mjones@proclivis.com>
+## Date:         2013-06-02
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60F120M {
+    display       "Freescale Kinetis TWR-K60F120M Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k60f120m.h
+    include_dir   cyg/hal
+    doc           ref/kinetis-twr-k60f120m.html
+    hardware
+    description   "
+        The Freescale TWR K60F120M Platform HAL package provides the support
+        needed to run eCos on the TWR K60F120M development system. This package
+        can also be used for other boards that employ a controller from Kinetis
+        families."
+
+    compile       twr_k60f120m_misc.c
+
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET)
+                  implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }
+
+    implements    CYGINT_HAL_CACHE
+
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT == "F" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT == 60 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 30 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 50 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 70 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == "1M0" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE == 0x1000 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART5
+    implements    CYGINT_IO_FREESCALE_I2C0
+
+    implements    CYGINT_HAL_FREESCALE_UART5
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+    implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+    implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+    implements    CYGINT_HAL_CORTEXM_KINETIS_150
+
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX == 75000000 }
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX == 75000000 }
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX == 25000000 }
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+        (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K60F120M\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000"
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP {
+        display "Platform suggested system frequency setpoint"
+        flavor data
+        no_define
+        legal_values 96000000 100000000 120000000 150000000 200000000
+        default_value 120000000
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP {
+        display "Platform suggested auxiliary frequency setpoint"
+        flavor data
+        no_define
+        legal_values 96000000 100000000 120000000 150000000 200000000
+        default_value 120000000
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platgorm XTAL/OSC Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 12000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ {
+        display "Platform XTAL1/OSC1 Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 12000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC1_CAP {
+        display "Platform requred XTAL1 || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port
+            if the console and GDB port are the same."
+    }
+
+    cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK {
+        display "ENET MII MDC clock provided by HAL"
+        flavor data
+        active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+        parent CYGPKG_DEVS_ETH_FREESCALE_ENET
+        calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS
+        description "
+            ENET needs a clock with typical frequency of up to 2.5 MHz for
+            MII MDC. The input clock, typically provided by HAL, is further
+            divided by ENET according to setting of ENET MSCR register in order to
+            provide frequency within 2.5 MHz range."
+     }
+
+    cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT {
+        display "IEEE 1588 Port"
+        active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        flavor data
+        default_value { "B" }
+        legal_values { "B" "C" "User" }
+        description "
+            Digital I/O provided by HAL for ENET IEEE 1588 timers."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+        requires  { (is_active(CYGSEM_HAL_DCACHE_STARTUP_MODE)
+                    && CYGINT_DEVS_SPI_DSPI_DMA_USE)
+                    implies CYGSEM_HAL_DCACHE_STARTUP_MODE == "WRITETHRU" }
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            legal_values { 0 1 2 3 4 5 }
+            default_value 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+            implements CYGINT_FREESCALE_DSPI1_CS1
+            implements CYGINT_FREESCALE_DSPI1_CS2
+            implements CYGINT_FREESCALE_DSPI1_CS3
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60F120M_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml
new file mode 100644
index 0000000..d2c133a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/doc/twr_k60f120m.sgml
@@ -0,0 +1,113 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     twr_k60f120m.sgml                                        -->
+<!--                                                                 -->
+<!--     TWR-K60F120M board documentation.                        -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contrib(s):  Mike Jones                                         -->
+<!-- Contact(s):  mjones@proclivis.com                               -->
+<!-- Date:        2013/06/02                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>-->
+
+<refentry id="kinetis-twr-k60f120m">
+  <refmeta>
+    <refentrytitle>TWR-K60F120M Development kit</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60F120M</refname>
+    <refpurpose>eCos Support for Freescale TWR-K60F120M development kit</refpurpose>
+  </refnamediv>
+  
+  <refsect1 id="kinetis-twr-k60f120m-description"><title>Description</title>
+    <para>
+    The Freescale TWR-K60F120M is a development kit for <link linkend="hal-cortexm-kinetis-var">
+    Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers the K60
+    microcontroller subfamily. K60FN1M0 is a high end member comprising on-chip 1 MiB FLASH
+    and 128 KiB SRAM memory as well as a 16 KiB unified cache.
+    K60 parts are equipped with a rich set of communication interfaces including Ethernet USB, UARTs
+    CAN, SPI and I2C. They also have a Graphics controller and a DMA controller, as well as FlexBus and SDRAM
+    external memory interfaces. They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. 
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-twr-k60f120m-config"><title>Configuration</title>
+    <refsect2 id="kinetis-twr-k60f120m-config-hardware"><title>Hardware Setup</title>
+      <refsect3 id="kinetis-twr-k60f120m-config-hardware-cpu"><title>TWR-K60F120M setup</title>
+      <para>
+      Factory jumper settings on TWR-K60F120M are fitted for standalone operation of the board.
+      In order to use it with the Ethernet PHY from TWR-SER, some jumpers have to be changed
+      on both TWR-K60F120M and TWR-SER. Jumper settings for TWR-SER are given in
+      <link linkend="kinetis-twr-k60n512-config">TWR-K60N512 Configuration</link> and here are the TWR-K60F120M
+      settings.
+      </para>
+      <table frame="all"><title>TWR-K60F120M Jumper setting</title>
+        <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="jumper" colwidth="1*" >
+          <colspec colnum="2" colname="jumpset" colwidth="1*" >
+          <colspec colnum="3" colname="desc" colwidth="3*" >
+          <thead>
+            <row>
+              <entry>Jumper</entry>
+              <entry>Setting</entry>
+              <entry>Description</entry>
+            </row>
+          </thead>
+          <tbody>
+            <row>
+              <entry>J18</entry>
+              <entry>ON</entry>
+              <entry>On board 50MHz oscillator is disabled</entry>
+            </row>
+            <row>
+              <entry>J19</entry>
+              <entry>ON</entry>
+              <entry>On board 50MHz oscillator is powered</entry>
+            </row>
+          </tbody>
+        </tgroup>
+      </table>
+      </refsect3>
+    </refsect2>
+    <refsect2 id="kinetis-twr-k60f120m-config-ecos"><title>eCos Configuration</title>
+      <refsect3 id="twr-k60f120m-clocking"><title>Clocking</title>
+      <para>
+      The TWR-K60F120M package defines requirements for the platform clocking.
+      </para>
+      </refsect3>  
+      <refsect3 id="twr-k60f120m-memory"><title>Memory</title>
+      <para>
+      The K60 has two 64 KiB SRAM banks giving a total of 128KiB on chip SRAM.
+      </para>
+      </refsect3>
+    </refsect2>
+  </refsect1>
+</refentry>
+
+<!--</part>-->
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h
new file mode 100644
index 0000000..b9eed4b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contrib(s):  Mike Jones <mjones@proclivis.com>
+// Date:        2013-06-02
+// Purpose:     TWR-K60F120M platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h
new file mode 100644
index 0000000..d4eb499
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contrib(s):  Mike Jones <mjones@proclivis.com>
+// Purpose:     TWR-K60F120M platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h
new file mode 100644
index 0000000..6abb4d2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/include/plf_io.h
@@ -0,0 +1,175 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contrib(s):  Mike Jones <mjones@proclivis.com>
+// Date:        2013-06-02
+// Purpose:     TWR-K60F120M platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>
+
+
+// UART PINs
+#ifndef CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 9, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 8, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_FREESCALE_UART5_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_FREESCALE_UART5_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_FREESCALE_UART5_PIN_CTS
+#endif
+
+#ifndef CYGHWR_HAL_FREESCALE_UART0_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_RX CYGHWR_HAL_KINETIS_PIN(A, 1, 2, 0)
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_TX CYGHWR_HAL_KINETIS_PIN(A, 2, 2, 0)
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_FREESCALE_UART0_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_FREESCALE_UART0_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_FREESCALE_UART0_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_FREESCALE_UART0_PIN_CTS
+#endif
+
+// ENET PINs
+
+// MDIO
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO    CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC     CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0)
+// Both RMII and MII interface
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER    CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \
+                                                    CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1    CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0    CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN    CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0    CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1    CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0)
+// RMII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV  CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0)
+// MII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3     CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2     CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK    CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2     CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK    CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3     CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS      CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER     CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL      CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0)
+// IEEE 1588 timers
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN    CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0)
+
+#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0)
+#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
+#endif
+
+// DSPI
+// DSPI Pins
+
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \
+                                  CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define KINETIS_PIN_SPI1_SCK_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M)
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \
+                                  CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#define KINETIS_PIN_SPI1_0_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 1, 7, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 3, 7, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_SCK_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0)
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
+
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm
new file mode 100644
index 0000000..e0bb505
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/misc/redboot_K60_ROM_FPU.ecm
@@ -0,0 +1,83 @@
+# Redboot minimal configuration
+# Target: TWR-K60F120M
+# Startup: ROM
+
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "RedBoot Kinetis TWR-K60F120M" ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU {
+    user_value 1
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH {
+    user_value ALL
+};
+
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 0
+};
+
+#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+#    user_value 1
+#};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    user_value -1
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+    user_value -2
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+    user_value 16
+};
+
+#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+#    user_value 0x20000
+#};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    user_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    user_value ROM
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    user_value 1
+};
+
+cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA {
+    user_value 1
+};
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c
new file mode 100644
index 0000000..34bc5e7
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60f120m/current/src/twr_k60f120m_misc.c
@@ -0,0 +1,252 @@
+//==========================================================================
+//
+//      twr_k60f120m_misc.c
+//
+//      Cortex-M4 TWR-K60N512 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Ilija Kocho <ilijak@siva.com.mk>
+// Contrib(s):     Mike Jones <mjones@proclivis.com>
+// Date:           2013-06-02
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60f120m.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if !defined(CYG_HAL_STARTUP_RAM)
+    cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P;
+
+    hal_wdog_disable();
+    hal_misc_init();
+
+    // if ACKISO is set you must clear ackiso before calling pll_init
+    //    or pll init hangs waiting for OSC to initialize
+    if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M)
+        pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M;
+
+    hal_start_clocks();
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc1 |= CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M;
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1        }, // System bus RAM partition
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1      }, // On-chip SRAM
+#elif defined CYGMEM_REGION_sram_l
+    { CYGMEM_REGION_sram_l,     CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1  }, // On-chip SRAM lower bank
+#endif
+#ifdef CYGMEM_REGION_ramcod
+    { CYGMEM_REGION_ramcod,      CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition
+#endif
+#ifdef CYGMEM_REGION_ramnc
+    { CYGMEM_REGION_ramnc,      CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1    }, // Non cachable RAM partition
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1    }, // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1        }, // External flash [currently none]
+#endif
+    { 0xE0000000,               0x00000000-1                                      }, // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                      }  // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) &&
+            ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_sram_l
+# define CASE_CODE 3
+# define CASE_RAMNC 4
+    case 2:
+        *start = (unsigned char *)CYGMEM_REGION_sram_l;
+        *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE);
+        break;
+#else
+# define CASE_CODE 2
+# define CASE_RAMNC 3
+#endif
+
+#ifdef CYGMEM_REGION_ramcod
+    case CASE_CODE:
+        *start = (unsigned char *)CYGMEM_REGION_ramcod;
+        *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE);
+        break;
+#endif
+
+#ifdef CYGMEM_REGION_ramnc
+    case CASE_RAMNC:
+        *start = (unsigned char *)CYGMEM_REGION_ramnc;
+        *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k60f120m_misc.c
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
new file mode 100644
index 0000000..41b6295
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/ChangeLog
@@ -0,0 +1,66 @@
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k60n512_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2012-10-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k60n512_misc.c: Initialization for separate SRAM regions
+	synchronized with variant.                  [Bugzilla 1001606]
+
+2012-05-19  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl: Reference per-package
+	documentation.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* doc/twr_k60n512.sgml:
+	New file -- TWR-K60N512 platform documentation. [Bug 1001580]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:
+	* include/plf_io.h:
+	* src/twr_k60n512_misc.c:
+	Add entry for DMA, Add CYG_HAL_STARTUP_ENV. Add DSPI pins for SPI1 bus.
+	Updated for early clock start.  [Bugzilla 1001450]
+
+2011-03-26  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/twr_k60n512_misc.c:
+	New package -- Freescale TWR-K60N512 board.
+	
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
new file mode 100644
index 0000000..b6472de
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/cdl/hal_cortexm_kinetis_twr_k60n512.cdl
@@ -0,0 +1,332 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k60n512.cdl
+##
+##      Cortex-M Freescale TWR-K60N512 platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011, 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-02-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512 {
+    display       "Freescale Kinetis TWR-K60N512 Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k60n512.h
+    include_dir   cyg/hal
+    doc           ref/kinetis-twr-k60n512.html
+    hardware
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET)
+                  implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART3
+    implements    CYGINT_IO_FREESCALE_I2C0
+    
+    implements    CYGINT_HAL_FREESCALE_UART3
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+    description   "
+        The Freescale TWR K60N512 Platform HAL package provides the support
+        needed to run eCos on the TWR K60N512 development system. This package
+        can also be used for other boards that employ a controller from Kinetis
+        families."
+
+    compile       twr_k60n512_misc.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+        (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K60N512\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platform Clock Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 25000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+        This option controls the default baud rate used for the
+        console connection.
+        Note: this should match the value chosen for the GDB port if the
+        diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port
+            if the console and GDB port are the same."
+    }
+
+    cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK {
+        display "ENET MII MDC clock provided by HAL"
+        flavor data
+        active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+        parent CYGPKG_DEVS_ETH_FREESCALE_ENET
+        calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS
+        description "
+            ENET needs a clock with typical frequency of up to 2.5 MHz for
+            MII MDC. The input clock, typically provided by HAL, is further
+            divided by ENET according to setting of ENET MSCR register in order to
+            provide frequency within 2.5 MHz range."
+     }
+
+    cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT {
+        display "IEEE 1588 Port"
+        active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        flavor data
+        default_value { "B" }
+        legal_values { "B" "C" "User" }
+        description "
+            Digital I/O provided by HAL for ENET IEEE 1588 timers."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+        Global build options including control over
+        compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+            This option controls the global compiler flags which are used to
+            compile all packages by default. Individual packages may define
+            options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+            This option controls the global linker flags. Individual
+            packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60N512_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml
new file mode 100644
index 0000000..d7c0175
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/doc/twr_k60n512.sgml
@@ -0,0 +1,134 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     twr_k60n512.sgml                                             -->
+<!--                                                                 -->
+<!--     TWR-K60N512 board documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>-->
+
+<refentry id="kinetis-twr-k60n512">
+  <refmeta>
+    <refentrytitle>TWR-K60N512-KIT Development kit</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512</refname>
+    <refpurpose>eCos Support for the Freescale TWR-K60N512 development kit</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="kinetis-twr-k60n512-description"><title>Description</title>
+    <para>
+    The Freescale TWR-K60N512-KIT is a development kit for <link linkend="hal-cortexm-kinetis-var">
+    Freescale Kinetis</link> Cortex-M4 based microcontrollers.
+    It covers K60, K10 and K20 microcontroller families.
+    K60N512 is a high end member comprising 512 KiB FLASH and 128 KiB SRAM,
+    as well as rich set of communication interfaces inclduing Ethernet USB, UARTs CAN, SPI and I2C.
+    K60 micro-controllres also have a DMA controller and a FlexBus external memory interface.
+    They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. 
+    </para>
+  </refsect1>
+
+  <refsect1 id="kinetis-twr-k60n512-config"><title>Configuration</title>
+    <refsect2 id="kinetis-twr-k60n512-config-hardware"><title>Hardware Setup</title>
+      <para>
+      Factory jumper settings on the TWR-K60N512 are fitted for standalone operation of the TWR-K60N512.
+      In order to use it with the Ethernet PHY on TWR-SER, some jumpers have to be changed from their factory
+      settings on both TWR-K60N512 and TWR-SER:
+      </para>
+      <table frame="all"><title>TWR-K60N512 Jumper setting differences from factory settings</title>
+        <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="jumper" colwidth="1*" >
+          <colspec colnum="2" colname="jumpset" colwidth="1*" >
+          <colspec colnum="3" colname="desc" colwidth="3*" >
+        <thead>
+          <row>
+            <entry>Jumper</entry>
+            <entry>Setting</entry>
+            <entry>Description</entry>
+          </row>
+        </thead>
+        <tbody>
+          <row>
+            <entry>J6</entry>
+            <entry>2-3</entry>
+            <entry>Select TWR-SER oscillator as clock source.</entry>
+          </row>
+        </tbody>
+      </tgroup>
+      </table>
+      
+      <table frame="all"><title>TWR-SER Jumper settings differences from factory settings</title>
+      <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="jumper" colwidth="1*" >
+          <colspec colnum="2" colname="jumpset" colwidth="1*" >
+          <colspec colnum="3" colname="desc" colwidth="3*" >
+        <thead>
+          <row>
+            <entry>Jumper</entry>
+            <entry>Setting</entry>
+            <entry>Description</entry>
+          </row>
+        </thead>
+        <tbody>
+          <row>
+            <entry>J2</entry>
+            <entry>3-4</entry>
+            <entry>Ethernet PHY clock select: 50MHz</entry>
+          </row>
+          <row>
+            <entry>J3</entry>
+            <entry>2-3</entry>
+            <entry>Route 50MHz to CLOCKIN0</entry>
+          </row>
+          <row>
+            <entry>J12</entry>
+            <entry>9-10</entry>
+            <entry>Ethernet PHY config: select RMII mode</entry>
+          </row>
+        </tbody>
+      </tgroup>
+    </table>
+     </refsect2>
+    <refsect2 id="kinetis-twr-k60n512-config-ecos"><title>eCos Configuration</title>
+  <refsect3 id="twr-k60n512-clocking"><title>Clocking</title>
+    <para>
+    TWR-K60N512 uses default Kinetis variant clocking.
+    </para>
+  </refsect3>  
+  <refsect3 id="twr-k60n512-memory"><title>Memory</title>
+    <para> K60 has two 64KiB SRAM banks giving a total of 128KiB on chip SRAM. </para>
+  </refsect3>
+ </refsect2>
+  </refsect1>
+</refentry>
+
+<!--</part>-->
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h
new file mode 100644
index 0000000..cb6ab53
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributor(s):
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512 platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h
new file mode 100644
index 0000000..530458c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512 platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
new file mode 100644
index 0000000..76a46f8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/include/plf_io.h
@@ -0,0 +1,151 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512 platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
+
+
+// UART PINs
+
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+#endif
+
+// ENET PINs
+
+// MDIO
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO    CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC     CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0)
+// Both RMII and MII interface
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER    CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \
+                                                    CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1    CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0    CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN    CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0    CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1    CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0)
+// RMII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV  CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0)
+// MII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3     CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2     CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK    CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2     CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK    CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3     CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS      CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER     CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL      CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0)
+// IEEE 1588 timers
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN    CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0)
+
+#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0)
+#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
+#endif
+
+
+// DSPI
+// DSPI Pins
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c
new file mode 100644
index 0000000..146499f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512/current/src/twr_k60n512_misc.c
@@ -0,0 +1,208 @@
+//==========================================================================
+//
+//      twr_k60n512_misc.c
+//
+//      Cortex-M4 TWR-K60N512 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
+    hal_wdog_disable();
+    hal_misc_init();
+    hal_start_clocks();
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // Main RAM
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1      },      // External flash
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k60n512_misc.c
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
new file mode 100644
index 0000000..9f52f91
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog
@@ -0,0 +1,103 @@
+2013-04-28  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h: (New)
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi: (New)
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_ram.h: (Remove)
+	* include/pkgconf/mlt_kinetis_flash_sram2s_ram.ldi: (Remove)
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h:
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h:
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi:
+	* include/plf_io.h:
+	* misc/redboot_K60_FXM_SST25XX_ROM.ecm: (New)
+	* src/twr_k60n512_fxm_misc.c:
+	Rich memory layout for FlexBus RAM with support for caching.
+	Remove redundant MLT files. [ Bugzilla 1001837 ]
+
+2013-04-09  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k60n512_fxm_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2012-11-06 Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	Removed (obsolete) implementation of CYGINT_HAL_CORTEXM4_CODE.
+
+2012-10-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi:
+	* src/twr_k60n512_misc_fxm.c: Initialization for separate SRAM regions
+	synchronized with variant.                  [Bugzilla 1001606]
+
+2012-01-06 Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl,
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
+	* /src/twr_k60n512_fxm_misc.c
+	Fixed memory layout for FlexBus memory. Add different pin options
+	[Bugzilla 1001579]
+
+2012-01-06 Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* include/hal_kinetis_flexbus.h
+	* src/twr_k60n512_fxm_misc.c:
+	* include/pkgconf/mltkinetis_flash_sram2s_extram_rom.h
+	* include/pkgconf/mltkinetis_flash_sram2s_extram_rom.ldi
+	* include/pkgconf/mltkinetis_flash_sram2s_jtag.h
+	* include/pkgconf/mltkinetis_flash_sram2s_jtag.ldi
+	* include/pkgconf/mltkinetis_flash_sram2s_ram.h
+	* include/pkgconf/mltkinetis_flash_sram2s_ram.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_extram.h
+	* include/pkgconf/mltkinetis_flash_unisram_extram_jtag.h
+	* include/pkgconf/mltkinetis_flash_unisram_extram_jtag.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_extram.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_extram_ram.h
+	* include/pkgconf/mltkinetis_flash_unisram_extram_ram.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_extram_rom.h
+	* include/pkgconf/mltkinetis_flash_unisram_extram_rom.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_jtag.h
+	* include/pkgconf/mltkinetis_flash_unisram_jtag.ldi
+	* include/pkgconf/mltkinetis_flash_unisram_ram.h
+	* include/pkgconf/mltkinetis_flash_unisram_ram.ldi
+	New package -- Freescale TWR-K60N512-FXM board.  [Bugzilla 1001450]
+	
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl
new file mode 100644
index 0000000..5f370ce
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl
@@ -0,0 +1,648 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k60n512_fxm.cdl
+##
+##      Cortex-M Freescale TWR-K60N512 + TWR-FXM platform HAL configuration
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-09-26
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K60N512_FXM {
+    display       "Freescale Kinetis TWR-K60N512-FXM Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k60n512_fxm.h
+    include_dir   cyg/hal
+    hardware
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+    implements    CYGINT_IO_FREESCALE_I2C0
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART4
+    implements    CYGINT_HAL_FREESCALE_UART4
+
+    description   "
+    The Freescale TWR K60N512 FXM Platform package provides the support
+    needed to run eCos on the TWR K60N512 development system equipped
+    with TWR-FXM external memory board. This package
+    can also be used for other boards that employ a controller from Kinetis
+    families."
+
+    compile       twr_k60n512_fxm_misc.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+        (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K60N512-FXM\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYG_HAL_STARTUP_PLF {
+        display       "By platform"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { "ROM" }
+        legal_values  { "ByVariant" "ROM" "RAM" }
+        requires      { CYG_HAL_STARTUP_PLF != "ByVariant" implies
+                        CYGPKG_HAL_CORTEXM_KINETIS_FBRAM == 1 }
+
+        description   "
+            Startup tupes provided by the platform, in addition to variant
+            startup types.
+            If 'ByVariant' is selected, then startup type shall be selected from
+            the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup builds
+            application similar to Variant's 'ROM' but using external RAM (FlexBus).
+            'RAM' startup builds application intended for loading by RedBoot into
+            external RAM."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT_PLF {
+        display "Memory layout by platform"
+        flavor data
+        no_define
+        active_if { CYG_HAL_STARTUP_PLF != "ByVariant" }
+        implements CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+        parent  CYGHWR_MEMORY_LAYOUT
+        calculated {
+            (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" :
+            (CYG_HAL_STARTUP == "RAM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_ram" :
+            (CYG_HAL_STARTUP == "ROM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_rom" :
+            "Error!" }
+        description "Combination of 'Startup type' and 'Kinetis member in use'
+        produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_RAM_RESERVED {
+            display "Reserved RAM space \[Bytes\]"
+            flavor  data
+            legal_values 0 to 0x40000
+            default_value 0x20000
+        }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platform Clock Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        default_value 50000000
+        legal_values { 25000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 1
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+        The TWR board has one serial port fitted to RS232 connector. This option
+        chooses which port will be used to connect to a host
+        running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+        The TWR has one serial port fitted to RS232 connector. This option
+        chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+        This option controls the default baud rate used for the
+        console connection.
+        Note: this should match the value chosen for the GDB port if the
+        diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+        This option controls the default baud rate used for the
+        GDB connection.
+        Note: this should match the value chosen for the console port if the
+        console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+        }
+    }
+
+    cdl_option CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR {
+        display "SST25XX Flash Mapping Address"
+        flavor data
+        parent CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0
+        default_value 0xD0000000
+    }
+    cdl_component CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_BUS {
+        display "SST25xx SPI bus"
+        flavor data
+        parent CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+
+        cdl_option CYGHWR_DEVS_FLASH_SST25XX_DEV0_SPI_CS {
+            display "Device number (CS)"
+            flavor data
+            calculated 1
+            implements CYGINT_FREESCALE_DSPI1_CS1
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGPKG_HAL_EXTRN_MEMORY {
+        display "External memory devices"
+        parent CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+        flavor none
+        active_if {
+            CYGHWR_HAL_KINETIS_FB_CS0 || CYGHWR_HAL_KINETIS_FB_CS1 ||
+            CYGHWR_HAL_KINETIS_FB_CS2 || CYGHWR_HAL_KINETIS_FB_CS3 ||
+            CYGHWR_HAL_KINETIS_FB_CS4 || CYGHWR_HAL_KINETIS_FB_CS5
+        }
+        description "
+        This is a container for  memory devices attached to
+        external bus such as RAM, FLASH, etc."
+    }
+# FlexBus Implementation
+    implements CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
+    implements CYGINT_HAL_EXTRN_MEMORY
+
+# CS0 Implementation
+    implements CYGINT_HAL_KINETIS_FB_CS0
+    implements CYGINT_DEVS_RAM0_MICRON_CELLULAR
+    requires { is_active(CYGPKG_HAL_CORTEXM_KINETIS_FBRAM) implies
+                         CYGHWR_HAL_KINETIS_FBR_SIZE == CYGHWR_HAL_KINETIS_FB_CS0_SIZE }
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_CS0_AR {
+        display "Base address"
+        flavor data
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+        default_value  0x60000000
+    }
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_CS0_SIZE {
+        display "Size \[Bytes\]"
+        flavor data
+        legal_values  { 0x00040000  0x00400000 CYGHWR_RAM0_MICRON_CELLULAR_SIZE }
+        parent        CYGHWR_HAL_KINETIS_FB_CS0
+        default_value CYGHWR_RAM0_MICRON_CELLULAR_SIZE
+    }
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_CS0_BASE {
+        display "Memory base address"
+        flavor data
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+        calculated CYGHWR_HAL_KINETIS_FB_CS0_AR
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS0_MR {
+        display "Mask register"
+        flavor data
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+        default_value 0x00FF0001
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_MR_WP {
+            display "Write protect"
+            flavor bool
+            default_value 0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR {
+        display "Control register"
+        flavor none
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_WS {
+            display "Wait states"
+            flavor data
+            default_value 3
+            legal_values 0 to 63
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BLS {
+            display "Byte lane shift"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_AA {
+            display "Auto acknowledge enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR_PSB {
+            display "Port size (bits)"
+            flavor data
+            legal_values { 32 8 16 "-16" }
+            default_value 16
+
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_SWSEN {
+            display "Secondary wait states enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_SWS {
+            display "Secondary wait states"
+            flavor data
+            legal_values 0 to 63
+            default_value 0
+
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_EXALE {
+            display "Extended address latch enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_ASET {
+            display "Address setup"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_RDAH {
+            display "Read address hold or deselect"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_WRAH {
+            display "Write address hold or deselect"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BEM {
+            display "Byte enable mode"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BSTR {
+            display "Burst read enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_BSTW {
+            display "Burst write enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+        }
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS0_CR_IS {
+        display "Control register initial setting."
+        flavor none
+        parent CYGHWR_HAL_KINETIS_FB_CS0
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_WS {
+            display "Wait states"
+            flavor data
+            default_value 3
+            legal_values 0 to 63
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_AA {
+            display "Auto acknowledge enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_SWSEN {
+            display "Secondary wait states enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_SWS {
+            display "Secondary wait states"
+            flavor data
+            legal_values 0 to 63
+            default_value 0
+
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_EXALE {
+            display "Extended address latch enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_ASET {
+            display "Address setup"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_RDAH {
+            display "Read address hold or deselect"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_WRAH {
+            display "Write address hold or deselect"
+            flavor data
+            legal_values { 0 1 2 3 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BEM {
+            display "Byte enable mode"
+            flavor data
+            legal_values { 0 1 }
+            default_value 1
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BSTR {
+            display "Burst read enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS0_CR_IS_BSTW {
+            display "Burst write enable"
+            flavor data
+            legal_values { 0 1 }
+            default_value 0
+        }
+    }
+# CS0 Implementation End
+# FlexBus  Implementation End
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE {
+        display "External RAM size"
+        flavor data
+        calculated CYGHWR_HAL_KINETIS_FB_CS0_SIZE
+    }
+
+    cdl_option CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE {
+        display "External RAM base address"
+        flavor data
+        calculated CYGHWR_HAL_KINETIS_FB_CS0_BASE
+    }
+
+    cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK {
+        display "ENET MII MDC clock provided by HAL"
+        flavor data
+        active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+        parent CYGPKG_DEVS_ETH_FREESCALE_ENET
+        calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS
+        description "
+            ENET needs a clock with typical frequency of up to 2.5 MHz for
+            MII MDC. The input clock, typically provided by HAL, is further
+            divided by ENET according to setting of ENET MSCR register in order to
+            provide frequency within 2.5 MHz range."
+     }
+
+    cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT {
+        display "IEEE 1588 Port"
+        active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        flavor data
+        default_value { "B" }
+        legal_values { "B" "C" "User" }
+        description "
+            Digital I/O provided by HAL for ENET IEEE 1588 timers."
+    }
+
+
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+        Global build options including control over
+        compiler flags, linker flags and choice of toolchain."
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+            This option specifies the command prefix used when
+            invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+            This option controls the global compiler flags which are used to
+            compile all packages by default. Individual packages may define
+            options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+            This option controls the global linker flags. Individual
+            packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+        Enable this option if this program is to be used as a ROM monitor,
+        i.e. applications will be loaded into RAM on the board, and this
+        ROM monitor may process exceptions or interrupts generated from the
+        application. This enables features such as utilizing a separate
+        interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+        Support can be enabled for different varieties of ROM monitor.
+        This support changes various eCos semantics such as the encoding
+        of diagnostic output, or the overriding of hardware interrupt
+        vectors.
+        Firstly there is \"Generic\" support which prevents the HAL
+        from overriding the hardware vectors that it does not use, to
+        instead allow an installed ROM monitor to handle them. This is
+        the most basic support which is likely to be common to most
+        implementations of ROM monitor.
+        \"GDB_stubs\" provides support when GDB stubs are included in
+        the ROM monitor or boot ROM."
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK60N512_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "This component causes the ELF image generated by the
+        build process to be converted to S-Record and binary
+        files."
+    }
+}
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h
new file mode 100644
index 0000000..ac10c73
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h
@@ -0,0 +1,143 @@
+#ifndef CYGONCE_FLEXBUS_H
+#define CYGONCE_FLEXBUS_H
+//=============================================================================
+//
+//      flexbus.h
+//
+//      Kinetis FlexBus specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-08-05
+// Purpose:     Kinetis FlexBus specific registers
+// Description:
+// Usage:       #include <cyg/hal/flexbus.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//--------------------------------------------------------------------------
+// Flexbus pins
+
+#define KINETIS_PIN_FB_OPT CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M
+#define KINETIS_PIN_FB     5
+#define KINETIS_PIN_FB6    6
+
+#define CYGHWR_KINETIS_FB_PIN_AD0  CYGHWR_HAL_KINETIS_PIN(D, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD1  CYGHWR_HAL_KINETIS_PIN(D, 5, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD2  CYGHWR_HAL_KINETIS_PIN(D, 4, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD3  CYGHWR_HAL_KINETIS_PIN(D, 3, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD4  CYGHWR_HAL_KINETIS_PIN(D, 2, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD5  CYGHWR_HAL_KINETIS_PIN(C, 10, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD6  CYGHWR_HAL_KINETIS_PIN(C, 9, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD7  CYGHWR_HAL_KINETIS_PIN(C, 8, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD8  CYGHWR_HAL_KINETIS_PIN(C, 7, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD9  CYGHWR_HAL_KINETIS_PIN(C, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD10 CYGHWR_HAL_KINETIS_PIN(C, 5, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD11 CYGHWR_HAL_KINETIS_PIN(C, 4, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD12 CYGHWR_HAL_KINETIS_PIN(C, 2, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD13 CYGHWR_HAL_KINETIS_PIN(C, 1, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD14 CYGHWR_HAL_KINETIS_PIN(C, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD15 CYGHWR_HAL_KINETIS_PIN(B, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD16 CYGHWR_HAL_KINETIS_PIN(B, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD17 CYGHWR_HAL_KINETIS_PIN(B, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD18 CYGHWR_HAL_KINETIS_PIN(B, 11, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD19 CYGHWR_HAL_KINETIS_PIN(B, 10, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD20 CYGHWR_HAL_KINETIS_PIN(B, 9, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD21 CYGHWR_HAL_KINETIS_PIN(B, 8, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD22 CYGHWR_HAL_KINETIS_PIN(B, 7, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD23 CYGHWR_HAL_KINETIS_PIN(B, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD24 CYGHWR_HAL_KINETIS_PIN(C, 15, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD25 CYGHWR_HAL_KINETIS_PIN(C, 14, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD26 CYGHWR_HAL_KINETIS_PIN(C, 13, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD27 CYGHWR_HAL_KINETIS_PIN(C, 12, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD28 CYGHWR_HAL_KINETIS_PIN(B, 23, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD29 CYGHWR_HAL_KINETIS_PIN(B, 22, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD30 CYGHWR_HAL_KINETIS_PIN(B, 21, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_AD31 CYGHWR_HAL_KINETIS_PIN(B, 20, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_A16 CYGHWR_HAL_KINETIS_PIN(D, 8, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A17 CYGHWR_HAL_KINETIS_PIN(D, 9, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A18 CYGHWR_HAL_KINETIS_PIN(D, 10, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A19 CYGHWR_HAL_KINETIS_PIN(D, 11, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A20 CYGHWR_HAL_KINETIS_PIN(D, 12, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A21 CYGHWR_HAL_KINETIS_PIN(D, 13, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A22 CYGHWR_HAL_KINETIS_PIN(D, 14, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_A23 CYGHWR_HAL_KINETIS_PIN(D, 15, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_CLKOUT CYGHWR_HAL_KINETIS_PIN(C, 3, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CLKOUT_OFF                                     \
+            CYGHWR_HAL_KINETIS_PIN(C, 3, CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO, \
+                                         CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+
+#define CYGHWR_KINETIS_FB_PIN_RW CYGHWR_HAL_KINETIS_PIN(C, 11, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_OE CYGHWR_HAL_KINETIS_PIN(B, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+// Following pins are additionally multiplexed by FB_CSPMCR
+
+#define CYGHWR_KINETIS_FB_PIN_BE23_16 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BE31_24 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BE15_8  CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BE7_0   CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_BLS15_8  CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BLS7_0   CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BLS23_16 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_BLS31_24 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_CS5 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS4 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(D, 1, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_CS0_LOW  \
+                    CYGHWR_HAL_KINETIS_PIN(D, 1, CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO, \
+                             CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+
+#define CYGHWR_KINETIS_FB_PIN_TSIZ0 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_TSIZ1 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_TST   CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_ALE   CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+#define CYGHWR_KINETIS_FB_PIN_TS    CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT)
+
+#define CYGHWR_KINETIS_FB_PIN_TA    CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT)
+
+//-----------------------------------------------------------------------------
+// end of flexbus.h
+#endif // CYGONCE_FLEXBUS_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
new file mode 100644
index 0000000..daf0474
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
@@ -0,0 +1,32 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
new file mode 100644
index 0000000..6095daa
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
@@ -0,0 +1,41 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE
+    sram   : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA)
+    SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
+
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
new file mode 100644
index 0000000..a00ce95
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
@@ -0,0 +1,40 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_BASE)
+//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE)
+//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
new file mode 100644
index 0000000..3888a13
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
@@ -0,0 +1,49 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    sram   : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000, FOLLOWING (.got))
+    SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h
new file mode 100644
index 0000000..53dceb8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi
new file mode 100644
index 0000000..f8330ee
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi
@@ -0,0 +1,35 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE
+    sram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
new file mode 100644
index 0000000..b466a08
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
@@ -0,0 +1,28 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
new file mode 100644
index 0000000..bab581b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
@@ -0,0 +1,39 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+
+MEMORY
+{
+    sram   : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
+    SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA)
+    SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
new file mode 100644
index 0000000..5c6db56
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
@@ -0,0 +1,32 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
new file mode 100644
index 0000000..b43ce41
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
@@ -0,0 +1,47 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram   : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h
new file mode 100644
index 0000000..5370f8f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h
@@ -0,0 +1,24 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi
new file mode 100644
index 0000000..e74d8a9
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH security configuration. Must be present at 0x00000400
+    // Warning: Omitting FLASH security configuration or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+    
+    .flash_security 0x00000400 : { KEEP (*(.flash_security)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h
new file mode 100644
index 0000000..329056b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributor(s):
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512-FXM platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h
new file mode 100644
index 0000000..a443eed
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512-FXM platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h
new file mode 100644
index 0000000..6b2ddab
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h
@@ -0,0 +1,194 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-02-05
+// Purpose:     TWR-K60N512 platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>
+
+// UART PINs
+
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# if 0
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 5, 3, 0)
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 4, 3, 0)
+# elif 0
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0)
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0)
+# else
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#  define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# endif
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# if 0
+#  define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+#  define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+#  define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+#  define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+# endif
+#endif
+
+#if 1
+#ifndef CYGHWR_HAL_FREESCALE_UART4_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 25, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 24, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_FREESCALE_UART4_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_FREESCALE_UART4_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_FREESCALE_UART4_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_FREESCALE_UART4_PIN_CTS
+
+#endif
+#endif
+
+
+// ENET PINs
+
+// MDIO
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO    CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC     CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0)
+// Both RMII and MII interface
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER    CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \
+                                                    CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1    CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0    CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN    CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0    CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1    CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0)
+// RMII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV  CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0)
+// MII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3     CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2     CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK    CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2     CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK    CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3     CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS      CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER     CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL      CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0)
+// IEEE 1588 timers
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN    CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0)
+
+#if defined(CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT_B)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0)
+#elif defined(CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT_C)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
+#endif
+
+// FlexBus Memory
+#define CYGHWR_HAL_FB_CSPMCR_G1_SEL CYGHWR_HAL_FB_CSPMCR_G1_TS
+#define CYGHWR_HAL_FB_CSPMCR_G2_SEL CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24
+#define CYGHWR_HAL_FB_CSPMCR_G3_SEL CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16
+#define CYGHWR_HAL_FB_CSPMCR_G4_SEL CYGHWR_HAL_FB_CSPMCR_G4_CS2
+#define CYGHWR_HAL_FB_CSPMCR_G5_SEL CYGHWR_HAL_FB_CSPMCR_G5_TA
+
+#define CYGHWR_HAL_FB_CSPMCR_SETSEL (CYGHWR_HAL_FB_CSPMCR_G1_SEL + \
+                                     CYGHWR_HAL_FB_CSPMCR_G2_SEL + \
+                                     CYGHWR_HAL_FB_CSPMCR_G3_SEL + \
+                                     CYGHWR_HAL_FB_CSPMCR_G4_SEL + \
+                                     CYGHWR_HAL_FB_CSPMCR_G5_SEL )
+
+// DSPI
+// DSPI Pins
+
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M)
+
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M)
+
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm
new file mode 100644
index 0000000..59dd5b0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/misc/redboot_K60_FXM_SST25XX_ROM.ecm
@@ -0,0 +1,81 @@
+# Redboot minimal configuration
+# Target: TWR-K70F120M
+# Startup: ROM with external RAM
+
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "RedBoot Kinetis TWR-K60N512-FXM" ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_component CYGHWR_DEVS_FLASH_SPI_SST25XX_DEV0 {
+    user_value 1
+};
+
+cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP {
+    user_value 100000000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+    user_value 16384
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 0
+};
+
+#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+#    user_value 1
+#};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    user_value -4
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+    user_value -8
+};
+
+#cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+#    user_value 16
+#};
+
+#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+#    user_value 0x20000
+#};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    user_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    user_value ROM
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    user_value 1
+};
+
+cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA {
+    user_value 1
+};
+
+
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c
new file mode 100644
index 0000000..5a17836
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c
@@ -0,0 +1,446 @@
+//==========================================================================
+//
+//      twr_k60n512_fxm_misc.c
+//
+//      Cortex-M3 TWR-K60N512 EVAL + TWR_FXM HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+#include <cyg/hal/hal_kinetis_flexbus.h>
+#include <cyg/devs/ram_micron_cellularram.h>
+
+// Dependent on FlexBus memory properties up to two flexbus setting stages
+// may be needed
+
+// Macro for final setting of CSCR
+// Final settings take place when system clock is completely initialized and
+// it is possible to program FlexBus memory with desired setting.
+#define CYGHWR_HAL_FB_CSCR(__bits,__cs) \
+            VALUE_(CYGHWR_HAL_FB_CSCR_##__bits##_S, \
+                   CYGHWR_HAL_KINETIS_FB_CS##__cs##_CR_##__bits)
+
+#define CYGHWR_HAL_KINETIS_FB_CS_CR(__cs) ( CYGHWR_HAL_FB_CSCR(SWS, __cs)  + \
+         CYGHWR_HAL_FB_CSCR(SWSEN, __cs) + CYGHWR_HAL_FB_CSCR(EXALE, __cs) + \
+         CYGHWR_HAL_FB_CSCR(ASET, __cs)  + CYGHWR_HAL_FB_CSCR(RDAH, __cs)  + \
+         CYGHWR_HAL_FB_CSCR(WRAH, __cs)  + CYGHWR_HAL_FB_CSCR(WS, __cs)    + \
+         CYGHWR_HAL_FB_CSCR(BLS, __cs)   + CYGHWR_HAL_FB_CSCR(AA, __cs)    + \
+         CYGHWR_HAL_FB_CSCR(PS, __cs)    + CYGHWR_HAL_FB_CSCR(BEM, __cs)   + \
+         CYGHWR_HAL_FB_CSCR(BSTR, __cs)  + CYGHWR_HAL_FB_CSCR(BSTW, __cs))
+
+// Macros for initial settings of CSCR
+// Initial settings are used immediately after boot and make it possible to
+// utilize FlexBus memory with it's power-up setting.
+#define CYGHWR_HAL_FB_CSCR_IS(__bits,__cs) \
+            VALUE_(CYGHWR_HAL_FB_CSCR_##__bits##_S, \
+                   CYGHWR_HAL_KINETIS_FB_CS##__cs##_CR_IS_##__bits)
+
+#define CYGHWR_HAL_KINETIS_FB_CS_CR_IS(__cs) ( CYGHWR_HAL_FB_CSCR_IS(SWS, __cs)   + \
+          CYGHWR_HAL_FB_CSCR_IS(SWSEN, __cs) + CYGHWR_HAL_FB_CSCR_IS(EXALE, __cs) + \
+          CYGHWR_HAL_FB_CSCR_IS(ASET, __cs)  + CYGHWR_HAL_FB_CSCR_IS(RDAH, __cs)  + \
+          CYGHWR_HAL_FB_CSCR_IS(WRAH, __cs)  + CYGHWR_HAL_FB_CSCR_IS(WS, __cs)    + \
+          CYGHWR_HAL_FB_CSCR(BLS, __cs)      + CYGHWR_HAL_FB_CSCR_IS(AA, __cs)    + \
+          CYGHWR_HAL_FB_CSCR(PS, __cs)       + CYGHWR_HAL_FB_CSCR_IS(BEM, __cs)   + \
+          CYGHWR_HAL_FB_CSCR_IS(BSTR, __cs)  + CYGHWR_HAL_FB_CSCR_IS(BSTW, __cs))
+
+// Functions for final and initial FlexBus setting
+// Description is with the code below.
+static inline void hal_flexbus_init_initial(void);
+static inline void hal_flexbus_init_final(void);
+#endif //  CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
+    hal_wdog_disable();
+    hal_misc_init();
+# ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+    {
+        // This delay is needed for Micron RAM wake-up.
+        cyg_uint32 busy_delay;
+        for(busy_delay = 0x100000; busy_delay; busy_delay--)
+            __asm__ volatile ("nop\n");
+
+        hal_flexbus_init_initial();
+
+        hal_start_clocks();
+
+        for(busy_delay = 0x100000; busy_delay; busy_delay--)
+            __asm__ volatile ("nop\n");
+
+        hal_flexbus_init_final();
+    }
+# else
+        hal_start_clocks();
+# endif
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+
+// FlexBus
+
+static const cyg_uint32 const flexbus_pins[] = {
+    CYGHWR_KINETIS_FB_PIN_CLKOUT_OFF,
+
+    CYGHWR_KINETIS_FB_PIN_CS0,
+    CYGHWR_KINETIS_FB_PIN_OE,
+    CYGHWR_KINETIS_FB_PIN_RW,
+# if 0 //(CYGHWR_HAL_KINETIS_FB_CS_CR(0) & CYGHWR_HAL_FB_CSCR_BLS_M)
+    CYGHWR_KINETIS_FB_PIN_BLS7_0,
+    CYGHWR_KINETIS_FB_PIN_BLS15_8,
+# else
+    CYGHWR_KINETIS_FB_PIN_BE23_16,
+    CYGHWR_KINETIS_FB_PIN_BE31_24,
+# endif
+    CYGHWR_KINETIS_FB_PIN_TS,
+
+    CYGHWR_KINETIS_FB_PIN_AD0,
+    CYGHWR_KINETIS_FB_PIN_AD1,
+    CYGHWR_KINETIS_FB_PIN_AD2,
+    CYGHWR_KINETIS_FB_PIN_AD3,
+    CYGHWR_KINETIS_FB_PIN_AD4,
+    CYGHWR_KINETIS_FB_PIN_AD5,
+    CYGHWR_KINETIS_FB_PIN_AD6,
+    CYGHWR_KINETIS_FB_PIN_AD7,
+    CYGHWR_KINETIS_FB_PIN_AD8,
+    CYGHWR_KINETIS_FB_PIN_AD9,
+    CYGHWR_KINETIS_FB_PIN_AD10,
+    CYGHWR_KINETIS_FB_PIN_AD11,
+    CYGHWR_KINETIS_FB_PIN_AD12,
+    CYGHWR_KINETIS_FB_PIN_AD13,
+    CYGHWR_KINETIS_FB_PIN_AD14,
+    CYGHWR_KINETIS_FB_PIN_AD15,
+    CYGHWR_KINETIS_FB_PIN_AD16,
+    CYGHWR_KINETIS_FB_PIN_AD17
+# if CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000
+    ,
+    CYGHWR_KINETIS_FB_PIN_AD18,
+    CYGHWR_KINETIS_FB_PIN_AD19,
+    CYGHWR_KINETIS_FB_PIN_AD20,
+    CYGHWR_KINETIS_FB_PIN_AD21
+#  if CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00400000
+    ,
+    CYGHWR_KINETIS_FB_PIN_AD22,
+    CYGHWR_KINETIS_FB_PIN_AD23
+#   if 0 //!(CYGHWR_HAL_KINETIS_FB_CS_CR(0) & CYGHWR_HAL_FB_CSCR_BLS_M)
+    ,
+    CYGHWR_KINETIS_FB_PIN_AD24,
+    CYGHWR_KINETIS_FB_PIN_AD25,
+    CYGHWR_KINETIS_FB_PIN_AD26,
+    CYGHWR_KINETIS_FB_PIN_AD27,
+    CYGHWR_KINETIS_FB_PIN_AD28,
+    CYGHWR_KINETIS_FB_PIN_AD29,
+    CYGHWR_KINETIS_FB_PIN_AD30,
+    CYGHWR_KINETIS_FB_PIN_AD31
+#   endif
+#  endif  // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00400000
+# endif // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000
+};
+
+static const cyg_uint32 const flexbus_pins_final_diff[] = {
+    CYGHWR_KINETIS_FB_PIN_CLKOUT
+};
+
+// Initialize FlexBus for use until we have main clock.
+// Asynchronous mode.
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_flexbus_init_initial(void)
+{
+    cyghwr_hal_kinetis_fb_t *fb_p = CYGHWR_HAL_KINETIS_FB_P;
+
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS);
+
+# ifdef CYGHWR_HAL_KINETIS_FB_CS0
+    fb_p->csel[0] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS0_AR,
+              CYGHWR_HAL_KINETIS_FB_CS0_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(0) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS1
+    fb_p->csel[1] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS1_AR,
+              CYGHWR_HAL_KINETIS_FB_CS1_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(1) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS2
+    fb_p->csel[2] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS2_AR,
+              CYGHWR_HAL_KINETIS_FB_CS2_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(2) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS3
+    fb_p->csel[3] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS3_AR,
+              CYGHWR_HAL_KINETIS_FB_CS3_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(3) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS4
+    fb_p->csel[4] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS4_AR,
+              CYGHWR_HAL_KINETIS_FB_CS4_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(4) };
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS4
+    fb_p->csel[5] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS5_AR,
+              CYGHWR_HAL_KINETIS_FB_CS5_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(5) };
+# endif
+
+    fb_p->cspmcr = CYGHWR_HAL_FB_CSPMCR_SETSEL;
+
+    HAL_SET_PINS(flexbus_pins);
+}
+
+// Initialize FlexBus to it's normal working condition
+// Synchronous mode with burst support
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_flexbus_init_final(void)
+{
+    cyghwr_hal_kinetis_fb_t *fb_p = CYGHWR_HAL_KINETIS_FB_P;
+
+    // Enable RAM synchronous/burst mode
+    ram_micron_reg_set(CYGHWR_DEVS_RAM_MICRON_BCR,
+                           CYGHWR_RAM0_MICRON_BCR_SETTO,
+                           (cyg_uint16 *)CYGHWR_HAL_KINETIS_FB_CS0_AR,
+                       CYGHWR_RAM0_MICRON_CELLULAR_SIZE);
+
+    // Apply FlexBus clock...
+    HAL_SET_PINS(flexbus_pins_final_diff);
+
+    // ...and final CS setting for burst, etc.
+# ifdef CYGHWR_HAL_KINETIS_FB_CS0
+    fb_p->csel[0].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(0);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS1
+    fb_p->csel[1].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(1);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS2
+    fb_p->csel[2].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(2);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS3
+    fb_p->csel[3].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(3);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS4
+    fb_p->csel[4].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(4);
+# endif
+# ifdef CYGHWR_HAL_KINETIS_FB_CS5
+    fb_p->csel[5].cscr = CYGHWR_HAL_KINETIS_FB_CS_CR(5);
+# endif
+}
+
+#endif // CYGHWR_HAL_CORTEXM_KINETIS_FLEXBUS
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1        }, // System bus RAM partition
+#if 1 //def CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1      }, // On-chip SRAM
+#elif defined CYGMEM_REGION_sram_l
+    { CYGMEM_REGION_sram_l,     CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1  }, // On-chip SRAM lower bank
+#endif
+#ifdef CYGMEM_REGION_ramcod
+    { CYGMEM_REGION_ramcod,      CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition
+#endif
+#ifdef CYGMEM_REGION_ramnc
+    { CYGMEM_REGION_ramnc,      CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1    }, // Non cachable RAM partition
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1    }, // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1        }, // External flash [currently none]
+#endif
+    { 0xE0000000,               0x00000000-1                                      }, // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                      }  // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) &&
+            ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external RAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_sram_l
+# define CASE_CODE 3
+# define CASE_RAMNC 4
+    case 2:
+        *start = (unsigned char *)CYGMEM_REGION_sram_l;
+        *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE);
+        break;
+#else
+# define CASE_CODE 2
+# define CASE_RAMNC 3
+#endif
+
+#ifdef CYGMEM_REGION_ramcod
+    case CASE_CODE:
+        *start = (unsigned char *)CYGMEM_REGION_ramcod;
+        *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE);
+        break;
+#endif
+
+#ifdef CYGMEM_REGION_ramnc
+    case CASE_RAMNC:
+        *start = (unsigned char *)CYGMEM_REGION_ramnc;
+        *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k60n512_fxm_misc.c
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
new file mode 100644
index 0000000..1d90bda
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
@@ -0,0 +1,110 @@
+2013-04-09  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+
+	Add requirement for WRITETHRU data cache startup mode when eDMA is in use.
+	Sync with change in eDMA driver [ Bugzilla 1001838 ]
+
+2013-04-09  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	* include/plf_io.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/twr_k70f120m_misc.c: Clock gating synchronised with variant.
+	[ Bugzilla 1001814 ]
+
+2013-03-09  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* misc/redboot_K70_ROM_FPU.ecm: Add ECM file
+
+2012-11-30  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Sync with variant changes due to
+	hardware floating point support. Implements CYGINT_HAL_FPV4_SP_D16.
+	Changed maximum peripheral bus clocks to 75MHz.
+	[Bugzilla 1001607]
+
+2012-11-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
+	Recognize 256 Bytes space for virtual vectors in sram.
+
+	* twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	Add settings for Kinetis internal flash.  [Bugzilla 1001561]
+
+2012-09-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
+	* current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
+	* current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
+	* current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
+	* src/twr_k70f120m_misc.c:
+	Synchronized with Kinetis variant changes to SDRAM controller support.
+	Memory layouts adapted to separate data and code cacing partitions.
+	                                            [Bugzilla 1001606]
+
+2012-05-19  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Reference per-package
+	documentation.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* doc/twr_k70f120m.sgml:
+	New file -- TWR-K70F120M platform documentation. [Bug 1001580]
+
+2012-05-17  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	Bug fix: Do not implement external memory interface if Platform startup is
+	not selected. [ Bugzilla 1001590 ]
+
+2012-02-25  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h:
+	* pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi:
+	* pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h:
+	* pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi:
+	* pkgconf/mlt_kinetis_flash_unisram_extram_ram.h:
+	* pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi:
+	* pkgconf/mlt_kinetis_flash_unisram_extram_rom.h:
+	* pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi:
+	* src/twr_k70f120m_misc.c:	
+	New package -- Freescale TWR-K70F120M board. [Bugzilla 1001579]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
new file mode 100644
index 0000000..6d469cf
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl
@@ -0,0 +1,444 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis_twr_k70f120m.cdl
+##
+##      Cortex-M Freescale TWR-K70F120M platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2012-02-25
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M {
+    display       "Freescale Kinetis TWR-K70F120M Platform"
+    parent        CYGPKG_HAL_CORTEXM_KINETIS
+    define_header hal_cortexm_kinetis_twr_k70f120m.h
+    include_dir   cyg/hal
+    doc           ref/kinetis-twr-k70f120m.html
+    hardware
+    description   "
+        The Freescale TWR K70F120M Platform HAL package provides the support
+        needed to run eCos on the TWR K70F120M development system. This package
+        can also be used for other boards that employ a controller from Kinetis
+        families."
+
+    compile       twr_k70f120m_misc.c
+
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    requires      { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET)
+                  implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }
+
+    implements    CYGINT_HAL_CACHE
+
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT == "F" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT == 70 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 30 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 40 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 50 }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == "1M0" }
+    requires      { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE == 0x1000 }
+    requires      { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies
+                    CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 }
+
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART2
+    implements    CYGINT_IO_FREESCALE_I2C0
+    
+    implements    CYGINT_HAL_FREESCALE_UART2
+    implements    CYGINT_HAL_CORTEXM_KINETIS_RTC
+    
+    implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+    implements    CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+    implements    CYGINT_HAL_CORTEXM_KINETIS_150
+
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX == 75000000 }
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX == 75000000 }
+    requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX == 25000000 }
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+        (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) }
+    requires      { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies
+        (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32) }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale TWR-K70F120M\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000"
+    }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYG_HAL_STARTUP_PLF {
+        display       "By platform"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { "ROM" }
+        legal_values  { "ByVariant" "ROM" "RAM" }
+
+        requires      { CYG_HAL_STARTUP_PLF != "ByVariant" implies
+                        CYGPKG_HAL_CORTEXM_KINETIS_DDRMC == 1 }
+
+        description   "
+            Startup tupes provided by the platform, in addition to variant
+            startup types.
+            If 'ByVariant' is selected, then startup type shall be selected
+            from the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup
+            builds application similar to Variant's 'ROM' but using external
+            RAM (DDRAM). 'RAM' startup builds application intended for loading
+            by RedBoot into external RAM."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT_PLF {
+        display "Memory layout by platform"
+        flavor data
+        active_if { CYG_HAL_STARTUP_PLF != "ByVariant" }
+        implements CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+        no_define
+        parent  CYGHWR_MEMORY_LAYOUT
+        calculated {
+            (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" :
+            (CYG_HAL_STARTUP == "RAM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_ram" :
+            (CYG_HAL_STARTUP == "ROM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_extram_rom" :
+            "Error!"
+        }
+        description "
+            Combination of 'Startup type' and 'Kinetis member in use'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_RAM_RESERVED {
+            display "Reserved RAM space \[Bytes\]"
+            flavor  data
+            legal_values 0 to 0x40000
+            default_value 0x20000
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP {
+        display "Platform suggested system frequency setpoint"
+        flavor data
+        no_define
+        legal_values 96000000 100000000 120000000 150000000 200000000
+        default_value 120000000
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP {
+        display "Platform suggested auxiliary frequency setpoint"
+        flavor data
+        no_define
+        legal_values 96000000 100000000 120000000 150000000 200000000
+        default_value 120000000
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ {
+        display "Platgorm XTAL/OSC Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 12000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ {
+        display "Platform XTAL1/OSC1 Frequency"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC" ||
+                   CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        default_value 50000000
+        legal_values { 12000000 50000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP {
+        display "Platform requred XTAL || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC1_CAP {
+        display "Platform requred XTAL1 || C \[pF\]"
+        flavor bool
+        default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+        active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP == 20 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC {
+        display "Platform requred RTC XTAL || C \[pF\]"
+        flavor bool
+        default_value 0
+        parent CYGHWR_HAL_CORTEXM_KINETIS_RTC
+        requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 }
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR board has one serial port fitted to RS232 connector.
+            This option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The TWR has one serial port fitted to RS232 connector.
+            This option chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port
+            if the console and GDB port are the same."
+    }
+
+    cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK {
+        display "ENET MII MDC clock provided by HAL"
+        flavor data
+        active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+        parent CYGPKG_DEVS_ETH_FREESCALE_ENET
+        calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS
+        description "
+            ENET needs a clock with typical frequency of up to 2.5 MHz for
+            MII MDC. The input clock, typically provided by HAL, is further
+            divided by ENET according to setting of ENET MSCR register in order to
+            provide frequency within 2.5 MHz range."
+     }
+
+    cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT {
+        display "IEEE 1588 Port"
+        active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588
+        flavor data
+        default_value { "B" }
+        legal_values { "B" "C" "User" }
+        description "
+            Digital I/O provided by HAL for ENET IEEE 1588 timers."
+    }
+
+    cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS {
+        display "MMC Disk SPI bus"
+        flavor data
+        parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI
+        calculated 1
+
+        requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1
+        implements CYGINT_DEVS_SPI_FREESCALE_DSPI1
+        implements CYGINT_FREESCALE_DSPI1_HAS_MASS
+        requires  { (is_active(CYGSEM_HAL_DCACHE_STARTUP_MODE)
+                    && CYGINT_DEVS_SPI_DSPI_DMA_USE)
+                    implies CYGSEM_HAL_DCACHE_STARTUP_MODE == "WRITETHRU" }
+
+        cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS {
+            display "Device number (CS)"
+            flavor data
+            legal_values { 0 1 2 3 4 5 }
+            default_value 0
+            implements CYGINT_FREESCALE_DSPI1_CS0
+            implements CYGINT_FREESCALE_DSPI1_CS1
+            implements CYGINT_FREESCALE_DSPI1_CS2
+            implements CYGINT_FREESCALE_DSPI1_CS3
+        }
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+
+
+    cdl_component CYGBLD_HAL_CORTEXM_TWR_MK70F120M_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description "
+            This component causes the ELF image generated by the
+            build process to be converted to S-Record and binary
+            files."
+    }
+}
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml
new file mode 100644
index 0000000..6178f5b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml
@@ -0,0 +1,165 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     twr_k70f120m.sgml                                        -->
+<!--                                                                 -->
+<!--     TWR-K70F120M board documentation.                        -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>-->
+
+<refentry id="kinetis-twr-k70f120m">
+  <refmeta>
+    <refentrytitle>TWR-K70F120M Development kit</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M</refname>
+    <refpurpose>eCos Support for Freescale TWR-K70F120M development kit</refpurpose>
+  </refnamediv>
+  
+  <refsect1 id="kinetis-twr-k70f120m-description"><title>Description</title>
+    <para>
+    The Freescale TWR-K70F120M is a development kit for <link linkend="hal-cortexm-kinetis-var">
+    Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers K70, K60, K10 and K20
+    microcontroller subfamilies. K70FN1M0 is a high end member comprising on-chip 1 MiB FLASH
+    and 128 KiB SRAM memory as well as a 16 KiB unified cache.
+    K70 parts are equipped with a rich set of communication interfaces including Ethernet USB, UARTs
+    CAN, SPI and I2C. They also have a Graphics controller and a DMA controller, as well as FlexBus and SDRAM
+    external memory interfaces. They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. 
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-twr-k70f120m-config"><title>Configuration</title>
+    <refsect2 id="kinetis-twr-k70f120m-config-hardware"><title>Hardware Setup</title>
+      <refsect3 id="kinetis-twr-k70f120m-config-hardware-cpu"><title>TWR-K70F120M setup</title>
+      <para>
+      Factory jumper settings on TWR-K70F120M are fitted for standalone operation of the board.
+      In order to use it with the Ethernet PHY from TWR-SER, some jumpers have to be changed
+      on both TWR-K70F120M and TWR-SER. Jumper settings for TWR-SER are given in
+      <link linkend="kinetis-twr-k60n512-config">TWR-K60N512 Configuration</link> and here are the TWR-K70F120M
+      settings.
+      </para>
+      <table frame="all"><title>TWR-K70F120M Jumper setting</title>
+        <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="jumper" colwidth="1*" >
+          <colspec colnum="2" colname="jumpset" colwidth="1*" >
+          <colspec colnum="3" colname="desc" colwidth="3*" >
+          <thead>
+            <row>
+              <entry>Jumper</entry>
+              <entry>Setting</entry>
+              <entry>Description</entry>
+            </row>
+          </thead>
+          <tbody>
+            <row>
+              <entry>J19</entry>
+              <entry>OFF</entry>
+              <entry>On board 50MHz oscillator is not powered</entry>
+            </row>
+          </tbody>
+        </tgroup>
+      </table>
+      </refsect3>
+    </refsect2>
+    <refsect2 id="kinetis-twr-k70f120m-config-ecos"><title>eCos Configuration</title>
+      <refsect3 id="twr-k70f120m-clocking"><title>Clocking</title>
+      <para>
+      The TWR-K70F120M package defines requirements for the platform clocking.
+      </para>
+      </refsect3>  
+      <refsect3 id="twr-k70f120m-memory"><title>Memory</title>
+      <para>
+      The K70 has two 64 KiB SRAM banks giving a total of 128KiB on chip SRAM. In addition, on-board there is
+      128 MiB of external RAM (SDRAM) and 256 MiB of NAND Flash.
+      External RAM is divided in two regions: 
+      </para>
+      <variablelist>
+        <varlistentry>
+          <term>ram</term>
+          <listitem><para> Regular RAM.</para></listitem>
+        </varlistentry>
+        <varlistentry>
+          <term>ramnc</term>
+          <listitem><para>Non cached RAM. This region contains <literal>.noncache</literal> section.</para></listitem>
+        </varlistentry>
+      </variablelist>
+      </refsect3>
+    </refsect2>
+    <refsect2 id="kinetis-twr-k70f120m-memory"><title>Memory layouts</title>
+      <para>
+      Additional platform memory layouts follow the <link linkend="kinetis-var-memory">variant</link>
+      ones only by putting all RAM sections except <literal>.sram</literal> in the <literal>ram</literal> region.
+      The linker file names incorporate the segment <filename>_extram_</filename>.
+      </para>
+      <refsect3 id="kinetis-twr-k70f120m-memory-ldscript-location"><title>Linker 
+      Script Location</title>
+      <para>
+      Linker scripts are found at:
+      <filename class="directory">hal/kinetis/twr-k70f120m/&lt;version&gt;/include/pkgconf</filename>
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-twr-k70f120m-memory-ldscript-naming"><title>Linker Script Naming</title>
+      <para>
+      Linker script file names have following form:
+      <filename>mlt_kinetis_&lt;NVM&gt;_&lt;SRAM&gt;_&lt;STARTUP_extram.ldi</filename>
+      where <filename>PLF</filename> is an optional extension for platform specific scripts and
+      other segments have meaning as described <link linkend="kinetis-var-table-ldscript-naming">here</link>.
+      </para>
+      </refsect3>
+    </refsect2>
+    <refsect2 id="kinetis-twr-k70f120m-startup"><title>Startup types</title>
+      <para>
+      The platform startup <literal>CYG_HAL_STARTUP_PLF</literal> offers the following startups:
+      </para>
+      <variablelist>
+        <varlistentry>
+          <term><literal>ROM (Platform)</literal></term>
+          <listitem><para>Normal startup for stand-alone operation. The eCos image has to be flashed
+            in internal flash. External RAM is used as main memory.
+            </para>
+            <para>
+            Note: This startup has a name like the one in the variant but generates different images 
+            by invoking a different set of linker scripts.
+            </para></listitem></varlistentry>
+        <varlistentry>
+          <term><literal>RAM (Platform)</literal></term>
+          <listitem><para>The image is loaded in external RAM by means of RedBoot.
+            </para></listitem></varlistentry>
+        <varlistentry>
+          <term><literal>ByVariant</literal></term>
+          <listitem><para>Activates the <link linkend="kinetis-var-startup">variant startup types</link>.
+            </para></listitem></varlistentry>
+      </variablelist>
+    </refsect2>
+  </refsect1>
+</refentry>
+
+<!--</part>-->
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
new file mode 100644
index 0000000..80ff30e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h
@@ -0,0 +1,32 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
new file mode 100644
index 0000000..feb1b8f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi
@@ -0,0 +1,41 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE
+    sram   : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA)
+    SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
+
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
new file mode 100644
index 0000000..bdfde58
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h
@@ -0,0 +1,40 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE)
+//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE)
+//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
new file mode 100644
index 0000000..4a09a9b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi
@@ -0,0 +1,49 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    sram   : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000, FOLLOWING (.got))
+    SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
new file mode 100644
index 0000000..69ba037
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h
@@ -0,0 +1,28 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
new file mode 100644
index 0000000..3cd913d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi
@@ -0,0 +1,39 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+
+MEMORY
+{
+    sram   : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA)
+    SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA)
+    SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
new file mode 100644
index 0000000..e0339ca
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h
@@ -0,0 +1,32 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE)
+#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE)
+#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE)
+#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE)
+#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
new file mode 100644
index 0000000..694fb95
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi
@@ -0,0 +1,47 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram   : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash  : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+    ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE
+    ram    : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE
+    ramnc  : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA)
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h
new file mode 100644
index 0000000..3e631ed
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Contributor(s):
+// Date:        2012-02-15
+// Purpose:     TWR-K70F120M platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h
new file mode 100644
index 0000000..0d92bd6
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2012-02-25
+// Purpose:     TWR-K70F120M platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h
new file mode 100644
index 0000000..1329b3c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h
@@ -0,0 +1,171 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2012-02-25
+// Purpose:     TWR-K70F120M platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>
+
+
+// UART PINs
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+#endif
+
+#ifndef CYGHWR_HAL_FREESCALE_UART2_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 17, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 16, 3, 0)
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_FREESCALE_UART2_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_FREESCALE_UART2_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_FREESCALE_UART2_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_FREESCALE_UART2_PIN_CTS
+#endif
+
+// ENET PINs
+
+// MDIO
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO    CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC     CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0)
+// Both RMII and MII interface
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER    CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \
+                                                    CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1    CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0    CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN    CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0    CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1    CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0)
+// RMII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV  CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0)
+// MII interface only
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3     CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2     CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK    CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2     CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK    CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3     CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS      CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER     CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0)
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL      CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0)
+// IEEE 1588 timers
+#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN    CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0)
+
+#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0)
+#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0  CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1  CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2  CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0)
+# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3  CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0)
+#endif
+
+// DSPI
+// DSPI Pins
+
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \
+                                  CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+#define KINETIS_PIN_SPI1_SCK_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M)
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \
+                                  CYGHWR_HAL_KINETIS_PORT_PCR_PE_M)
+
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#define KINETIS_PIN_SPI1_0_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN  CYGHWR_HAL_KINETIS_PIN(E, 1, 7, KINETIS_PIN_SPI1_IN_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 3, 7, KINETIS_PIN_SPI1_OUT_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK  CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_SCK_OPT)
+
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0  CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1  CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2  CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3  CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT)
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4  CYGHWR_HAL_KINETIS_PIN_NONE
+#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5  CYGHWR_HAL_KINETIS_PIN_NONE
+
+// I2C
+// I2C Pins
+
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 18, 4, 0)
+# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 19, 4, 0)
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
+
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm
new file mode 100644
index 0000000..d1e3c8f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm
@@ -0,0 +1,83 @@
+# Redboot minimal configuration
+# Target: TWR-K70F120M
+# Startup: ROM with external RAM
+
+
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "RedBoot Kinetis TWR-K70F120M" ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU {
+    user_value 1
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH {
+    user_value ALL
+};
+
+cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 0
+};
+
+#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH {
+#    user_value 1
+#};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    user_value -1
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK {
+    user_value -2
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT {
+    user_value 16
+};
+
+#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE {
+#    user_value 0x20000
+#};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    user_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    user_value ROM
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    user_value 1
+};
+
+cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA {
+    user_value 1
+};
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c
new file mode 100644
index 0000000..08500ef
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c
@@ -0,0 +1,316 @@
+//==========================================================================
+//
+//      twr_k70f120m_misc.c
+//
+//      Cortex-M4 TWR-K60N512 EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2012-02-25
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+static inline void hal_misc_init(void);
+
+// DATA and BSS locations
+__externC cyg_uint32 __ram_data_start;
+__externC cyg_uint32 __ram_data_end;
+__externC cyg_uint32 __rom_data_start;
+__externC cyg_uint32 __sram_data_start;
+__externC cyg_uint32 __sram_data_end;
+__externC cyg_uint32 __srom_data_start;
+__externC cyg_uint32 __bss_start;
+__externC cyg_uint32 __bss_end;
+
+#ifdef CYGHWR_HAL_DDR_SYNC_MODE
+#define SYNC_ASYNC 0x3
+#else
+#define SYNC_ASYNC 0
+#endif
+
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+
+// DDRAM controller setup parameters
+const cyg_uint32 kinetis_ddr_cfg[] = {
+    0x00000400,  // DDR_CR00
+    0x02000031,  // DDR_CR02
+    0x02020506,  // DDR_CR03
+    0x06090202,  // DDR_CR04
+    0x02020302,  // DDR_CR05
+    0x02904002,  // DDR_CR06
+    0x01000303,  // DDR_CR07
+    0x05030201,  // DDR_CR08
+    0x020000c8,  // DDR_CR09
+    0x03003207,  // DDR_CR10
+    0x01000000,  // DDR_CR11
+    0x04920031,  // DDR_CR12
+    0x00000005,  // DDR_CR13
+    0x00C80002,  // DDR_CR14
+    0x00000032,  // DDR_CR15
+    0x00000001,  // DDR_CR16
+    0x00030300,  // DDR_CR20
+    0x00040232,  // DDR_CR21
+    0x00000000,  // DDR_CR22
+    0x00040302,  // DDR_CR23
+    0x0A010201,  // DDR_CR25
+    0x0101FFFF,  // DDR_CR26
+    0x01010101,  // DDR_CR27
+    0x00000003,  // DDR_CR28
+    0x00000000,  // DDR_CR29
+    0x00000001,  // DDR_CR30
+    0x02020101,  // DDR_CR34
+    0x01010201,  // DDR_CR36
+    0x00000200,  // DDR_CR37
+    0x00200000,  // DDR_CR38
+    0x01010020,  // DDR_CR39
+    0x00002000 | SYNC_ASYNC,  // DDR_CR40
+    0x01010020,  // DDR_CR41
+    0x00002000 | SYNC_ASYNC,  // DDR_CR42
+    0x01010020,  // DDR_CR43
+    0x00000000 | SYNC_ASYNC,  // DDR_CR44
+    0x03030303,  // DDR_CR45
+    0x02006401,  // DDR_CR46
+    0x01020202,  // DDR_CR47
+    0x01010064,  // DDR_CR48
+    0x00020101,  // DDR_CR49
+    0x00000064,  // DDR_CR50
+    0x02000602,  // DDR_CR52
+    0x03c80000,  // DDR_CR53
+    0x03c803c8,  // DDR_CR54
+    0x03c803c8,  // DDR_CR55
+    0x020303c8,  // DDR_CR56
+    0x01010002   // DDR_CR57
+};
+#endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_system_init( void )
+{
+#if !defined(CYG_HAL_STARTUP_RAM)
+    cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P;
+
+    hal_wdog_disable();
+    hal_misc_init();
+
+    // if ACKISO is set you must clear ackiso before calling pll_init
+    //    or pll init hangs waiting for OSC to initialize
+    if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M)
+        pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M;
+
+    hal_start_clocks();
+# ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+    HAL_CORTEXM_KINETIS_DDRMC_INIT( kinetis_ddr_cfg );
+# endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+#endif
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M           \
+            (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M |   \
+             CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M)
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_misc_init(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
+
+    // Enable some peripherals' clocks.
+    sim_p->scgc1 |= CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M;
+    sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M;
+    sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M;
+
+    // Disable MPU
+    mpu_p->cesr = 0;
+}
+
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1        }, // System bus RAM partition
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1      }, // On-chip SRAM
+#elif defined CYGMEM_REGION_sram_l
+    { CYGMEM_REGION_sram_l,     CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1  }, // On-chip SRAM lower bank
+#endif
+#ifdef CYGMEM_REGION_ramcod
+    { CYGMEM_REGION_ramcod,      CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition
+#endif
+#ifdef CYGMEM_REGION_ramnc
+    { CYGMEM_REGION_ramnc,      CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1    }, // Non cachable RAM partition
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1    }, // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1        }, // External flash [currently none]
+#endif
+    { 0xE0000000,               0x00000000-1                                      }, // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                      }  // Chip specific peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
+        if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) &&
+            ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_sram_l
+# define CASE_CODE 3
+# define CASE_RAMNC 4
+    case 2:
+        *start = (unsigned char *)CYGMEM_REGION_sram_l;
+        *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE);
+        break;
+#else
+# define CASE_CODE 2
+# define CASE_RAMNC 3
+#endif
+
+#ifdef CYGMEM_REGION_ramcod
+    case CASE_CODE:
+        *start = (unsigned char *)CYGMEM_REGION_ramcod;
+        *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE);
+        break;
+#endif
+
+#ifdef CYGMEM_REGION_ramnc
+    case CASE_RAMNC:
+        *start = (unsigned char *)CYGMEM_REGION_ramnc;
+        *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+//==========================================================================
+// EOF twr_k70f120m_misc.c
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/var/current/ChangeLog
new file mode 100644
index 0000000..1130967
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/ChangeLog
@@ -0,0 +1,207 @@
+2014-02-13  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cortexm/kinetis/var/current/include/var_intr.h:
+	Add interrupt numbers for second eDMA controller.
+
+	* cortexm/kinetis/var/current/include/var_io_clkgat.h:
+	Add clock gating for ADC2
+
+	* cortexm/kinetis/var/current/include/var_io_gpio.h:
+	Add GPIO port F.
+
+2013-04-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_intr.h : Redefine CYGNUM_HAL_INTERRUPT_RTC_RTC because of
+	conflict with same named macro defined in hal_intr.h (Cortex-M architecture).
+	Define some interrrupt numbers, previously reservrd.
+	* include/var_io.h : Upgrade RTC registers. [ Bugzilla 1001904 ]
+
+2013-06-12 Mike Jones <mike@proclivis.com>
+
+	* include/var_io_gpio.h
+	Clean up macros to support interrupts and set/get features.
+	
+2013-04-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl: 
+	* cdl/kinetis_ddram.cdl: (New file)
+	* cdl/kinetis_fbram.cdl: (New file)
+	Add FlexBus RAM configuration and caching, DDRAM CDL moved
+	to a separate file. Updated FlexNVM configuration with 512KiB FlexNVM
+	and 16KiB FlexMemory.
+	* cdl/kinetis_clocking.cdl: CYGINT_HAL_CORTEXM_KINETIS_150
+	moved to hal_cortexm_kinetis.cdl
+	* include/var_io_lmem.h, include/hal_cache.h: Add more cache functions.
+	[ Bugzilla 1001837 ]
+	
+2013-04-09  Tomas Frydrych <tomas@sleepfive.com>
+
+	* cdl/kinetis_irq_scheme.cdl:
+	* include/var_io_devs.h:
+	Implemented support for I2C  [Bugzilla 1001397]
+
+2013-04-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_io.h, include/var_io_clkgat.h, include/var_io_devs.h,
+	* src/hal_diag.c, src/kinetis_ddram.c, src/kinetis_misc.c
+	Add clock gating management and API. [ Bugzilla 1001814 ]
+
+2012-11-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl: Changes to Kinetis part builder related to
+	addition of archhitectural hardware floating point support.
+	CYGHWR_HAL_CORTEXM_KINETIS_FPU and CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM
+	look and feel like other name building options. Added new Kinetis
+	members to part selection.
+	* include/var_io.h, src/kinetis_misc.c: Enumerated PORT F.
+	[Bugzilla 1001607]
+
+2012-11-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_io.h: Define register access to FTFL module. 
+	Contributed by Nicolas Aujoux at 2012-09-07 [Bugzilla 1001561]
+
+2012-09-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* var/current/cdl/hal_cortexm_kinetis.cdl
+	* var/current/cdl/kinetis_clocking.cdl
+	* var/current/doc/kinetis.sgml
+	* var/current/include/hal_cache.h
+	* var/current/include/var_io_ddrmc.h
+	* var/current/include/var_io_lmem.h
+	* var/current/src/kinetis_ddram.c
+	* var/current/src/kinetis_misc.c:
+	Separate data and code caches, as well as text indentation suggested by Jifl.
+	Fixes to cache and SDRAM CDL and functions Improved SDRAM controller
+	support due to better manufacturer documentation: Configurable pad control.
+	                                           [Bugzilla 1001606]
+
+2012-08-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/var_io.h, src/kinetis_misc.c: Add functions and macros
+	for clock gating control to Kinetis.       [Bugzilla 1001642]
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* include/hal_cache.h, src/kinetis_misc.c: Provide for cache
+	enablement in RAM startup mode            [Bugzilla 1001606]
+
+2012-05-19  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/kinetis.sgml: Close <para> and <refsect2> blocks.
+	* cdl/hal_cortexm_kinetis.cdl: Reference per-package documentation.
+
+2012-05-18  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* doc/kinetis_begin.sgml:
+	* doc/kinetis_end.sgml:
+	* doc/kinetis.sgml:
+	New files -- Kinetis variant documentation. [Bug 1001580]
+
+2012-05-17  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	Bug fix: Do not refer external memory if Platform startup is
+	not selected.  [ Bugzilla 1001590 ]
+
+2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	* src/kinetis_clocking.cdl:
+	* src/kinetis_clocking.c:
+	* include/hal_cache.h
+	* include/var_io_lmem.h:
+	* include/var_io_ddrmc.h:
+	* include/var_io_devs.h:
+	* include/var_io.h:
+	* src/kinetis_ddram.c:
+	* src/kinetis_misc.c:
+	Add: Clocking support for PLL1 (K70), DDRAM controller
+	Cache, eDMA - 32 chan. [Bugzilla 1001579]
+
+2012-01-11  Tomas Frydrych <tomas@sleepfive.com>
+
+	* include/var_io.h:
+	Allow for overriding of CYGHWR_HAL_KINETIS_SIM_SCGC?_ALL_M mask
+	from platform definitions.
+
+	* include/var_io_devs.h:
+	Define base pointer for SLCD controller
+
+2012-01-05  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/kinetis_irq_scheme.cdl
+	Centralized IRQ priority scheme.
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	* cdl/kinetis_flexbus.cdl
+	* include/var_io_devs.h:
+	* include/var_io.h:
+	* src/kinetis_clocking.c:
+	* src/kinetis_misc.c:
+	Add I/O defs for eDMA, DSPI. Add flexbus control.
+	CYG_HAL_STARTUP parenthed bt CYG_HAL_STARTUP_ENV.
+	Early clock start [Bugzilla 1001450]
+
+2011-11-15  Tomas Frydrych <tomas@sleepfive.com>
+
+	* include/var_io_gpio.h:
+	Convenience macros for manipulating GPIO pins.
+
+2011-10-19  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_kinetis.cdl:
+	* cdl/kinetis_clocking.cdl:
+	* src/hal_diag.c:
+	* src/kinetis_misc.c:
+	* src/kinetis_clocking.c:
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/variant.inc:
+	* include/var_arch.h:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* include/var_io_devs.h:
+	* include/var_io_flexbus.h:
+	* include/pkgconf/mlt_kinetis_flash_sram2s_rom.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi
+	* include/pkgconf/mlt_kinetis_flash_sram2s_sram.h
+	* include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_rom.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi
+	* include/pkgconf/mlt_kinetis_flash_unisram_sram.h
+	* include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi
+	* include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h
+	* include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi
+	* include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h
+	* include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi
+	* include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h
+	* include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi
+	* include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h
+	* include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi
+	New package -- Freescale Kinetis variant HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011, 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
new file mode 100644
index 0000000..e8ee8f8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
@@ -0,0 +1,867 @@
+##==========================================================================
+##
+##      hal_cortexm_kinetis.cdl
+##
+##      Cortex-M Freescale Kinetis variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
+    display       "Freescale Kinetis Cortex-M4 Variant"
+    parent        CYGPKG_HAL_CORTEXM
+    doc           ref/hal-cortexm-kinetis-var.html
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_kinetis.h
+    description   "
+        This package provides generic support for the Freescale Cortex-M4
+        based Kinetis microcontroller family.
+        It is also necessary to select a variant and platform HAL package."
+
+    compile       hal_diag.c kinetis_misc.c kinetis_clocking.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M4" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_kinetis.h>"
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS {
+        display          "Kinetis part"
+        flavor           data
+        calculated { "MK" . CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM .
+            CYGHWR_HAL_CORTEXM_KINETIS_FPU . CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM .
+            CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME }
+        description   "
+            Kinetis family has several sub-families, with various peripheral
+            sets and CPU options. Each sub-family consists of several
+            members differing by sizes of on-chip FLASH and SRAM. This
+            control, enables the user to build Kinetis member part and so
+            tailor HAL for a specific microcontroller by selection of
+            microcontroller's properties such as microcontroller sub-family,
+            memory options, etc."
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM {
+            display        "Sub-family"
+            flavor         data
+            no_define
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT }
+            legal_values   { 10 11 12 20 21 22 30 40 50 51 60 61 70 }
+            description    "
+                Kinetis family consists of several sub-families differing by
+                features and CPU power."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT {
+                display        "Default sub-family"
+                flavor         data
+                no_define
+                default_value  { 60 }
+                legal_values   { 10 11 12 20 21 22 30 40 50 51 60 61 70 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FPU {
+            display       "Floating Point Unit part name option"
+            flavor        data
+            no_define
+            legal_values  { "D" "F" }
+            default_value { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT }
+            description   "
+                Select whether the part has Floating Point Unit. \"F\" - stands for
+                parts with FPU, while \"D\" for ones without. Note:
+                Selection of part with FPU does not imply that the FPU is used -
+                CYGHWR_HAL_CORTEXM_FPU activates the FPU."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT {
+                display       "Default FPU part name option"
+                flavor        data
+                no_define
+                legal_values  { "D" "F" }
+                default_value { "D" }
+            }
+
+            cdl_option CYGIMP_HAL_CORTEXM_KINETIS_FPU {
+                display    "FPU implemented"
+                no_define
+                calculated { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "F" }
+                active_if  { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "F" }
+                implements CYGINT_HAL_FPV4_SP_D16
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM {
+            display        "FlexNVM name option"
+            flavor         data
+            no_define
+            legal_values   { "N" "X" }
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT }
+            description    "Select whether the part has FlexNVM."
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT {
+                display        "Default FlexNVM name option"
+                flavor         data
+                no_define
+                legal_values   { "N" "X" }
+                default_value  { "N" }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME {
+            display        "Flash name segment"
+            flavor           data
+            no_define
+            legal_values   { 32 64 96 128 256 512 "1M0" }
+            default_value  { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT }
+            description    "
+                Flash size is represented in part name encoded as KiB
+                (e.g. 512) or MiB (e.g. 1M0)."
+
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT {
+                display        "Default Flash name segment"
+                flavor           data
+                no_define
+                legal_values   { 32 64 96 128 256 512 "1M0" }
+                default_value  { 512 }
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_REV {
+            display       "Kinetis revision"
+            flavor        data
+            legal_values  { 1 2 }
+            default_value 1
+            description " Revision"
+        }
+
+        cdl_interface CYGINT_HAL_CORTEXM_KINETIS_150 {
+            display       "Is a 150MHz device"
+            description   "
+                150Mhz and 120MHz devices have some properties different than 100MHz
+                devices of same types. This interface shall be implemented if the
+                device is 150Mhz or 120MHz."
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU exception priority level bits"
+        flavor        data
+        default_value 4
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M
+            CPU implements."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING {
+        display     "Clocking"
+        flavor      data
+        no_define
+        calculated  CYGHWR_HAL_CORTEXM_KINETIS_MCG
+        description "Configure system clock and subsystem clocking."
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP {
+            display      "System frequency clock setpoint"
+            flavor        data
+            legal_values  32768 to 220000000
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP ?
+                CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP : 96000000 }
+            description "Desired system clock frequency"
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP {
+            display       "Auxiliary clock frequency setpoint"
+            flavor        data
+            active_if     CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+            legal_values  32768 to 220000000
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP ?
+                            CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP : 96000000 }
+            description    "Desired auxiliary clock frequency"
+        }
+
+        script kinetis_clocking.cdl
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP
+        description   "Set clock ISR priority. Default setting is lowest priority."
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "
+                The period defined here is something of a fake, it is
+                expressed in terms of a notional 1MHz clock. The value
+                actually installed in the hardware is calculated from
+                the current settings of the clock generation hardware."
+        }
+    }
+
+    cdl_option CYG_HAL_STARTUP_VAR {
+        display      "By variant"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { (CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ?
+                        "ByPlatform" : "ROM" }
+        legal_values  { "ROM" "SRAM" }
+        active_if     ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant"))
+        description   "
+            'ROM' startup builds a stand-alone application which will
+            be placed into flash. SRAM startup builds application
+            intended for loading in on-chip SRAM by means of JTAG/SWD.
+            Note: Variant Startup Type can be overriden/overloaded by
+            Platform Startup Type."
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type calculator"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        calculated    { (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ?
+                        CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR}
+        no_define
+        define        -file system.h CYG_HAL_STARTUP
+        description   "
+            Startup type defines what type of application shall be built.
+            Startup type  can be defined by variant (CYG_HAL_STARTUP_VAR)
+            or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_CONF {
+        display "FlexNVM configuration"
+        flavor none
+        no_define
+        active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" }
+        requires {
+            CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <=
+            CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE {
+            display "Enhanced EEPROM (EEE)"
+            flavor  bool;
+
+            cdl_option CYGHWR_HAL_KINETIS_EEE_SIZE {
+                display      "EEE Size \[Bytes\]"
+                flavor        data
+                legal_values  { 0 32 64 128 256 512 1024 2048 4096
+                    CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 16384 ? 8196 : 0
+                    CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 16384 ? 16384 : 0
+                }
+                default_value CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+            }
+
+            cdl_component CYGHWR_HAL_KINETIS_EEE_SPLIT {
+                display       "EEE Split ratio"
+                flavor data
+                legal_values  { 0 2 4 8 }
+                default_value 0
+                description "
+                    Enhanced EEPROM is split in two partitions that are
+                    represented by separate sections in MLT files.
+                    The split, CYGHWR_HAL_KINETIS_EEE_SPLIT, represents
+                    partition size ratio where EEE0 partition size is
+                    1/CYGHWR_HAL_KINETIS_EEE_SPLIT of EEE size, and EEE1
+                    is the rest. As a special arrangement
+                    (CYGHWR_HAL_KINETIS_EEE_SPLIT == 0) is a PHONY, where
+                    split equals 2 but in MLT files whole EEE is counted
+                    as a single section."
+
+                cdl_option CYGHWR_HAL_KINETIS_EEE0_SIZE {
+                    display "e_eeprom0 section size \[Bytes\]"
+                    flavor data
+                    calculated { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 ?
+                        CYGHWR_HAL_KINETIS_EEE_SIZE /
+                        CYGHWR_HAL_KINETIS_EEE_SPLIT :
+                        CYGHWR_HAL_KINETIS_EEE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_EEE1_SIZE {
+                    display "e_eeprom1 section size \[Bytes\]"
+                    flavor data
+                    active_if { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 }
+                    calculated { CYGHWR_HAL_KINETIS_EEE_SIZE -
+                        CYGHWR_HAL_KINETIS_EEE0_SIZE }
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB {
+                display "FlexNVM partition used for EEE \[KiB\]"
+                flavor     data
+                calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 512 ?
+                             CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_512_PART_KIB :
+                             CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_256_PART_KIB
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_256_PART_KIB {
+                    display "FlexNVM partition used for EEE \[KiB\]"
+                    flavor data
+                    active_if      CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 256
+                    default_value  32
+                    legal_values { 32 64 128 192 224 256 }
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_512_PART_KIB {
+                    display "FlexNVM partition used for EEE \[KiB\]"
+                    flavor data
+                    active_if      CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB == 512
+                    default_value  64
+                    legal_values { 64 128 256 384 448 512 }
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE {
+            display "FlexNVM D Flash"
+            flavor data
+            active_if { CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <
+                CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB}
+            calculated {
+                1024 * ( CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB -
+                         CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_RAM {
+            display "Flexram ordinary RAM"
+            flavor data
+            active_if { !CYGHWR_HAL_CORTEXM_KINETIS_EEE }
+            calculated CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_SIZE {
+            display "Flexram size"
+            flavor data
+            legal_values  { 4096 16384 }
+            default_value CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 70 ? 16384 : 4096
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB {
+            display "FlexNVM size \[KiB\]"
+            flavor data
+            calculated CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
+        }
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        parent CYG_HAL_STARTUP_ENV
+        calculated {
+            (CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF :
+            (CYG_HAL_STARTUP == "ROM" ) ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_rom" :
+            (CYG_HAL_STARTUP == "SRAM") ? "kinetis_"
+            . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT  . "_sram" :
+            "undefined" }
+        description "
+            Combination of 'Startup type' and 'Kinetis part'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED {
+        display  "Unified on chip SRAM region"
+        flavor    bool
+        default_value    { 1 }
+        description "
+            Kinetis have two equal SRAM banks SRAM_L and SRAM_U that
+            occupy consecutive memory blocks with \(possibility for
+            simultaneous\) access from on separate buses.
+            SRAM_L is placed below 0x20000000 and SRAM_U above 0x20000000.
+            This option provides for selection between memory layout with
+            single (unified) (S)RAM region and layout with two separate
+            (S)RAM regions."
+    }
+
+    cdl_option CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION {
+        display "Utilize \".kinetis_misc\" section for HAL"
+        flavor bool
+        default_value { CYG_HAL_STARTUP == "ROM" }
+        active_if { CYG_HAL_STARTUP == "ROM" }
+        description "
+            Kinetis use FLASH locations between 0x400 and 0x40F for FLASH
+            security configuration. This leaves FLASH area below 0x400
+            out of standard linker sections. Special section
+            \".kinetis_misc\" provides linker access to this area.
+            Setting this option instructs linker to place some HAL
+            (variant/platform) \"misc.\" functions in this area."
+    }
+
+    cdl_option CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION {
+        display "HAL diag. in \".kinetis_misc\" section"
+        flavor bool
+        active_if CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION
+        default_value 0
+        description "
+        By default only misc. HAL functions are stored in
+        \".kinetis_misc\" section. In addition HAL diagnostc
+        functions may be placed as well."
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_MEMORY_RESOURCES {
+        display "On chip memory resources"
+        flavor none
+        no_define
+        description "
+        View and manage on-chip memory resources.
+        Output is used for naming of 'mlt' files."
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB {
+            display "On chip Flash option \[KiB\]"
+            flavor data
+            calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == "1M0")
+                ? 1024 : CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB {
+            display "Kinetis on chip SRAM size \[KiB\]"
+            flavor data
+            calculated {
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 1024 ||
+                 CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 512)   ? 128 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 256)   ? 64 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 128)   ? 32 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 96 ||
+                 CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 64)    ? 16 :
+                (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 32)    ? 8 :
+                "Unknown"
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT {
+            display "SRAM layout"
+            flavor data
+            no_define
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ?
+                "unisram" :
+                "sram2s"
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT {
+            display "On-chip memory layout"
+            flavor data
+            no_define
+            calculated {(CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" ? "flexnvm_": "flash_")
+                . CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_SIZE {
+            display "Kinetis on chip FLASH size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB * 0x400 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SRAM_SIZE {
+            display "Kinetis on chip SRAM size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB * 0x400 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE {
+            display "Kinetis onchip RAM bank size"
+            flavor  data
+            calculated { CYGHWR_HAL_KINETIS_SRAM_SIZE/2 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLASH_SIZE {
+            display "Kinetis on chip FlexNVM FLASH size"
+            flavor data
+            active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" }
+            calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB
+                          - CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)* 0x400 }
+            }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLEXRAM_SIZE {
+            display   "Kinetis on chip FlexRAM size"
+            flavor    data
+            active_if { (CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X") &&
+                !CYGHWR_HAL_CORTEXM_KINETIS_EEE }
+            calculated { CYGHWR_HAL_KINETIS_FLEXRAM_SIZE }
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CACHE {
+        display "Platform has cache"
+        flavor bool
+    }
+
+    cdl_interface CYGINT_HAL_HAS_NONCACHED {
+        display "Platform has non-cached regions"
+        flavor bool
+    }
+
+    cdl_component CYGPKG_HAL_KINETIS_CACHE {
+        display "Cache memory"
+        flavor bool
+
+        default_value CYGINT_HAL_CACHE
+        active_if (CYGINT_HAL_CACHE)
+    }
+
+    cdl_component CYGHWR_HAL_NONCACHED {
+        display "Non cached RAM memory regions"
+        flavor        booldata
+        active_if     CYGINT_HAL_HAS_NONCACHED
+        legal_values  { "\".sram\"" "\".noncache\"" }
+        default_value { "\".noncache\"" }
+        description   "
+            Non cached memory sections may be usful for storage that
+            is unsuitable for caching, such as sharing buffers between
+            the CPU and other bus masters such as DMA, ENET, etc.
+            The  \".sram\" section is located in the internal SRAM,
+            which is is always present and never cached.
+            Additionaly, as an option, a partition of external memory:
+            DDRAM or FlexRAM, if one is present, can be configured
+            non-cached and accommodate \".noncache\" section."
+
+        cdl_option CYGHWR_HAL_ENET_TCD_SECTION {
+            display       "Ethernet buffer descriptor memory section"
+            flavor data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".sram\"" }
+
+            description "Ethernet is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_ENET_BUF_SECTION {
+            display       "Ethernet buffer memory section"
+            flavor        data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".noncache\"" }
+
+            description "Ethernet is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_EDMA_TCD_SECTION {
+            display       "eDMA transfer control descriptor memory section"
+            flavor        data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".sram\"" }
+
+            description   "eDMA is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+
+        cdl_option CYGHWR_HAL_EDMA_BUF_SECTION {
+            display       "eDMA buffer memory section"
+            flavor data
+            legal_values  { "\".sram\"" "\".noncache\"" }
+            default_value { "\".noncache\"" }
+
+            description   "eDMA is a bus master so buffers/buffer
+                descriptos must reside in non-cached memory"
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_DDRAM {
+        display "Platform uses DDRAM"
+        flavor bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DDRAM and if DDRAM is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC {
+        display       "DDRAM"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+        default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+        description   "DDRAM on Kinetis is mirrored at several address ranges.
+                Each mirror has its own caching options that may include:
+                non-cached, write-through and write-back.
+                By eCos configuration, DDRAM is split in 3 partitions:
+                Cached, Non-cached and Code.
+                Cached partition is intended for general purpose main memory.
+                Non-cached partition is convenient for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc. Code partition is for executable code."
+
+        requires       CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+        compile        kinetis_ddram.c
+
+        script kinetis_ddram.cdl
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FBRAM {
+        display "Platform uses FlexBus RAM"
+        flavor bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides FlexBus and if FlexBus is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FBRAM {
+        display       "FlexBus RAM"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+        default_value CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+        requires      CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+        description   "FBRAM on Kinetis is mirrored at several address ranges.
+                Each mirror has its own caching options that may include:
+                non-cached, write-through and write-back.
+                By eCos configuration, FlexBus RAM is split in 3 partitions:
+                Cached, Non-cached and Code.
+                Cached partition is intended for general purpose main memory.
+                Non-cached partition is convenient for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc. Code partition is for executable code."
+
+        script kinetis_fbram.cdl
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS {
+        display     "Platform uses FlexBus"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides FlexBus and if FlexBus is
+            used on target hardware"
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS {
+        display       "FlexBus"
+        flavor bool
+        active_if     CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
+        default_value CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
+        description   "FlexBus provides access for external memory."
+
+        script        kinetis_flexbus.cdl
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF {
+        display "Flash configuration field"
+        flavor   none
+        no_define
+
+        active_if { CYG_HAL_STARTUP == "ROM" }
+
+        description "
+            The program flash memory contains a 16-byte flash
+            configuration field that stores default protection settings
+            (loaded on reset) and security information that allows the MCU to
+            restrict access to the flash module.
+            Note: Changing some values in Flash configuration field may make
+            flash inaccessible and disable further re-programming of the flash
+            permanently. Consult respective Kinetis' documentation before dealing
+            with the Flash configuration field. Default values are equal
+            to the factory values."
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY {
+            display "Backdoor comparison key"
+            flavor data
+            default_value { "\{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff \}" }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT {
+            display "Program flash protection"
+            flavor data
+            default_value { "\{ 0xff, 0xff, 0xff, 0xff \}" }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC {
+            display "Flash security byte"
+            flavor data
+            default_value 0xfe
+
+            description "
+                Note: FSEC default value is deliberately set to
+                0xfe in order to disable chip lockout."
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT {
+            display "Flash nonvolatile option byte"
+            flavor data
+            default_value 0xff
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT {
+            display "Data flash protection byte"
+            flavor data
+            default_value 0xff
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT {
+            display "EEPROM protection byte"
+            flavor data
+            default_value 0xff
+        }
+    }
+
+    cdl_option CYGNUM_HAL_KINETIS_MEM_SEGMENTS {
+        display    "RAM memory segments"
+        flavor     data
+        no_define
+        active_if  is_active(CYGBLD_REDBOOT_MAX_MEM_SEGMENTS)
+        requires   { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS >= CYGNUM_HAL_KINETIS_MEM_SEGMENTS }
+
+        calculated {
+            ((CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ? 1 : 2) +
+            (CYGPKG_HAL_CORTEXM_KINETIS_DDRMC        ? 2 : 0) +
+            (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE  ? 1 : 0) +
+            (CYGPKG_HAL_CORTEXM_KINETIS_FBRAM        ? 2 : 0) +
+            (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE  ? 1 : 0))
+        }
+    }
+
+    for { set ::channel 0 } { $::channel < 6 } { incr ::channel } {
+
+        cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] {
+            display     "Platform provides UART [set ::channel] HAL"
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                controller being used has on-chip UART [set ::channel],
+                and if that UART is accessible on the target hardware."
+        }
+
+        cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel]_RTSCTS {
+            display     "Platform provides HAL for UART[set ::channel] hardware flow control."
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                on-chip UART [set ::channel] has RTS/CTS flow control
+                that is accessible on the target hardware."
+        }
+    }
+
+    cdl_interface CYGINT_HAL_DMA {
+        display     "Platform uses DMA"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DMA and if DMA is
+            used on target hardware"
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+        display     "Variant IRQ priority defaults"
+        no_define
+        flavor      none
+        parent      CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+        description "
+            Interrupt priorities defined by Kinetis variant"
+        script kinetis_irq_scheme.cdl
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_OPTIONS {
+        display      "Build options"
+        flavor       none
+        no_define
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Kinetis variant HAL package. These flags
+                are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Kinetis variant HAL package. These flags
+                are removed from the set of global flags if present."
+        }
+    }
+}
+
+# EOF hal_cortexm_kinetis.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl
new file mode 100644
index 0000000..0d785d1
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl
@@ -0,0 +1,978 @@
+##==========================================================================
+##
+##      kinetis_clocking.cdl
+##
+##      Cortex-M Freescale Kinetis Clocking
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-10-19
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING
+#    display       "Clocking"
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ {
+        display "System frequency actual value"
+        flavor data
+        calculated {
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC   ?
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC   :
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC   ?
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC   :
+            (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL ||
+             CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1)   ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV:
+            CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL      ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV :
+            0
+        }
+        description "Operating system clock frequency."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG {
+        display "MCG"
+        flavor data
+        no_define
+        calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK . " " .
+            ((CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ+500000)/1000000) . "MHz, " . (
+                  (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK") ?
+                  CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS :
+                  CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC)
+
+        }
+        description "Multipurpose Clock Generator"
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK {
+            display "System clock source"
+            flavor data
+            default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1 ? "PLL1" : "PLL" }
+            legal_values {
+                "PLL" "FLL" "EXT_REFCLK" ( CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 ? "PLL1" : "PLL" )
+            }
+            requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" implies
+                CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 1
+            }
+            requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" implies
+                CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1
+            }
+            description "
+                Select one of 3 options for MCG output clock:
+                PLL or FLL oscillator or External reference clock."
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT {
+            display "EXT_REFCLK source clock settings"
+            flavor none
+            no_define
+            active_if {
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK") ||
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK")
+            }
+            description "Set External Reference Clock frequency and type."
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT0 {
+                display "External freq ref 0"
+                flavor data
+                no_define
+                calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS . " " .
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ
+                }
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS {
+                    display "Clock type"
+                    flavor data
+                    default_value { "OSC" }
+                    legal_values { "OSC" "XTAL" "RTC"}
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC") implies
+                        (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 50000000)
+                    }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL") implies
+                        (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 3000000) &&
+                          (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 32000000)) ||
+                          ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 32000) &&
+                           (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 40000)))
+                    }
+
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1)
+                    }
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                    }
+                    requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
+                        implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ == 32768)
+                    }
+
+                    description "
+                    Ext reference can be External oscillator or a crystal
+                    for the on-chip oscillator or Real Time Clock."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ {
+                    display "Clock frequency"
+                    flavor data
+                    legal_values  0 to 50000000
+                    default_value {
+                        is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ) ?
+                        CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ :
+                        4000000
+                    }
+                    description "External oscillator or crystal reference in Hz."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP {
+                    display "XTAL parallel C \[pF\]"
+                    flavor data
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
+                    legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 }
+                    default_value 0
+                    description "
+                        The oscillator has 4 on-chip capacitors that combined
+                        produce capacitance in parallel to the crystal."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1 {
+                display "External freq ref 1"
+                flavor data
+                no_define
+                active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+                calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS . " " .
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ
+                }
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS {
+                    display "Clock type"
+                    flavor data
+                    default_value { "OSC" }
+                    legal_values { "OSC" "XTAL" }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC") implies
+                        (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 50000000)
+                    }
+
+                    requires {
+                        (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL") implies
+                        (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 3000000) &&
+                          (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 32000000)) ||
+                          ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 32000) &&
+                           (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 40000)))
+                    }
+
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 0)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 0)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1)
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                   }
+                   requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC")
+                       implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ == 32768)
+                   }
+
+                    description "
+                    Ext reference can be External oscillator or a crystal
+                    for the on-chip oscillator or Real Time Clock."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ {
+                    display "Clock frequency"
+                    flavor data
+                    legal_values  0 to 50000000
+                    default_value {
+                        is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ) ?
+                        CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ :
+                        4000000
+                    }
+                    description "External oscillator or crystal reference in Hz."
+                }
+
+                cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP {
+                    display "XTAL parallel C \[pF\]"
+                    flavor data
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" }
+                    legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 }
+                    default_value 0
+                    description "
+                        The oscillator has 4 on-chip capacitors that combined
+                        produce capacitance in parallel to the crystal."
+                }
+            }
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL {
+            display "FLL / PLL configuration"
+            flavor none
+            no_define
+            description "
+                PLL / FLL parameters are being calculated on a
+                base of required system frequrncy and output as well as
+                reference oscillator/frequency settings."
+
+            cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP {
+                display "PLL/FLL output frequency set point"
+                flavor data
+                legal_values  32768 to 220000000
+                calculated {
+                    ((CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL") ||
+                     (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")) ?
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP :
+                        CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP
+                }
+                description "Desired PLL output frequency."
+            }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC {
+                display "Reference clock source for FLL or PLL"
+                flavor data
+                default_value { "EXT_REFCLK" }
+
+                requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "INT_RC_32KHZ")
+                    implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
+                }
+
+                legal_values { "INT_RC_32KHZ" "EXT_REFCLK" "EXT_REFCLK1" }
+                description "
+                PLL/FLL oscillators can use one of external reference
+                clock references as well as Low (32768 Hz) or High (2MHz)
+                Frequency Internal oscillator"
+            }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_PLL1_REFSRC {
+                display "Reference clock source for PLL1"
+                active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+                flavor data
+                default_value { "EXT_REFCLK" }
+
+                legal_values { "EXT_REFCLK" "EXT_REFCLK1" }
+                description "
+                    PLL1 oscillator can use one of 2 external reference clock
+                    references."
+            }
+
+            cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ {
+                display "Reference frequency."
+                flavor data
+                calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ?
+                    CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ :
+                    (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC
+                     == "INT_RC_32KHZ" ? 32768 : 2000000 )
+                }
+            }
+
+            cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL {
+                display "FLL oscillator"
+                flavor none
+                no_define
+                active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" ||
+                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK"
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE {
+                    display "Reference frequency range"
+                    flavor data
+                    legal_values 0 1 2
+                    calculated {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ > 8000000 ? 2 :
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 1000000 ? 1 :
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 32000) &&
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ <= 40000)) ? 0 :
+                        -1
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV {
+                    display "Calculated FLL divider"
+                    flavor data
+                    calculated {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE >= 1 ?
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+32768*16) / (32768*32)) :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ?
+                         ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+16384) / 32768) : -1)
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG {
+                    display "FLL divider register value"
+                    flavor data
+                    legal_values 0 1 2 3 4 5 6 7
+                    default_value {
+                        CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ?
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) <= 5 ?
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) : 5
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS {
+                    display "DCO Range Select"
+                    flavor data
+                    legal_values 0 1 2 3
+                    default_value {
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 80000000 ? 3 :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 60000000 ? 2 :
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 40000000 ? 1 : 0
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 {
+                    display "DCO max. frequency with 32768 reference"
+                    flavor data
+                    legal_values { 0 0x80 }
+                    default_value {
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 96000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 72000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 48000000) ||
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 9600000)) ?
+                        0x80 : 0x00
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT {
+                    display "FLL factor"
+                    flavor data
+                    calculated {
+                        (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 == 0x80) ?
+                        ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ?  732 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1464 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 2197 : 2929 ) :
+                        ((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ?  640 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1280 :
+                         (CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 1920 : 2560 )
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN {
+                    display "DCO input frequency"
+                    flavor data
+                    calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                        ( CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG == 0 ?
+                         ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 1 : 32 ) :
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG *
+                          ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 2 : 64)))
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN_CHECK {
+                    display "DCO input frequency check"
+                    flavor data
+                    no_define
+                    legal_values { "OK" "NOK" "not applicable" }
+                    calculated {
+                        CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ?
+                        ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) &&
+                         (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063) ?
+                         "OK" : "NOK" ) :
+                        "NotApplicable"
+                    }
+                    active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" }
+                    requires {
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) &&
+                        (CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063)
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV {
+                    display "FLL output frequency actual value"
+                    flavor data
+                    calculated {CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN *
+                        CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT }
+                }
+            }
+
+            cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL {
+                display "PLL oscillator"
+                flavor bool
+                default_value 1
+#                { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ? 0 : 1 }
+#                active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" ||
+#                    CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK"
+#                }
+
+                cdl_component CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL {
+                    display "100 Mhz line"
+                    flavor none
+                    no_define
+                    active_if !CYGINT_HAL_CORTEXM_KINETIS_150
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X {
+                        display "Phase detector proposed input frequency"
+                        no_define
+                        flavor data
+                        calculated {
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 180000000) ?
+                            3800000 :
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 110000000) ?
+                            3000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 3) ? 2000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4) ? 2000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 5) ? 2500000 :
+                            300000
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV {
+                        display "PLL External Reference Divider"
+                        flavor data
+                        legal_values 1 to 25
+                        default_value {
+                            CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ {
+                        display "Phase detector input frequency"
+                        no_define
+                        flavor data
+                        legal_values 2000000 to 4000000
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV) : -1
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV {
+                        display "VCO Divider"
+                        flavor data
+                        legal_values 24 to 55
+                        default_value { CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP /
+                             CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV {
+                        display "PLL output frequency actual value"
+                        flavor data
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV *
+                             CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV) : -1
+                        }
+                    }
+                }
+
+                cdl_component CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL {
+                    display "150 Mhz line"
+                    flavor none
+                    no_define
+                    active_if CYGINT_HAL_CORTEXM_KINETIS_150
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X {
+                        display "Phase detector proposed input frequency"
+                        no_define
+                        flavor data
+                        legal_values 1000000 to 32000000
+                        default_value {
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ == 50000000) ?
+                            (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 30000000) ? 30000000 :
+                            !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4000000) ? 4000000 :
+                            5000000
+                        }
+                    }
+
+                    cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL {
+                        display "PLL0 Reference Oscillator select"
+                        flavor data
+                        default_value 0
+                        legal_values 0 1
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV {
+                        display "PLL External Reference Divider"
+                        flavor data
+                        legal_values 1 to 8
+                        default_value {
+                            CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ {
+                        display "Phase detector input frequency"
+                        no_define
+                        flavor data
+                        legal_values 1000000 to 32000000
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ?
+                            (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV) : -1
+                        }
+                    }
+
+                    cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV {
+                        display "VCO Divider"
+                        flavor data
+                        legal_values 16 to 47
+                        default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ ?
+                            ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP /
+                             CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ) * 2) : -1
+                        }
+                    }
+
+                    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV {
+                        display "PLL output frequency actual value"
+                        flavor data
+                        calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ?
+                            ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV *
+                             CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) / 2) : -1
+                        }
+                    }
+                }
+
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV {
+                    display "PLL External Reference Divider"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV :
+                        CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV
+                    }
+                }
+
+                cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV {
+                    display "PLL External Reference Divider"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        (CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) :
+                        CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV
+                    }
+                }
+
+                cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV {
+                    display "PLL output frequency actual value"
+                    flavor data
+                    calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ?
+                        CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV :
+                        CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV
+                    }
+                }
+            }
+        }
+
+        cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC {
+            display "Internal Reference Clock"
+            flavor data
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI ? 2000000 : 32768 }
+            active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK ==  "INT_REFCLK" }
+
+            cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI {
+                display "Use highh frequency internal osc."
+                flavor bool
+                default_value 1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC {
+            display "External Reference Clock"
+            flavor data
+            calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ
+            active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK ==  "EXT_REFCLK" }
+        }
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_DIST {
+        display "Subsystem clocking"
+        flavor none
+        no_define
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS {
+            display "Peripheral bus"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 50000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value { !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                                  CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP + 1)
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH {
+            display "Flash"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 25000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value {
+                    !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP + 1)
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS {
+            display "Flex bus"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 50000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP {
+                display "Calculated value"
+                flavor data
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX ?
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX
+                }
+                legal_values  0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX
+            }
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS {
+                display "Divider"
+                flavor data
+                legal_values 1 to 16
+
+                default_value {
+                    !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP)  :
+                    (CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP + 1)
+                }
+            }
+        }
+
+
+        cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB {
+            display "USB clock"
+            flavor data
+            calculated { CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX {
+                display "Frequency limit"
+                flavor data
+                default_value 48000000
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC {
+                display "Fractional Divider"
+                flavor data
+                legal_values 1 to 2
+                default_value {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <
+                    CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX ? 1 :
+                    ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN) >
+                     (CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP * 4) ? 1 :
+                     (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN %
+                      CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP ? 2 : 1))
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV {
+                display "Divider"
+                flavor data
+                legal_values 1 to 8
+                default_value { !((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                                   CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC) %
+                                   CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP)  ?
+                    (CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                     CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                     CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP)  :
+                    ((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
+                      CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
+                      CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) +1)
+                }
+            }
+
+            cdl_option CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN {
+                display "USB divider input frequency"
+                flavor data
+                calculated {
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP {
+                display "Desired"
+                flavor data
+                calculated 48000000
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK {
+            display "Trace clock source"
+            flavor data
+            default_value { "CORE" }
+            legal_values { "CORE" "MCGOUT" }
+
+        }
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT {
+            display "Enable Trace Clock out"
+            flavor bool
+            default_value 0
+        }
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_RTC {
+        display "System uses Real Time Clock"
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_KINETIS_RTC {
+        display "Real Time Clock"
+        flavor bool
+        default_value CYGINT_HAL_CORTEXM_KINETIS_RTC
+
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP {
+            display "RTC XTAL parallel C \[pF\]"
+            flavor data
+            legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
+                30 32 }
+            default_value 0
+            description "
+                The Real Time Clock oscillator has 4 capacitors that
+                combined produce capacitance in parallel to the crystal."
+        }
+    }
+
+    #   PLL1 and OSC1 Configuration
+    #   PLL1
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 {
+        display "MCG Has PLL1"
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 {
+        display "MCG Has OSC1"
+    }
+
+    cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 {
+        display "PLL1 oscillator"
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL
+        flavor bool
+        default_value CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+        active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP {
+            display "PLL1 output frequency set point"
+            flavor data
+            legal_values  32768 to 220000000
+            calculated {
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1") ?
+                     CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP :
+                     CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP
+            }
+            description "Desired PLL1 output frequency."
+        }
+
+        cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ {
+            display "Reference frequency."
+            flavor data
+            calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ?
+                CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ :
+                (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC
+                 == "INT_RC_32KHZ" ? 32768 : 2000000 )
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X {
+            display "Phase detector proposed input frequency"
+            no_define
+            flavor data
+            legal_values 1000000 to 32000000
+            default_value {
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ == 50000000) ?
+                (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) :
+                !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 30000000) ? 30000000 :
+                !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 4000000) ? 4000000 :
+                5000000
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL {
+            display "PLL10 Reference Oscillator select"
+            flavor data
+            default_value 0
+            legal_values 0 1
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            legal_values 1 to 8
+            default_value {
+                CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ?
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                 CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ) : -1
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ {
+            display "Phase detector input frequency"
+            no_define
+            flavor data
+            legal_values 1000000 to 32000000
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ?
+                (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                 CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV) : -1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV {
+            display "VCO Divider"
+            flavor data
+            legal_values 16 to 47
+            default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ ?
+                ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP /
+                  CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ) * 2) : -1
+            }
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV {
+            display "PLL1 output frequency actual value"
+            flavor data
+            calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ?
+                ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ /
+                  CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV *
+                  CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV) / 2) : -1
+            }
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV
+        }
+
+        cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV {
+            display "PLL1 External Reference Divider"
+            flavor data
+            calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV
+        }
+
+        cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV {
+            display "PLL1 output frequency actual value"
+            flavor data
+            calculated CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV
+        }
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV {
+        display "Frequency of selected PLL"
+        flavor data
+        parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL
+        calculated {CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" ?
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV :
+            CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV
+        }
+    }
+
+    # EOF kinetis_clocking.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl
new file mode 100644
index 0000000..55cdf99
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_ddram.cdl
@@ -0,0 +1,259 @@
+##==========================================================================
+##
+##      kinetis_ddram.cdl
+##
+##      Cortex-M Freescale Kinetis DDRAM configuration
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2013-04-28
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC {
+#        display       "DDRAM"
+#        flavor bool
+#        active_if     CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+#        default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM
+#        description   "DDRAM on Kinetis is mirrored at several address ranges.
+#                Each mirror has its own caching options that may include:
+#                non-cached, write-through and write-back.
+#                By eCos configuration, DDRAM is split in 3 partitions:
+#                Cached, Non-cached and Code.
+#                Cached partition is intended for general purpose main memory.
+#                Non-cached partition is convenient for sharing
+#                buffers with other bus masters such as Ethernet controller,
+#                DMA, etc. Code partition is for executable code."
+#
+#        requires       CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+#        compile        kinetis_ddram.c
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_SIZE_MIB {
+            display       "DDRAM size \[MiB\]"
+            flavor        data
+            default_value 128
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE {
+                display    "DDRAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB * (1024 * 1024) * 0x1 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB {
+            display      "Non-cached DDRAM data partition \[MiB\]"
+            requires     { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB <=
+                           CYGHWR_HAL_KINETIS_DDR_SIZE_MIB }
+            flavor       data
+
+            implements   CYGINT_HAL_HAS_NONCACHED
+
+            legal_values { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) }
+
+            default_value CYGHWR_HAL_KINETIS_DDR_SIZE_MIB / 4
+
+            description "
+                Non-cached DDRAM partition, intended for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc."
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE {
+                display    "Non-cached DDRAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB
+                             * (1024 * 1024) * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE {
+                display    "Non-cached DDRAM base address"
+                flavor     data
+
+                calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_MIRROR +
+                             CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE +
+                             CYGHWR_HAL_KINETIS_DDR_CODE_SIZE }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_MIRROR {
+                display       "Non-cached DDRAM mirror base"
+                flavor        data
+                no_define
+                calculated    { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR == 0x70000000 ?
+                    0x80000000 : 0x70000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB {
+            display       "DDRAM code partition \[MiB\]"
+            requires      { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB <=
+                            CYGHWR_HAL_KINETIS_DDR_SIZE_MIB }
+            flavor        data
+
+            legal_values  { 1 to (CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - 8) }
+
+            default_value CYGHWR_HAL_KINETIS_DDR_SIZE_MIB / 4
+
+            description "
+                DDRAM code partition - for use as program memory.
+                On systems with cache this partition is cached in PC cache.
+                Caching is always write-through"
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_SIZE {
+                display    "DDRAM code partition size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB
+                             * (1024 * 1024) * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CODE_BASE {
+                display    "DDRAM code partition base address"
+                flavor     data
+
+                calculated { 0x08000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB {
+            display    "Cached DDRAM data partition \[MiB\]"
+            flavor     data
+            requires   { CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB >= 8 }
+            calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB -
+                         CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB -
+                         CYGHWR_HAL_KINETIS_DDR_CODE_SIZE_MIB }
+
+            description "
+                Cached DDRAM data partition - for general use as main data memory.
+                On systems with cache this partition is cached in PS cache.
+                Caching can be either copy-back or write-through and is determined by
+                general cache mode setting."
+
+            cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE {
+                display    "Cached DDRAM size \[Bytes\]"
+                flavor      data
+                calculated  { (CYGHWR_HAL_KINETIS_DDR_SIZE -
+                              CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE -
+                              CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) * 0x1 }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_BASE {
+                    display       "Cached DDRAM base address"
+                    flavor        data
+                    calculated    { CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR +
+                                    CYGHWR_HAL_KINETIS_DDR_CODE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_DDR_CACHE_TYPE {
+                    display     "DDRAM cache type"
+                    flavor       data
+                    calculated  CYGSEM_HAL_DCACHE_STARTUP_MODE
+                    description "DDRAM cache type is determined by general cache setting"
+                }
+
+                cdl_component CYGHWR_HAL_KINETIS_DDR_CACHED_MIRROR {
+                    display         "Cached DDRAM mirror base"
+                    flavor data
+                    no_define
+                    legal_values     { 0x70000000 0x80000000 }
+                    default_value    { 0x70000000 }
+                    description   "
+                        According to Kinetis Reference Manual rev. 2, the DDRAM mirror
+                        mapped at 0x80000000 (supporting write-thru caching only)
+                        is not accesible by ENET, SDH and some other bus masters,
+                        and that the mirror at 0x70000000 (supporting copy-back caching)
+                        is accessible by them.
+                        The practical tests prove that it is the opposite, actually as
+                        it should be.
+                        Until this discrepancy is resolved, this option selects the
+                        default (non)cached mirror and provides the user with possibilty for
+                        manual override.
+                        Note: The behavior may change in future."
+                }
+        }
+
+        cdl_option CYGHWR_HAL_DDR_SYNC_MODE {
+            display       "Use synchronous mode"
+            flavor        bool
+            requires      { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" }
+            default_value { 1 }
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS {
+            display      "DDRAM bus configuration"
+            flavor        data
+            legal_values  0 1 2 3 6
+            default_value 6
+            description "
+                DDRAM configuration: 0 - LPDDR Half Strength,
+                1 - LPDDR Full Strength, 2 - DDR2 Half Strength,
+                3 - DDR1, 6 - DDR2 Full Strength"
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL {
+            display    "Pad control"
+            flavor     data
+
+            calculated {
+                (CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT << 24) |
+                CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL |
+                0x00000200
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_ODT {
+                display       "On Die Termination"
+                flavor        data
+                legal_values  { 0 1 2 3 }
+                default_value 1
+
+                description   "On Die Termination \[Ohm\]: 0 - Off, 1 - 75,
+                    2 - 150, 3 - 50"
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL_SPARE_DLY_CTRL {
+                display       "Delay chains in spare logic"
+                flavor        data
+                legal_values  { 0 1 2 3 }
+                default_value 3
+
+                description "Delay chains in spare logic: 0 - No buffer, 1 - 4 buffers,
+                    2 - 7 buffers, 11 - 10 buffers"
+            }
+        }
+#    }
+
+# EOF kinetis_ddram.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl
new file mode 100644
index 0000000..ea97ad8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_fbram.cdl
@@ -0,0 +1,205 @@
+##==========================================================================
+##
+##      kinetis_fbram.cdl
+##
+##      Cortex-M Freescale Kinetis FBRAM configuration
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2013-04-28
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FBRAM {
+#        display       "FlexBus RAM"
+#        flavor bool
+#        active_if     CYGINT_HAL_CORTEXM_KINETIS_DBRAM
+#        default_value CYGINT_HAL_CORTEXM_KINETIS_FBRAM
+#        description   "FlexBus RAM on Kinetis is mirrored at several address ranges.
+#                Each mirror has its own caching options that may include:
+#                non-cached, write-through and write-back.
+#                By eCos configuration, FlexBus RAM is split in 3 partitions:
+#                Cached, Non-cached and Code.
+#                Cached partition is intended for general purpose main memory.
+#                Non-cached partition is convenient for sharing
+#                buffers with other bus masters such as Ethernet controller,
+#                DMA, etc. Code partition is for executable code."
+#
+
+        cdl_option CYGHWR_HAL_KINETIS_FBR_SIZE {
+            display       "FlexBus RAM size \[Bytes\]"
+            flavor        data
+            default_value CYGHWR_HAL_KINETIS_FB_CS0_SIZE ? CYGHWR_HAL_KINETIS_FB_CS0_SIZE * 1 : 0
+        }
+
+        cdl_option CYGHWR_HAL_KINETIS_FBR_SIZE_KIB {
+            display       "FlexBus RAM size \[KiB\]"
+            flavor        data
+            calculated    { CYGHWR_HAL_KINETIS_FBR_SIZE / 1024 }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB {
+            display      "Non-cached FlexBus data RAM partition \[KiB\]"
+            requires     { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB <=
+                           CYGHWR_HAL_KINETIS_FBR_SIZE_KIB }
+            flavor       data
+
+            implements   CYGINT_HAL_HAS_NONCACHED
+
+            legal_values { 64 to (CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - 64) }
+
+            default_value { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB / 4 }
+
+            description "
+                Non-cached FlexBus RAM partition, intended for sharing
+                buffers with other bus masters such as Ethernet controller,
+                DMA, etc."
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE {
+                display    "Non-cached FlexBus RAM size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB
+                             * 1024 * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE {
+                display    "Non-cached FlexBus RAM base address"
+                flavor     data
+
+                calculated { CYGHWR_HAL_KINETIS_FBR_NON_CACHED_MIRROR +
+                             CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE +
+                             CYGHWR_HAL_KINETIS_FBR_CODE_SIZE }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_NON_CACHED_MIRROR {
+                display       "Non-cached FlexBus RAM mirror base"
+                flavor        data
+                no_define
+                legal_values     { 0x60000000 CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : 0x80000000 }
+                default_value    { CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 :
+                                                                    0x60000000 }
+            }
+
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB {
+            display       "FlexBus RAM code partition \[KiB\]"
+            requires      { CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB <=
+                            CYGHWR_HAL_KINETIS_FBR_SIZE_KIB }
+            flavor        data
+
+            legal_values  { 64 to (CYGHWR_HAL_KINETIS_FBR_SIZE_KIB - 64) }
+
+            default_value { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB / 4 }
+
+            description "
+               FlexBus RAM code partition - for use as program memory.
+               On systems with cache this partition is cached in PC cache
+               and is always write-through"
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CODE_SIZE {
+                display    "FlexBus RAM code partition size \[Bytes\]"
+                flavor     data
+                calculated { CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB
+                             * 1024 * 0x1 }
+            }
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CODE_BASE {
+                display    "FlexBus RAM code partition base address"
+                flavor     data
+
+                legal_values     { 0x60000000
+                                   CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x18000000 :
+                                                                    0x60000000 }
+                default_value { CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x18000000 :
+                                                                 0x60000000 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE_KIB {
+            display    "Cached FlexBus RAM data partition \[KiB\]"
+            flavor     data
+            requires   { CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE_KIB >= 64 }
+            calculated { CYGHWR_HAL_KINETIS_FBR_SIZE_KIB -
+                         CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE_KIB -
+                         CYGHWR_HAL_KINETIS_FBR_CODE_SIZE_KIB }
+
+            description "
+               Cached FlexBus RAM data partition - for general use as main data memory.
+               On systems with cache this partition is cached in PS cache.
+               Caching can be either copy-back or write-through and is determined
+               by general cache mode setting."
+
+            cdl_option CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE {
+                display    "Cached FlexBus RAM size \[Bytes\]"
+                flavor      data
+                calculated  { (CYGHWR_HAL_KINETIS_FBR_SIZE -
+                              CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE -
+                              CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) * 0x1 }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_FBR_CACHED_BASE {
+                    display       "Cached FlexBus RAM base address"
+                    flavor        data
+                    calculated    { CYGHWR_HAL_KINETIS_FBR_CACHED_MIRROR +
+                                    CYGHWR_HAL_KINETIS_FBR_CODE_SIZE }
+                }
+
+                cdl_option CYGHWR_HAL_KINETIS_FBR_CACHE_TYPE {
+                    display     "FlexBus RAM cache type"
+                    flavor       data
+                    calculated  CYGSEM_HAL_DCACHE_STARTUP_MODE
+                    description "FlexBus RAM cache type is determined by general
+                        cache setting"
+                }
+
+                cdl_component CYGHWR_HAL_KINETIS_FBR_CACHED_MIRROR {
+                    display         "Cached FlexBus RAM mirror base"
+                    flavor data
+                    no_define
+                    legal_values     { 0x60000000 CYGINT_HAL_CORTEXM_KINETIS_150 ? 0x90000000 : 0x80000000 }
+                    default_value    { 0x60000000 }
+                    description      "Cached DDRAM base "
+                }
+        }
+
+#    }
+
+# EOF kinetis_fbram.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl
new file mode 100644
index 0000000..96c49a4
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl
@@ -0,0 +1,84 @@
+##==========================================================================
+##
+##      kinetis_flexbus.cdl
+##
+##      Cortex-M Freescale Kinetis FlexBus
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-12-11
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+#        cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS {
+#        display       "FlexBus"
+
+for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } {
+
+    cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] {
+        display     "Platform uses Chip select [set ::chipsel]"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides chip select [set ::chipsel], and if
+            that chip select is used on target hardware."
+    }
+
+    cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] {
+        display       "Chip select [set ::chipsel]"
+        flavor        bool
+        active_if     CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
+        default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
+        description   "
+            This option includes initialization data for
+            chip select [set ::chipsel]."
+
+        cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS {
+            display "Port size (encoded)"
+            flavor data
+            calculated ( \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8  ? 1 : \
+               CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3)
+        }
+    }
+}
+
+
+# EOF kinetis_flexbus.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl
new file mode 100644
index 0000000..bfc3c04
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl
@@ -0,0 +1,202 @@
+##==========================================================================
+##
+##      kinetis_irq_scheme.cdl
+##
+##      Cortex-M Freescale Kinetis IRQ configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+
+#    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+#        display "Variant IRQ priority defaults"
+#        no_define
+#        flavor none
+#        parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+#        description "
+#            Interrupt priorities defined by Kinetis variant"
+
+        cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP {
+            display       "Clock IRQ priority"
+            flavor        data
+            no_define
+            default_value 0xE0
+            description   "Set clock ISR priority. Default setting is lowest priority."
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+
+        }
+
+        cdl_option CYGNUM_DEVS_ETH_FREESCALE_ENET0_INTPRIO_SP {
+            display "Ethernet IRQ priority"
+            flavor data
+            no_define
+            active_if CYGPKG_DEVS_ETH_FREESCALE_ENET
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+            default_value 0xE0
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_UART {
+            display "UART IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY_SP {
+                display "UART0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY_SP {
+                display "UART1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY_SP {
+                display "UART2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY_SP {
+                display "UART3 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART3
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY_SP {
+                display "UART4 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART4
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY_SP {
+                display "UART5 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART5
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_DSPI {
+            display "DSPI IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI0_ISR_PRI_SP {
+                display "DSPI bus 0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI1_ISR_PRI_SP {
+                display "DSPI bus 1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+
+            cdl_option CYGNUM_DEVS_SPI_FREESCALE_DSPI2_ISR_PRI_SP {
+                display "DSPI bus 2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGHWR_DEVS_SPI_FREESCALE_DSPI2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0xD0
+            }
+        }
+        
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_I2C {
+            display "I2C interrupt priorities"
+            flavor none
+            no_define
+            
+            for { set ::bus 0 } { $::bus < 2 } { incr ::bus } {
+                
+                cdl_option CYGNUM_DEVS_FREESCALE_I2C[set ::bus]_IRQ_PRIORITY {
+                    display       "I2C bus [set ::bus] interrupt priority"
+                    flavor        data
+                    active_if     CYGHWR_DEVS_FREESCALE_I2C[set ::bus]
+                    default_value 0x90
+                    legal_values  { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 
+                        0x90  0xA0 0xB0 0xC0 0xD0 0xE0 }
+                }
+            }
+        }
+
+#    }
+
+
+# EOF kinetis_irq_scheme.cdl
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml
new file mode 100644
index 0000000..9afa24e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis.sgml
@@ -0,0 +1,308 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     kinetis.sgml                                                -->
+<!--                                                                 -->
+<!--     KINETIS          documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!-- <part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title> -->
+
+<refentry id="hal-cortexm-kinetis-var">
+  <refmeta>
+    <refentrytitle>Freescale Kinetis Variant</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname><literal>CYGPKG_HAL_CORTEXM_KINETIS</literal></refname>
+    <refpurpose>eCos Support for Freescale Kinetis Micro-controllers</refpurpose>
+  </refnamediv>
+  
+  <refsect1 id="hal-cortexm-kinetis-var-description"><title>Description</title>
+    <para>
+    Kinetis is a Freescale microcontroller family based on the ARM Cortex-M4 core. The
+    family consists of subfamilies: K10, K20, K30, K40, K50, K60 and K70
+    that gradually add-on performance and features.
+    </para>
+    <para>
+    The Kinetis variant HAL provides generic support for hardware found on some
+    or all Kinetis members. The variant package <literal>CYGPKG_HAL_CORTEXM_KINETIS</literal>
+    provides configurable components that aim to support the complete set of options
+    found in the Kinetis family.
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-var-sup"><title>What's supported</title>
+    <para>
+    The current Kinetis software includes a Kinetis variant HAL, some Platform BSPs,
+    as well as DMA, UART, Wallclock, Ethernet and SPI support.
+    </para>
+  </refsect1>
+  <refsect1 id="kinetis-var-config"><title>Configuration</title>
+    <para>    Kinetis is a set of families of micro-controllers packed with highly configurable components.
+    In order to facilitate system configuration for the user, the CDL configuration items are organized as a set of
+    expert components. Typically, for a given peripheral, the user chooses the required hardware
+    options and desirable parameters, and the respective CDL configuration options and settings are calculated from these.
+    If it is not possible to achieve exact values, the configurator attempts to provide 
+    approximate settings, then the user can manually do the fine tuning.</para>
+    <refsect2 id="kinetis-var-cpu-select"><title>Kinetis Part Selection</title>
+      <para>
+      Within a family and/or across families the chips are further differentiated by their features
+      such as: optional FPU, amount of memory, etc. The family member options are reflected in the
+      controller naming scheme (see respective Freescale Kinetis product brief(s) and reference manual(s)). 
+      The Kinetis part builder <literal>CYGHWR_HAL_CORTEXM_KINETIS</literal>, respects this naming scheme and
+      enables the user to interactively configure eCos for the desired part by selecting
+      the requested part name segments.
+      Based on user input, the CDL computes the part-specific eCos configuration. This includes calculation
+      of on-chip FLASH and SRAM layout as well as the activation/deactivation of options such as FPU and
+      Ethernet.
+      </para>
+    </refsect2>
+    <refsect2 id="kinetis-var-clocking"><title>Clocking</title>
+      <para>
+      Kinetis is packed with a rich set of clocking options provided by the Multipurpose Clock Generator - MCG.
+      Dependent on the part, MCG can have outlets for one or two external frequency reference sources 
+      <emphasis>OSC</emphasis> and <emphasis>OSC1</emphasis> and one
+      or two PLL oscillators <emphasis>PLL</emphasis> and <emphasis>PLL1</emphasis>.
+      Each of the external frequency reference sources can be either a crystal or external
+      oscillator and associated with either or both PLL oscillators. <emphasis>OSC</emphasis> can also be a
+      reference source for the FLL oscillator.
+      Besides <emphasis>OSC</emphasis> and <emphasis>OSC1</emphasis>, there are additional clock sources
+      including two RC oscillators and a (battery backed) RTC clock with it's own 32768 Hz crystal oscillator.
+      MCG gives the user a wide choice of system and peripheral clock source(s) that can be
+      external clock(s), internal clocks, a PLL or the FLL. An external or on-chip
+      oscillator can be used as a system clock or as a reference for PLL/FLL oscillator(s).
+      </para>
+      <note><para> In the documentation of Kinetis parts with two oscillators, <emphasis>OSC</emphasis>
+      and <emphasis>PLL</emphasis> are described as <emphasis>OSC0</emphasis> and <emphasis>PLL0</emphasis> respectively.
+      </para></note>
+      <para>
+      Clocking component <literal>CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING</literal> provides some expert
+      functionality in order to facilitate clock system configuration. Normally, the user sets requirements:
+      clock source, clock reference, desired core frequency and upper limits for peripheral
+      clock frequencies. The component automatically calculates MCG and other peripheral register
+      settings in order to achieve the required clock frequencies. This setting is not always perfect but
+      fits (exactly or close) for commonly used frequencies. If necessary, the user can fine tune the
+      clock settings interactively using the eCos Configuration Tool.
+      The two clock sources are named:
+      </para>
+      <variablelist>
+        <varlistentry>
+          <term>System clock</term>
+          <listitem><para>The clock source that provides the clock for the Cortex-M core.
+            It may also provide the clock for some peripherals.
+            </para></listitem></varlistentry>
+        <varlistentry>
+          <term>Auxiliary clock</term>
+          <listitem><para>This is optional and may provide a clock for peripherals but not for the Cortex-M core.
+            </para></listitem></varlistentry>
+      </variablelist>
+      <para>
+      The user can select which source is the system clock. The choices for system clock are: <emphasis>PLL</emphasis>,
+      <emphasis>FLL</emphasis>, <emphasis>External reference clock</emphasis> and, when available, <emphasis>PLL1</emphasis>.
+      The auxiliary clock, when available is: <emphasis>PLL</emphasis> if <emphasis>PLL1</emphasis> is selected 
+      for system the clock or <emphasis>PLL1</emphasis> if any other source is selected for the system clock.
+      </para>
+    </refsect2>
+    <refsect2 id="kinetis-var-memory"><title>Memory layouts</title>
+      <para>
+      The memory layouts and startup types which don't employ external memory should be applicable to all
+      Kinetis platforms so they are defined and maintained at the variant level.
+      This is somewhat different than common eCos practice but has some advantages brought by universal,
+      single copy linker scripts for single chip configurations. The linker scripts are further enhanced/generalized
+      by utilization of macros provided by CDL and calculated on the basis of the
+      <link linkend="kinetis-var-cpu-select">selected Kinetis part</link>.
+      </para>
+      <refsect3 id="kinetis-var-memory-ldscript-location"><title>Variant Linker 
+      Script Location</title>
+      <para>
+      Variant linker scripts are found at:
+      <filename class="directory">hal/kinetis/var/&lt;version&gt;/include/pkgconf</filename>
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-ldscript-naming"><title>Linker Script Naming</title>
+      <para>
+      Linker script file names are composed of segments
+      <filename>mlt_kinetis_&lt;NVM&gt;_&lt;SRAM&gt;_&lt;STARTUP&gt;[_&lt;PLF&gt;].ldi</filename>
+      where <filename>PLF</filename> is an optional extension for platform specific scripts and
+      other segments have meanings as described in the following table.
+      </para>
+      <table frame="all" id="kinetis-var-table-ldscript-naming"><title>Linker script name segments</title>
+        <tgroup cols="3" align="center">
+          <colspec colnum="1" colname="segment" colwidth="1*" >
+          <colspec colnum="2" colname="desc" colwidth="2*" >
+          <colspec colnum="3" colname="values" colwidth="1*" >
+          <thead>
+            <row>
+              <entry>Segment</entry>
+              <entry>Description</entry>
+              <entry>Values</entry>
+            </row>
+          </thead>
+          <tbody>
+            <row>
+              <entry><filename>NVM</filename></entry>
+              <entry>Kinetis non-volatile memory configuration</entry>
+              <entry>
+              <filename>flash</filename>,
+              <filename>flexnvm</filename>
+              </entry>
+            </row>
+            <row>
+              <entry><filename>SRAM</filename></entry>
+              <entry>SRAM memory sectioning</entry>
+              <entry>
+              <filename>unisram</filename>,
+              <filename>sram2s</filename>
+              </entry>
+            </row>
+            <row>
+              <entry><filename>STARTUP</filename></entry>
+              <entry>Startup type</entry>
+              <entry>
+              <filename>rom</filename>,
+              <filename>sram</filename>
+              </entry>
+            </row>
+          </tbody>
+        </tgroup>
+      </table>
+      <para>
+      <note><para>Never attempt to flash Kinetis with an image for SRAM startup. SRAM startup images
+      do not contain a <literal>.flash_conf</literal> section so random contents may be written in 
+      flash protection area and lock your Kinetis device. This lock-out can be permanent.
+      </para></note>
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-plf-spec"><title>Platform Specific Memory Layouts</title>
+      <para>
+      Platforms, if needed, can provide their own layouts in addition to the variant ones. Typically
+      they will cover systems with external memory. The <link linkend="kinetis-var-startup">
+      startup type</link> implicitly determines whether variant and platform defined
+      layout shall be used.
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-sram"><title>On-chip SRAM</title>
+      <para>
+      Kinetis on chip SRAM memory consists of two equal banks that occupy consecutive locations anchored
+      below and above <literal>0x20000000</literal>. This fact is reflected in memory layout scripts.
+      There are linker scripts that treat SRAM as a single section (<filename>unisram</filename>) or as
+      2 separate sections (<filename>sram2s</filename>).
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-flash"><title>On-chip FLASH</title>
+      <para>
+      Kinetis on-chip flash contains a special area <literal>[0x400-0x40F]</literal> 
+      that holds the flash security configuration. In order to preserve this area from 
+      accidental writing and at the same time provide regular access,
+      a custom linker section <literal>.flash_conf</literal> is created. In addition, in order
+      to utilize the FLASH pool below <literal>0x400</literal> the <emphasis>USER_SECTION</emphasis> 
+      <literal>.kinetis_misc</literal> is defined. This section typically contains 
+      code parts from <filename>kinetis_misc.c</filename>.
+      </para>
+      </refsect3>
+      <refsect3 id="kinetis-var-memory-cache"><title>Cache</title>
+      <para>
+      Kinetis members with operating frequencies of 120 MHz and 150 MHz are equipped with cache memory.
+      Due to the Harvard architecture, there are two cache memories connected to code 
+      - <emphasis>PC</emphasis> and system - <emphasis>PS</emphasis> buses respectively.
+      Although both modules can cache both instructions and data (unified caches), with the provided
+      memory they act as instruction (<emphasis>PC</emphasis>) and data (<emphasis>PS</emphasis>) caches.
+      </para>
+      <para>
+      A common caching issue is sharing memory resources with bus masters such as DMA, Ethernet controller, etc.
+      In order to keep shared data such as buffers and transfer control descriptors consistent,
+      cached data have to be flushed and/or invalidated. An alternative approach, used here is usage of
+      non-cachable memory for shared data. <literal>CYGHWR_HAL_NON_CACHABLE</literal> provides for
+      the configuration of non-cachable memory. If some bus masters have provision for non-cache able memory,
+      such configuration options can be parenthed by <literal>CYGHWR_HAL_NON_CACHABLE</literal>.
+      </para>
+      </refsect3>
+      </refsect2>
+      <refsect2 id="kinetis-var-startup"><title>Startup types</title>
+        <para>
+        There are <emphasis>two levels</emphasis> of startup type:
+        </para>
+        <variablelist>
+          <varlistentry>
+            <term>Variant <literal>CYG_HAL_STARTUP_VAR</literal></term>
+            <listitem><para>This is always present and provides startup
+              types for systems without external memory.
+              </para></listitem></varlistentry>
+          <varlistentry>
+            <term>Platform <literal>CYG_HAL_STARTUP_PLF</literal></term>
+            <listitem><para>This is optional and is 
+              provided by a platform package. Typically it provides startup types for systems
+              that employ external memory.
+              </para></listitem></varlistentry>
+        </variablelist>
+        <para>
+        </para>
+        <para>
+        When present, the platform startup overloads the variant startup and has precedence over it.
+        User can activate the variant startup by setting platform startup to
+        <literal>ByVariant</literal>.
+        </para>
+        <refsect3 id="kinetis-var-startup-byvariant"><title>Startup types provided variant</title>
+        <para>
+        The following startup types are provided for Kinetis at the variant level:
+        </para>
+        <variablelist>
+          <varlistentry>
+            <term><literal>ROM</literal></term>
+            <listitem><para>Normal startup for stand-alone operation. eCos image has to be flashed
+              in internal flash;
+              </para></listitem></varlistentry>
+          <varlistentry>
+            <term><literal>SRAM</literal></term>
+            <listitem><para>Image is loaded in internal SRAM by means of JTAG/SWD and executed
+              under debugger control.
+              </para></listitem></varlistentry>
+        </variablelist>      
+        <note><para>(IMPORTANT) Never, ever attempt to flash Kinetis with an image for SRAM startup.
+        SRAM startup images do not contain a <literal>.flash_conf</literal> section so random contents
+        may be written to the flash protection area and lock your Kinetis device. This lock-out can be permanent.
+        </para></note>
+        </refsect3>
+      </refsect2>
+      <refsect2 id="kinetis-interrupt-priority-scheme"><title>Interrupt priority scheme</title>
+        <para>
+        In case of multiple simultaneous interrupts, interrupt service request resolution is based
+        on a relative comparison of interrupt priorities, rather than on individual interrupt priority values.
+        <emphasis>Interrupt priority scheme</emphasis> gives a consolidated overview and control
+        of priorities of all interrupt sources. Interrupt priorities can be provided by either variant
+        <literal>CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR</literal>
+        or platform <literal>CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME</literal>.
+        </para>
+      </refsect2>
+    </refsect1>
+    
+  </refentry>
+  
+  <!--</part>-->
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml
new file mode 100644
index 0000000..9fd6e90
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_begin.sgml
@@ -0,0 +1,37 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     kinetis_begin.sgml                                          -->
+<!--                                                                 -->
+<!--     Kinetis documentation.                                      -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml
new file mode 100644
index 0000000..0d70d93
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/doc/kinetis_end.sgml
@@ -0,0 +1,37 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     kinetis_end.sgml                                             -->
+<!--                                                                 -->
+<!--     Kinetis documentation.                                      -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2012 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2012/01/10                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+</part>
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h
new file mode 100644
index 0000000..8c5445b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h
@@ -0,0 +1,282 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour, ilijak
+// Contributors:
+// Date:         2012-05-02
+// Purpose:      Cache control API
+// Description:  The macros defined here provide the HAL APIs for handling
+//               cache control operations.
+//
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+#ifdef CYGINT_HAL_CACHE
+
+// Data cache
+#define HAL_DCACHE_SIZE                 8192    // Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
+#define HAL_DCACHE_WAYS                 2       // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE                 8192    // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
+#define HAL_ICACHE_WAYS                 2       // Associativity of the cache
+
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+#include <cyg/hal/var_io.h>
+#include <cyg/hal/var_io_lmem.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE() HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE() HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL() HAL_CORTEXM_KINETIS_CACHE_PS_INVALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC() HAL_CORTEXM_KINETIS_CACHE_PS_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL() HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)                         \
+    CYG_MACRO_START                                            \
+        (_state_) = HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED(); \
+    CYG_MACRO_END
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                  \
+            HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base_, _size_)
+
+// Write dirty cache lines to memory and invalidate the cache entries
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )                  \
+            HAL_CORTEXM_KINETIS_CACHE_PS_CLR(_base_, _size_)
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE() HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE() HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL() HAL_CORTEXM_KINETIS_CACHE_PC_INVALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC() HAL_CORTEXM_KINETIS_CACHE_PC_SYNC()
+
+// Purge contents of data cache
+#define HAL_ICACHE_PURGE_ALL() HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)                         \
+    CYG_MACRO_START                                            \
+        (_state_) = HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED(); \
+    CYG_MACRO_END
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )                  \
+            HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base_, _size_)
+
+#else // CYGINT_HAL_CACHE
+
+// Data cache
+//#define HAL_DCACHE_SIZE                 0     // Size of data cache in bytes
+//#define HAL_DCACHE_LINE_SIZE            0     // Size of a data cache line
+//#define HAL_DCACHE_WAYS                 0      // Associativity of the cache
+
+// Instruction cache
+//#define HAL_ICACHE_SIZE                 0     // Size of cache in bytes
+//#define HAL_ICACHE_LINE_SIZE            0      // Size of a cache line
+//#define HAL_ICACHE_WAYS                 0      // Associativity of the cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+    CYG_MACRO_START                    \
+    (_state_) = 0;                     \
+    CYG_MACRO_END
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+
+//#define HAL_DCACHE_WRITETHRU_MODE       0
+//#define HAL_DCACHE_WRITEBACK_MODE       1
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+    CYG_MACRO_START                    \
+        (_state_) = 0;                 \
+    CYG_MACRO_END
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+#endif // CYGINT_HAL_CACHE
+
+// End of hal_cache.h
+#endif // CYGONCE_HAL_CACHE_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h
new file mode 100644
index 0000000..77bd8f5
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/hal_diag.h
@@ -0,0 +1,92 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2011-02-05
+// Purpose:        HAL diagnostics
+// Description: 
+// Usage:          #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#define HAL_DIAG_INIT()          hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void hal_plf_diag_init(void);
+__externC void hal_plf_diag_putc(char);
+__externC cyg_uint8 hal_plf_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_plf_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc()
+# endif
+
+#endif
+
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h
new file mode 100644
index 0000000..734bb2f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi
new file mode 100644
index 0000000..3e53672
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_rom.ldi
@@ -0,0 +1,45 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    ram  : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+    SECTION_data (ram, 0x20000000, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h
new file mode 100644
index 0000000..ebb5c73
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.h
@@ -0,0 +1,22 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram_u (0x20000000)
+#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_u+CYGMEM_REGION_sram_u_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi
new file mode 100644
index 0000000..818c241
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_sram2s_sram.ldi
@@ -0,0 +1,35 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    sram_u  : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram_l, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA)
+    SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram_u, 0x20000000, LMA_EQ_VMA)
+    SECTION_rodata1 (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h
new file mode 100644
index 0000000..3924c2c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.h
@@ -0,0 +1,22 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi
new file mode 100644
index 0000000..360fc30
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_rom.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h
new file mode 100644
index 0000000..688f12a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.h
@@ -0,0 +1,18 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi
new file mode 100644
index 0000000..f928d42
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flash_unisram_sram.ldi
@@ -0,0 +1,34 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h
new file mode 100644
index 0000000..2452f06
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.h
@@ -0,0 +1,45 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+# define CYGMEM_REGION_flexnvm (0x10000000)
+# define CYGMEM_REGION_flexnvm_SIZE (CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE)
+# define CYGMEM_REGION_flexnvm_ATTR (CYGMEM_REGION_ATTR_R)
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_KINETIS_EEE) && CYGHWR_HAL_CORTEXM_KINETIS_EEE
+#  define CYGMEM_REGION_eeeprom0 (0x14000000)
+#  define CYGMEM_REGION_eeeprom0_SIZE (CYGHWR_HAL_KINETIS_EEE0_SIZE)
+#  define CYGMEM_REGION_eeeprom0_ATTR (CYGMEM_REGION_ATTR_R)
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+#  define CYGMEM_REGION_eeeprom1 (0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE )
+#  define CYGMEM_REGION_eeeprom1_SIZE (CYGHWR_HAL_KINETIS_EEE1_SIZE)
+#  define CYGMEM_REGION_eeeprom1_ATTR (CYGMEM_REGION_ATTR_R)
+# endif
+#else
+# define CYGMEM_REGION_flexram (0x14000000)
+# define CYGMEM_REGION_flexram_SIZE (CYGHWR_HAL_KINETIS_FLEXRAM_SIZE)
+# define CYGMEM_REGION_flexram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi
new file mode 100644
index 0000000..8897d2d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_rom.ldi
@@ -0,0 +1,67 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    ram  : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+    flexnvm : ORIGIN = 0x10000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE
+    eeeprom0 : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_EEE0_SIZE
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+    eeeprom1 : ORIGIN = 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE, LENGTH = CYGHWR_HAL_KINETIS_EEE1_SIZE
+# endif
+#else
+    flexram : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+#endif
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (code_sram, sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA)
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+    USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA)
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE
+    USER_SECTION(e_eeprom0, eeeprom0, 0x14000000 (NOLOAD), LMA_EQ_VMA)
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+    USER_SECTION(e_eeprom1, eeeprom1, 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE (NOLOAD), LMA_EQ_VMA)
+# endif
+#else
+    USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA)
+#endif
+    SECTION_data (ram, 0x20000000, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h
new file mode 100644
index 0000000..ebb5c73
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.h
@@ -0,0 +1,22 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram_u (0x20000000)
+#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram_u+CYGMEM_REGION_sram_u_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi
new file mode 100644
index 0000000..ee32874
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_sram2s_sram.ldi
@@ -0,0 +1,35 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram_l  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE
+    sram_u  : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, LMA_EQ_VMA)
+    SECTION_RELOCS (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram_l, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram_u, 0x20000000 , LMA_EQ_VMA)
+    SECTION_rodata1 (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram_u, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h
new file mode 100644
index 0000000..67d4559
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.h
@@ -0,0 +1,42 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R)
+
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+# define CYGMEM_REGION_flexnvm (0x10000000)
+# define CYGMEM_REGION_flexnvm_SIZE (CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE)
+# define CYGMEM_REGION_flexnvm_ATTR (CYGMEM_REGION_ATTR_R)
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_KINETIS_EEE) && CYGHWR_HAL_CORTEXM_KINETIS_EEE
+#  define CYGMEM_REGION_eeeprom0 (0x14000000)
+#  define CYGMEM_REGION_eeeprom0_SIZE (CYGHWR_HAL_KINETIS_EEE0_SIZE)
+#  define CYGMEM_REGION_eeeprom0_ATTR (CYGMEM_REGION_ATTR_R)
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+#  define CYGMEM_REGION_eeeprom1 (0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE )
+#  define CYGMEM_REGION_eeeprom1_SIZE (CYGHWR_HAL_KINETIS_EEE1_SIZE)
+#  define CYGMEM_REGION_eeeprom1_ATTR (CYGMEM_REGION_ATTR_R)
+# endif
+#else
+# define CYGMEM_REGION_flexram (0x14000000)
+# define CYGMEM_REGION_flexram_SIZE (CYGHWR_HAL_KINETIS_FLEXRAM_SIZE)
+# define CYGMEM_REGION_flexram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi
new file mode 100644
index 0000000..acd8375
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_rom.ldi
@@ -0,0 +1,65 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+    flexnvm : ORIGIN = 0x10000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE
+    eeeprom0 : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_EEE0_SIZE
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+    eeeprom1 : ORIGIN = 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE, LENGTH = CYGHWR_HAL_KINETIS_EEE1_SIZE
+# endif
+#else
+    flexram : ORIGIN = 0x14000000, LENGTH = CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
+#endif
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA)
+
+    // Kinetis FLASH configuration field. Must be present at 0x00000400
+    // Warning: Omitting FLASH configuration field or moving it to
+    //          other location may lock Kinetis controller.
+    // See src/kinetis_mis.c for definition
+
+    .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash
+
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+#ifdef CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE
+    USER_SECTION(d_flash, flexnvm, 0x10000000 (NOLOAD), LMA_EQ_VMA)
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_EEE
+    USER_SECTION(e_eeprom0, eeeprom0, 0x14000000 (NOLOAD), LMA_EQ_VMA)
+# if CYGHWR_HAL_KINETIS_EEE_SPLIT > 1
+    USER_SECTION(e_eeprom1, eeeprom1, 0x14000000 + CYGHWR_HAL_KINETIS_EEE0_SIZE (NOLOAD), LMA_EQ_VMA)
+# endif
+#else
+    USER_SECTION(flex_ram, flexram, 0x14000000 (NOLOAD), LMA_EQ_VMA)
+#endif
+    SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h
new file mode 100644
index 0000000..688f12a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.h
@@ -0,0 +1,18 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi
new file mode 100644
index 0000000..f928d42
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/pkgconf/mlt_kinetis_flexnvm_unisram_sram.ldi
@@ -0,0 +1,34 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h
new file mode 100644
index 0000000..61f02de
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/plf_stub.h
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008,
+//               2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:jskov, gthomas, jlarmour
+// Date:        2008-07-30
+// Purpose:     Platform HAL stub support for Kinetis variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/cortexm_stub.h>           // architecture stub support
+
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_arch.h
new file mode 100644
index 0000000..8e99007
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      Kinetis variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2011-02-05
+// Purpose:      Kinetis variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_intr.h
new file mode 100644
index 0000000..5aedc18
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_intr.h
@@ -0,0 +1,244 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for Kinetis variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Date:          2011-02-05
+// Purpose:       Define Interrupt support
+// Description:   The interrupt specifics for Freescale Kinetis variants are
+//                defined here.
+//
+// Usage:         #include <cyg/hal/var_intr.h>
+//                However applications should include using <cyg/hal/hal_intr.h>
+//                instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+typedef enum {
+    CYGNUM_HAL_INTERRUPT_DMA0
+        = CYGNUM_HAL_INTERRUPT_EXTERNAL,  // DMA Channel 0 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA1,            // DMA Channel 1 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA2,            // DMA Channel 2 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA3,            // DMA Channel 3 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA4,            // DMA Channel 4 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA5,            // DMA Channel 5 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA6,            // DMA Channel 6 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA7,            // DMA Channel 7 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA8,            // DMA Channel 8 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA9,            // DMA Channel 9 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA10,           // DMA Channel 10 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA11,           // DMA Channel 11 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA12,           // DMA Channel 12 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA13,           // DMA Channel 13 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA14,           // DMA Channel 14 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA15,           // DMA Channel 15 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA_ERROR,       // DMA Error Int
+    CYGNUM_HAL_INTERRUPT_MCM,             // Normal Int
+    CYGNUM_HAL_INTERRUPT_FTFL,            // FTFL Int
+    CYGNUM_HAL_INTERRUPT_READ_COLLISION,  // Read Collision Int
+    CYGNUM_HAL_INTERRUPT_LVD_LVW,         // Low Volt Detect, Low Volt Warn
+    CYGNUM_HAL_INTERRUPT_LLW,             // Low Leakage Wakeup
+    CYGNUM_HAL_INTERRUPT_WDOG,            // WDOG Int
+    CYGNUM_HAL_INTERRUPT_RNGB,            // RNGB Int
+    CYGNUM_HAL_INTERRUPT_I2C0,            // I2C0 int
+    CYGNUM_HAL_INTERRUPT_I2C1,            // I2C1 int
+    CYGNUM_HAL_INTERRUPT_SPI0,            // SPI0 Int
+    CYGNUM_HAL_INTERRUPT_SPI1,            // SPI1 Int
+    CYGNUM_HAL_INTERRUPT_SPI2,            // SPI2 Int
+    CYGNUM_HAL_INTERRUPT_CAN0_ORED_MESSAGE_BUFFER,// CAN0 OR'd Msg Buffs Int
+    CYGNUM_HAL_INTERRUPT_CAN0_BUS_OFF,    // CAN0 Bus Off Int
+    CYGNUM_HAL_INTERRUPT_CAN0_ERROR,      // CAN0 Error Int
+    CYGNUM_HAL_INTERRUPT_CAN0_TX_WARNING, // CAN0 Tx Warning Int
+    CYGNUM_HAL_INTERRUPT_CAN0_RX_WARNING, // CAN0 Rx Warning Int
+    CYGNUM_HAL_INTERRUPT_CAN0_WAKE_UP,    // CAN0 Wake Up Int
+    CYGNUM_HAL_INTERRUPT_CAN0_IMEU,       // CAN0 Ind. Match El Update (IMEU) Int
+    CYGNUM_HAL_INTERRUPT_CAN0_LOST_RX,    // CAN0 Lost Receive Int
+    CYGNUM_HAL_INTERRUPT_CAN1_ORED_MESSAGE_BUFFER, // CAN1 OR'd Msg Buffs Int
+    CYGNUM_HAL_INTERRUPT_CAN1_BUS_OFF,     // CAN1 Bus Off Int
+    CYGNUM_HAL_INTERRUPT_CAN1_ERROR,      // CAN1 Error Int
+    CYGNUM_HAL_INTERRUPT_CAN1_TX_WARNING, // CAN1 Tx Warning Int
+    CYGNUM_HAL_INTERRUPT_CAN1_RX_WARNING, // CAN1 Rx Warning Int
+    CYGNUM_HAL_INTERRUPT_CAN1_WAKE_UP,    // CAN1 Wake Up Int
+    CYGNUM_HAL_INTERRUPT_CAN1_IMEU,       // CAN1 Ind. Match El Update (IMEU) Int
+    CYGNUM_HAL_INTERRUPT_CAN1_LOST_RX,    // CAN1 Lost Receive Int
+    CYGNUM_HAL_INTERRUPT_UART0_RX_TX,     // UART0 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART0_ERR,       // UART0 Error int
+    CYGNUM_HAL_INTERRUPT_UART1_RX_TX,     // UART1 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART1_ERR,       // UART1 Error int
+    CYGNUM_HAL_INTERRUPT_UART2_RX_TX,     // UART2 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART2_ERR,       // UART2 Error int
+    CYGNUM_HAL_INTERRUPT_UART3_RX_TX,     // UART3 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART3_ERR,       // UART3 Error int
+    CYGNUM_HAL_INTERRUPT_UART4_RX_TX,     // UART4 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART4_ERR,       // UART4 Error int
+    CYGNUM_HAL_INTERRUPT_UART5_RX_TX,     // UART5 Receive/Transmit int
+    CYGNUM_HAL_INTERRUPT_UART5_ERR,       // UART5 Error int
+    CYGNUM_HAL_INTERRUPT_ADC0,            // ADC0 int
+    CYGNUM_HAL_INTERRUPT_ADC1,            // ADC1 int
+    CYGNUM_HAL_INTERRUPT_CMP0,            // CMP0 int
+    CYGNUM_HAL_INTERRUPT_CMP1,            // CMP1 int
+    CYGNUM_HAL_INTERRUPT_CMP2,            // CMP2 int
+    CYGNUM_HAL_INTERRUPT_FTM0,            // FTM0 fault, overflow and channels int
+    CYGNUM_HAL_INTERRUPT_FTM1,            // FTM1 fault, overflow and channels int
+    CYGNUM_HAL_INTERRUPT_FTM2,            // FTM2 fault, overflow and channels int
+    CYGNUM_HAL_INTERRUPT_CMT,             // CMT int
+    CYGNUM_HAL_INTERRUPT_RTC_RTC,         // RTC int
+    CYGNUM_HAL_INTERRUPT_RTC_SECONDS,     // RTC seconds interrupt
+    CYGNUM_HAL_INTERRUPT_PIT0,            // PIT timer channel 0 int
+    CYGNUM_HAL_INTERRUPT_PIT1,            // PIT timer channel 1 int
+    CYGNUM_HAL_INTERRUPT_PIT2,            // PIT timer channel 2 int
+    CYGNUM_HAL_INTERRUPT_PIT3,            // PIT timer channel 3 int
+    CYGNUM_HAL_INTERRUPT_PDB0,            // PDB0 Int
+    CYGNUM_HAL_INTERRUPT_USB0,            // USB0 int
+    CYGNUM_HAL_INTERRUPT_USBDCD,          // USBDCD Int
+    CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER, // ENET MAC IEEE 1588 Timer Int
+    CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT,   // ENET MAC Transmit Int
+    CYGNUM_HAL_INTERRUPT_ENET_RECEIVE,    // ENET MAC Receive Int
+    CYGNUM_HAL_INTERRUPT_ENET_ERROR,      // ENET MAC Error and miscelaneous Int
+    CYGNUM_HAL_INTERRUPT_I2S0,            // I2S0 Int
+    CYGNUM_HAL_INTERRUPT_SDHC,            // SDHC Int
+    CYGNUM_HAL_INTERRUPT_DAC0,            // DAC0 int
+    CYGNUM_HAL_INTERRUPT_DAC1,            // DAC1 int
+    CYGNUM_HAL_INTERRUPT_TSI0,            // TSI0 Int
+    CYGNUM_HAL_INTERRUPT_MCG,             // MCG Int
+    CYGNUM_HAL_INTERRUPT_LPTIMER,         // LPTimer int
+    CYGNUM_HAL_INTERRUPT_LCD,             // Segment LCD int
+    CYGNUM_HAL_INTERRUPT_PORTA,           // Port A int
+    CYGNUM_HAL_INTERRUPT_PORTB,           // Port B int
+    CYGNUM_HAL_INTERRUPT_PORTC,           // Port C int
+    CYGNUM_HAL_INTERRUPT_PORTD,           // Port D int
+    CYGNUM_HAL_INTERRUPT_PORTE,           // Port E int
+    CYGNUM_HAL_INTERRUPT_PORTF,           // Port F interrupt
+    CYGNUM_HAL_INTERRUPT_DDR,             // DDR interrupt
+    CYGNUM_HAL_INTERRUPT_SWI,             // Software interrupt
+    CYGNUM_HAL_INTERRUPT_NFC,             // NAND flash controller interrupt
+    CYGNUM_HAL_INTERRUPT_USBHS,           // USB high speed OTG interrupt
+    CYGNUM_HAL_INTERRUPT_GLCD,            // Graphical LCD interrupt
+    CYGNUM_HAL_INTERRUPT_CMP3,            // CMP3 interrupt
+    CYGNUM_HAL_INTERRUPT_TAMPER,          // Tamper detect interrupt
+    CYGNUM_HAL_INTERRUPT_Reserved116,     // Reserved interrupt 116
+    CYGNUM_HAL_INTERRUPT_FTM3,            // FTM3 fault, overflow and channels interrupt
+    CYGNUM_HAL_INTERRUPT_ADC2,            // ADC2 interrupt
+    CYGNUM_HAL_INTERRUPT_ADC3,            // ADC3 interrupt
+    CYGNUM_HAL_INTERRUPT_I2S1_TX,         // I2S1 transmit interrupt
+    CYGNUM_HAL_INTERRUPT_I2S1_RX          // I2S1 receive interrupt
+} KinetisExtInterrupt_e;
+
+// DMA16..31 share interrupt vectors with DMA0..15 respectively.
+
+#define    CYGNUM_HAL_INTERRUPT_DMA16  CYGNUM_HAL_INTERRUPT_DMA0
+#define    CYGNUM_HAL_INTERRUPT_DMA17  CYGNUM_HAL_INTERRUPT_DMA1
+#define    CYGNUM_HAL_INTERRUPT_DMA18  CYGNUM_HAL_INTERRUPT_DMA2
+#define    CYGNUM_HAL_INTERRUPT_DMA19  CYGNUM_HAL_INTERRUPT_DMA3
+#define    CYGNUM_HAL_INTERRUPT_DMA20  CYGNUM_HAL_INTERRUPT_DMA4
+#define    CYGNUM_HAL_INTERRUPT_DMA21  CYGNUM_HAL_INTERRUPT_DMA5
+#define    CYGNUM_HAL_INTERRUPT_DMA22  CYGNUM_HAL_INTERRUPT_DMA6
+#define    CYGNUM_HAL_INTERRUPT_DMA23  CYGNUM_HAL_INTERRUPT_DMA7
+#define    CYGNUM_HAL_INTERRUPT_DMA34  CYGNUM_HAL_INTERRUPT_DMA8
+#define    CYGNUM_HAL_INTERRUPT_DMA25  CYGNUM_HAL_INTERRUPT_DMA9
+#define    CYGNUM_HAL_INTERRUPT_DMA26  CYGNUM_HAL_INTERRUPT_DMA10
+#define    CYGNUM_HAL_INTERRUPT_DMA27  CYGNUM_HAL_INTERRUPT_DMA11
+#define    CYGNUM_HAL_INTERRUPT_DMA28  CYGNUM_HAL_INTERRUPT_DMA12
+#define    CYGNUM_HAL_INTERRUPT_DMA29  CYGNUM_HAL_INTERRUPT_DMA13
+#define    CYGNUM_HAL_INTERRUPT_DMA30  CYGNUM_HAL_INTERRUPT_DMA14
+#define    CYGNUM_HAL_INTERRUPT_DMA31  CYGNUM_HAL_INTERRUPT_DMA15
+
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_I2S1_RX)
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX            CYGNUM_HAL_INTERRUPT_I2S1_RX
+#define CYGNUM_HAL_ISR_COUNT          (CYGNUM_HAL_ISR_MAX + 1)
+
+#define CYGNUM_HAL_VSR_MIN            0
+#ifndef CYGNUM_HAL_VSR_MAX
+# define CYGNUM_HAL_VSR_MAX           (CYGNUM_HAL_VECTOR_SYS_TICK+ \
+                                       CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+
+#define CYGNUM_HAL_VSR_COUNT          (CYGNUM_HAL_VSR_MAX+1)
+
+//==========================================================================
+// Interrupt mask and config for variant-specific devices
+
+// PORT Pin interrupts
+
+#define CYGHWR_HAL_KINETIS_PIN_IRQ_VECTOR(__pin) \
+    (CYGNUM_HAL_INTERRUPT_PORTA + CYGHWR_HAL_KINETIS_PIN_PORT(__pin))
+
+//===========================================================================
+// Interrupt resources exported by HAL to device drivers
+
+// Export Interrupt vectors to serial driver.
+
+#define CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART0_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART1_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART2_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART3_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART4_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART5_RX_TX
+
+// Export Interrupt vectors to ENET driver.
+
+#define CYGNUM_FREESCALE_ENET0_1588_TIMER_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER
+#define CYGNUM_FREESCALE_ENET0_TRANSMIT_INT_VECTOR   \
+            CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT
+#define CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR    \
+            CYGNUM_HAL_INTERRUPT_ENET_RECEIVE
+#define CYGNUM_FREESCALE_ENET0_ERROR_INT_VECTOR      \
+            CYGNUM_HAL_INTERRUPT_ENET_ERROR
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io.h
new file mode 100644
index 0000000..18df202
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io.h
@@ -0,0 +1,1206 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//===========================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-02-05
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <pkgconf/hal_cortexm_kinetis.h>
+
+#include <cyg/hal/plf_io.h>
+
+//===========================================================================
+// Cortex-M architecture
+//---------------------------------------------------------------------------
+//--------------------------------------------------------------------------
+// Cortex-M architecture overrides
+//---------------------------------------------------------------------------
+// VTOR - Vector Table Offset Register
+#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM (BIT_(29) -                       \
+                                           CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE)
+#endif
+
+//=============================================================================
+// Kinetis system configuration
+//---------------------------------------------------------------------------
+// Utilize Freescale Kinetis flash between startup vectors and 0x400
+// for misc funtions.
+#ifdef CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION
+# define CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR \
+         CYGBLD_ATTRIB_SECTION(".kinetis_misc")
+#else
+# define CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+#endif
+
+//===========================================================================
+// KINETIS FLASH configuration field
+//===========================================================================
+
+// Note: KINETIS FLASH configuration field must be present in Kinetis flash
+//       image and ocupy addresses 0x00000400 to 0x0000040f.
+
+typedef struct cyghwr_hal_kinetis_flash_conf_s {
+    cyg_uint8 backdoor_key[8]; // 0x400 .. 0x407
+    cyg_uint8 fprot[4];        // 0x408 .. 0x40b
+    cyg_uint8 fsec;            // 0x40c
+    cyg_uint8 fopt;            // 0x40d
+    cyg_uint8 feprot;          // 0x40e
+    cyg_uint8 fdprot;          // 0x40f
+} cyghwr_hal_kinetis_flash_conf_t;
+
+__externC const cyghwr_hal_kinetis_flash_conf_t *hal_kinetis_flash_conf_p( void );
+
+//===========================================================================
+// Kinetis Peripherals
+//---------------------------------------------------------------------------
+// Internal Flash
+
+typedef volatile struct cyghwr_hal_kinetis_flash_s {
+    cyg_uint8 fstat;    // Flash status register
+    cyg_uint8 fcnfg;    // Flash configuration register
+    cyg_uint8 fsec;     // Flash security register
+    cyg_uint8 fopt;     // Flash option register
+    cyg_uint8 fccob3;   // Flash common command object registers
+    cyg_uint8 fccob2;
+    cyg_uint8 fccob1;
+    cyg_uint8 fccob0;
+    cyg_uint8 fccob7;
+    cyg_uint8 fccob6;
+    cyg_uint8 fccob5;
+    cyg_uint8 fccob4;
+    cyg_uint8 fccobB;
+    cyg_uint8 fccobA;
+    cyg_uint8 fccob9;
+    cyg_uint8 fccob8;
+    cyg_uint8 fprot3;   // Program flash protection registers
+    cyg_uint8 fprot2;
+    cyg_uint8 fprot1;
+    cyg_uint8 fprot0;
+    cyg_uint8 reserved[2];
+    cyg_uint8 feprot;   // EEPROM Protection register
+    cyg_uint8 fdprot;   // Data flash protection register
+} cyghwr_hal_kinetis_flash_t;
+
+#define CYGHWR_HAL_KINETIS_FLASH_P ((cyghwr_hal_kinetis_flash_t *) 0x40020000)
+
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_CCIF_M           0x80
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_RDCOLERR_M       0x40
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_ACCERR_M         0x20
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_FPVIOL_M         0x10
+#define CYGHWR_HAL_KINETIS_FLASH_FSTAT_MGSTAT0_M        0x01
+
+//---------------------------------------------------------------------------
+// Oscillator
+
+#define CYGHWR_HAL_KINETIS_OSC_CR          (0x40065000)
+#define CYGHWR_HAL_KINETIS_OSC_CR_P        ((volatile cyg_uint8*) 0x40065000)
+
+#define CYGHWR_HAL_KINETIS_OSC1_CR         (0x400E5000)
+#define CYGHWR_HAL_KINETIS_OSC1_CR_P       ((volatile cyg_uint8*) 0x400E5000)
+
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_M      0x01
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_S         0
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_M       0x02
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_S          1
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC4P_M       0x04
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC4P_S          2
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC2P_M       0x08
+#define CYGHWR_HAL_KINETIS_OSC_CR_SC2P_S          3
+#define CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M   0x20
+#define CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_S      5
+#define CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M    0x80
+#define CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_S       7
+
+//---------------------------------------------------------------------------
+// MCG
+
+typedef volatile struct cyghwr_hal_kinetis_mcg_s {
+    cyg_uint8 c1;      // MCG Control 1 Register
+    cyg_uint8 c2;      // MCG Control 2 Register
+    cyg_uint8 c3;      // MCG Control 3 Register
+    cyg_uint8 c4;      // MCG Control 4 Register
+    cyg_uint8 c5;      // MCG Control 5 Register
+    cyg_uint8 c6;      // MCG Control 6 Register
+    cyg_uint8 status;  // MCG Status Register
+    cyg_uint8 mcg_res0;
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1
+    cyg_uint8 atc;     // MCG Auto Trim Control Register
+#elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+    cyg_uint8 sc;     // MCG Status and Control Register
+#endif
+    cyg_uint8 mcg_res1;
+    cyg_uint8 atcvh;   // MCG Auto Trim Compare Value High Register
+    cyg_uint8 atcvl;   // MCG Auto Trim Compare Value Low Register
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+    cyg_uint8 c7;      // MCG Control 7 Register
+    cyg_uint8 c8;      // MCG Control 8 Register
+#endif
+#if CYGINT_HAL_CORTEXM_KINETIS_150
+    cyg_uint8 c10;     // MCG Control 10 Register
+    cyg_uint8 mcg_res2;
+    cyg_uint8 c11;     // MCG Control 11 Register
+    cyg_uint8 c12;     // MCG Control 12 Register
+    cyg_uint8 s2;      // MCG Status 2 Register
+#endif //CYGINT_HAL_CORTEXM_KINETIS_150
+} cyghwr_hal_kinetis_mcg_t;
+
+#define CYGHWR_HAL_KINETIS_MCG_P  ((cyghwr_hal_kinetis_mcg_t *)0x40064000)
+
+// C1 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C1_IREFSTEN_M    0x01
+#define CYGHWR_HAL_KINETIS_MCG_C1_IREFSTEN_S    0
+#define CYGHWR_HAL_KINETIS_MCG_C1_IRCLKEN_M     0x02
+#define CYGHWR_HAL_KINETIS_MCG_C1_IRCLKEN_S     1
+#define CYGHWR_HAL_KINETIS_MCG_C1_IREFS_M       0x4
+#define CYGHWR_HAL_KINETIS_MCG_C1_IREFS_S       2
+#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_M       0x38
+#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_S       3
+#define CYGHWR_HAL_KINETIS_MCG_C1_FRDIV(_div_)  \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C1_FRDIV_S, _div_)
+#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M        0xC0
+#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS_S        6
+#define CYGHWR_HAL_KINETIS_MCG_C1_CLKS(_clks_)  \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_S, _clks_)
+enum {
+    CYGHWR_HAL_KINETIS_MCG_C1_CLKS_FLL_PLL,
+    CYGHWR_HAL_KINETIS_MCG_C1_CLKS_INT_REF,
+    CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF,
+    CYGHWR_HAL_KINETIS_MCG_C1_CLKS_RESERVED
+};
+// C2 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C2_IRCS_M        0x01
+#define CYGHWR_HAL_KINETIS_MCG_C2_IRCS_S        0
+#define CYGHWR_HAL_KINETIS_MCG_C2_LP_M          0x02
+#define CYGHWR_HAL_KINETIS_MCG_C2_LP_S          1
+#define CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M       0x04
+#define CYGHWR_HAL_KINETIS_MCG_C2_EREFS_S       2
+#define CYGHWR_HAL_KINETIS_MCG_C2_HGO_M         0x08
+#define CYGHWR_HAL_KINETIS_MCG_C2_HGO_S         3
+#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_M       0x30
+#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S       4
+#define CYGHWR_HAL_KINETIS_MCG_C2_RANGE(__v)    \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S, __v)
+
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+#define CYGHWR_HAL_KINETIS_MCG_C2_LOCRE0_M      0x80
+#define CYGHWR_HAL_KINETIS_MCG_C2_LOCRE0_S      7
+#endif
+// C3 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_M      0xFF
+#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S      0
+#define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM(__v)   \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S, __v)
+// C4 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C4_SCFTRIM_M     0x01
+#define CYGHWR_HAL_KINETIS_MCG_C4_SCFTRIM_S     0
+#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_M      0x1E
+#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_S      1
+#define CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM(__v)   \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C4_FCTRIM_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_M    0x60
+#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_S    5
+#define CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS(__v) \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C4_DMX32_M       0x80
+#define CYGHWR_HAL_KINETIS_MCG_C4_DMX32_S       7
+// C5 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M       0x1F
+#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_S       0
+#define CYGHWR_HAL_KINETIS_MCG_C5_PRDIV(__v)    \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M     0x20
+#define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_S     5
+#define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M    0x40
+#define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_S    6
+#if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1
+# define CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_M  0x80
+# define CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_S  7
+#endif
+// C6 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M        0x1F
+#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S        0
+#define CYGHWR_HAL_KINETIS_MCG_C6_VDIV(__v)     \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C6_CME_M         0x20
+#define CYGHWR_HAL_KINETIS_MCG_C6_CME_S         5
+#define CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M        0x40
+#define CYGHWR_HAL_KINETIS_MCG_C6_PLLS_S        6
+#define CYGHWR_HAL_KINETIS_MCG_C6_LOLIE_M       0x80
+#define CYGHWR_HAL_KINETIS_MCG_C6_LOLIE_S       7
+// S Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_S_IRCST_M        0x01
+#define CYGHWR_HAL_KINETIS_MCG_S_IRCST_S        0
+#define CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M      0x02
+#define CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_S      1
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_M        0x0C
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_S        2
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST(__v)     \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_S_CLKST_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL  CYGHWR_HAL_KINETIS_MCG_S_CLKST(0)
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_INT  CYGHWR_HAL_KINETIS_MCG_S_CLKST(1)
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT  CYGHWR_HAL_KINETIS_MCG_S_CLKST(2)
+#define CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL  CYGHWR_HAL_KINETIS_MCG_S_CLKST(3)
+#define CYGHWR_HAL_KINETIS_MCG_S_IREFST_M       0x10
+#define CYGHWR_HAL_KINETIS_MCG_S_IREFST_S       4
+#define CYGHWR_HAL_KINETIS_MCG_S_PLLST_M        0x20
+#define CYGHWR_HAL_KINETIS_MCG_S_PLLST_S        5
+#define CYGHWR_HAL_KINETIS_MCG_S_LOCK_M         0x40
+#define CYGHWR_HAL_KINETIS_MCG_S_LOCK_S         6
+#define CYGHWR_HAL_KINETIS_MCG_S_LOLS_M         0x80
+#define CYGHWR_HAL_KINETIS_MCG_S_LOLS_S         7
+
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1
+// ATC Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_M       0x20
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_S       5
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_M       0x40
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_S       6
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_M       0x80
+#define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_S       7
+#elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+// SC Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_SC_LOCS0_M       0x01
+#define CYGHWR_HAL_KINETIS_MCG_SC_LOCS0_S       0
+#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_M      0x0E
+#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_S      1
+#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV(__v) \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_SC_FLTPRSRV_M    0x10
+#define CYGHWR_HAL_KINETIS_MCG_SC_FLTPRSRV_S    4
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATMF_M        0x20
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATMF_S        5
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATMS_M        0x40
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATMS_S        6
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATME_M        0x80
+#define CYGHWR_HAL_KINETIS_MCG_SC_ATME_S        7
+#endif //  CYGHWR_HAL_CORTEXM_KINETIS_REV
+// ATCVH Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_M    0xFF
+#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S    0
+#define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH(__v) \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S, __v)
+// ATCVL Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_M    0xFF
+#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S    0
+#define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL(__v) \
+VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S, __v)
+
+#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+// C7 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_M      0x1
+#define CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_S      0
+// C8 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOCS1_M       0x1
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOCS1_S       0
+#define CYGHWR_HAL_KINETIS_MCG_C8_CME1_M        0x20
+#define CYGHWR_HAL_KINETIS_MCG_C8_CME1_S        5
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOLRE_M       0x40
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOLRE_S       6
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOCRE1_M      0x80
+#define CYGHWR_HAL_KINETIS_MCG_C8_LOCRE1_S      7
+#endif // CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+
+#if CYGINT_HAL_CORTEXM_KINETIS_150
+
+// C10 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C10_EREFS1_M      0x04
+#define CYGHWR_HAL_KINETIS_MCG_C10_EREFS1_S      2
+#define CYGHWR_HAL_KINETIS_MCG_C10_HGO1_M        0x08
+#define CYGHWR_HAL_KINETIS_MCG_C10_HGO1_S        3
+#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_M      0x30
+#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_S      4
+#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1(__v)    \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C10_LOCRE0_M      0x80
+#define CYGHWR_HAL_KINETIS_MCG_C10_LOCRE0_S      7
+// C11 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_M       0x7
+#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_S       0
+#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1(__v)    \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M        0x10
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_S        4
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_M     0x20
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_S     5
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_M    0x40
+#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_S    6
+# define CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_M  0x80
+# define CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_S  7
+// C12 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_M        0x1F
+#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_S        0
+#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1(__v)     \
+        VALUE_(CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_S, __v)
+#define CYGHWR_HAL_KINETIS_MCG_C12_CME2_M         0x20
+#define CYGHWR_HAL_KINETIS_MCG_C12_CME2_S         5
+#define CYGHWR_HAL_KINETIS_MCG_C12_LOLIE1_M       0x80
+#define CYGHWR_HAL_KINETIS_MCG_C12_LOLIE1_S       7
+// S2 Bit Fields
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOCS2_M        0x01
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOCS2_S        0
+#define CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_M     0x02
+#define CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_S     1
+#define CYGHWR_HAL_KINETIS_MCG_S2_PLLCST_M       0x10
+#define CYGHWR_HAL_KINETIS_MCG_S2_PLLCST_S       4
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M        0x40
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_S        6
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOLS1_M        0x80
+#define CYGHWR_HAL_KINETIS_MCG_S2_LOLS1_S        7
+
+#endif //CYGINT_HAL_CORTEXM_KINETIS_150
+
+
+//---------------------------------------------------------------------------
+// Real Time Clock
+
+typedef volatile struct cyghwr_hal_kinetis_rtc_s {
+    cyg_uint32 tsr;                    // Time Seconds Register
+    cyg_uint32 tpr;                    // Time Prescaler Register
+    cyg_uint32 tar;                    // Time Alarm Register
+    cyg_uint32 tcr;                    // Time Compensation Register
+    cyg_uint32 cr;                     // Control Register
+    cyg_uint32 sr;                     // Status Register
+    cyg_uint32 lr;                     // Lock Register
+    cyg_uint32 ier;                    // Enterrupt Enable Register
+    cyg_uint32 ttsr;                   // Tamper Times Seconds Register
+    cyg_uint32 mer;                    // Monotonic Enable Register
+    cyg_uint32 mclr;                   // Monotonic Counter Low Register
+    cyg_uint32 mchr;                   // Monotonic Counter High Register
+    cyg_uint32 ter;                    // Tamper Enable Register
+    cyg_uint32 tdr;                    // Tamper Detect Register
+    cyg_uint32 ttr;                    // Tamper Trim Register
+    cyg_uint32 tir;                    // Tamper Interrupt Register
+    cyg_uint8 reserved[1984];
+    cyg_uint32 war;                    // Write Access Register
+    cyg_uint32 rar;                    // Read Access Register
+} cyghwr_hal_kinetis_rtc_t;
+
+#define CYGHWR_HAL_KINETIS_RTC_P   ((cyghwr_hal_kinetis_rtc_t *)0x4003D000)
+
+#define CYGHWR_HAL_KINETIS_RTC_TCR_TCR_M (0x000000FF)
+#define CYGHWR_HAL_KINETIS_RTC_TCR_CIR_S 8
+#define CYGHWR_HAL_KINETIS_RTC_TCR_CIR(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_RTC_TCR_CIR_S, _div_)
+#define CYGHWR_HAL_KINETIS_RTC_TCR_CIC_S 16
+#define CYGHWR_HAL_KINETIS_RTC_TCR_TCV_S 24
+
+#define CYGHWR_HAL_KINETIS_RTC_CR_SWR  BIT_(0)
+#define CYGHWR_HAL_KINETIS_RTC_CR_WPE  BIT_(1)
+#define CYGHWR_HAL_KINETIS_RTC_CR_SUP  BIT_(2)
+#define CYGHWR_HAL_KINETIS_RTC_CR_UM   BIT_(3)
+#define CYGHWR_HAL_KINETIS_RTC_CR_OSCE BIT_(8)
+#define CYGHWR_HAL_KINETIS_RTC_CR_CLKO BIT_(9)
+#define CYGHWR_HAL_KINETIS_RTC_CR_SCP \
+        VALUE_(10, (CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP/2))
+
+#define CYGHWR_HAL_KINETIS_RTC_SR_TCE BIT_(4)
+#define CYGHWR_HAL_KINETIS_RTC_SR_TAF BIT_(2)
+#define CYGHWR_HAL_KINETIS_RTC_SR_TOF BIT_(1)
+#define CYGHWR_HAL_KINETIS_RTC_SR_TIF BIT_(0)
+
+//---------------------------------------------------------------------------
+// Watch dog
+
+// WDOG - Peripheral register structure
+typedef volatile struct CygHwr_HAL_Kinetis_wdog_s {
+    cyg_uint16 StCtrlH;    // Status and Control Register High
+    cyg_uint16 StCtrlL;    // Status and Control Register Low
+    cyg_uint16 ToValH;     // Time-out Value Register High
+    cyg_uint16 ToValL;     // Time-out Value Register Low
+    cyg_uint16 WinH;       // Window Register High
+    cyg_uint16 WinL;       // Window Register Low
+    cyg_uint16 Refresh;    // Refresh Register
+    cyg_uint16 Unlock;     // Unlock Register
+    cyg_uint16 TmrOutH;    // Timer Output Register High
+    cyg_uint16 TmrOutL;    // Timer Output Register Low
+    cyg_uint16 RstCnt;     // Reset Count Register
+    cyg_uint16 Presc;      // Prescaler Register
+} CygHwr_HAL_Kinetis_wdog_t;
+
+#define CYGHWR_HAL_KINETIS_WDOG_P ((CygHwr_HAL_Kinetis_wdog_t *)0x40052000)
+
+// STCTRLH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WDOGEN_M          0x0001
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WDOGEN_S          0
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_CLKSRC_M          0x0002
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_CLKSRC_S          1
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_IRQRSTEN_M        0x0004
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_IRQRSTEN_S        2
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WINEN_M           0x0008
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WINEN_S           3
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_M     0x0010
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_S     4
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DBGEN_M           0x0020
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DBGEN_S           5
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STOPEN_M          0x0040
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STOPEN_S          6
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WAITEN_M          0x0080
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_WAITEN_S          7
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STNDBYEN_M        0x0100
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_STNDBYEN_S        8
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTWDOG_M        0x0400
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTWDOG_S        10
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTSEL_M         0x0800
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_TESTSEL_S         11
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_M         0x3000
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_S         12
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL(__v)      \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_STCTRLH_BYTESEL_S, __v)
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DISTESTWDOG_M     0x4000
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLH_DISTESTWDOG_S     14
+// STCTRLL Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLL_INTFLG_M          0x8000
+#define CYGHWR_HAL_KINETIS_WDOG_STCTRLL_INTFLG_S          15
+// TOVALH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_M        0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_S        0
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH(__v)     \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_TOVALH_TOVALHIGH_S, __v)
+// TOVALL Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_M         0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_S         0
+#define CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW(__v)      \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_TOVALL_TOVALLOW_S, __v)
+// WINH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_M            0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_S            0
+#define CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH(__v)         \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_WINH_WINHIGH_S, __v)
+// WINL Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_M             0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_S             0
+#define CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW(__v)          \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_WINL_WINLOW_S, __v)
+// REFRESH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_M     0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_S     0
+#define CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH(__v)  \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_REFRESH_WDOGREFRESH_S, __v)
+// UNLOCK Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_M       0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_S       0
+#define CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK(__v)    \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_UNLOCK_WDOGUNLOCK_S, __v)
+// TMROUTH Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_M    0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_S    0
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH(__v) \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_TMROUTH_TIMEROUTHIGH_S, __v)
+// TMROUTL Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_M     0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_S     0
+#define CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW(__v)  \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_TMROUTL_TIMEROUTLOW_S, __v)
+// RSTCNT Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_M           0xFFFF
+#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_S           0
+#define CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT(__v)        \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_RSTCNT_RSTCNT_S, __v)
+// PRESC Bit Fields
+#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_M          0x700
+#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_S          8
+#define CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL(__v)       \
+        VALUE(CYGHWR_HAL_KINETIS_WDOG_PRESC_PRESCVAL_S, __v)
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_wdog_unlock(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p);
+__externC void hal_wdog_disable(void);
+
+#endif // __ASSEMBLER__
+
+//---------------------------------------------------------------------------
+// SIM - System Integration Module
+
+// SIM - Peripheral register structure
+typedef volatile struct cyghwr_hal_kinetis_sim_s {
+    cyg_uint32 sopt1;           // System Options Register 1
+    cyg_uint8  reserved_0[4096];
+    cyg_uint32 sopt2;           // System Options Register 2
+    cyg_uint8  reserved_1[4];
+    cyg_uint32 sopt4;           // System Options Register 4
+    cyg_uint32 sopt5;           // System Options Register 5
+    cyg_uint32 sopt6;           // System Options Register 6
+    cyg_uint32 sopt7;           // System Options Register 7
+    cyg_uint8  Reserved_2[8];
+    cyg_uint32 sdid;            // System Device Identification Register
+    cyg_uint32 scgc1;           // System Clock Gating Control Register 1
+    cyg_uint32 scgc2;           // System Clock Gating Control Register 2
+    cyg_uint32 scgc3;           // System Clock Gating Control Register 3
+    cyg_uint32 scgc4;           // System Clock Gating Control Register 4
+    cyg_uint32 scgc5;           // System Clock Gating Control Register 5
+    cyg_uint32 scgc6;           // System Clock Gating Control Register 6
+    cyg_uint32 scgc7;           // System Clock Gating Control Register 7
+    cyg_uint32 clk_div1;        // System Clock Divider Register 1
+    cyg_uint32 clk_div2;        // System Clock Divider Register 2
+    cyg_uint32 fcfg1;           // Flash Configuration Register 1
+    cyg_uint32 fcfg2;           // Flash Configuration Register 2
+    cyg_uint32 uidh;            // Unique Identification Register High
+    cyg_uint32 uidmh;           // Unique Identification Register Mid-High
+    cyg_uint32 uidml;           // Unique Identification Register Mid Low
+    cyg_uint32 uidl;            // Unique Identification Register Low
+
+    cyg_uint32 clkdiv3;         // System Clock Divider Register 3
+    cyg_uint32 clkdiv4;         // System Clock Divider Register 4
+    cyg_uint32 mcr;             // Misc control register
+} cyghwr_hal_kinetis_sim_t;
+
+#define CYGHWR_HAL_KINETIS_SIM_P ((cyghwr_hal_kinetis_sim_t *) 0x40047000)
+
+// SOPT1 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_M         0xF000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_S         12
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE(__val)    \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT1_RAMSIZE_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_OSC32KSEL_M       0x80000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_OSC32KSEL_S       19
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_MS_M              0x800000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_MS_S              23
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBSTBY_M         0x40000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBSTBY_S         30
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBREGEN_M        0x80000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT1_USBREGEN_S        31
+// SOPT2 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M       0x1
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_S       0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_M            0x300
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_S            8
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL(__val)       \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_FBSL_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_CMTUARTPAD_M      0x800
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_CMTUARTPAD_S      11
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M     0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_S     12
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M       0x10000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_S       16
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_USBSRC_M          0x40000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_USBSRC_S          18
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_M         0x300000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_S         20
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC(__val)    \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_TIMESRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_M          0x3000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_S          24
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC(__val)     \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_I2SSRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_M         0x30000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_S         28
+#define CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC(__val)    \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT2_SDHCSRC_S, __val)
+// SOPT4 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT0_M        0x1
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT0_S        0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT1_M        0x2
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT1_S        1
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT2_M        0x4
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0FLT2_S        2
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1FLT0_M        0x10
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1FLT0_S        4
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2FLT0_M        0x100
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2FLT0_S        8
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_M      0xC0000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_S      18
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CH0SRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_M      0x300000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_S      20
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CH0SRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0CLKSEL_M      0x1000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM0CLKSEL_S      24
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CLKSEL_M      0x2000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM1CLKSEL_S      25
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CLKSEL_M      0x4000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT4_FTM2CLKSEL_S      26
+// SOPT5 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_M      0x3
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_S      0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0TXSRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_M      0xC
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_S      2
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART0RXSRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_M       0x30
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_S       4
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UARTTXSRC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_M      0xC0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_S      6
+#define CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT5_UART1RXSRC_S, __val)
+// SOPT6 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_M       0x1F000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_S       24
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTSEL_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_M        0xE0000000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_S        29
+#define CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT6_RSTFLTEN_S, __val)
+// SOPT7 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_M      0xF
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_S      0
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0TRGSEL_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0PRETRGSEL_M   0x10
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0PRETRGSEL_S   4
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0ALTTRGEN_M    0x80
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC0ALTTRGEN_S    7
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_M      0xF00
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_S      8
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1TRGSEL_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1PRETRGSEL_M   0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1PRETRGSEL_S   12
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1ALTTRGEN_M    0x8000
+#define CYGHWR_HAL_KINETIS_SIM_SOPT7_ADC1ALTTRGEN_S    15
+// SDID Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID_M            0xF
+#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SDID_PINID(__val)       \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_PINID_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_M            0x70
+#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_S            4
+#define CYGHWR_HAL_KINETIS_SIM_SDID_FAMID(__val)       \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_FAMID_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_M            0xF000
+#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S            12
+#define CYGHWR_HAL_KINETIS_SIM_SDID_REVID(__val)       \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S, __val)
+
+//---------------------------------------------------------------------------
+// Clock distribution
+// The following encodes the control register and clock bit number
+// into clock configuration descriptor (CLKCD).
+#define CYGHWR_HAL_KINETIS_SIM_SCGC(__reg,__bit) ((((__reg) - 1 ) & 0xF) + \
+                                                  (((__bit) << 8) & 0x1F00))
+
+// Macros to extract encoded values.
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_REG(__clkcd) (((__clkcd) & 0xF))
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(__clkcd) (((__clkcd) >> 8) & 0x1F)
+
+// Functions and macros to enable/disable clocks.
+#define CYGHWR_HAL_SCGC_NONE (0xFFFFFFFF)
+__externC void hal_clock_enable(cyg_uint32 clkcd);
+__externC void hal_clock_disable(cyg_uint32 clkcd);
+
+#define CYGHWR_HAL_CLOCK_ENABLE(__clkcd) hal_clock_enable(__clkcd)
+#define CYGHWR_HAL_CLOCK_DISABLE(__clkcd) hal_clock_disable(__clkcd)
+
+#include <cyg/hal/var_io_clkgat.h>
+
+// CLKDIV1 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_M       0xF0000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_S       16
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_M       0xF00000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_S       20
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_M       0xF000000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_S       24
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_M       0xF0000000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_S       28
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1_S, __val)
+// CLKDIV2 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M       0x1
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_S       0
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_M        0xE
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_S        1
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_M       0xFF00
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_S       8
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SFRAC_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_M        0xFFF00000
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_S        20
+#define CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_CLKDIV2_I2SDIV_S, __val)
+// FCFG1 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_M          0xF00
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_S          8
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART(__val)     \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_DEPART_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_M          0xF0000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_S          16
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE(__val)     \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_EESIZE_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_M           0xFF000000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_S           24
+#define CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE(__val)      \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG1_FSIZE_S, __val)
+// FCFG2 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_M        0x3F0000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_S        16
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR1_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_PFLSH_M           0x800000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_PFLSH_S           23
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_M        0x3F000000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_S        24
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_FCFG2_MAXADDR0_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_SWAPPFLSH_M       0x80000000
+#define CYGHWR_HAL_KINETIS_SIM_FCFG2_SWAPPFLSH_S       31
+// UIDH Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID_M              0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID_S              0
+#define CYGHWR_HAL_KINETIS_SIM_UIDH_UID(__val)         \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDH_UID_S, __val)
+// UIDMH Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_M             0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_S             0
+#define CYGHWR_HAL_KINETIS_SIM_UIDMH_UID(__val)        \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDMH_UID_S, __val)
+// UIDML Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID_M             0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID_S             0
+#define CYGHWR_HAL_KINETIS_SIM_UIDML_UID(__val)        \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDML_UID_S, __val)
+// UIDL Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_M              0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S              0
+#define CYGHWR_HAL_KINETIS_SIM_UIDL_UID(__val)         \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S, __val)
+// MCR Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_M           0xE000
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_S           5
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG(__val)      \
+        VALUE_(CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_S, __val)
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_M        0x8
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_S        3
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_M           0x4
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_S           2
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_M             0x2
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_S             1
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M          0x1
+#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_S          0
+
+
+
+//--------------------------------------------------------------------------
+// AXBS - Crossbar switch
+
+#define CYGHWR_HAL_KINETIS_AXBS_SLAVES_K    7
+#define CYGHWR_HAL_KINETIS_AXBS_MASTERS_K   8
+
+typedef volatile struct cyghwr_hal_kinetis_axbs_s {
+    volatile struct cyghwr_hal_kinetis_axbs_slave_s {
+        cyg_uint32 prs;
+        cyg_uint32 res0[3];
+        cyg_uint32 crs;
+        cyg_uint32 res1[59];
+    } slave[8];
+    volatile struct cyghwr_hal_kinetis_axbs_master_s {
+        cyg_uint32 res0[64];
+        cyg_uint32 mgprc;
+    } master[8];
+} cyghwr_hal_kinetis_axbs_t;
+
+#define CYGHWR_HAL_KINETIS_AXBS_P ((cyghwr_hal_kinetis_axbs_t *) 0x40004000)
+
+// PRS Fields
+#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_) ((_master_) * 4)
+#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(_master_) \
+            (0x7 << CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_))
+
+#define CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(_master_,_prs)           \
+            (((_prs) & CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(_master_)) >>  \
+             CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(_master_))
+// CRS Fields
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_PARK_M     0x7
+
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_M     0x30
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_S     4
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL(_x_)  (((_x_) << CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_S) & \
+                                                         CYGHWR_HAL_KINETIS_AXBS_CRS_PCTL_M)
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M      0x300
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_S      8
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_ARB(_x_)   (((_x_) << CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_S) & \
+                                                        CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M)
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_HLP_M      0x40000000
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_RO_M       0x80000000
+
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB(_slave_i,_arb)          \
+CYG_MACRO_START                                                     \
+    cyg_uint32 regval;                                              \
+    cyghwr_hal_kinetis_axbs_t* _axbs_p = CYGHWR_HAL_KINETIS_AXBS_P; \
+    regval = _axbs_p->slave[_slave_i].crs;                          \
+    regval &= ~CYGHWR_HAL_KINETIS_AXBS_CRS_ARB_M;                   \
+    regval |= CYGHWR_HAL_KINETIS_AXBS_CRS_ARB(_arb);                \
+    _axbs_p->slave[_slave_i].crs = regval;                          \
+CYG_MACRO_END
+
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB_RR(_slave_i)    \
+            CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB((_slave_i), 1)
+
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB_FIX(_slave_i)   \
+            CYGHWR_HAL_KINETIS_AXBS_CRS_SET_ARB((_slave_i), 0)
+
+// MGPCR Bit Fields
+#define CYGHWR_HAL_KINETIS_AXBS_CRS_AXBS_MGPCR_AULB_M  0x7
+
+//---------------------------------------------------------------------------
+// PORT - Peripheral register structure
+
+typedef volatile struct cyghwr_hal_kinetis_port_s {
+    cyg_uint32 pcr[32];      // Pin Control Register n, array
+    cyg_uint32 gpclr;        // Global Pin Control Low Register
+    cyg_uint32 gpchr;        // Global Pin Control High Register
+    cyg_uint8 reserved0[24];
+    cyg_uint32 isfr;         // Interrupt Status Flag Register
+    cyg_uint8 reserved1[28];
+    cyg_uint32 dfer;         // Digital Filter Enable Register
+    cyg_uint32 dfcr;         // Digital Filter Clock Register
+    cyg_uint32 dfwr;         // Digital Filter Width Register
+} cyghwr_hal_kinetis_port_t;
+
+// PORT - Peripheral instance base addresses
+#define CYGHWR_HAL_KINETIS_PORTA_P  ((cyghwr_hal_kinetis_port_t *)0x40049000)
+#define CYGHWR_HAL_KINETIS_PORTB_P  ((cyghwr_hal_kinetis_port_t *)0x4004A000)
+#define CYGHWR_HAL_KINETIS_PORTC_P  ((cyghwr_hal_kinetis_port_t *)0x4004B000)
+#define CYGHWR_HAL_KINETIS_PORTD_P  ((cyghwr_hal_kinetis_port_t *)0x4004C000)
+#define CYGHWR_HAL_KINETIS_PORTE_P  ((cyghwr_hal_kinetis_port_t *)0x4004D000)
+#define CYGHWR_HAL_KINETIS_PORTF_P  ((cyghwr_hal_kinetis_port_t *)0x4004E000)
+
+enum {
+    CYGHWR_HAL_KINETIS_PORTA, CYGHWR_HAL_KINETIS_PORTB,
+    CYGHWR_HAL_KINETIS_PORTC, CYGHWR_HAL_KINETIS_PORTD,
+    CYGHWR_HAL_KINETIS_PORTE, CYGHWR_HAL_KINETIS_PORTF
+};
+
+#define CYGHWR_HAL_KINETIS_PORT(__port, __reg) \
+        (CYGHWR_HAL_KINETIS_PORT##__port##_P)->__reg
+
+// PCR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PS_M          0x1
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PS_S          0
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PE_M          0x2
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PE_S          1
+#define CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M         0x4
+#define CYGHWR_HAL_KINETIS_PORT_PCR_SRE_S         2
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PFE_M         0x10
+#define CYGHWR_HAL_KINETIS_PORT_PCR_PFE_S         4
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ODE_M         0x20
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ODE_S         5
+#define CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M         0x40
+#define CYGHWR_HAL_KINETIS_PORT_PCR_DSE_S         6
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_M         0x700
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_S         8
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__val)    \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_PCR_MUX_S, __val)
+#define CYGHWR_HAL_KINETIS_PORT_PCR_LK_M          0x8000
+#define CYGHWR_HAL_KINETIS_PORT_PCR_LK_S          15
+#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_M        0xF0000
+#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_S        16
+#define CYGHWR_HAL_KINETIS_PORT_PCR_IRQC(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_PCR_IRQC_S, __val)
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ISF_M         0x1000000
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ISF_S         24
+
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_ANALOG    0
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_DIS       0
+#define CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO      1
+
+#define CYGHWR_HAL_KINETIS_PORT_PCR_ISFR_CLEAR(__port, __pin) \
+        CYGHWR_HAL_KINETIS_PORT(__port, pcr[__pin]) |= BIT_(24)
+
+#define CYGHWR_HAL_KINETIS_PORT_ISFR_CLEAR(__port, __pin)     \
+        CYGHWR_HAL_KINETIS_PORT(__port, isfr) |= BIT_(__pin)
+
+#define CYGHWR_HAL_KINETIS_PIN_CFG(__port, __bit, __mux, __irqc, __cnf) \
+        ((CYGHWR_HAL_KINETIS_PORT##__port << 20) | ((__bit) << 27)      \
+         | CYGHWR_HAL_KINETIS_PORT_PCR_IRQC(__irqc)                     \
+         | CYGHWR_HAL_KINETIS_PORT_PCR_MUX(__mux) | (__cnf))
+
+#define CYGHWR_HAL_KINETIS_PIN(__port, __bit, __mux, __cnf) \
+        CYGHWR_HAL_KINETIS_PIN_CFG(__port, __bit, __mux, 0, __cnf)
+
+#define CYGHWR_HAL_KINETIS_PIN_PORT(__pin) (((__pin) >> 20) & 0x7)
+#define CYGHWR_HAL_KINETIS_PIN_BIT(__pin)  (((__pin) >> 27 ) & 0x1f)
+#define CYGHWR_HAL_KINETIS_PIN_FUNC(__pin) ((__pin) & 0x010f8777)
+#define CYGHWR_HAL_KINETIS_PIN_NONE (0xffffffff)
+
+// GPCLR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_M      0xFFFF
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_S      0
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWD_S, __val)
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_M      0xFFFF0000
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_S      16
+#define CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCLR_GPWE_S, __val)
+// GPCHR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_M      0xFFFF
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_S      0
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWD_S, __val)
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_M      0xFFFF0000
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_S      16
+#define CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE(__val) \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_GPCHR_GPWE_S, __val)
+// ISFR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_M        0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_S        0
+#define CYGHWR_HAL_KINETIS_PORT_ISFR_ISF(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_ISFR_ISF_S, __val)
+// DFER Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE_M        0xFFFFFFFF
+#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE_S        0
+#define CYGHWR_HAL_KINETIS_PORT_DFER_DFE(__val)   \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_DFER_DFE_S, __val)
+// DFCR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_DFCR_CS_M         0x1
+#define CYGHWR_HAL_KINETIS_PORT_DFCR_CS_S         0
+// DFWR Bit Fields
+#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_M       0x1F
+#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_S       0
+#define CYGHWR_HAL_KINETIS_PORT_DFWR_FILT(__val)  \
+        VALUE_(CYGHWR_HAL_KINETIS_PORT_DFWR_FILT_S, __val)
+
+#ifndef __ASSEMBLER__
+
+// Pin configuration related functions
+__externC void  hal_set_pin_function(cyg_uint32 pin);
+__externC void  hal_dump_pin_function(cyg_uint32 pin);
+__externC void  hal_dump_pin_setting(cyg_uint32 pin);
+
+#endif
+
+#define HAL_SET_PINS(_pin_array) \
+CYG_MACRO_START \
+    const cyg_uint32 *_pin_p; \
+    for(_pin_p = &_pin_array[0]; \
+        _pin_p < &_pin_array[0] + sizeof(_pin_array)/sizeof(_pin_array[0]); \
+        hal_set_pin_function(*_pin_p++)); \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+// PMC Power Management Controller
+
+typedef volatile struct cyghwr_hal_kinetis_pmc_s {
+    cyg_uint8 lvdsc1;   // Low Voltage Detect Status and Control 1 Register
+    cyg_uint8 lvdsc2;   // Low Voltage Detect Status and Control 2 Register
+    cyg_uint8 regsc;    // Regulator Status and Control Register
+} cyghwr_hal_kinetis_pmc_t;
+
+// PMC base address
+#define CYGHWR_HAL_KINETIS_PMC_P  ((cyghwr_hal_kinetis_pmc_t *)0x4007D000)
+
+// LVDSC1 Bit Fields
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M      0x3
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV(__val) \
+        ((__val) & CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M)
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_M     0x10
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_S     4
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_M     0x20
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_S     5
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDACK_M    0x40
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDACK_S    6
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDF_M      0x80
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDF_S      7
+// LVDSC2 Bit Fields
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M      0x3
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV(__val) \
+        ((__val) & CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M)
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_M     0x20
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_S     5
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_M    0x40
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_S    6
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWF_M      0x80
+#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWF_S      7
+// REGSC Bit Fields
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGBE_M       0x1
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGBE_S       0
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_REGONS_M     0x4
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_REGONS_S     2
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M     0x8
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_S     3
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGEN_M       0x10
+#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGEN_S       4
+
+//---------------------------------------------------------------------------
+// FMC Flash Memory Controller
+
+#define CYGHWR_HAL_KINETIS_FMC_BASE     (0x4001F000)
+#define CYGHWR_HAL_KINETIS_FMC_PFAPR    (CYGHWR_HAL_KINETIS_FMC_BASE)
+#define CYGHWR_HAL_KINETIS_FMC_PFB0CR   (CYGHWR_HAL_KINETIS_FMC_BASE + 4)
+#define CYGHWR_HAL_KINETIS_FMC_PFB1CR   (CYGHWR_HAL_KINETIS_FMC_BASE + 8)
+
+enum {
+    CYGHWR_HAL_KINETIS_FMC_CACHE_W0,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_W1,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_W2,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_W3,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_WAYS
+};
+
+enum {
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S0,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S1,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S2,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S3,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S4,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S5,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S6,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_S7,
+    CYGHWR_HAL_KINETIS_FMC_CACHE_SIDES
+};
+
+#define CYGHWR_HAL_KINETIS_FMC_TAG(__way,__side) \
+          (CYGHWR_HAL_KINETIS_FMC_BASE + 0x100 + (__way)*0x20 + (__side)*4)
+#define CYGHWR_HAL_KINETIS_FMC_DATA_U(__way,side) \
+          (CYGHWR_HAL_KINETIS_FMC_BASE + 0x200 + (__way)*0x20 + (__side)*8)
+#define CYGHWR_HAL_KINETIS_FMC_DATA_L(__way,side) \
+          (CYGHWR_HAL_KINETIS_FMC_BASE + 0x204 + (__way)*0x40 + (__side)*8)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MPFD_M(__master) (1 << ((__master) + 16))
+enum {
+    CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_NO_ACCESS,
+    CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RO,
+    CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_WO,
+    CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP_RW
+};
+#define CYGHWR_HAL_KINETIS_FMC_PFAPR_MAP(__master, __access) \
+          ((__access) <<(2 * (__master)))
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_RWSC_M (0xf0000000)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(__way) ((1 << (__way)) << 24)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_ALL \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CLCK_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(__way) ((1 << (__way)) << 20)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_ALL \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W0) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W1) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W2) | \
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CINV_WAY(CYGHWR_HAL_KINETIS_FMC_CACHE_W3)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_SBINV (1 << 19)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BMW   (7 << 17)
+
+enum{
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_LRU,
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_res0,
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW01IF23D,
+    CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC_IND_LRUW02ID3D
+};
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_CRC   (__cache_repl_con) \
+                                       ((__cache_repl_con) << 5)
+
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDCE  (0x10)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BICE  (0x08)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BDPE  (0x04)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BIPE  (0x02)
+#define CYGHWR_HAL_KINETIS_FMC_PFBCR_BSEBE (0x01)
+
+//---------------------------------------------------------------------------
+// MPU Memory Protection unit
+
+typedef volatile struct cyghwr_hal_kinetis_mpu_s {
+    cyg_uint32 cesr;          // Control/Error Status Register
+    cyg_uint8 reserved0[12];
+    struct {
+        cyg_uint32 ear;       // Error Address Register, Slave Port n
+        cyg_uint32 edr;       // Error Detail Register, Slave Port n
+    } slave_port[5];
+    cyg_uint8 reserved1[968];
+    struct {  // Region Descriptors, Word 0..Region Descriptor n, Word 3
+        cyg_uint32 word[4];
+    }reg_desc[12];
+    cyg_uint8 reserved2[832];
+    cyg_uint32 reg_daac[12];  // Region Descriptor Alternate Access Control n
+} cyghwr_hal_kinetis_mpu_t;
+
+#define CYGHWR_HAL_KINETIS_MPU_P  (cyghwr_hal_kinetis_mpu_t *)0x4000d000
+
+//---------------------------------------------------------------------------
+// FlexBus
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS
+# include <cyg/hal/var_io_flexbus.h>
+#endif
+
+//----------------------------------------------------------------------------
+// DDRMC - SDRAM controller
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+# include <cyg/hal/var_io_ddrmc.h>
+#endif
+
+//---------------------------------------------------------------------------
+// GPIO
+#include <cyg/hal/var_io_gpio.h>
+
+//=============================================================================
+// DEVS:
+// Following macros may also be, and usually are borrwed by some device drivers.
+//-----------------------------------------------------------------------------
+#include <cyg/hal/var_io_devs.h>
+
+// End Peripherals
+
+// Some miscelaneous function prototypes
+// Clock related functions are in kinetis_clocking.c
+__externC void hal_start_clocks(void);
+__externC void hal_update_clock_var(void);
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+
+#endif // CYGONCE_HAL_VAR_IO_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h
new file mode 100644
index 0000000..9374971
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_clkgat.h
@@ -0,0 +1,336 @@
+#ifndef CYGONCE_HAL_VAR_IOCLKGAT_H
+#define CYGONCE_HAL_VAR_IOCLKGAT_H
+//===========================================================================
+//
+//      var_io_clkgat.h
+//
+//      Kinetis clock gating
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2013-03-17
+// Purpose:       Kinetis clock distribution macros
+// Description:
+// Usage:         This file is included by <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//---------------------------------------------------------------------------
+// Clock distribution
+
+// SCGC1 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M            0x20
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S            5
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M           0x400
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S           10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M           0x800
+#define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S           11
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_OSC1  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART4 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART5 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(1, CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S)
+
+// SCGC2 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M            0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M            0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S            12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M            0x2000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S            13
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ENET \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC0 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DAC1 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(2, CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S)
+
+// SCGC3 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_M            0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M            0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M        0x10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S        4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_M             0x100
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S             8
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M            0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S            12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M             0x4000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S             14
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_M            0x8000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S            15
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M            0x20000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S            17
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_M            0x40000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S            22
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M            0x1000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S            24
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_M            0x2000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM3_S            25
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M            0x8000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S            27
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M            0x10000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S            28
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGA     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGA_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_RNGB     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN1 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_NFC      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_NFC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DDR      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI1     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SAI1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SDHC     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_LCDC     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_LCDC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM2     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC1     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC3     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(3, CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S)
+
+// SCGC4 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M             0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S             1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M             0x4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S             2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M            0x40
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S            6
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M            0x80
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S            7
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_M           0x400
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S           10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_M           0x800
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S           11
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M           0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S           12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M           0x2000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S           13
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M          0x40000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S          18
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M             0x80000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S             19
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M            0x100000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S            20
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M            0x10000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S            28
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_EWM    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMT    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART0  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART1  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART2  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_UART3  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBOTG \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_CMP    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_VREF   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_LLWU   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(4, CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S)
+
+// SCGC5 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M         0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S         0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_M         0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S         1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_M          0x4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S          2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_M        0x8
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S        3
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_M             0x20
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S             5
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M           0x200
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S           9
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M           0x400
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S           10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M           0x800
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S           11
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M           0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S           12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M           0x2000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S           13
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M           0x4000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S           14
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_LPTIMER   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_REGFILE   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_REGFILE_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICE    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICE_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DRYICESR  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_DRYICESR_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_TSI       \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_TSI_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTA     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTB     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTC     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTD     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTE     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PORTF     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(5, CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S)
+
+// SCGC6 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M            0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S            0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M          0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S          1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_M         0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S         1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_M         0x4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S         2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M        0x10
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S        4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_M            0x1000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S            12
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_M            0x2000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S            13
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_M             0x8000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S             15
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_M            0x8000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S            15
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_M             0x40000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S             18
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_M           0x100000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S           20
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_M          0x200000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S          21
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_M             0x400000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S             22
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_M             0x800000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S             23
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_M            0x1000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S            24
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M            0x2000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S            25
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M            0x8000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S            27
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_M            0x10000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_S            28
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M             0x20000000
+#define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S             29
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTFL     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1  \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXCAN0 \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SPI1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_I2S      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_I2S_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_SAI0     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_SAI0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_CRC      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_CRC_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBHS    \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBHS_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_USBDCD   \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_USBDCD_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PDB      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PDB_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_PIT      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_PIT_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM0     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FTM1     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC0     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_ADC2     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC2_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_RTC      \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(6, CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S)
+
+// SCGC7 Bit Fields
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M         0x1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S         0
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M             0x2
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S             1
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M             0x4
+#define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S             2
+
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_DMA     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_S)
+#define CYGHWR_HAL_KINETIS_SIM_SCGC_MPU     \
+        CYGHWR_HAL_KINETIS_SIM_SCGC(7, CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S)
+
+//-----------------------------------------------------------------------------
+// end of var_io_clkgat.h
+
+#endif // CYGONCE_HAL_VAR_IOCLKGAT_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h
new file mode 100644
index 0000000..8090a53
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h
@@ -0,0 +1,111 @@
+#ifndef CYGONCE_HAL_VAR_IO_DDRMC_H
+#define CYGONCE_HAL_VAR_IO_DDRMC_H
+//===========================================================================
+//
+//      var_io_ddrmc.h
+//
+//      Kinetis DDRam controller specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2012-03-08
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io_ddrmc.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+//----------------------------------------------------------------------------
+// DDRMC - SDRAM controller
+
+# define CYGNUM_HAL_KINETIS_DDRMC_CR_N 64  // Number of DDRMC control registers
+
+typedef volatile struct cyghwr_hal_kinetis_ddrmc_s {
+    cyg_uint32 cr[CYGNUM_HAL_KINETIS_DDRMC_CR_N]; // Control registers
+    cyg_uint32 reserved1[32];
+    cyg_uint32 rcr;                               // RCR control register
+    cyg_uint32 reserved2[10];
+    cyg_uint32 pad_ctrl;                          // I/O Pad control register
+} cyghwr_hal_kinetis_ddrmc_t;
+
+# define CYGHWR_HAL_KINETIS_DDRMC_P  ((cyghwr_hal_kinetis_ddrmc_t *)0x400ae000)
+
+// RCR
+# define CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M 0x40000000
+// PAD CTRL
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_M 0x03000000
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_S 20
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT(_x_)  \
+        VALUE_(CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_S, _x_)
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_DIS 0
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_50  3
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_75  1
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_150 2
+
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_M 0x0000000f
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_S 0
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY(_x_)  \
+        VALUE_(CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_S, _x_)
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_0BUF  0
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_4BUF  1
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_7BUF  2
+# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_10BUF 3
+
+# define CYGHWR_HAL_KINETIS_DDRMC_CR00_START 0x1
+# define CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL 0x400
+
+# define CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M 0x0000ffff
+
+# ifndef CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP
+#  define CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG(CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS)| \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_M * 0)                         | \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_M * 1)                            | \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_M * 0)                              | \
+          (CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M * 0 ))
+# endif
+
+__externC void hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 src[]);
+# define HAL_CORTEXM_KINETIS_DDRMC_INIT(__inidat) \
+        hal_cortexm_kinetis_ddrmc_init(__inidat)
+__externC void hal_cortexm_kinetis_ddrmc_diag(void);
+
+//-----------------------------------------------------------------------------
+// end of var_io_ddrmc.h
+#endif // CYGONCE_HAL_VAR_IO_DDRMC_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h
new file mode 100644
index 0000000..a9acaab
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h
@@ -0,0 +1,415 @@
+#ifndef CYGONCE_HAL_VAR_IO_DEVS_H
+#define CYGONCE_HAL_VAR_IO_DEVS_H
+//===========================================================================
+//
+//      var_io_devs.h
+//
+//      Variant specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-02-05
+// Purpose:       Kinetis variant IO provided to various device drivers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h> //var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//=============================================================================
+// DEVS:
+// Following macros may be, and usually are borrwed by some device drivers.
+
+// Peripheral clock [Hz];
+__externC cyg_uint32 hal_get_peripheral_clock(void);
+
+//-----------------------------------------------------------------------------
+// Freescale UART
+// Borrow some HAL resources to Freescale UART driver
+// UART  macros are used by both:
+//      src/hal_diag.c
+//      devs/serial/<version>/src/ser_freescale_uart.c
+
+#define CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE  0x4006A000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE  0x4006B000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE  0x4006C000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE  0x4006D000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE  0x400EA000
+#define CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE  0x400EB000
+
+// UART Clock gating
+
+#define CYGHWR_IO_FREESCALE_UART0_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART0
+#define CYGHWR_IO_FREESCALE_UART1_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART1
+#define CYGHWR_IO_FREESCALE_UART2_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART2
+#define CYGHWR_IO_FREESCALE_UART3_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART3
+#define CYGHWR_IO_FREESCALE_UART4_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART4
+#define CYGHWR_IO_FREESCALE_UART5_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_UART5
+
+// UART PIN configuration
+// Note: May be overriden by plf_io.h
+
+#define CYGHWR_HAL_KINETIS_PORT_PIN_NONE CYGHWR_HAL_KINETIS_PIN_NONE
+
+#ifndef CYGHWR_IO_FREESCALE_UART0_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART1_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART1_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART2_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART4_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART5_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE
+#endif
+
+// Lend some HAL dependent functions to the UART serial device driver
+
+#ifndef __ASSEMBLER__
+
+# define CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) \
+        hal_freescale_uart_setbaud(__uart_p, _baud_)
+
+# define CYGHWR_IO_FREESCALE_UART_PIN(__pin) \
+        hal_set_pin_function(__pin)
+
+
+// Set baud rate
+__externC void hal_freescale_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+#endif
+
+//---------------------------------------------------------------------------
+// ENET
+// Lend some HAL dependent functions to the Ethernet device driver
+#define CYGADDR_IO_ETH_FREESCALE_ENET0_BASE  (0x400C0000)
+// Clock gating
+#define CYGHWR_IO_FREESCALE_ENET0_CLOCK CYGHWR_HAL_KINETIS_SIM_SCGC_ENET
+
+#ifndef __ASSEMBLER__
+
+# define CYGHWR_IO_FREESCALE_ENET_PIN(__pin) \
+        hal_set_pin_function(__pin)
+
+#endif
+
+//----------------------------------------------------------------------------
+// DSPI
+// Lend some HAL dependent macros to DSPI device driver
+
+// DSPI - Peripheral instance base addresses
+#define CYGADDR_IO_SPI_FREESCALE_DSPI0_P ((cyghwr_devs_freescale_dspi_t*)0x4002C000)
+#define CYGADDR_IO_SPI_FREESCALE_DSPI1_P ((cyghwr_devs_freescale_dspi_t*)0x4002D000)
+#define CYGADDR_IO_SPI_FREESCALE_DSPI2_P ((cyghwr_devs_freescale_dspi_t*)0x400AC000)
+
+#define CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK hal_get_peripheral_clock();
+
+#define CYGHWR_IO_FREESCALE_DSPI0_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_SPI0
+#define CYGHWR_IO_FREESCALE_DSPI1_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_SPI1
+#define CYGHWR_IO_FREESCALE_DSPI2_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_SPI2
+
+# define CYGHWR_IO_FREESCALE_DSPI_PIN(__pin) hal_set_pin_function(__pin)
+
+#ifndef KINETIS_PIN_SPI0_OUT_OPT
+#define KINETIS_PIN_SPI0_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI0_CS_OPT
+#define KINETIS_PIN_SPI0_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI0_IN_OPT
+#define KINETIS_PIN_SPI0_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+
+#ifndef KINETIS_PIN_SPI1_OUT_OPT
+#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI1_CS_OPT
+#define KINETIS_PIN_SPI1_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI1_IN_OPT
+#define KINETIS_PIN_SPI1_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_OUT_OPT
+#define KINETIS_PIN_SPI2_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_CS_OPT
+#define KINETIS_PIN_SPI2_CS_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_SRE_M)
+#endif
+#ifndef KINETIS_PIN_SPI2_IN_OPT
+#define KINETIS_PIN_SPI2_IN_OPT  (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M |  \
+                                 CYGHWR_HAL_KINETIS_PORT_PCR_PS_M)
+#endif
+
+//---------------------------------------------------------------------------
+// I2C
+// Lend some HAL dependent macros to I2C device driver
+// Base pointers
+#define CYGADDR_IO_I2C_FREESCALE_I2C0_BASE  (0x40066000)
+#define CYGADDR_IO_I2C_FREESCALE_I2C1_BASE  (0x40067000)
+// Clocking
+#define CYGHWR_IO_I2C_FREESCALE_I2C_CLOCK hal_get_peripheral_clock()
+#define CYGHWR_IO_FREESCALE_I2C0_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_I2C0
+#define CYGHWR_IO_FREESCALE_I2C1_CLK  CYGHWR_HAL_KINETIS_SIM_SCGC_I2C1
+// Pins
+# define CYGHWR_IO_FREESCALE_I2C_PIN(__pin) hal_set_pin_function(__pin)
+
+# ifndef CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE
+// Fix an error in Kinetis I2C Manual. There is an unconfirmed
+// error in Kinetis I2C divider and hold value table.
+#if 0 // Values as are in Kinetis Reference Manuals
+#define I2C_FREQ_TABLE_ENTRY_8 28
+#define I2C_FREQ_TABLE_ENTRY_9 32
+#else // Values that give correct result according to measurements
+#define I2C_FREQ_TABLE_ENTRY_8 30
+#define I2C_FREQ_TABLE_ENTRY_9 34
+#endif
+typedef cyg_uint16 dev_i2c_freescale_frequency_entry_t;
+#  define CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE                                    \
+    20, 22, 24, 26, 28, 30, 34, 40, I2C_FREQ_TABLE_ENTRY_8, I2C_FREQ_TABLE_ENTRY_9,  \
+    36, 40, 44, 48, 56, 68, 48, 56, 64,                                              \
+    72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240, 160, 192, 224,       \
+    256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, 640, 768,       \
+    896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840
+
+
+# endif // CYGHWR_IO_FREESCALE_I2C_FREQUENCY_TABLE
+
+// DMA MUX ------------------------------------------------------------------
+// DMAMUX DMA request sources
+#define FREESCALE_DMAMUX_SRC_KINETIS_DISABLE      0
+#define FREESCALE_DMAMUX_SRC_KINETIS_RESERVE      1
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART0R       2
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART0T       3
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART1R       4
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART1T       5
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART2R       6
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART2T       7
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART3R       8
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART3T       9
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART4R      10
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART4T      11
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART5R      12
+#define FREESCALE_DMAMUX_SRC_KINETIS_UART5T      13
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2S0R       14
+#define FREESCALE_DMAMUX_SRC_KINETIS_I3S0T       15
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI0R       16
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI0T       17
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI1R       18
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI1T       19
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI2R       20
+#define FREESCALE_DMAMUX_SRC_KINETIS_SPI2T       21
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2C0        22
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2C1        23 // Either I2C1
+#define FREESCALE_DMAMUX_SRC_KINETIS_I2C2        23 // or I2C2
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C0      24
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C1      25
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C2      26
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C3      27
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C4      28
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C5      29
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C6      30
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C7      31
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM1C0      32
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM1C1      33
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM2C0      34
+#define FREESCALE_DMAMUX_SRC_KINETIS_FTM2C1      35
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T0      36
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T1      37
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T2      38
+#define FREESCALE_DMAMUX_SRC_KINETIS_1588T3      39
+#define FREESCALE_DMAMUX_SRC_KINETIS_ADC0        40
+#define FREESCALE_DMAMUX_SRC_KINETIS_ADC1        41
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP0        42
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP1        43
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMP2        44
+#define FREESCALE_DMAMUX_SRC_KINETIS_DAC0        45
+#define FREESCALE_DMAMUX_SRC_KINETIS_DAC1        46
+#define FREESCALE_DMAMUX_SRC_KINETIS_CMT         47
+#define FREESCALE_DMAMUX_SRC_KINETIS_PDB         48
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTA       49
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTB       50
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTC       51
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTD       52
+#define FREESCALE_DMAMUX_SRC_KINETIS_PORTE       53
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX0     54
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX1     55
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX2     56
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX3     57
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX4     58
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX5     59
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX6     60
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX7     61
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX8     62
+#define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX9     63
+
+// DMAMUX1 DMA request sources
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DISABLE     0
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE     1
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART0R      2
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART0T      3
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART1R      4
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART1T      5
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART2R      6
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART2T      7
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART3R      8
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART3T      9
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART4R     10
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART4T     11
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART5R     12
+#define FREESCALE_DMAMUX1_SRC_KINETIS_UART5T     13
+#define FREESCALE_DMAMUX1_SRC_KINETIS_I2S0R      14
+#define FREESCALE_DMAMUX1_SRC_KINETIS_I3S0T      15
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI0R      16
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI0T      17
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI1R      18
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI1T      19
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI2R      20
+#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI2T      21
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_22 22
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_23 23
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C0     24
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C1     25
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C2     26
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C3     27
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C4     28
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C5     29
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C6     30
+#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C7     31
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_32 32
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_33 33
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_34 34
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_35 35
+#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T0     36
+#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T1     37
+#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T2     38
+#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T3     39
+#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC0       40
+#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC1       41
+#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC2       42
+#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC3       43
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_44 44
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DAC0       45
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DAC1       46
+#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP0       47
+#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP1       48
+#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP2       49
+#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP3       50
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_51 51
+#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_52 52
+#define FREESCALE_DMAMUX1_SRC_KINETIS_PORTF      53
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX0    54
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX1    55
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX2    56
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX3    57
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX4    58
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX5    59
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX6    60
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX7    61
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX8    62
+#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX9    63
+
+#define FREESCALE_DMAMUX_SRC_SPI0_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI0R
+#define FREESCALE_DMAMUX_SRC_SPI0_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI0T
+#define FREESCALE_DMAMUX_SRC_SPI1_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI1R
+#define FREESCALE_DMAMUX_SRC_SPI1_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI1T
+#define FREESCALE_DMAMUX_SRC_SPI2_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI2R
+#define FREESCALE_DMAMUX_SRC_SPI2_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI2T
+
+//----------------------------------------------------------------------------
+// eDMA
+// Lend some eDMA macros to device driver that use DMA
+
+// Base address
+#define CYGHWR_HAL_FREESCALE_EDMA0_P  ((cyghwr_hal_freescale_edma_t *)0x40008000)
+// DMAMUX base addresses
+#define CYGHWR_HAL_FREESCALE_DMAMUX0_P ((cyghwr_hal_freescale_dmamux_t *) 0x40021000)
+#define CYGHWR_HAL_FREESCALE_DMAMUX1_P ((cyghwr_hal_freescale_dmamux_t *) 0x40022000)
+
+#define CYGHWR_IO_FREESCALE_EDMA0_P CYGHWR_HAL_FREESCALE_EDMA0_P
+#define CYGHWR_IO_FREESCALE_DMAMUX0_P CYGHWR_HAL_FREESCALE_DMAMUX0_P
+#define CYGHWR_IO_FREESCALE_DMAMUX1_P CYGHWR_HAL_FREESCALE_DMAMUX1_P
+
+//Clock distribution
+#define CYGHWR_IO_CLOCK_ENABLE(__scgc) hal_clock_enable(__scgc)
+
+#define CYGHWR_IO_FREESCALE_EDMA0_CLK   CYGHWR_HAL_KINETIS_SIM_SCGC_DMA
+#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0
+#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0
+#define CYGHWR_IO_FREESCALE_DMAMUX1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1
+//-----------------------------------------------------------------------------
+// end of var_io_devs.h
+#endif // CYGONCE_HAL_VAR_IO_DEVS_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h
new file mode 100644
index 0000000..6c303af
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_flexbus.h
@@ -0,0 +1,173 @@
+#ifndef CYGONCE_HAL_VAR_IO_FLEXBUS_H
+#define CYGONCE_HAL_VAR_IO_FLEXBUS_H
+//===========================================================================
+//
+//      var_io_flexbus.h
+//
+//      Kinetis FlexBus specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-02-05
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//---------------------------------------------------------------------------
+// FlexBus
+
+// FlexBus chip select control registers
+typedef struct cyghwr_hal_kinetis_fbcs_s{
+    cyg_uint32 csar;    // Chip select address register
+    cyg_uint32 csmr;    // Chip select mask register
+    cyg_uint32 cscr;    // Chip select control register
+} cyghwr_hal_kinetis_fbcs_t;
+
+#define CYGNUM_HAL_KINETIS_FBCS_N 6 // Kinetis has up to 6 chip selects
+
+// FlexBus control
+typedef volatile struct cyghwr_hal_kinetis_fb_s {
+  cyghwr_hal_kinetis_fbcs_t csel[CYGNUM_HAL_KINETIS_FBCS_N]; //Chip Selects
+  cyg_uint8 reserved[24];
+  cyg_uint32 cspmcr;      //Chip select port multiplexing control register
+} cyghwr_hal_kinetis_fb_t;
+
+#define CYGHWR_HAL_KINETIS_FB_P ((cyghwr_hal_kinetis_fb_t *) 0x4000C000)
+
+// CSAR - Chip Select Address Register
+// CSAR Bit Fields
+#define CYGHWR_HAL_FB_CSAR_BA_M        0xFFFF0000
+#define CYGHWR_HAL_FB_CSAR_BA_S        16
+#define CYGHWR_HAL_FB_CS_AR_BA(__val)  VALUE_(CYGHWR_HAL_FB_CSAR_BA_S, __val)
+
+// CSMR - Chup Select Mask Register
+// CSMR Bit Fields
+#define CYGHWR_HAL_FB_CSMR_V_M         0x1
+#define CYGHWR_HAL_FB_CSMR_V_S         0
+#define CYGHWR_HAL_FB_CSMR_WP_M        0x100
+#define CYGHWR_HAL_FB_CSMR_WP_S        8
+#define CYGHWR_HAL_FB_CSMR_BAM_M       0xFFFF0000
+#define CYGHWR_HAL_FB_CSMR_BAM_S       16
+#define CYGHWR_HAL_FB_CS_MR_BAM(__val) VALUE_(CYGHWR_HAL_FB_CSMR_BAM_S, __val)
+
+// CSCR - Chip Select Control register
+// CSCR Bit Fields
+#define CYGHWR_HAL_FB_CSCR_BSTW_M      0x8
+#define CYGHWR_HAL_FB_CSCR_BSTW_S      3
+#define CYGHWR_HAL_FB_CSCR_BSTR_M      0x10
+#define CYGHWR_HAL_FB_CSCR_BSTR_S      4
+#define CYGHWR_HAL_FB_CSCR_BEM_M       0x20
+#define CYGHWR_HAL_FB_CSCR_BEM_S       5
+#define CYGHWR_HAL_FB_CSCR_PS_M        0xC0
+#define CYGHWR_HAL_FB_CSCR_PS_S        6
+#define CYGHWR_HAL_FB_CSCR_AA_M        0x100
+#define CYGHWR_HAL_FB_CSCR_AA_S        8
+#define CYGHWR_HAL_FB_CSCR_BLS_M       0x200
+#define CYGHWR_HAL_FB_CSCR_BLS_S       9
+#define CYGHWR_HAL_FB_CSCR_WS_M        0xFC00
+#define CYGHWR_HAL_FB_CSCR_WS_S        10
+#define CYGHWR_HAL_FB_CSCR_WRAH_M      0x30000
+#define CYGHWR_HAL_FB_CSCR_WRAH_S      16
+#define CYGHWR_HAL_FB_CSCR_RDAH_M      0xC0000
+#define CYGHWR_HAL_FB_CSCR_RDAH_S      18
+#define CYGHWR_HAL_FB_CSCR_ASET_M      0x300000
+#define CYGHWR_HAL_FB_CSCR_ASET_S      20
+#define CYGHWR_HAL_FB_CSCR_EXALE_M     0x400000
+#define CYGHWR_HAL_FB_CSCR_EXALE_S     22
+#define CYGHWR_HAL_FB_CSCR_SWSEN_M     0x800000
+#define CYGHWR_HAL_FB_CSCR_SWSEN_S     23
+#define CYGHWR_HAL_FB_CSCR_SWS_M       0xFC000000
+#define CYGHWR_HAL_FB_CSCR_SWS_S       26
+
+// CSPMCR Bit Fields
+#define CYGHWR_HAL_FB_CSPMCR_G5_M  0xF000
+#define CYGHWR_HAL_FB_CSPMCR_G5_S  12
+#define CYGHWR_HAL_FB_CSPMCR_G4_M  0xF0000
+#define CYGHWR_HAL_FB_CSPMCR_G4_S  16
+#define CYGHWR_HAL_FB_CSPMCR_G3_M  0xF00000
+#define CYGHWR_HAL_FB_CSPMCR_G3_S  20
+#define CYGHWR_HAL_FB_CSPMCR_G2_M  0xF000000
+#define CYGHWR_HAL_FB_CSPMCR_G2_S  24
+#define CYGHWR_HAL_FB_CSPMCR_G1_M  0xF0000000
+#define CYGHWR_HAL_FB_CSPMCR_G1_S  28
+
+// FlexBus control pin multiplexing
+#define CYGHWR_HAL_FB_CSPMCR(__group, __val) VALUE_(__group, __val)
+
+#define CYGHWR_HAL_FB_CSPMCR_G1_ALE \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G1_CS1 \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G1_TS  \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 2)
+
+#define CYGHWR_HAL_FB_CSPMCR_G2_CS4      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G2_TSIZ0    \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24 \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 2)
+
+#define CYGHWR_HAL_FB_CSPMCR_G3_CS5      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G3_TSIZ1    \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16 \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 2)
+
+#define CYGHWR_HAL_FB_CSPMCR_G4_TST      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G4_CS2      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G4_BE_15_8  \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 2)
+
+#define CYGHWR_HAL_FB_CSPMCR_G5_TA       \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 0)
+#define CYGHWR_HAL_FB_CSPMCR_G5_CS3      \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 1)
+#define CYGHWR_HAL_FB_CSPMCR_G5_BE_7_0   \
+            CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 2)
+
+//-----------------------------------------------------------------------------
+// end of var_io_flexbus.h
+#endif // CYGONCE_HAL_VAR_IO_FLEXBUS_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h
new file mode 100644
index 0000000..349e351
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_gpio.h
@@ -0,0 +1,123 @@
+#ifndef CYGONCE_HAL_VAR_IO_GPIO_H
+#define CYGONCE_HAL_VAR_IO_GPIO_H
+//===========================================================================
+//
+//      var_io_gpio.h
+//
+//      Kinetis GPIO
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Tomas Frydrych <tomas@sleepfive.com>
+// Date:          2011-11-14
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//---------------------------------------------------------------------------
+// GPIO
+typedef volatile struct cyghwr_hal_kinetis_gpio_s {
+  cyg_uint32 pdor;
+  cyg_uint32 psor;
+  cyg_uint32 pcor;
+  cyg_uint32 ptor;
+  cyg_uint32 pdir;
+  cyg_uint32 pddr;
+} cyghwr_hal_kinetis_gpio_t;
+
+// PTA-PTE base pointers
+#define CYGHWR_HAL_KINETIS_GPIO_PORTA_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF000u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTB_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF040u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTC_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF080u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTD_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF0C0u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTE_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF100u)
+#define CYGHWR_HAL_KINETIS_GPIO_PORTF_P ((cyghwr_hal_kinetis_gpio_t*)0x400FF140u)
+
+// GPIO register on a given port (register name is lower case)
+#define CYGHWR_HAL_KINETIS_GPIO(__port, __reg)           \
+  (CYGHWR_HAL_KINETIS_GPIO_PORT##__port##_P)->__reg
+
+// Get values for entire port
+#define CYGHWR_HAL_KINETIS_GPIO_GET(__port)              \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pdir)
+
+// Output values for entire port
+#define CYGHWR_HAL_KINETIS_GPIO_PUT(__port, __val)       \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pdor) = __val
+
+// Set values for entire port based on bitmask
+#define CYGHWR_HAL_KINETIS_GPIO_SET(__port, __val)       \
+  CYGHWR_HAL_KINETIS_GPIO(__port, psor) = __val
+
+// Clear values for entire port based on bitmask
+#define CYGHWR_HAL_KINETIS_GPIO_CLEAR(__port, __val)     \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pcor) = __val
+
+// Toggle values for entire port based on bitmask
+#define CYGHWR_HAL_KINETIS_GPIO_TOGGLE(__port, __val)    \
+  CYGHWR_HAL_KINETIS_GPIO(__port, ptor) = __val
+
+// Get value for a single pin on given port
+#define CYGHWR_HAL_KINETIS_GPIO_GET_PIN(__port, __pin)   \
+  (BIT_(__pin) &  CYGHWR_HAL_KINETIS_GPIO_GET(__port))
+
+// Set a single pin on a given register
+#define CYGHWR_HAL_KINETIS_GPIO_SET_PIN(__port, __pin)   \
+  CYGHWR_HAL_KINETIS_GPIO_SET(__port, BIT_(__pin))
+
+// Clear a single pin on a given register
+#define CYGHWR_HAL_KINETIS_GPIO_CLEAR_PIN(__port, __pin) \
+  CYGHWR_HAL_KINETIS_GPIO_CLEAR(__port, BIT_(__pin))
+
+// Toggle a single pin on a given register
+#define CYGHWR_HAL_KINETIS_GPIO_TOGGLE_PIN(__port, __pin)  \
+  CYGHWR_HAL_KINETIS_GPIO_TOGGLE(__port, BIT_(__pin))
+
+// Set pin data direction
+#define CYGHWR_HAL_KINETIS_GPIO_PIN_DDR_OUT(__port, __pin) \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pddr) |= BIT_(__pin)
+
+#define CYGHWR_HAL_KINETIS_GPIO_PIN_DDR_IN(__port, __pin)  \
+  CYGHWR_HAL_KINETIS_GPIO(__port, pddr) &= ~BIT_(__pin)
+
+//-----------------------------------------------------------------------------
+// end of var_io_gpio.h
+#endif // CYGONCE_HAL_VAR_IO_GPIO_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h
new file mode 100644
index 0000000..cbdd067
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h
@@ -0,0 +1,302 @@
+#ifndef CYGONCE_HAL_VAR_IO_LMEM_H
+#define CYGONCE_HAL_VAR_IO_LMEM_H
+//===========================================================================
+//
+//      var_io_lmem.h
+//
+//      Kinetis Local memory controller specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2012-04-28
+// Purpose:       Kinetis variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io_lmem.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+//----------------------------------------------------------------------------
+// LMEM - Local memory controller
+
+typedef volatile struct cyghwr_hal_kinetis_lmem_s {
+    cyg_uint32 ccr;    // Cache control register
+    cyg_uint32 clcr;   // Cache line control register
+    void *csar;        // Cache search address register
+    cyg_uint32 cvr;    // Cache read/write value register
+    cyg_uint8  reserved[16];
+    cyg_uint32 rmr;    // Cache regions mode register
+} cyghwr_hal_kinetis_lmem_t;
+
+#define CYGHWR_HAL_KINETIS_LMEM_PC_P  ((cyghwr_hal_kinetis_lmem_t *) 0xE0082000)
+#define CYGHWR_HAL_KINETIS_LMEM_PS_P  ((cyghwr_hal_kinetis_lmem_t *) 0xE0082800)
+
+// CCR Bit Fields
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M          0x1
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M          0x2
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M            0x1000000
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M           0x2000000
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M            0x4000000
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M           0x8000000
+#define CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M               0x80000000
+
+//CLCR Bit Fields
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M             0x1
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_M       0xFFC
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S       2
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR(_ca_) \
+            ((_ca_) << CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S)
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_WSEL_M            0x4000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_TDSEL_M           0x10000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIVB_M           0x100000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIMB_M           0x200000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCWAY_M           0x400000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S            24
+
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(_cmd_) \
+            ((_cmd_) << CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S)
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_SRCH         0
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL        1
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_PUSH         2
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_CLR          3
+
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M          0x4000000
+#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LACC_M            0x8000000
+
+// CSAR Bit Fields
+#define CYGHWR_HAL_KINETIS_LMEM_CSAR_LGO_M             0x1
+#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_M         0xFFFFFFFC
+#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S         2
+#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR(_adr_) \
+            ((_adr_) << CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S)
+
+// CCVR Bit Fields
+#define CYGHWR_HAL_KINETIS_LMEM_CCVR_DATA_M            0xFFFFFFFF
+
+// PCCRMR Bit Fields
+
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_M           0x3
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION(_region_,_mask_) \
+            ((_mask_) << ((15 - (_region_)) * 2))
+
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M 0
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M 2
+#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M 3
+
+#define CYGHWR_HAL_KINETIS_LMEM_FLASH_0000     0
+#define CYGHWR_HAL_KINETIS_LMEM_DRAM_0800      1
+#define CYGHWR_HAL_KINETIS_LMEM_FLEXNVM_1000   2
+#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_1800   3
+#define CYGHWR_HAL_KINETIS_LMEM_SRAM_L         4
+#define CYGHWR_HAL_KINETIS_LMEM_SRAM_U         5
+#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_6000   6
+#define CYGHWR_HAL_KINETIS_LMEM_DRAM_7000      7
+#define CYGHWR_HAL_KINETIS_LMEM_DRAM_8000      8
+#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_9000   9
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() \
+            hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE() \
+            hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE() \
+            hal_cortexm_kinetis_cache_disable(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE() \
+            hal_cortexm_kinetis_cache_disable(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_INVALL() \
+            hal_cortexm_kinetis_cache_inval(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_INVALL() \
+            hal_cortexm_kinetis_cache_inval(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_SYNC() \
+            hal_cortexm_kinetis_cache_sync(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_SYNC() \
+            hal_cortexm_kinetis_cache_sync(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR() \
+            hal_cortexm_kinetis_cache_clear(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR() \
+            hal_cortexm_kinetis_cache_clear(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED() \
+            hal_cortexm_kinetis_cache_is_enabled(CYGHWR_HAL_KINETIS_LMEM_PC_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED() \
+            hal_cortexm_kinetis_cache_is_enabled(CYGHWR_HAL_KINETIS_LMEM_PS_P)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_SRCH(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_SRCH)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_PUSH(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_PUSH)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PS_CLR(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_CLR)
+
+#define HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base, _size_) \
+        hal_cortexm_kinetis_cache_lines(CYGHWR_HAL_KINETIS_LMEM_PC_P, _base, _size_, \
+                                       CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_INVAL)
+
+#if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK && defined CYG_HAL_STARTUP_RAM
+
+#define CYGHWR_HAL_KINETIS_CACHE_WAIT(_lmem_p)                            \
+CYG_MACRO_START                                                           \
+    cyg_uint32 prs_tmp, prs_save;                                         \
+    cyg_uint32 m0, m1;                                                    \
+    cyghwr_hal_kinetis_axbs_t* _axbs_p = CYGHWR_HAL_KINETIS_AXBS_P;       \
+    prs_save = prs_tmp = _axbs_p->slave[5].prs;                           \
+    m0 = CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(0, prs_tmp);             \
+    m1 = CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_PRIO(1, prs_tmp);             \
+    if(m1 > m0) {                                                         \
+        prs_tmp &= ~(CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(0) |            \
+                     CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_M(1));            \
+        prs_tmp |= (m0 << CYGHWR_HAL_KINETIS_AXBS_PRS_MASTER_S(1)) | m1;  \
+        _axbs_p->slave[5].prs = prs_tmp;                                  \
+    }                                                                     \
+    while((_lmem_p)->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M);             \
+    _axbs_p->slave[5].prs = prs_save;                                     \
+CYG_MACRO_END
+
+#else // CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK
+
+#define CYGHWR_HAL_KINETIS_CACHE_WAIT(_lmem_p)          \
+            while((_lmem_p)->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M)
+
+#endif // CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_enable(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr = ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M
+                   );
+    CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_disable(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr = 0;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_inval(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M |
+              CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M |
+              CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M
+              );
+    CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_store(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M |
+                     CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M |
+                     CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M
+                    );
+    CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_clear(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M |
+                    CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M
+                   );
+    CYGHWR_HAL_KINETIS_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_sync(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    hal_cortexm_kinetis_cache_store(lmem_p);
+    hal_cortexm_kinetis_cache_clear(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE bool
+hal_cortexm_kinetis_cache_is_enabled(cyghwr_hal_kinetis_lmem_t* lmem_p)
+{
+    return lmem_p->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M;
+}
+
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_kinetis_cache_lines(cyghwr_hal_kinetis_lmem_t* lmem_p,
+                               cyg_uint8* addr_p, cyg_uint32 size,
+                               const cyg_uint32 oper)
+{
+    cyg_uint32 line_k;
+    line_k = (((cyg_uint32)addr_p & (HAL_DCACHE_LINE_SIZE-1)) + size) / HAL_DCACHE_LINE_SIZE + 1;
+
+    lmem_p->clcr = CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M |
+                   CYGHWR_HAL_KINETIS_LMEM_CLCR_TDSEL_M  |
+                   CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(oper);
+
+    addr_p = (cyg_uint8*)((((cyg_uint32) addr_p) & 0xfffffff0) |
+                          CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M);
+    do {
+        lmem_p->csar = addr_p;
+        while(lmem_p->clcr & CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M);
+        addr_p += HAL_DCACHE_LINE_SIZE;
+    } while(--line_k);
+}
+
+//-----------------------------------------------------------------------------
+// end of var_io_lmem.h
+#endif // CYGONCE_HAL_VAR_IO_LMEM_H
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/include/variant.inc b/ecos/packages/hal/cortexm/kinetis/var/current/include/variant.inc
new file mode 100644
index 0000000..11875f2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/include/variant.inc
@@ -0,0 +1,53 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_kinetis.h>
+
+//==========================================================================
+// EOF variant.inc
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c
new file mode 100644
index 0000000..caadc51
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/src/hal_diag.c
@@ -0,0 +1,410 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Ilija Kocho <ilijak@siva.com.mk>
+// Contributors:
+// Date:        2011-02-04
+// Purpose:     HAL diagnostic input/output
+// Description: Implementations of HAL diagnostic input/output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+ */
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+
+#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/hal/var_io.h>             //
+#include <cyg/io/ser_freescale_uart.h>  // UART registers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32 uart;
+    CYG_ADDRESS base;
+    cyg_int32 msec_timeout;
+    cyg_int32 isr_vector;
+    cyg_uint32 rx_pin;
+    cyg_uint32 tx_pin;
+    cyg_uint32 clock_gate;
+    cyg_int32 baud_rate;
+    cyg_int32 irq_state;
+} channel_data_t;
+
+channel_data_t plf_ser_channels[] = {
+#ifdef CYGINT_HAL_FREESCALE_UART0
+    { 0, CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART0_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART0_PIN_RX, CYGHWR_HAL_FREESCALE_UART0_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART0_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART1
+    { 1, CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART1_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART1_PIN_RX, CYGHWR_HAL_FREESCALE_UART1_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART1_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART2
+    { 2, CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART2_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART2_PIN_RX, CYGHWR_HAL_FREESCALE_UART2_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART2_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART3
+    { 3, CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART3_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART3_PIN_RX, CYGHWR_HAL_FREESCALE_UART3_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART3_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART4
+    { 4, CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART4_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART4_PIN_RX, CYGHWR_HAL_FREESCALE_UART4_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART4_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART5
+    { 5, CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART5_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART5_PIN_RX, CYGHWR_HAL_FREESCALE_UART5_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART5_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
+#endif
+};
+
+#if defined(CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION) && \
+        CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION
+#  define CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR         \
+        CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+#else
+#  define CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+#endif
+
+//-----------------------------------------------------------------------------
+
+void  CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_putc(void *__ch_data, char c);
+
+
+static void  CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = chan->base;
+
+    // Bring clock to the device
+    CYGHWR_IO_CLOCK_ENABLE(chan->clock_gate);
+    // Configure PORT pins
+    hal_set_pin_function(chan->rx_pin);
+    hal_set_pin_function(chan->tx_pin);
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C1, 0);
+    CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_p, chan->baud_rate);
+    // Enable RX and TX
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2,
+                    (CYGHWR_DEV_FREESCALE_UART_C2_TE |
+                     CYGHWR_DEV_FREESCALE_UART_C2_RE));
+}
+
+void  CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_putc(void* __ch_data, char ch_out)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint32 uart_s1;
+
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    } while (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_TDRE));
+
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_out);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* p_ch_in)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint8 uart_s1;
+    cyg_uint8 ch_in;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    if (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF))
+        return false;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
+    *p_ch_in = ch_in;
+
+    return true;
+}
+
+cyg_uint8 CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* p_ch_in)
+{
+    int delay_count;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    // delay in .1 ms steps
+    delay_count = ((channel_data_t*)__ch_data)->msec_timeout * 10;
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, p_ch_in);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 ser_port_reg;
+    int ret = 0;
+    va_list ap;
+
+    CYGARC_HAL_SAVE_GP();
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        cyg_hal_plf_serial_init_channel(chan);
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint8 uart_s1;
+    int res = 0;
+    cyg_uint8 ch_in;
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
+        if( cyg_hal_is_break( (char *) &ch_in , 1 ) )
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur;
+    int chan_i;
+
+    cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Init channels
+    for(chan_i=0; chan_i<CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; chan_i++) {
+        cyg_hal_plf_serial_init_channel(&plf_ser_channels[chan_i]);
+
+        // Setup procs in the vector table
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(chan_i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[chan_i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+    }
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] );
+#endif
+}
+
+void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+    initialized = 1;
+    cyg_hal_plf_serial_init();
+}
+
+#else // !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+// #if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void hal_plf_diag_init(void)
+{
+    cyg_hal_plf_serial_init( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+void hal_plf_diag_putc(char c)
+{
+    cyg_hal_plf_serial_putc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8 hal_plf_diag_getc(void)
+{
+    return cyg_hal_plf_serial_getc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+#endif // defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c
new file mode 100644
index 0000000..65d26e5
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c
@@ -0,0 +1,463 @@
+//==========================================================================
+//
+//      kinetis_clocking.c
+//
+//      Cortex-M Kinetis HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija kocho <ilijak@siva.com.mk>
+// Date:         2011-10-19
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/cortexm_endian.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+#include <cyg/io/ser_freescale_uart.h>
+
+//===========================================================================
+// Forward declarations
+//===========================================================================
+
+cyg_uint32 hal_cortexm_systick_clock;
+cyg_uint32 hal_kinetis_sysclk;
+cyg_uint32 hal_kinetis_busclk;
+
+cyg_uint32 hal_get_cpu_clock(void);
+
+void hal_start_main_clock(void);
+void hal_set_clock_dividers(void);
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
+void hal_start_rtc_clock(void);
+#endif
+
+
+//==========================================================================
+// Setup up system clocks
+//
+// Set up clocks from configuration. In the future this should be extended so
+// that clock rates can be changed at runtime.
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_clocks( void )
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT
+    cyghwr_hal_kinetis_port_t *port_p = CYGHWR_HAL_KINETIS_PORTA_P;
+#endif
+#if !defined(CYG_HAL_STARTUP_RAM)
+# ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
+    // Real Time Clock
+    hal_start_rtc_clock();
+# endif
+    hal_set_clock_dividers();
+    // Main clock - MCG
+    hal_start_main_clock();
+#endif
+    // Trace clock
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK_CORE
+    sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M;
+#else
+    sim_p->sopt2 &= ~CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M;
+#endif
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT
+    port_p->pcr[6] = CYGHWR_HAL_KINETIS_PORT_PCR_MUX(0x7);
+#endif
+}
+
+
+#define MCG_WAIT_WHILE(_condition_) do{}while(_condition_)
+
+// Setup MCG
+// Note: Currently only PBE mode is supported and tested.
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL
+
+// MCG can have 1 or 2 PLL oscillators.
+// PLL0 aka PLL is always present.
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_pll0(cyghwr_hal_kinetis_mcg_t *mcg_p)
+{
+    mcg_p->c5 = CYGHWR_HAL_KINETIS_MCG_C5_PRDIV(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV-1) |
+          CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M
+# ifdef CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1
+          | CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_M
+# endif //CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1
+          ;
+# if CYGINT_HAL_CORTEXM_KINETIS_150
+    mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-16);
+# else
+    mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-24);
+# endif
+    mcg_p->c5 |= CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M;
+    MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M));
+}
+#endif //CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+
+// PLL1 Oscillator is present on some devices.
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_pll1(cyghwr_hal_kinetis_mcg_t *mcg_p)
+{
+    mcg_p->c11 = CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M;
+    mcg_p->c11 = CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV-1) |
+          CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_M
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1
+          | CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M
+# endif
+# ifdef CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_1
+          | CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_M
+# endif
+          ;
+    mcg_p->c12 = CYGHWR_HAL_KINETIS_MCG_C12_VDIV1(
+          CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV-16);
+    mcg_p->c11 |= CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_M;
+    MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M));
+}
+#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+
+// There are 1 or 2 external oscillators
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_ext_ref(void)
+{
+    volatile cyg_uint8 *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_P;
+
+# if defined CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_0 || \
+     defined CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_0
+#  ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+    // Set the oscillator 0
+    *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP / 2;
+#  elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC
+    // Select external oscillator
+    *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M |
+          CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M;
+#  endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+# endif // CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_0 || ...
+
+# if defined CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 || \
+     defined CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_1
+#  ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL
+    // Set the oscillator 1
+    osc_cr_p = CYGHWR_HAL_KINETIS_OSC1_CR_P;
+    *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP / 2;
+#  elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_OSC
+    // Select external oscillator
+    *osc_cr_p = CYGHWR_HAL_KINETIS_OSC1_CR_ERCLKEN_M |
+          CYGHWR_HAL_KINETIS_OSC1_CR_EREFSTEN_M;
+#  endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL
+# endif // CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 || ...
+}
+#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_main_clock(void)
+{
+    cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P;
+#if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL ||\
+    defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1 ||\
+    (defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC &&\
+    CYGHWR_HAL_CORTEXM_KINETIS_REV == 1)
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+#endif
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
+    // Select RTC clock source for MCG reference
+# if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1
+    sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M;
+# elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+    mcg_p->c7 |= CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_M;
+# endif // CYGHWR_HAL_CORTEXM_KINETIS_REV == 2
+#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
+
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+    hal_start_ext_ref();
+# endif
+
+#if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
+    defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \
+    defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || \
+    defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+
+    mcg_p->c2 = CYGHWR_HAL_KINETIS_MCG_C2_RANGE(
+                    CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE)
+#  ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+          | CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M | CYGHWR_HAL_KINETIS_MCG_C2_HGO_M
+#  endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+          ;
+
+    mcg_p->c1 = CYGHWR_HAL_KINETIS_MCG_C1_FRDIV(
+        CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG)
+# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+        |CYGHWR_HAL_KINETIS_MCG_C1_CLKS(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF)
+# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL*
+        ;
+
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
+    // Wait for oscillator start up
+    MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M));
+# endif
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL
+    // Wait for oscillator 1 start up
+    MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_M));
+# endif
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+    // Wait for reference clock to switch to external reference
+    MCG_WAIT_WHILE(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_IREFST_M);
+    // Wait for status flags update
+    MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
+#  if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
+      defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \
+      defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+            CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT
+#  else
+            CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL
+#  endif
+            );
+# endif //  CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
+
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL
+    // Configure FLL
+    mcg_p->c4 = (mcg_p->c4 & 0x1f) |
+          (CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 |
+           CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS(
+               CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS));
+
+# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL
+
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL
+    hal_start_pll0(mcg_p);
+# endif
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+    hal_start_pll1(mcg_p);
+# endif
+# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1)
+    // Switch to PBE mode
+    mcg_p->c6 |=  CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M;
+
+    MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
+                   CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT);
+    MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_PLLST_M));
+#  ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL
+    MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M));
+#  endif
+#  if defined CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+    MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M));
+#  endif // CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1
+
+    // Enter PEE mode
+    mcg_p->c1 &= ~CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M;
+    MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
+                   CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL);
+# endif // defined CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL*
+
+# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \
+     defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+    sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M;
+# endif
+
+#endif // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) ||
+       // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) ||
+       // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) ||
+       // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+}
+
+cyg_uint32 CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_get_cpu_clock(void)
+{
+    cyg_uint32 freq;
+#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL
+    cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P;
+
+# if CYGINT_HAL_CORTEXM_KINETIS_150
+    freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+          ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) *
+          ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+16) / 2;
+# else
+    freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+          ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) *
+          ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+24);
+# endif
+#elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1
+    cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P;
+
+    freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
+          ((mcg_p->c11 & CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_M)+1) *
+          ((mcg_p->c12 & CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_M)+16) / 2;
+#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL)
+    freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV;
+#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
+    freq = CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC;
+#else // ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_none
+#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_end
+
+    return freq;
+}
+
+
+// Clock dividers provide clock sources for various peripherals.
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_set_clock_dividers(void)
+{
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+
+    sim_p->clk_div1 = CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(0) |
+          CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2(
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS-1)  |
+          CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3(
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS-1) |
+          CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4(
+                CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH-1);
+
+    sim_p->clk_div2 = CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV(
+                          CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV-1) |
+                          (CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC==2 ?
+                               CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M : 0);
+}
+
+#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_start_rtc_clock(void)
+{
+    cyghwr_hal_kinetis_rtc_t *rtc_p = CYGHWR_HAL_KINETIS_RTC_P;
+
+    rtc_p->ier=0; // Disable RTC interrupts
+
+    //Start RTC clock if not already started
+    if(!(rtc_p->cr & CYGHWR_HAL_KINETIS_RTC_CR_OSCE)){
+        rtc_p->cr = CYGHWR_HAL_KINETIS_RTC_CR_OSCE |
+              CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP;
+# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
+        {
+            volatile cyg_uint32 busycnt;
+            for(busycnt=1000000; busycnt; busycnt--)
+                __asm__ volatile ("nop\n");
+        }
+# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
+    }
+}
+#endif
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current clock settings.
+
+
+void  CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud)
+{
+    cyg_uint32 sbr, brfa;
+    cyg_uint32 regval;
+
+    switch(uart_p) {
+    case CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE:
+    case CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE:
+        sbr = hal_kinetis_sysclk/(16*baud);
+        break;
+    case CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE:
+    case CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE:
+    case CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE:
+    case CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE:
+        sbr = hal_kinetis_busclk/(16*baud);
+        break;
+    default:
+        sbr=0;
+        break;
+    }
+    if(sbr) {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval);
+        regval &= 0xE0;
+        regval |= sbr >> 8;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval);
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDL, (sbr & 0xFF));
+        brfa = (((32*hal_kinetis_busclk)/(16*baud))-(32*sbr));
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval);
+        regval &= 0xE0;
+        regval |= brfa & 0x1f;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval);
+    }
+}
+
+
+void hal_update_clock_var(void)
+{
+    hal_kinetis_sysclk=hal_get_cpu_clock();
+    hal_kinetis_busclk=hal_kinetis_sysclk /
+          CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS;
+    hal_cortexm_systick_clock=hal_kinetis_sysclk;
+}
+
+
+cyg_uint32 hal_get_peripheral_clock(void)
+{
+    return hal_kinetis_busclk;
+}
+
+//==========================================================================
+// EOF kinetis_clocking.c
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c
new file mode 100644
index 0000000..2b934cf
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c
@@ -0,0 +1,129 @@
+//==========================================================================
+//
+//      kinetis_ddram.c
+//
+//      Cortex-M Kinetis HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija kocho <ilijak@siva.com.mk>
+// Date:         2012-03-08
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/cortexm_endian.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+// DDRAM Controller
+#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+
+// DDRAM controller register indices.
+const cyg_uint8 const kinetis_ddr_reg_ix[] = {
+    0,
+    2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+    20, 21, 22, 23,
+    25, 26, 27, 28, 29, 30,
+    34,
+    36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
+    52, 53, 54, 55, 56, 57
+};
+
+// Initialize DDRAM controller.
+// inidat[] is an array of ordered pairs: (register-index, register-value).
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 inidat[])
+{
+    cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P;
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    volatile cyg_uint32* cr_p;
+    cyg_uint32 cr_ix;
+    cyg_uint32 cr_i;
+    cyg_uint32 regval;
+    
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_DDR);
+
+    regval = sim_p->mcr & ~CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M;
+    sim_p->mcr   = regval | CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP;
+
+    ddrmc_p->rcr |= CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M;
+    ddrmc_p->pad_ctrl = CYGHWR_HAL_KINETIS_DDRMC_PAD_CTRL;
+    cr_p = ddrmc_p->cr;
+    for(cr_ix = 0; cr_ix < sizeof(kinetis_ddr_reg_ix); cr_ix++) {
+        cr_i = kinetis_ddr_reg_ix[cr_ix];
+        cr_p[cr_i] = *inidat++;
+    };
+    __asm__ volatile ("nop\n");
+    ddrmc_p->cr[0] |= CYGHWR_HAL_KINETIS_DDRMC_CR00_START;
+    while(!(ddrmc_p->cr[30] & CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL));
+}
+
+void
+hal_cortexm_kinetis_ddrmc_diag(void)
+{
+    cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P;
+    cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
+    volatile cyg_uint32* cr_p;
+    cyg_uint32 cr_i;
+
+    diag_printf("SCGC3 = 0x%08x, MCR = 0x%08x\n", sim_p->scgc3, sim_p->mcr);
+    diag_printf("RCR= 0x%08x, PAD_CTRL= 0x%08x\n", ddrmc_p->rcr, ddrmc_p->pad_ctrl);
+    cr_p = ddrmc_p->cr;
+    for(cr_i=0; cr_i < 64; cr_i++){
+        diag_printf("  CR%02d = 0x%08x\n", cr_i, cr_p[cr_i]);
+    }
+}
+
+#endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC
+
+//==========================================================================
+// EOF kinetis_ddram.c
diff --git a/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
new file mode 100644
index 0000000..391c034
--- /dev/null
+++ b/ecos/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c
@@ -0,0 +1,309 @@
+//==========================================================================
+//
+//      kinetis_misc.c
+//
+//      Cortex-M Kinetis HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija kocho <ilijak@siva.com.mk>
+// Date:         2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_kinetis.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/cortexm_endian.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+#include <cyg/hal/hal_cache.h>
+
+void sst25xx_freescale_dspi_reg(void);
+
+#if defined CYG_HAL_STARTUP_ROM && !defined CYG_HAL_STARTUP_RAM
+
+//===========================================================================
+// KINETIS FLASH configuration field
+//===========================================================================
+
+// Note: KINETIS FLASH configuration field must be present in Kinetis flash
+//       image and ocupy addresses 0x00000400 to 0x0000040f.
+
+// For ".flash_conf" section definition see MLT files.
+
+const cyghwr_hal_kinetis_flash_conf_t CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD
+__attribute__((section(".flash_conf"), used)) = {
+    .backdoor_key = CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY,
+    .fprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT,
+    .fsec = CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC,
+    .fopt = CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT,
+    .feprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT,
+    .fdprot = CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT
+};
+
+const cyghwr_hal_kinetis_flash_conf_t *
+CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_kinetis_flash_conf_p( void )
+{
+    return &CYGHWR_HAL_KINETIS_FLASH_CONF_FIELD;
+}
+
+#endif // defined CYG_HAL_STARTUP_ROM && !defined CYG_HAL_STARTUP_RAM
+
+//=== KINETIS FLASH security configuration END. ============================
+
+#if defined CYGPKG_HAL_KINETIS_CACHE
+
+// Function for demotion of caching memory regions
+static void
+hal_cortexm_kinetis_conf_cache_regions(cyghwr_hal_kinetis_lmem_t* lmem_p,
+                                      cyg_uint32 reg_n, const cyg_uint32 *reg_mode_p)
+{
+    cyg_uint32 region;
+    cyg_uint32 mode;
+    cyg_uint32 regval;
+    cyg_uint32 reg_mode;
+
+    regval = lmem_p->rmr;
+    for(; reg_n; reg_n--){
+        reg_mode = *reg_mode_p++;
+        region = reg_mode >> 16;
+        mode = reg_mode & 0x0000ffff;
+        regval &= ~(0x3 << (15-region)*2);
+        regval |= mode << (15-region)*2;
+    }
+    lmem_p->rmr = regval;
+}
+
+const cyg_uint32 cache_reg_modes_pc[] = {
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M,
+
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M
+};
+
+const cyg_uint32 cache_reg_modes_ps[] = {
+    (CYGHWR_HAL_KINETIS_LMEM_FLASH_0000 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M,
+
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_0800 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M,
+
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) |
+#if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_WRITETHRU
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M,
+#elif defined CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M,
+#else
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M,
+#endif
+
+    (CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 << 16) |
+    CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M
+};
+
+#endif // defined CYGPKG_HAL_KINETIS_CACHE
+
+//==========================================================================
+// Setup variant specific hardware
+//=========================================================================
+
+void hal_variant_init( void )
+{
+#if defined CYGPKG_HAL_KINETIS_CACHE
+# if defined CYG_HAL_STARTUP_RAM
+    register CYG_INTERRUPT_STATE oldints;
+# endif
+#endif
+
+    hal_update_clock_var();
+
+#if defined CYGPKG_HAL_KINETIS_CACHE
+# if defined CYG_HAL_STARTUP_RAM
+    HAL_DISABLE_INTERRUPTS(oldints);
+    HAL_DCACHE_SYNC();
+    HAL_DCACHE_DISABLE();
+    HAL_DCACHE_PURGE_ALL();
+    HAL_ICACHE_DISABLE();
+    HAL_ICACHE_INVALIDATE_ALL();
+# endif // defined CYG_HAL_STARTUP_RAM
+    hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PS_P,
+        sizeof(cache_reg_modes_ps)/sizeof(cache_reg_modes_ps[0]),
+        cache_reg_modes_ps);
+    hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PC_P,
+        sizeof(cache_reg_modes_pc)/sizeof(cache_reg_modes_pc[0]),
+        cache_reg_modes_pc);
+# if defined CYG_HAL_STARTUP_RAM
+    HAL_RESTORE_INTERRUPTS(oldints);
+# endif
+# ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
+    HAL_ICACHE_ENABLE();
+# endif
+# ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+    HAL_DCACHE_ENABLE();
+# endif
+#endif // defined CYGPKG_HAL_KINETIS_CACHE
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//===========================================================================
+// The  WDOG at Freescale Kinetis is enabled after reset. hal_wdog_disable
+// provides functionality for disabling it at startup.
+//===========================================================================
+
+static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_kinetis_wdog_unlock_simple(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p)
+{
+    wdog_p->Unlock = 0xC520;
+    wdog_p->Unlock = 0xD928;
+}
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_kinetis_wdog_unlock(volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p)
+{
+    CYGARC_CPSID( i );
+    hal_kinetis_wdog_unlock_simple(wdog_p);
+    CYGARC_CPSIE( i );
+}
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_wdog_disable(void)
+{
+    volatile CygHwr_HAL_Kinetis_wdog_t *wdog_p = CYGHWR_HAL_KINETIS_WDOG_P;
+    hal_kinetis_wdog_unlock_simple(wdog_p);
+    wdog_p->StCtrlH = CYGHWR_HAL_KINETIS_WDOG_STCTRLH_ALLOWUPDATE_M;
+}
+
+//==========================================================================
+// Pin configuration functions
+//
+
+static cyghwr_hal_kinetis_port_t * const Ports[] = {
+    CYGHWR_HAL_KINETIS_PORTA_P, CYGHWR_HAL_KINETIS_PORTB_P,
+    CYGHWR_HAL_KINETIS_PORTC_P, CYGHWR_HAL_KINETIS_PORTD_P,
+    CYGHWR_HAL_KINETIS_PORTE_P, CYGHWR_HAL_KINETIS_PORTF_P
+};
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_set_pin_function(cyg_uint32 pin)
+{
+    cyghwr_hal_kinetis_port_t *port_p;
+
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        port_p = Ports[CYGHWR_HAL_KINETIS_PIN_PORT(pin)];
+        port_p->pcr[CYGHWR_HAL_KINETIS_PIN_BIT(pin)] =
+              CYGHWR_HAL_KINETIS_PIN_FUNC(pin);
+    }
+}
+
+void
+hal_dump_pin_function(cyg_uint32 pin)
+{
+    cyghwr_hal_kinetis_port_t *port_p;
+
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        port_p = Ports[CYGHWR_HAL_KINETIS_PIN_PORT(pin)];
+        diag_printf("Port        %d: %p[%d] fun=%x\n",
+            CYGHWR_HAL_KINETIS_PIN_PORT(pin),
+            port_p,
+            CYGHWR_HAL_KINETIS_PIN_BIT(pin),
+            port_p->pcr[CYGHWR_HAL_KINETIS_PIN_BIT(pin)]);
+    }
+}
+
+void
+hal_dump_pin_setting(cyg_uint32 pin)
+{
+    if(pin != CYGHWR_HAL_KINETIS_PIN_NONE) {
+        diag_printf("Pin: 0x%08x Port=%d bit=%d fun=%x\n",
+            pin,
+            CYGHWR_HAL_KINETIS_PIN_PORT(pin),
+            CYGHWR_HAL_KINETIS_PIN_BIT(pin),
+            CYGHWR_HAL_KINETIS_PIN_FUNC(pin));
+    }
+}
+
+//==========================================================================
+// Clock distribution
+//
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_clock_enable(cyg_uint32 desc)
+{
+    volatile cyg_uint32 *scgc_p;
+
+    if(desc != CYGHWR_HAL_SCGC_NONE) {
+        scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 +
+                 CYGHWR_HAL_KINETIS_SIM_SCGC_REG(desc);
+        *scgc_p |= 1 << CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(desc);
+    }
+}
+
+void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
+hal_clock_disable(cyg_uint32 desc)
+{
+    volatile cyg_uint32 *scgc_p;
+
+    if(desc != CYGHWR_HAL_SCGC_NONE) {
+        scgc_p = &CYGHWR_HAL_KINETIS_SIM_P->scgc1 +
+                 CYGHWR_HAL_KINETIS_SIM_SCGC_REG(desc);
+        *scgc_p &= ~(1 << CYGHWR_HAL_KINETIS_SIM_SCGC_BIT(desc));
+    }
+}
+
+//==========================================================================
+// EOF kinetis_misc.c
diff --git a/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/ChangeLog b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/ChangeLog
new file mode 100644
index 0000000..738b455
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/ChangeLog
@@ -0,0 +1,39 @@
+2011-02-09  John Dallaway  <john@dallaway.org.uk>
+
+	* doc/ek_lm3s811.sgml: Eliminate underscores in SGML ID strings. They
+	cause problems for some installations of openjade.
+
+	* cdl/hal_cortexm_ek_lm3s811.cdl: Fix documentation filename to match
+	the above change.
+
+2011-01-18  Christophe Coutand  <ccoutand@stmi.com>
+
+	* cdl/hal_cortexm_ek_lm3s811.cdl:
+	* doc/ek_lm3s811.sgml:
+	* src/ek_lm3s811_misc.c:
+	* src/platform_i2c.c:
+	New package -- Stellaris Cortex-M3 EK-LM3S811 platform HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/cdl/hal_cortexm_ek_lm3s811.cdl b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/cdl/hal_cortexm_ek_lm3s811.cdl
new file mode 100644
index 0000000..ee64fb1
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/cdl/hal_cortexm_ek_lm3s811.cdl
@@ -0,0 +1,78 @@
+# ====================================================================
+##
+##      hal_cortexm_ek_lm3s811.cdl
+##
+##      Stellaris Cortex-M3 EK-LM3S811 board platform HAL
+##
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ccoutand
+# Contributors:   
+# Date:           2011-01-18
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_EK_LM3S811 {
+    display       "Stellaris EK-LM3S811 Development Board HAL"
+    doc           ref/hal-cortexm-lm3s-ek-lm3s811.html
+    parent        CYGPKG_HAL_CORTEXM_LM3S8XX
+    define_header hal_cortexm_ek_lm3s811.h
+    include_dir   cyg/hal
+    hardware
+
+    description   "
+        The EK-LM3S811 HAL package provides the support needed to run
+        eCos on the Stellaris EK-LM3S811 EVAL board."
+
+    compile       ek_lm3s811_misc.c platform_i2c.c
+
+    requires      { CYGHWR_HAL_CORTEXM_LM3S == "LM3S8XX" }
+    requires      { CYGHWR_HAL_CORTEXM_LM3S8XX == "LM3S811" }
+    requires      { CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ == 6000000 }
+    requires      { CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT == 1 }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_ek_lm3s811.h>"
+        puts $::cdl_header "#include <pkgconf/hal_cortexm_lm3s8xx.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3 - LM3S811\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Stellaris EK-LM3S811\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+}
+
+# EOF hal_cortexm_ek_lm3s811.cdl
diff --git a/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml
new file mode 100644
index 0000000..f358d73
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/doc/ek_lm3s811.sgml
@@ -0,0 +1,140 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     ek_lm3s811.sgml                                             -->
+<!--                                                                 -->
+<!--     ek_lm3s811 board documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2011 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   ccoutand                                           -->
+<!-- Contact(s):  ccoutand                                           -->
+<!-- Date:        2011/01/18                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<part id="hal-cortexm-lm3s-ek-lm3s811"><title>Stellaris EKK-LM3S811 Board Support</title>
+
+<refentry id="lm3s-ek-lm3s811">
+  <refmeta>
+    <refentrytitle>Overview</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>eCos Support for the Stellaris EKK-LM3S811 Board</refname>
+    <refpurpose>Overview</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="lm3s-ek-lm3s811-description"><title>Description</title>
+    <para>
+The Stellaris EKK-LM3S811 evaluation kit uses the Stellaris LM3S811 microcontroller from the 
+800 Series. The LM3S811 is an ARM cortex-M3 based microcontroller with 64KB of FLASH 
+and 8KB of SRAM. The device has various peripherals such as UART, I2C, ADC or Analog
+Comparator. The kit features an OLED graphical display and UART0 is accessible via the 
+on-board USB to UART converter.
+    </para>
+    <para>
+Due to extreme limited RAM ressources (8KB SRAM only), the eCos port targets standalone ROM  
+application using the eCos kernel in single user thread environment. The cortex-M architecture HAL 
+requires a seperate stack to handle interrupts, thus the minimum kernel enable application requires 3 
+stacks. The interrupt stack, the Idle thread stack and the user stack. All stacks are set to the architecture 
+minimum allowed size of CYGNUM_HAL_STACK_SIZE_MINIMUM ( 1360 bytes ). 
+    </para>
+  </refsect1>
+
+  <refsect1 id="lm3s-ek-lm3s811-config"><title>Configuration</title>
+    <para>
+The minimum board configuration includes the Microcontroller HAL alongs with the ADC and I2C device 
+drivers.
+    </para>
+    <variablelist>
+      <varlistentry>
+        <term><varname>LM3S811 Microcontroller</varname></term>
+        <listitem>
+        <para>
+CYGPKG_HAL_CORTEXM_LM3S8XX - The microcontroller configuration 
+requirements are minimal. With the default setup, the microcontroller runs from the 
+external clock source, a crystal of 6MHz. The chip internal PLL generates a fix 
+200MHz clock that is divided down to the default system clock frequency of 50MHz. 
+In this scenario, the device uses full processing power. The system clock divider 
+allows down scaling of the system clock frequency to reduce the overall power 
+consumption of the device. The microcontroller also offers the option to run from an
+internal oscillator. This option has 2 modes, 3MHz or 12MHz. When selecting the
+internal oscillator, the PLL is bypassed. The system clock frequency becomes at
+best 12MHz if no further clock division is applied.
+        </para>
+        </listitem>
+      </varlistentry>
+
+      <varlistentry>
+        <term><varname>I2C Interface</varname></term>
+        <listitem><para>
+CYGPKG_DEVS_I2C_CORTEXM_LM3S - The microcontroller uses the I2C bus 
+to communicate with the SD1300 controller of the OLED 96 x 16 display. The SD1300 
+controller eCos driver is not currently available.
+The I2C is default set to use the low frequency mode ( 100KHz bus clock ). The high 
+frequency mode ( 400 KHz ) is available by changing CYGNUM_HAL_CORTEXM_LM3S_I2C_CLK_SPEED.
+        </para></listitem>
+      </varlistentry>
+      <varlistentry>
+        <term><varname>ADC Interface</varname></term>
+        <listitem><para>
+CYGPKG_DEVS_ADC_CORTEXM_LM3S - The LM3S811 includes 4 ADC channels including an
+optional internal temperature probe. There are many ways to use the on-chip ADC.
+The current eCos driver uses a single sequencer (sequencer 0) to schedule sampling of all 
+channels. This practically means that all channels are sampled from the same trigger, a periodic timer
+interrupt in the current driver. The timer to use
+is selected from CYGNUM_DEVS_ADC_CORTEXM_LM3S_ADC0_SELECT_TIMER, with timer 0 as
+default value. The timer is used in 32 bits periodic mode, therefore cannot be re-used
+for any other user purpose. While the ADC has the possibility to trigger sampling on external 
+IO events, the driver does not offer that flexibility. Finally, the driver only allows measurement of
+single-ended IOs.
+        </para></listitem>
+      </varlistentry>
+    </variablelist>
+  </refsect1>
+
+  <refsect1 id="lm3s-ek-lm3s811-rebuild"><title>Build ROM type applications</title>
+    <para>
+The steps needed to build the HAL library for the EKK-LM3S811 board are:
+    </para>
+    <screen>
+$ mkdir ek_lm3s811
+$ cd ek_lm3s811
+$ ecosconfig new ek-lm3s811 minimal
+$ ecosconfig import $ECOS_REPOSITORY/hal/cortexm/lm3s/ek_lm3s811/current/misc/default_ROM.ecm
+$ ecosconfig resolve
+$ ecosconfig tree
+$ make
+    </screen>
+    <para>
+At the end of the build the <filename
+class="directory">install/lib</filename> subdirectory should contain the library and linker script and the <filename
+class="directory">install/include</filename> subdirectory the necessary includes to compile the application.
+    </para>
+  </refsect1>
+
+
+</refentry>
+
+</part>
diff --git a/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/ek_lm3s811_misc.c b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/ek_lm3s811_misc.c
new file mode 100644
index 0000000..e77ef6c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/ek_lm3s811_misc.c
@@ -0,0 +1,163 @@
+//==========================================================================
+//
+//      ek_lm3s811_misc.c
+//
+//      Cortex-M3 Stellaris EK-LM3S811 HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Original for STM3210E EVAL: nickg
+//              Updated for EK-LM3S811: ccoutand
+// Date:        2011-01-18
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+
+
+// On-board status LED
+#define CYGHWR_HAL_EK_LM3S811_STATUS_LED \
+        CYGHWR_HAL_LM3S_GPIO( C, 5, OUT, 4_MA, PULLUP, DISABLE )
+
+// OLED regulator control
+#define CYGHWR_HAL_EK_LM3S811_OLED_PWD \
+        CYGHWR_HAL_LM3S_GPIO( D, 7, OUT, NONE, NONE, DISABLE )
+
+
+//==========================================================================
+// Drive OLED power ON/OFF IO
+
+__externC void
+hal_ek_lm3s811_oled_pwd( bool pwd )
+{
+    cyg_uint32      oled_pwd_io = CYGHWR_HAL_EK_LM3S811_OLED_PWD;
+
+    // Power ON regulator
+    if ( pwd == true )
+        CYGHWR_HAL_LM3S_GPIO_OUT( oled_pwd_io, 1 );
+    else
+        CYGHWR_HAL_LM3S_GPIO_OUT( oled_pwd_io, 0 );
+}
+
+
+//==========================================================================
+// Setup platform
+
+__externC void
+hal_platform_init( void )
+{
+    cyg_uint32      led_io = CYGHWR_HAL_EK_LM3S811_STATUS_LED;
+    cyg_uint32      oled_pwd_io = CYGHWR_HAL_EK_LM3S811_OLED_PWD;
+
+    // OLED power switch IO is on port D and user LED on port C
+    CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOC, 1 );
+    CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOD, 1 );
+    CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_I2C0, 0 );
+
+    // Status LED -> ON
+    CYGHWR_HAL_LM3S_GPIO_SET( led_io );
+    CYGHWR_HAL_LM3S_GPIO_OUT( led_io, 1 );
+
+    // Shutdown power regulator
+    CYGHWR_HAL_LM3S_GPIO_SET( oled_pwd_io );
+
+    hal_ek_lm3s811_oled_pwd( false );
+}
+
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS     start;             // Region start address
+    CYG_ADDRESS     end;               // End address (last byte)
+} hal_data_access[] = {
+#ifdef CYGMEM_REGION_sram              // On-chip SRAM
+    {
+    CYGMEM_REGION_sram, CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_flash             // On-chip flash
+    {
+    CYGMEM_REGION_flash,
+            CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1},
+#endif
+    {
+    0xE0000000, 0x00000000 - 1},       // Cortex-M peripherals
+    {
+    0x40000000, 0x50000000 - 1},       // Stellaris peripherals
+};
+
+__externC int
+cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int             i;
+    for( i = 0; i < sizeof( hal_data_access ) / sizeof( hal_data_access[0] );
+         i++ ) {
+        if( ( addr >= hal_data_access[i].start )
+            && ( addr + count ) <= hal_data_access[i].end )
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+
+//==========================================================================
+// EOF ek_lm3s811_misc.c
diff --git a/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/platform_i2c.c b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/platform_i2c.c
new file mode 100644
index 0000000..0889f36
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/ek_lm3s811/current/src/platform_i2c.c
@@ -0,0 +1,178 @@
+//==========================================================================
+//
+//      platform_i2c.c
+//
+//      Optional I2C support for Cortex-M3 Stellaris EK-LM3S811
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors: 
+// Date:         2011-01-18
+// Purpose:      
+// Description:  
+//              
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+//=============================================================================
+//                               INCLUDES
+//=============================================================================
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/hal/hal_endian.h>
+#include <cyg/hal/hal_intr.h>
+
+#ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S
+
+#include <cyg/io/i2c.h>
+#include <cyg/io/i2c_lm3s.h>
+
+//=============================================================================
+// Setup I2C bus 0
+//
+static void
+lm3s8xx_i2c0_init( struct cyg_i2c_bus *bus )
+{
+    cyg_uint32      scl_io = CYGHWR_HAL_LM3S_I2C_SCL;
+    cyg_uint32      sda_io = CYGHWR_HAL_LM3S_I2C_SDA;
+
+    //
+    // We only need to setup the pins here and
+    // leave the I2C driver to take care of the rest.
+    //
+    CYGHWR_HAL_LM3S_PERIPH_SET( CYGHWR_HAL_LM3S_P_GPIOB, 1 );
+    CYGHWR_HAL_LM3S_GPIO_SET( scl_io );
+    CYGHWR_HAL_LM3S_GPIO_SET( sda_io );
+    lm3s_i2c_init( bus );
+}
+
+
+//-----------------------------------------------------------------------------
+// I2C bus 0
+//
+CYG_LM3S_I2C_BUS(hal_lm3s8xx_i2c0_bus,
+                 &lm3s8xx_i2c0_init,
+                 CYGHWR_HAL_LM3S_I2C_M0,
+                 CYGHWR_HAL_LM3S_P_I2C0,
+                 CYGNUM_HAL_INTERRUPT_I2C,
+                 0x60,
+                 10);
+
+
+//-----------------------------------------------------------------------------
+// OLED
+//
+CYG_I2C_DEVICE(i2c_lm3s8xx_oled,
+               &hal_lm3s8xx_i2c0_bus,
+               0x3d,
+               0,
+               CYG_I2C_DEFAULT_DELAY);
+
+
+#define DELAY 1
+
+// Wrapper to TI OLED driver
+
+externC cyg_uint32
+lm3s8xx_oled_write_first( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    cyg_i2c_transaction_begin( &i2c_lm3s8xx_oled );
+
+    result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled,
+                                     true, ( cyg_uint8 * )&byte, 1, false );
+
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    return result;
+}
+
+externC cyg_uint32
+lm3s8xx_oled_write_byte( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled,
+                                     false, ( cyg_uint8 * )&byte, 1, false );
+
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    return result;
+}
+
+
+externC cyg_uint32
+lm3s8xx_oled_write_array( const cyg_uint8 *array, cyg_uint32 count )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled,
+                                     false, array, count, false );
+
+    return result;
+}
+
+
+externC cyg_uint32
+lm3s8xx_oled_write_final( cyg_uint8 byte )
+{
+    cyg_uint32      result;
+
+    result = cyg_i2c_transaction_tx( &i2c_lm3s8xx_oled,
+                                     false, ( cyg_uint8 * )&byte, 1, true );
+#ifdef CYGPKG_KERNEL
+    cyg_thread_delay( DELAY );
+#endif
+
+    cyg_i2c_transaction_end( &i2c_lm3s8xx_oled );
+
+    return result;
+}
+
+#endif // #ifdef CYGPKG_DEVS_I2C_CORTEXM_LM3S
+
+//-----------------------------------------------------------------------------
+// EOF platform_i2c.c
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/ChangeLog b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/ChangeLog
new file mode 100644
index 0000000..d3d3bec
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/ChangeLog
@@ -0,0 +1,42 @@
+2011-05-04  John Dallaway  <john@dallaway.org.uk>
+
+	* include/plf_io.h: Fix determination when CYGHWR_HAL_LM3S_ADC0_CHAN
+	should be 8. Patch from Anatoly Sokolov. [ Bugzilla 1001222 ]
+
+2011-01-18  Christophe Coutand  <ccoutand@stmi.com>
+
+	* cdl/hal_cortexm_lm3s8xx.cdl:
+	* include/pkgconf/mlt_cortexm_ek_lm3s811_rom.h:
+	* include/pkgconf/mlt_cortexm_ek_lm3s811_rom.ldi:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* misc/default_ROM.ecm:
+	* src/lm3s8xx_misc.c:
+	* tests/timers.c:
+	New package -- Stellaris Cortex M3 800 Series HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
+
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/cdl/hal_cortexm_lm3s8xx.cdl b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/cdl/hal_cortexm_lm3s8xx.cdl
new file mode 100644
index 0000000..b46415c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/cdl/hal_cortexm_lm3s8xx.cdl
@@ -0,0 +1,390 @@
+##==========================================================================
+##
+##    hal_cortexm_lm8xx.cdl
+##
+##    Stellaris Cortex-M3 800 Series variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Date:         2011-01-18
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LM3S8XX {
+    display       "Stellaris Cortex-M3 800 Series"
+    parent        CYGPKG_HAL_CORTEXM
+    include_dir   cyg/hal
+    define_header hal_cortexm_lm3s8xx.h
+    hardware
+    description   "
+        This package provides generic support for the Cortex-M3 based
+        Stellaris LM 800 Series microcontroller family.  It is also
+        necessary to select a variant and platform HAL package."
+
+    compile       lm3s8xx_misc.c
+
+    implements    CYGINT_DEVS_I2C_LM3S8XX_BUS_DEVICES
+
+    requires      { CYGHWR_HAL_CORTEXM_LM3S == "LM3S8XX" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_lm3s.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_IO_H"
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX {
+        display       "Stellaris LM 800 Series variant in use"
+        flavor        data
+        default_value { "LM3S811" }
+        legal_values  { "LM3S828" "LM3S818" "LM3S817"
+                        "LM3S815" "LM3S812" "LM3S811"
+                        "LM3S808" "LM3S801" "LM3S800" }
+        description   "
+               The Stellaris 800 Series has several variants, the main
+               difference being the numbers of some peripherals"
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+        }
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value { "ROM" }
+        legal_values  { "ROM" }
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            With its 8KB of SRAM, the 800 Series devices only allows
+            ROM startup."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display          "Memory layout"
+        flavor data
+        no_define
+        calculated       { (CYG_HAL_STARTUP == "ROM") ? \
+                           "cortexm_lm3s8xx_rom" : "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display       "Memory layout linker script fragment"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated    { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display       "Memory layout header file"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated    { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK {
+        display       "Clocking"
+        flavor        none
+        requires      { CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT || \
+                        CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT {
+            display      "External clock source"
+            active_if     ! CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT
+            flavor        bool
+            default_value 1
+
+            cdl_option CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ {
+                display       "Crystal frequency in Hz"
+                flavor        data
+                default_value 8000000
+                legal_values  { 1000000 to 8192000 }
+                description   "
+                    Select the external crystal frequency from 1 to
+                    8.192 MHz.  Selecting the internal PLL adds additional
+                    constraints to the external crystal frequency setting.
+                    Check-out CYGHWR_HAL_CORTEXM_LM3S8XX_PLL"
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT {
+            display       "Internal clock source"
+            active_if     ! CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT
+            flavor        bool
+            default_value 0
+
+            cdl_option CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ {
+                display       "Internal clock source frequency in Hz"
+                flavor        data
+                default_value 12000000
+                legal_values  { 12000000 3000000 }
+                description   "
+                    Select the internal clock source. The frequency of the
+                    internal clock source can either be 12MHz or 3MHz."
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LM3S8XX_PLL {
+            display       "Enable PLL"
+            flavor         bool
+            default_value  1
+            active_if      CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT
+
+            cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT {
+                display       "PLL input clock frequency"
+                flavor        data
+                calculated    { CYGNUM_HAL_CORTEXM_LM3S8XX_XTAL_FREQ }
+                legal_values  { 3579545 3686400 4000000 4096000 4915200 5000000 \
+                                5120000 6000000 6144000 7372800 8000000 8192000 }
+                description   "
+                    PLL output frequency is fixed to 200 MHz.  Using the
+                    PLL puts more constraints to the external reference
+                    clock. The PLL input clock frequency is not defined
+                    if internal chip reference clock is used."
+            }
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK {
+            display       "System Clock frequency"
+            flavor        data
+            calculated    { CYGHWR_HAL_CORTEXM_LM3S8XX_PLL ? ( 200000000 / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) : CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT ? ( CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL_FREQ / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) : ( CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ / CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV ) }
+            legal_values  { 1000000 to 50000000 }
+            description   "
+                The chip system clock frequency is 200 MHz divided
+                by the system clock divider when the PLL is in used,
+                otherwise the frequency value is the chip source clock
+                frequency divided by the system clock divider."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV {
+            display       "System Clock divider"
+            flavor        data
+            default_value 4
+            legal_values  { 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 }
+            description   "
+                Select the system clock divider."
+        }
+    }
+
+    # UART0 is available for diagnostic/debug use.
+    implements   CYGINT_HAL_CORTEXM_LM3S_UART0
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor        data
+        calculated    1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display       "Debug serial port"
+        active_if      CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        calculated    0
+        description   "
+            This option selects which port will be used to connect to
+            a host running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display       "Diagnostic serial port"
+         active_if     CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         calculated    0
+         description   "
+             This option selects which port will be used for diagnostic
+             output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.  Note: this should match the value chosen
+            for the GDB port if the diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the GDB
+            connection.  Note: this should match the value chosen for
+            the console port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display       "Global build options"
+        flavor        none
+        parent        CYGPKG_NONE
+        description   "
+            Global build options including control over compiler flags,
+            linker flags and choice of toolchain."
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display       "Global command prefix"
+            flavor        data
+            no_define
+            default_value { "arm-eabi" }
+            description   "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display       "Global compiler flags"
+            flavor        data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which
+                are used to compile all packages by default. Individual
+                packages may define options which override these global
+                flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display       "Global linker flags"
+            flavor        data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global
+                flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on
+            the board, and this ROM monitor may process exceptions or
+            interrupts generated from the application. This enables
+            features such as utilizing a separate interrupt stack when
+            exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent          CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM
+             monitor.  This support changes various eCos semantics such
+             as the encoding of diagnostic output, or the overriding of
+             hardware interrupt vectors.
+             Firstly there is \"Generic\" support which prevents the
+             HAL from overriding the hardware vectors that it does not
+             use, to instead allow an installed ROM monitor to handle
+             them. This is the most basic support which is likely to be
+             common to most implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included
+             in the ROM monitor or boot ROM."
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_LM3S8XX_GDB_STUBS {
+        display       "Create StubROM SREC and binary files"
+        active_if     CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated    1
+        requires      { CYG_HAL_STARTUP == "ROM" }
+        description   "
+            This component causes the ELF image generated by the build
+            process to be converted to S-Record and binary files."
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_LM3S8XX_TESTS {
+        display       "Stellaris Cortex-M3 800 Series tests"
+        active_if     CYGPKG_KERNEL
+        flavor        data
+        no_define
+        calculated    { "tests/timers" }
+        description   "
+            This option specifies the set of tests for the Stellaris
+            Cortex-M3 800 Series HAL."
+    }
+}
+
+# EOF hal_cortex_lm3s8xx.cdl
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.h b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.h
new file mode 100644
index 0000000..555211f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.h
@@ -0,0 +1,19 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00002000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (0x00010000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram_SIZE (0x00000000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.ldi b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.ldi
new file mode 100644
index 0000000..3a1d61d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/pkgconf/mlt_cortexm_lm3s8xx_rom.ldi
@@ -0,0 +1,34 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00002000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x00000000, LENGTH = 0x00010000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000400, FOLLOWING (.got))
+    SECTION_data (sram, ALIGN (0x8), FOLLOWING (.sram))
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*8;
+
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_arch.h b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_arch.h
new file mode 100644
index 0000000..5e8f85b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_arch.h
@@ -0,0 +1,60 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     Stellaris Cortex-M3 800 Series specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lm3s8xx.h>
+
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_ARCH_H
+// EOF plf_arch.h
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_intr.h b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_intr.h
new file mode 100644
index 0000000..2246e67
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_intr.h
@@ -0,0 +1,61 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     Stellaris Cortex-M3 800 Series specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lm3s8xx.h>
+
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX       (CYGNUM_HAL_INTERRUPT_FMS)
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_INTR_H
+// EOF plf_intr.h
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_io.h b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_io.h
new file mode 100644
index 0000000..dabc676
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/include/plf_io.h
@@ -0,0 +1,153 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Stellaris Cortex-M3 800 Series specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+#include <pkgconf/hal_cortexm_lm3s8xx.h>
+
+// Number of IOs on port A / B and C
+#define CYGHWR_HAL_LM3S_GPIOA_IOs                 6
+#define CYGHWR_HAL_LM3S_GPIOB_IOs                 8
+#define CYGHWR_HAL_LM3S_GPIOC_IOs                 8
+
+// Number of IOs on port D and E varies
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 8
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 6
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S828)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 4
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 2
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 8
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 2
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 8
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 4
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817)|| \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_GPIOD_IOs                 6
+#define CYGHWR_HAL_LM3S_GPIOE_IOs                 2
+#endif
+
+// UART1
+#define CYGHWR_HAL_LM3S_UART1_TX                  CYGHWR_HAL_LM3S_GPIO( D, 2, PERIPH, NONE, NONE, DISABLE )
+#define CYGHWR_HAL_LM3S_UART1_RX                  CYGHWR_HAL_LM3S_GPIO( D, 3, PERIPH, NONE, NONE, DISABLE )
+#define CYGHWR_HAL_LM3S_P_UART1_GPIO              CYGHWR_HAL_LM3S_P_GPIOD
+
+// Number of ADC channel
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815)
+#define CYGHWR_HAL_LM3S_ADC0_CHAN                 2
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811)
+#define CYGHWR_HAL_LM3S_ADC0_CHAN                 4
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_ADC0_CHAN                 6
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S828) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808)
+#define CYGHWR_HAL_LM3S_ADC0_CHAN                 8
+#endif
+
+// Number of PWM channel
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812)
+#define CYGHWR_HAL_LM3S_MAX_PWM_CHAN              2
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_PWM_CHAN                  6
+#endif
+
+// Number of I2C channels
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S828)
+#define CYGHWR_HAL_LM3S_I2C_CHAN                  1
+// I2C
+#define CYGHWR_HAL_LM3S_I2C_SCL                   CYGHWR_HAL_LM3S_GPIO( B, 3, PERIPH, 2_MA, OP_PULLUP, DISABLE )
+#define CYGHWR_HAL_LM3S_I2C_SDA                   CYGHWR_HAL_LM3S_GPIO( B, 2, PERIPH, 2_MA, OP_PULLUP, DISABLE )
+#endif
+
+// Number of analog Comparator
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S800) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S815)
+#define CYGHWR_HAL_LM3S_AC_CHAN                   3
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S808) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S811) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S812) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S817) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_AC_CHAN                   1
+#endif
+
+// Number of Quadrature Encoder Channel
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S801) || \
+        defined(CYGHWR_HAL_CORTEXM_LM3S8XX_LM3S818)
+#define CYGHWR_HAL_LM3S_QEI_CHAN                  1
+#endif
+
+// SSI channel
+#define CYGHWR_HAL_LM3S_SSI_CHAN                  1
+
+// Global timer channel
+#define CYGHWR_HAL_LM3S_GPTIM_CHAN                3
+
+//-----------------------------------------------------------------------------
+#endif //CYGONCE_HAL_PLF_IO_H
+// EOF plf_io.h
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/misc/default_ROM.ecm b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/misc/default_ROM.ecm
new file mode 100644
index 0000000..34dc97d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/misc/default_ROM.ecm
@@ -0,0 +1,22 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template minimal ;
+    package CYGPKG_KERNEL current ;
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 1536
+};
+
+cdl_option CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE {
+    user_value 1536
+};
+\ No newline at end of file
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/src/lm3s8xx_misc.c b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/src/lm3s8xx_misc.c
new file mode 100644
index 0000000..f611e6c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/src/lm3s8xx_misc.c
@@ -0,0 +1,246 @@
+//==========================================================================
+//
+//      lm3s8xx_misc.c
+//
+//      Stellaris Cortex-M3 800 Series HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2010-11-21
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+#include <cyg/hal/var_io.h>
+
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL)
+#if CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 3579545
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL CYGHWR_HAL_LM3S_SC_RCC_XTAL(4)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 3686400
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(5)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(6)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4096000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(7)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 4915200
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(8)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 5000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(9)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 5120000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(10)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 6000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(11)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 6144000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(12)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 7372800
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(13)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 8000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(14)
+#elif CYGHWR_HAL_CORTEXM_LM3S8XX_PLL_INPUT == 8192000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL  CYGHWR_HAL_LM3S_SC_RCC_XTAL(15)
+#endif
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT)
+#if CYGNUM_HAL_CORTEXM_LM3S8XX_CLOCK_INT_FREQ == 12000000
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC
+#else
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC_DIV4
+#endif
+#else
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MOSC
+#endif
+
+#if CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV != 1
+#define CYGHWR_HAL_CORTEXM_LM3S8XX_SC_RCC_SYSDIV_VAL \
+        CYGHWR_HAL_LM3S_SC_RCC_SYSDIV( (CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV-1) );
+#endif
+
+//==========================================================================
+
+void hal_lm3s8xx_periph_set( cyg_uint32 periph, cyg_uint32 on_off );
+
+__externC cyg_uint32 hal_cortexm_systick_clock;
+__externC cyg_uint32 hal_lm3s_sysclk;
+
+//==========================================================================
+// System init
+//
+// This code runs before the DATA is copied from ROM and the BSS cleared,
+// hence it cannot make use of static variables or data tables.
+
+__externC void
+hal_system_init( void )
+{
+}
+
+
+//==========================================================================
+// Setup up system clocks
+//
+void
+hal_start_clocks( void )
+{
+    CYG_ADDRESS     sc = CYGHWR_HAL_LM3S_SC;
+    cyg_uint32      rcc;
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL)
+    cyg_uint32      plllmis = CYGHWR_HAL_LM3S_SC_MISC_PLLLMIS;
+    cyg_uint32      plllris = CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS;
+    volatile cyg_uint16 wait;
+#endif
+
+    // At power up, the LM3S8xx is setup to use external oscillator.
+    // The PLL is powered down and bypass. Same goes for the system
+    // clock divider.
+
+    // For JTAG cold restart, first we make sure the PLL and system
+    // clock divider are bypassed, enable all clock source and shutdown
+    // the PLL.
+
+    HAL_READ_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    rcc &= ~( CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV |
+              CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS |
+              CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS );
+
+    rcc |= CYGHWR_HAL_LM3S_SC_RCC_BYPASS;
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    rcc |= ( CYGHWR_HAL_LM3S_SC_RCC_PWRDN | CYGHWR_HAL_LM3S_SC_RCC_OEN );
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    // PLL is setup if in use
+    //
+    // The XTAL frequency is configured. The PLL is powered and
+    // its output is enable
+
+    // Setup Clock Source
+    rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_OSCSRC_FIELD;
+
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL)
+
+    // Clear PLL lock bit
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_MISC, plllmis );
+
+    rcc &= ~( CYGHWR_HAL_LM3S_SC_RCC_XTAL_MASK |
+              ( CYGHWR_HAL_LM3S_SC_RCC_PWRDN ) |
+              ( CYGHWR_HAL_LM3S_SC_RCC_OEN ) );
+
+    rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_XTAL;
+
+#endif
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    //
+    // Setup System Clock divider
+    //
+
+#if CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK_DIV != 1
+
+    // Use system clock divider
+    rcc |= CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV;
+
+    // Clear system clock divider bits
+    rcc &= ~CYGHWR_HAL_LM3S_SC_RCC_SYSDIV_MASK;
+
+    // Configure divider
+    rcc |= CYGHWR_HAL_CORTEXM_LM3S8XX_SC_RCC_SYSDIV_VAL;
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+#endif
+
+    // Wait for PLL lock before feeding the clock to the
+    // device
+
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_PLL)
+
+    // Wait for PLL lock, potentially a dead lock
+    plllris = 0;
+    while ( 0 == ( plllris & CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS ) ) {
+        // Wait
+        for ( wait = 0; wait < ( ( 2 ^ 16 ) - 1 ); wait++ )
+            HAL_READ_UINT32( sc + CYGHWR_HAL_LM3S_SC_RIS, plllris );
+    }
+
+    // Clear bypass bit
+    rcc &= ~CYGHWR_HAL_LM3S_SC_RCC_BYPASS;
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+#endif
+
+    //
+    // Disable clock source not in use
+    //
+#if defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_EXT)
+
+    rcc |= CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS;
+
+#elif defined(CYGHWR_HAL_CORTEXM_LM3S8XX_CLOCK_INT)
+
+    rcc |= CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS;
+
+#endif
+
+    HAL_WRITE_UINT32( sc + CYGHWR_HAL_LM3S_SC_RCC, rcc );
+
+    hal_cortexm_systick_clock = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK;
+    hal_lm3s_sysclk = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK;
+}
+
+//==========================================================================
+// EOF lm3s8xx_misc.c
diff --git a/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/tests/timers.c b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/tests/timers.c
new file mode 100644
index 0000000..e8a5a82
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/lm3s8xx/current/tests/timers.c
@@ -0,0 +1,359 @@
+//=============================================================================
+//
+//      timers.c
+//
+//      Test for Stellaris Cortex-M3 Device Timers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg for STM32
+//               ccoutand updated for Stellaris Cortex-M3 Devices
+// Date:         2011-01-18
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#if defined(CYGPKG_KERNEL)
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/testcase.h>
+
+//=============================================================================
+// Check all required packages and components are present
+
+#if !defined(CYGPKG_KERNEL) || !defined(CYGPKG_KERNEL_API)
+# define NA_MSG  "Configuration insufficient"
+#endif
+
+//=============================================================================
+// If everything is present, compile the full test.
+
+#ifndef NA_MSG
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+
+#include <cyg/kernel/kapi.h>
+#include <cyg/infra/diag.h>
+#include <string.h>
+
+//=============================================================================
+
+#define LOOPS      24                  // 2 minutes
+#define SINGLE_TIMER 0                 // Full / Single timer test
+
+static int      test_stack[( CYGNUM_HAL_STACK_SIZE_MINIMUM / sizeof( int ) )];
+static cyg_thread test_thread;
+static cyg_handle_t main_thread;
+
+//=============================================================================
+
+struct timer {
+    cyg_uint32      timer;
+    cyg_uint32      base;
+    cyg_uint32      periph;
+    cyg_uint32      vector;
+    cyg_uint32      priority;
+    cyg_uint32      interval;
+
+    cyg_uint32      ticks;
+
+    cyg_uint32      preempt[10];
+
+    cyg_uint32      preempt_dsr[10];
+    cyg_uint32      dsr_count[10];
+
+    cyg_interrupt   interrupt_object;
+    cyg_handle_t    interrupt_handle;
+};
+
+struct timer    timers[] = {
+#if SINGLE_TIMER
+    {1, CYGHWR_HAL_LM3S_GPTIM0, CYGHWR_HAL_LM3S_P_TIMER0,
+     CYGNUM_HAL_INTERRUPT_GTIM0_A, 0x20, 1000},
+#else
+    {1, CYGHWR_HAL_LM3S_GPTIM0, CYGHWR_HAL_LM3S_P_TIMER0,
+     CYGNUM_HAL_INTERRUPT_GTIM0_A, 0x20, 127},
+    {2, CYGHWR_HAL_LM3S_GPTIM1, CYGHWR_HAL_LM3S_P_TIMER1,
+     CYGNUM_HAL_INTERRUPT_GTIM1_A, 0x60, 355},
+    {3, CYGHWR_HAL_LM3S_GPTIM2, CYGHWR_HAL_LM3S_P_TIMER2,
+     CYGNUM_HAL_INTERRUPT_GTIM2_A, 0x80, 731},
+#endif
+    {0, 0, 0, 0}
+};
+
+
+//=============================================================================
+
+volatile cyg_uint32 ticks = 0;
+volatile cyg_uint32 nesting = 0;
+volatile cyg_uint32 max_nesting = 0;
+volatile cyg_uint32 max_nesting_seen = 0;
+volatile cyg_uint32 current = 0;
+volatile cyg_uint32 in_dsr = 0;
+
+
+//=============================================================================
+
+void
+init_timer( cyg_uint32 base, cyg_uint32 periph, cyg_uint32 interval )
+{
+    cyg_uint32      period = CYGHWR_HAL_CORTEXM_LM3S8XX_SYSCLK;
+
+    CYGHWR_HAL_LM3S_PERIPH_SET( periph, 1 );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CTL, 0x0000 );
+
+    period = period / 1000000;
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAPR, period );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CFG,
+                      CYGHWR_HAL_LM3S_GPTIM_CFG_16BIT );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAMR,
+                      CYGHWR_HAL_LM3S_GPTIM_TAMR_PERIODIC );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAILR, interval );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_ICR,
+                      CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_IMR,
+                      CYGHWR_HAL_LM3S_GPTIM_IMR_TATOIM );
+
+    HAL_WRITE_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_CTL,
+                      CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN );
+}
+
+
+//=============================================================================
+
+cyg_uint32
+timer_isr( cyg_uint32 vector, CYG_ADDRWORD data )
+{
+    struct timer   *t = ( struct timer * )data;
+    cyg_uint32      preempt = current;
+    CYG_ADDRWORD    base = t->base;
+    cyg_uint32      cnt;
+
+    current = t->timer;
+    t->ticks++;
+    ticks++;
+    t->preempt[preempt]++;
+    nesting++;
+
+    // Count only first ISR to preempt a DSR
+    if( preempt == 0 )
+        t->preempt_dsr[in_dsr]++;
+
+    HAL_WRITE_UINT32( t->base + CYGHWR_HAL_LM3S_GPTIM_ICR,
+                      CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT );
+
+    if( nesting > max_nesting )
+        max_nesting = nesting;
+
+    // Loiter here for a proportion of the timer interval to give
+    // other timers the chance to preempt us.
+    do {
+        HAL_READ_UINT32( base + CYGHWR_HAL_LM3S_GPTIM_TAR, cnt );
+    } while( cnt < t->interval / 10 );
+
+    nesting--;
+    current = preempt;
+
+    if( ( t->ticks % 10 ) == 0 )
+        return 3;
+    else
+        return 1;
+}
+
+
+//=============================================================================
+
+void
+timer_dsr( cyg_uint32 vector, cyg_uint32 count, CYG_ADDRWORD data )
+{
+    struct timer   *t = ( struct timer * )data;
+    int             i;
+
+    in_dsr = t->timer;
+
+    if( count >= 8 )
+        count = 8;
+
+    t->dsr_count[count]++;
+
+    // Loiter for a while
+    for( i = 0; i < t->interval / 10; i++ )
+        continue;
+
+    in_dsr = 0;
+}
+
+
+//=============================================================================
+
+void
+timers_test( cyg_addrword_t data )
+{
+    int             loops = LOOPS;
+    int             i;
+    CYG_INTERRUPT_STATE istate;
+
+    CYG_TEST_INIT(  );
+
+    CYG_TEST_INFO( "Start Timers test" );
+
+    for( i = 0; timers[i].timer != 0; i++ ) {
+        struct timer   *t = &timers[i];
+
+        init_timer( t->base, t->periph, t->interval );
+
+        cyg_interrupt_create( t->vector,
+                              t->priority,
+                              ( cyg_addrword_t )t,
+                              timer_isr,
+                              timer_dsr,
+                              &t->interrupt_handle, &t->interrupt_object );
+
+        cyg_interrupt_attach( t->interrupt_handle );
+        cyg_interrupt_unmask( t->vector );
+
+    }
+
+    while( loops-- ) {
+        int             j;
+
+        // 5 second delay
+        cyg_thread_delay( 5 * 100 );
+
+        // Disable interrupts while we print details, otherwise it
+        // comes out very slowly.
+        HAL_DISABLE_INTERRUPTS( istate );
+
+        if( max_nesting > max_nesting_seen )
+            max_nesting_seen = max_nesting;
+
+        diag_printf( "\nISRs max_nesting %d max_nesting_seen %d\n",
+                     max_nesting, max_nesting_seen );
+        max_nesting = 0;
+
+        diag_printf( " T      Ticks " );
+
+        for( j = 0; j < 9; j++ )
+            diag_printf( "%9d ", j );
+        diag_printf( "\n" );
+
+        for( i = 0; timers[i].timer != 0; i++ ) {
+            struct timer   *t = &timers[i];
+
+            diag_printf( "%2d: %9d ", t->timer, t->ticks );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf( "%9d ", t->preempt[j] );
+            diag_printf( "\n" );
+
+        }
+
+        diag_printf( "DSRs\n" );
+
+        diag_printf( " T:           " );
+
+        for( j = 0; j < 9; j++ )
+            diag_printf( "%9d ", j );
+        diag_printf( "\n" );
+
+        for( i = 0; timers[i].timer != 0; i++ ) {
+            struct timer   *t = &timers[i];
+
+            diag_printf( "%2d:  preempt: ", t->timer );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf( "%9d ", t->preempt_dsr[j] );
+            diag_printf( "\n" );
+
+            diag_printf( "       count: " );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf( "%9d ", t->dsr_count[j] );
+            diag_printf( "\n" );
+        }
+
+        HAL_RESTORE_INTERRUPTS( istate );
+    }
+
+    CYG_TEST_PASS_FINISH( "Timers test" );
+}
+
+
+//=============================================================================
+
+void
+cyg_user_start( void )
+{
+    cyg_thread_create( 0,              // Priority
+                       timers_test,    //
+                       0,              //
+                       "timers test",  // Name
+                       test_stack,     // Stack
+                       CYGNUM_HAL_STACK_SIZE_MINIMUM,   // Stack size
+                       &main_thread,   // Handle
+                       &test_thread    // Thread data structure
+         );
+    cyg_thread_resume( main_thread );
+}
+
+//=============================================================================
+
+#else // NA_MSG
+
+void
+cyg_user_start( void )
+{
+    CYG_TEST_NA( NA_MSG );
+}
+
+#endif // NA_MSG
+
+//=============================================================================
+// EOF timers.c
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/ChangeLog b/ecos/packages/hal/cortexm/lm3s/var/current/ChangeLog
new file mode 100644
index 0000000..ef8b22a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/ChangeLog
@@ -0,0 +1,38 @@
+2011-01-18  Christophe Coutand  <ccoutand@stmi.com>
+
+	* cdl/hal_cortexm_lm3s.cdl
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/var_arch.h:
+	* include/variant.inc:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* src/hal_diag.c:
+	* src/lm3s_misc.c:
+	New package -- Stellaris Cortex M3 variant HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
+
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/cdl/hal_cortexm_lm3s.cdl b/ecos/packages/hal/cortexm/lm3s/var/current/cdl/hal_cortexm_lm3s.cdl
new file mode 100644
index 0000000..1953681
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/cdl/hal_cortexm_lm3s.cdl
@@ -0,0 +1,123 @@
+##==========================================================================
+##
+##    hal_cortexm_lm3s.cdl
+##
+##    Stellaris Cortex-M3 variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ccoutand
+## Date:         2011-01-18
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LM3S {
+    display       "Stellaris Cortex-M3 from Luminary Micro variant HAL"
+    parent        CYGPKG_HAL_CORTEXM
+    define_header hal_cortexm_lm3s.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        This package provides generic support for the Cortex-M3 based
+        Stellaris microcontroller family.  It is also necessary to select
+        a variant and platform HAL package."
+
+    compile       hal_diag.c lm3s_misc.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M3" }
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+
+    # Let the architectural HAL see this variant's files
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_IO_H"
+        puts $::cdl_system_header "#define CYGBLD_HAL_CORTEXM_VAR_ARCH_H"
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LM3S {
+        display       "Stellaris Cortex-M3 variant in use"
+        flavor        data
+        default_value { "LM3S8XX" }
+        legal_values  { "LM3S8XX" }
+        description   "
+            Currently only supported the Stellaris Cortex-M3 800 Series."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU priority levels"
+        flavor        data
+        calculated    3
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M3
+            CPU implements."
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    0xC0
+        description   "
+            Set clock ISR priority to lowest priority."
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART0 {
+        display       "Platform has UART0 serial port"
+        description   "
+            The platform has a socket on UART0."
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART1 {
+        display       "Platform has UART1 serial port"
+        description   "
+            The platform has a socket on UART1."
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_LM3S_UART2 {
+        display       "Platform has UART2 serial port"
+        description   "
+            The platform has a socket on UART2."
+    }
+
+}
+
+# EOF hal_cortex_lm3s.cdl
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/lm3s/var/current/include/hal_cache.h
new file mode 100644
index 0000000..450f2bf
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/include/hal_cache.h
@@ -0,0 +1,66 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Contributors: 
+// Date:         2011-01-18
+// Purpose:      Cache control API
+// Description:  The Stellaris LM3S Cortex-M3 microcontroller does not require
+//               cache control. File is kept empty.
+//
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/lm3s/var/current/include/hal_diag.h
new file mode 100644
index 0000000..9bf882f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/include/hal_diag.h
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     HAL diagnostics
+// Description: 
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+# define HAL_DIAG_INIT()          hal_if_diag_init()
+# define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+# define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void  hal_lm3s_diag_init(void);
+__externC void  hal_lm3s_diag_putc(char);
+__externC cyg_uint8 hal_lm3s_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_lm3s_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_lm3s_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_lm3s_diag_getc()
+# endif
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_DIAG_H
+// EOF of hal_diag.h
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/lm3s/var/current/include/plf_stub.h
new file mode 100644
index 0000000..0b5c216
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/include/plf_stub.h
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     Platform HAL stub support for Stellaris Cortex-M3
+//              variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/cortexm_stub.h>       // architecture stub support
+
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/lm3s/var/current/include/var_arch.h
new file mode 100644
index 0000000..424f196
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/include/var_arch.h
@@ -0,0 +1,61 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      Stellaris Cortex-M3 variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Purpose:      Stellaris Cortex-M3 variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_ARCH_H
+// EOF of var_arch.h
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/lm3s/var/current/include/var_intr.h
new file mode 100644
index 0000000..075b681
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/include/var_intr.h
@@ -0,0 +1,119 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for Stellaris Cortex-M3 variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for Stellaris Cortex-M3
+//               are defined here.
+//              
+// Usage:        #include <cyg/hal/var_intr.h>
+//               However applications should include using <cyg/hal/hal_intr.h>
+//               instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_GPIOA          (0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOB          (1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOC          (2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOD          (3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOE          (4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART0          (5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART1          (6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SSI0           (7+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C            (8+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM0           (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM1           (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM2           (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_QIE            (13+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ADC0_S0        (14+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ADC0_S1        (15+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ADC0_S2        (16+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ADC0_S3        (17+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_WDT            (18+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM0_A        (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM0_B        (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM1_A        (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM1_B        (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM2_A        (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM2_B        (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AC0            (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AC1            (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AC2            (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SCTL           (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_FMS            (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOF          (30+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOG          (31+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GPIOH          (32+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM3_A        (35+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_GTIM3_B        (36+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN0           (39+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ETH0           (42+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_HIM            (43+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#ifndef CYGNUM_HAL_INTERRUPT_NVIC_MAX
+# define CYGNUM_HAL_INTERRUPT_NVIC_MAX      (CYGNUM_HAL_INTERRUPT_HIM)
+#endif
+
+#define CYGNUM_HAL_ISR_MIN                  0
+#ifndef CYGNUM_HAL_ISR_MAX
+# define CYGNUM_HAL_ISR_MAX                 (CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+#define CYGNUM_HAL_ISR_COUNT                (CYGNUM_HAL_ISR_MAX + 1)
+
+#define CYGNUM_HAL_VSR_MIN                  0
+#ifndef CYGNUM_HAL_VSR_MAX
+# define CYGNUM_HAL_VSR_MAX                 (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+#define CYGNUM_HAL_VSR_COUNT                (CYGNUM_HAL_VSR_MAX+1)
+
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/include/var_io.h b/ecos/packages/hal/cortexm/lm3s/var/current/include/var_io.h
new file mode 100644
index 0000000..7e2ffc0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/include/var_io.h
@@ -0,0 +1,1371 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ccoutand
+// Date:        2011-01-18
+// Purpose:     Stellaris Cortex-M3 variant specific registers
+// Description: 
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_lm3s.h>
+
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Peripherals
+
+#define CYGHWR_HAL_LM3S_FLASH                    0x00000000
+#define CYGHWR_HAL_LM3S_SRAM                     0x20000000
+
+#define CYGHWR_HAL_LM3S_WDT0                     0x40000000
+#define CYGHWR_HAL_LM3S_GPIOA                    0x40004000
+#define CYGHWR_HAL_LM3S_GPIOB                    0x40005000
+#define CYGHWR_HAL_LM3S_GPIOC                    0x40006000
+#define CYGHWR_HAL_LM3S_GPIOD                    0x40007000
+#define CYGHWR_HAL_LM3S_SSI0                     0x40008000
+#define CYGHWR_HAL_LM3S_SSI1                     0x40009000
+#define CYGHWR_HAL_LM3S_UART0                    0x4000C000
+#define CYGHWR_HAL_LM3S_UART1                    0x4000D000
+#define CYGHWR_HAL_LM3S_UART2                    0x4000E000
+#define CYGHWR_HAL_LM3S_I2C_M0                   0x40020000
+#define CYGHWR_HAL_LM3S_I2C_S0                   0x40020800
+#define CYGHWR_HAL_LM3S_GPIOE                    0x40024000
+#define CYGHWR_HAL_LM3S_GPIOF                    0x40025000
+#define CYGHWR_HAL_LM3S_GPIOG                    0x40026000
+#define CYGHWR_HAL_LM3S_GPIOH                    0x40027000
+#define CYGHWR_HAL_LM3S_PWM                      0x40028000
+#define CYGHWR_HAL_LM3S_QEI0                     0x4002C000
+#define CYGHWR_HAL_LM3S_GPTIM0                   0x40030000
+#define CYGHWR_HAL_LM3S_GPTIM1                   0x40031000
+#define CYGHWR_HAL_LM3S_GPTIM2                   0x40032000
+#define CYGHWR_HAL_LM3S_GPTIM3                   0x40033000
+#define CYGHWR_HAL_LM3S_ADC0                     0x40038000
+#define CYGHWR_HAL_LM3S_AC                       0x4003C000
+#define CYGHWR_HAL_LM3S_CAN0                     0x40040000
+#define CYGHWR_HAL_LM3S_ETH0                     0x40048000
+#define CYGHWR_HAL_LM3S_FMC                      0x400FD000
+#define CYGHWR_HAL_LM3S_SC                       0x400FE000
+
+#define CYGHWR_HAL_LM3S_ITM                      0xE0000000
+#define CYGHWR_HAL_LM3S_DWT                      0xE0001000
+#define CYGHWR_HAL_LM3S_FPB                      0xE0002000
+#define CYGHWR_HAL_LM3S_CORTEXM3                 0xE000E000
+#define CYGHWR_HAL_LM3S_TPIU                     0xE0040000
+
+
+//=============================================================================
+// Device signature and ID registers
+
+#define CYGHWR_HAL_LM3S_MCU_ID                   (CYGHWR_HAL_LM3S_CORTEXM3 + 0xD00)
+#define CYGHWR_HAL_LM3S_MCU_ID_REV(__x)          ((__x)&0xF)
+#define CYGHWR_HAL_LM3S_MCU_PART_NO(__x)         (((__x)>>4)&0x0FFF)
+#define CYGHWR_HAL_LM3S_MCU_VAR_NO(__x)          (((__x)>>20)&0xF)
+
+
+//=============================================================================
+// System Control
+
+#define CYGHWR_HAL_LM3S_SC_DID0                  0x000
+#define CYGHWR_HAL_LM3S_SC_DID1                  0x004
+#define CYGHWR_HAL_LM3S_SC_DIC0                  0x008
+#define CYGHWR_HAL_LM3S_SC_DIC1                  0x010
+#define CYGHWR_HAL_LM3S_SC_DIC2                  0x014
+#define CYGHWR_HAL_LM3S_SC_DIC3                  0x018
+#define CYGHWR_HAL_LM3S_SC_DIC4                  0x01c
+#define CYGHWR_HAL_LM3S_SC_PBORCTL               0x030
+#define CYGHWR_HAL_LM3S_SC_LDORCTL               0x034
+#define CYGHWR_HAL_LM3S_SC_SRCR0                 0x040
+#define CYGHWR_HAL_LM3S_SC_SRCR1                 0x044
+#define CYGHWR_HAL_LM3S_SC_SRCR2                 0x048
+#define CYGHWR_HAL_LM3S_SC_RIS                   0x050
+#define CYGHWR_HAL_LM3S_SC_IMC                   0x054
+#define CYGHWR_HAL_LM3S_SC_MISC                  0x058
+#define CYGHWR_HAL_LM3S_SC_RESC                  0x05C
+#define CYGHWR_HAL_LM3S_SC_RCC                   0x060
+#define CYGHWR_HAL_LM3S_SC_PLLCFG                0x064
+#define CYGHWR_HAL_LM3S_SC_RCGC0                 0x100
+#define CYGHWR_HAL_LM3S_SC_RCGC1                 0x104
+#define CYGHWR_HAL_LM3S_SC_RCGC2                 0x108
+#define CYGHWR_HAL_LM3S_SC_SCGC0                 0x110
+#define CYGHWR_HAL_LM3S_SC_SCGC1                 0x114
+#define CYGHWR_HAL_LM3S_SC_SCGC2                 0x118
+#define CYGHWR_HAL_LM3S_SC_DCGC0                 0x120
+#define CYGHWR_HAL_LM3S_SC_DCGC1                 0x124
+#define CYGHWR_HAL_LM3S_SC_DCGC2                 0x128
+#define CYGHWR_HAL_LM3S_SC_FMPRE                 0x130
+#define CYGHWR_HAL_LM3S_SC_FMPPE                 0x134
+#define CYGHWR_HAL_LM3S_SC_USECRL                0x140
+#define CYGHWR_HAL_LM3S_SC_DSLPCLKCFG            0x144
+#define CYGHWR_HAL_LM3S_SC_CLKVCLR               0x150
+#define CYGHWR_HAL_LM3S_SC_LDOARST               0x160
+
+// PBORCTL bits
+#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORWT         BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORIOR        BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_PBORCTL_BORTIM(__x)   VALUE_(2,__x)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_SC_RIS_PLLFRIS           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RIS_BORRIS            BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RIS_LDORIS            BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_RIS_MOFRIS            BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RIS_IOFRIS            BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_RIS_CLFRIS            BIT_(5)
+#define CYGHWR_HAL_LM3S_SC_RIS_PLLLRIS           BIT_(6)
+
+// IMC bits
+#define CYGHWR_HAL_LM3S_SC_IMC_PLLFIM            BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_IMC_BORRIM            BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_IMC_LDOIM             BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_IMC_MOFIM             BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_IMC_IOFIM             BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_IMC_CLIM              BIT_(5)
+#define CYGHWR_HAL_LM3S_SC_IMC_PLLLFIM           BIT_(6)
+
+// MISC bits
+#define CYGHWR_HAL_LM3S_SC_MISC_BORMIS           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_MISC_LDOMIS           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_MISC_MOFMIS           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_MISC_IOFMIS           BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_MISC_CLMIS            BIT_(5)
+#define CYGHWR_HAL_LM3S_SC_MISC_PLLLMIS          BIT_(6)
+
+// RESC bits
+#define CYGHWR_HAL_LM3S_SC_RESC_EXT              BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RESC_POR              BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RESC_BOR              BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_RESC_WDT              BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RESC_SW               BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_RESC_LDO              BIT_(5)
+
+// RCC bits
+#define CYGHWR_HAL_LM3S_SC_RCC_MOSCDIS           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RCC_IOSCDIS           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RCC_MOSCVER           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_RCC_IOSCVER           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MOSC       VALUE_(4,0)
+#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC       VALUE_(4,1)
+#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_IOSC_DIV4  VALUE_(4,2)
+#define CYGHWR_HAL_LM3S_SC_RCC_OSCSRC_MASK       0x00000030
+#define CYGHWR_HAL_LM3S_SC_RCC_XTAL(__x)         VALUE_(6,__x)
+#define CYGHWR_HAL_LM3S_SC_RCC_XTAL_MASK         0x000003C0
+#define CYGHWR_HAL_LM3S_SC_RCC_PLLVER            BIT_(10)
+#define CYGHWR_HAL_LM3S_SC_RCC_BYPASS            BIT_(11)
+#define CYGHWR_HAL_LM3S_SC_RCC_OEN               BIT_(12)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWRDN             BIT_(13)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV2       VALUE_(14, 0x0)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV4       VALUE_(14, 0x1)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV8       VALUE_(14, 0x2)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV16      VALUE_(14, 0x3)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV32      VALUE_(14, 0x4)
+#define CYGHWR_HAL_LM3S_SC_RCC_PWMDIV_DIV64      VALUE_(14, 0x5)
+#define CYGHWR_HAL_LM3S_SC_RCC_USEPWMDIV         BIT_(20)
+#define CYGHWR_HAL_LM3S_SC_RCC_USESYSDIV         BIT_(22)
+#define CYGHWR_HAL_LM3S_SC_RCC_SYSDIV(__x)       VALUE_(23, __x)
+#define CYGHWR_HAL_LM3S_SC_RCC_SYSDIV_MASK       0x07800000
+#define CYGHWR_HAL_LM3S_SC_RCC_ACG               BIT_(27)
+
+// DSLPCLKCFG bits
+#define CYGHWR_HAL_LM3S_SC_DSLPCLKCFG_IOSC       BIT_(0)
+
+// CLKVCLR bits
+#define CYGHWR_HAL_LM3S_SC_CLKVCLR_VERCLR        BIT_(0)
+
+// LDOARST bits
+#define CYGHWR_HAL_LM3S_SC_LDOARST_BIT           BIT_(0)
+
+// RCGC0 bits
+#define CYGHWR_HAL_LM3S_SC_RCGC0_WDT0            BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_125K  VALUE_(8, 0x0)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_250K  VALUE_(8, 0x1)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_MAXADCSPD_500K  VALUE_(8, 0x2)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_ADC0            BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_RCGC0_PWM0            BIT_(20)
+
+// SCGC0 bits
+#define CYGHWR_HAL_LM3S_SC_SCGC0_WDT0            BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_125K  VALUE_(8, 0x0)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_250K  VALUE_(8, 0x1)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_MAXADCSPD_500K  VALUE_(8, 0x2)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_ADC0            BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_SCGC0_PWM0            BIT_(20)
+
+// DCGC0 bits
+#define CYGHWR_HAL_LM3S_SC_DCGC0_WDT0            BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_DCGC0_ADC0            BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_DCGC0_PWM0            BIT_(20)
+
+// RCGC1 bits
+#define CYGHWR_HAL_LM3S_SC_RCGC1_UART0           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_UART1           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_SSI0            BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_I2C0            BIT_(12)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER0          BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER1          BIT_(17)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_TIMER2          BIT_(18)
+#define CYGHWR_HAL_LM3S_SC_RCGC1_COMP0           BIT_(24)
+
+// SCSG1 bits
+#define CYGHWR_HAL_LM3S_SC_SCGC1_UART0           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_UART1           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_SSI0            BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_I2C0            BIT_(12)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER0          BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER1          BIT_(17)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_TIMER2          BIT_(18)
+#define CYGHWR_HAL_LM3S_SC_SCGC1_COMP0           BIT_(24)
+
+// DCSG1 bits
+#define CYGHWR_HAL_LM3S_SC_DCGC1_UART0           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_UART1           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_SSI0            BIT_(4)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_I2C0            BIT_(12)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER0          BIT_(16)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER1          BIT_(17)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_TIMER2          BIT_(18)
+#define CYGHWR_HAL_LM3S_SC_DCGC1_COMP0           BIT_(24)
+
+// RCGC2 bits
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOA           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOB           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOC           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOD           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_RCGC2_GPIOE           BIT_(4)
+
+// SCSG2 bits
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOA           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOB           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOC           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOD           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_SCGC2_GPIOE           BIT_(4)
+
+// DCSG2 bits
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOA           BIT_(0)
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOB           BIT_(1)
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOC           BIT_(2)
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOD           BIT_(3)
+#define CYGHWR_HAL_LM3S_SC_DCGC2_GPIOE           BIT_(4)
+
+// Define peripheral
+#define CYGHWR_HAL_LM3S_PERIPH_GC0               BIT_(31)
+#define CYGHWR_HAL_LM3S_P_WDT0                   ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_WDT0 )
+#define CYGHWR_HAL_LM3S_P_ADC0                   ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_ADC0 )
+#define CYGHWR_HAL_LM3S_P_PWM                    ( BIT_(31) | CYGHWR_HAL_LM3S_SC_SCGC0_PWM0 )
+#define CYGHWR_HAL_LM3S_PERIPH_GC1               BIT_(30)
+#define CYGHWR_HAL_LM3S_P_UART0                  ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_UART0 )
+#define CYGHWR_HAL_LM3S_P_UART1                  ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_UART1 )
+#define CYGHWR_HAL_LM3S_P_SSI0                   ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_SSI0 )
+#define CYGHWR_HAL_LM3S_P_I2C0                   ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_I2C0 )
+#define CYGHWR_HAL_LM3S_P_TIMER0                 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER0 )
+#define CYGHWR_HAL_LM3S_P_TIMER1                 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER1 )
+#define CYGHWR_HAL_LM3S_P_TIMER2                 ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_TIMER2 )
+#define CYGHWR_HAL_LM3S_P_COMP0                  ( BIT_(30) | CYGHWR_HAL_LM3S_SC_SCGC1_COMP0 )
+#define CYGHWR_HAL_LM3S_PERIPH_GC2               BIT_(29)
+#define CYGHWR_HAL_LM3S_P_GPIOA                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOA )
+#define CYGHWR_HAL_LM3S_P_GPIOB                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOB )
+#define CYGHWR_HAL_LM3S_P_GPIOC                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOC )
+#define CYGHWR_HAL_LM3S_P_GPIOD                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOD )
+#define CYGHWR_HAL_LM3S_P_GPIOE                  ( BIT_(29) | CYGHWR_HAL_LM3S_SC_RCGC2_GPIOE )
+
+__externC void hal_lm3s_periph_set( cyg_uint32 periph, cyg_uint32 on_off );
+
+#define CYGHWR_HAL_LM3S_PERIPH_SET(__periph, __on_off )  hal_lm3s_periph_set( __periph,  __on_off )
+
+//=============================================================================
+// Watchdog
+
+#define CYGHWR_HAL_LM3S_WDT_LOAD                 0x000
+#define CYGHWR_HAL_LM3S_WDT_VALUE                0x004
+#define CYGHWR_HAL_LM3S_WDT_CTL                  0x008
+#define CYGHWR_HAL_LM3S_WDT_ICR                  0x00c
+#define CYGHWR_HAL_LM3S_WDT_RIS                  0x010
+#define CYGHWR_HAL_LM3S_WDT_MIS                  0x014
+#define CYGHWR_HAL_LM3S_WDT_TEST                 0x418
+#define CYGHWR_HAL_LM3S_WDT_LOCK                 0xc00
+#define CYGHWR_HAL_LM3S_WDT_PID4                 0xfd0
+#define CYGHWR_HAL_LM3S_WDT_PID5                 0xfd4
+#define CYGHWR_HAL_LM3S_WDT_PID6                 0xfd8
+#define CYGHWR_HAL_LM3S_WDT_PID7                 0xfdc
+#define CYGHWR_HAL_LM3S_WDT_PID0                 0xfe0
+#define CYGHWR_HAL_LM3S_WDT_PID1                 0xfe4
+#define CYGHWR_HAL_LM3S_WDT_PID2                 0xfe8
+#define CYGHWR_HAL_LM3S_WDT_PID3                 0xfec
+#define CYGHWR_HAL_LM3S_WDT_PCID0                0xff0
+#define CYGHWR_HAL_LM3S_WDT_PCID1                0xff4
+#define CYGHWR_HAL_LM3S_WDT_PCID2                0xff8
+#define CYGHWR_HAL_LM3S_WDT_PCID3                0xffc
+
+
+#define CYGHWR_HAL_LM3S_WDT_CTL_INTEN            BIT_(0)
+#define CYGHWR_HAL_LM3S_WDT_CTL_RESEN            BIT_(1)
+
+#define CYGHWR_HAL_LM3S_WDT_RIS_RIS              BIT_(0)
+
+#define CYGHWR_HAL_LM3S_WDT_MIS_MIS              BIT_(0)
+
+#define CYGHWR_HAL_LM3S_WDT_TEST_STALL           BIT_(8)
+
+#define CYGHWR_HAL_LM3S_WDT_PID(__x)             ((__x)&0xFF)
+#define CYGHWR_HAL_LM3S_WDT_PCID(__x)            ((__x)&0xFF)
+
+
+//=============================================================================
+// GPIO ports
+
+#define CYGHWR_HAL_LM3S_GPIO_DATA                 0x000
+#define CYGHWR_HAL_LM3S_GPIO_DIR                  0x400
+#define CYGHWR_HAL_LM3S_GPIO_IS                   0x404
+#define CYGHWR_HAL_LM3S_GPIO_IBE                  0x408
+#define CYGHWR_HAL_LM3S_GPIO_IEV                  0x40c
+#define CYGHWR_HAL_LM3S_GPIO_IM                   0x410
+#define CYGHWR_HAL_LM3S_GPIO_RIS                  0x414
+#define CYGHWR_HAL_LM3S_GPIO_MIS                  0x418
+#define CYGHWR_HAL_LM3S_GPIO_ICR                  0x41c
+#define CYGHWR_HAL_LM3S_GPIO_AFSEL                0x420
+#define CYGHWR_HAL_LM3S_GPIO_DR2R                 0x500
+#define CYGHWR_HAL_LM3S_GPIO_DR4R                 0x504
+#define CYGHWR_HAL_LM3S_GPIO_DR8R                 0x508
+#define CYGHWR_HAL_LM3S_GPIO_ODR                  0x50c
+#define CYGHWR_HAL_LM3S_GPIO_PUR                  0x510
+#define CYGHWR_HAL_LM3S_GPIO_PDR                  0x514
+#define CYGHWR_HAL_LM3S_GPIO_SLR                  0x518
+#define CYGHWR_HAL_LM3S_GPIO_DEN                  0x51c
+#define CYGHWR_HAL_LM3S_GPIO_PID4                 0xfd0
+#define CYGHWR_HAL_LM3S_GPIO_PID5                 0xfd4
+#define CYGHWR_HAL_LM3S_GPIO_PID6                 0xfd8
+#define CYGHWR_HAL_LM3S_GPIO_PID7                 0xfdc
+#define CYGHWR_HAL_LM3S_GPIO_PID0                 0xfe0
+#define CYGHWR_HAL_LM3S_GPIO_PID1                 0xfe4
+#define CYGHWR_HAL_LM3S_GPIO_PID2                 0xfe8
+#define CYGHWR_HAL_LM3S_GPIO_PID3                 0xfec
+#define CYGHWR_HAL_LM3S_GPIO_PCID0                0xff0
+#define CYGHWR_HAL_LM3S_GPIO_PCID1                0xff4
+#define CYGHWR_HAL_LM3S_GPIO_PCID2                0xff8
+#define CYGHWR_HAL_LM3S_GPIO_PCID3                0xffc
+
+#define CYGHWR_HAL_LM3S_GPIO_DIR_IN               VALUE_(0,0)     // Input mode
+#define CYGHWR_HAL_LM3S_GPIO_DIR_OUT              VALUE_(0,1)     // Output mode
+
+#define CYGHWR_HAL_LM3S_GPIO_IS_EDGE_SENSE        VALUE_(0,0)     // Interrupt edge sensitive
+#define CYGHWR_HAL_LM3S_GPIO_IS_LEV_SENSE         VALUE_(0,1)     // Interrupt level sensitive
+
+#define CYGHWR_HAL_LM3S_GPIO_IBE_GPIOIEV          VALUE_(0,0)     // Interrupt control from GPIOIEV
+#define CYGHWR_HAL_LM3S_GPIO_IBE_BOTH_EDGE        VALUE_(0,1)     // Both edges can trigger interrupt
+
+#define CYGHWR_HAL_LM3S_GPIO_IEV_LOW              VALUE_(0,0)     // Falling edge or low triggers interrupt
+#define CYGHWR_HAL_LM3S_GPIO_IEV_HIGH             VALUE_(0,1)     // Rising edge or low triggers interrupt
+
+#define CYGHWR_HAL_LM3S_GPIO_IM_MASK              VALUE_(0,0)     // Interrupt is masked
+#define CYGHWR_HAL_LM3S_GPIO_IM_UMASK             VALUE_(0,1)
+
+// HAL definitions
+#define CYGHWR_HAL_LM3S_GPIO_MODE_IN              VALUE_(0,0)     // Input mode
+#define CYGHWR_HAL_LM3S_GPIO_MODE_OUT             VALUE_(0,1)     // Output mode
+#define CYGHWR_HAL_LM3S_GPIO_MODE_PERIPH          VALUE_(0,2)     // Peripheral function mode
+
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_NONE        VALUE_(2,0)     // Strength not specified
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_2_MA        VALUE_(2,1)     // Strength 2 mA
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_4_MA        VALUE_(2,2)     // Strength 4 mA
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH_8_MA        VALUE_(2,3)     // Strength 8 mA
+
+#define CYGHWR_HAL_LM3S_GPIO_CNF_NONE             VALUE_(4,0)     // Configuration not specified
+#define CYGHWR_HAL_LM3S_GPIO_CNF_PULLUP           VALUE_(4,1)     // Pull-up
+#define CYGHWR_HAL_LM3S_GPIO_CNF_PULLDOWN         VALUE_(4,2)     // Pull-down
+#define CYGHWR_HAL_LM3S_GPIO_CNF_OP               VALUE_(4,3)     // Open-drain
+#define CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP        VALUE_(4,4)     // Open-drain / Pull-up
+#define CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN      VALUE_(4,5)     // Open-drain / Pull-down
+#define CYGHWR_HAL_LM3S_GPIO_CNF_AIN              VALUE_(4,6)     // Analog
+
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_DISABLE          VALUE_(9,0)     // Interrupt disable
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_FALLING_EDGE     VALUE_(9,1)     // Interrupt on falling edge
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_RISING_EDGE      VALUE_(9,2)     // Interrupt on rising edge
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_BOTH_EDGES       VALUE_(9,3)     // Interrupt on both edges
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL        VALUE_(9,4)     // Interrupt on low level
+#define CYGHWR_HAL_LM3S_GPIO_IRQ_HIGH_LEVEL       VALUE_(9,5)     // Interrupt on high level
+
+// This macro packs the port number, bit number, mode, strength, irq and
+// configuration for a GPIO pin into a single word.
+// The packing puts:
+
+#define CYGHWR_HAL_LM3S_GPIO(                                           \
+    __port,                                                             \
+    __bit,                                                              \
+    __mode,                                                             \
+    __strength,                                                         \
+    __cnf,                                                              \
+    __irq)                                                              \
+(                                                                       \
+        (CYGHWR_HAL_LM3S_GPIO ## __port - CYGHWR_HAL_LM3S_GPIOA) |      \
+         (__bit << 24) |                                                \
+         (CYGHWR_HAL_LM3S_GPIO_MODE_ ## __mode) |                       \
+         (CYGHWR_HAL_LM3S_GPIO_STRENGTH_ ## __strength) |               \
+         (CYGHWR_HAL_LM3S_GPIO_IRQ_ ## __irq) |                         \
+         (CYGHWR_HAL_LM3S_GPIO_CNF_ ## __cnf)                           \
+)
+
+// Macros to extract encoded values
+#define CYGHWR_HAL_LM3S_GPIO_PORT(__pin)       (CYGHWR_HAL_LM3S_GPIOA+((__pin)&0x000FF000))
+#define CYGHWR_HAL_LM3S_GPIO_BIT(__pin)        (((__pin)>>24)&0x07)
+#define CYGHWR_HAL_LM3S_GPIO_MODE(__pin)       ((__pin)&0x0003)
+#define CYGHWR_HAL_LM3S_GPIO_STRENGTH(__pin)   ((__pin)&VALUE_(2,3))
+#define CYGHWR_HAL_LM3S_GPIO_CFG(__pin)        ((__pin)&VALUE_(4,7))
+#define CYGHWR_HAL_LM3S_GPIO_IRQ(__pin)        ((__pin)&VALUE_(9,7))
+
+#define CYGHWR_HAL_LM3S_GPIO_NONE              (0xFFFFFFFF)
+
+
+// Functions and macros to configure GPIO ports.
+
+__externC void hal_lm3s_gpio_set( cyg_uint32 pin );
+__externC void hal_lm3s_gpio_out( cyg_uint32 pin, int val );
+__externC void hal_lm3s_gpio_in ( cyg_uint32 pin, int *val );
+
+#define CYGHWR_HAL_LM3S_GPIO_SET(__pin )        hal_lm3s_gpio_set( __pin )
+#define CYGHWR_HAL_LM3S_GPIO_OUT(__pin, __val ) hal_lm3s_gpio_out( __pin, __val )
+#define CYGHWR_HAL_LM3S_GPIO_IN(__pin,  __val ) hal_lm3s_gpio_in( __pin, __val )
+
+
+//=============================================================================
+// UARTs
+
+#define CYGHWR_HAL_LM3S_UART_DR                   0x000
+#define CYGHWR_HAL_LM3S_UART_SR                   0x004
+#define CYGHWR_HAL_LM3S_UART_FR                   0x018
+#define CYGHWR_HAL_LM3S_UART_IBRD                 0x024
+#define CYGHWR_HAL_LM3S_UART_FBRD                 0x028
+#define CYGHWR_HAL_LM3S_UART_LCRH                 0x02c
+#define CYGHWR_HAL_LM3S_UART_CTL                  0x030
+#define CYGHWR_HAL_LM3S_UART_IFLS                 0x034
+#define CYGHWR_HAL_LM3S_UART_IM                   0x038
+#define CYGHWR_HAL_LM3S_UART_RIS                  0x03c
+#define CYGHWR_HAL_LM3S_UART_MIS                  0x040
+#define CYGHWR_HAL_LM3S_UART_ICR                  0x044
+#define CYGHWR_HAL_LM3S_UART_PID4                 0xfd0
+#define CYGHWR_HAL_LM3S_UART_PID5                 0xfd4
+#define CYGHWR_HAL_LM3S_UART_PID6                 0xfd8
+#define CYGHWR_HAL_LM3S_UART_PID7                 0xfdc
+#define CYGHWR_HAL_LM3S_UART_PID0                 0xfe0
+#define CYGHWR_HAL_LM3S_UART_PID1                 0xfe4
+#define CYGHWR_HAL_LM3S_UART_PID2                 0xfe8
+#define CYGHWR_HAL_LM3S_UART_PID3                 0xfec
+#define CYGHWR_HAL_LM3S_UART_PCID0                0xff0
+#define CYGHWR_HAL_LM3S_UART_PCID1                0xff4
+#define CYGHWR_HAL_LM3S_UART_PCID2                0xff8
+#define CYGHWR_HAL_LM3S_UART_PCID3                0xffc
+
+
+// DR Bits
+#define CYGHWR_HAL_LM3S_UART_DR_FE                BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_DR_PE                BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_DR_BE                BIT_(10)
+#define CYGHWR_HAL_LM3S_UART_DR_OE                BIT_(11)
+
+// SR Bits
+#define CYGHWR_HAL_LM3S_UART_SR_FE                BIT_(0)
+#define CYGHWR_HAL_LM3S_UART_SR_PE                BIT_(1)
+#define CYGHWR_HAL_LM3S_UART_SR_BE                BIT_(2)
+#define CYGHWR_HAL_LM3S_UART_SR_OE                BIT_(3)
+
+// FR bits
+#define CYGHWR_HAL_LM3S_UART_FR_BUSY              BIT_(3)
+#define CYGHWR_HAL_LM3S_UART_FR_RXFE              BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_FR_TXFF              BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_FR_RXFF              BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_FR_TXFE              BIT_(7)
+
+// LCRH bits
+#define CYGHWR_HAL_LM3S_UART_LCRH_BRK             BIT_(0)
+#define CYGHWR_HAL_LM3S_UART_LCRH_PEN             BIT_(1)
+#define CYGHWR_HAL_LM3S_UART_LCRH_EPS             BIT_(2)
+#define CYGHWR_HAL_LM3S_UART_LCRH_STP2            BIT_(3)
+#define CYGHWR_HAL_LM3S_UART_LCRH_FEN             BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_LCRH_WLEN(__x)       VALUE_(5,__x)
+#define CYGHWR_HAL_LM3S_UART_LCRH_WLEN_MASK       0x00000060
+#define CYGHWR_HAL_LM3S_UART_LCRH_SPS             BIT_(7)
+
+// CTL bits
+#define CYGHWR_HAL_LM3S_UART_CTL_UARTEN           BIT_(0)
+#define CYGHWR_HAL_LM3S_UART_CTL_LBE              BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_CTL_TXE              BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_CTL_RXE              BIT_(9)
+
+// IFLS bits
+#define CYGHWR_HAL_LM3S_UART_IFLS_RXIFLSEL(__x)   VALUE_(0,__x)
+#define CYGHWR_HAL_LM3S_UART_IFLS_RXIFLSEL_MASK   0x00000007
+#define CYGHWR_HAL_LM3S_UART_IFLS_TXIFLSEL(__x)   VALUE_(3,__x)
+#define CYGHWR_HAL_LM3S_UART_IFLS_TXIFLSEL_MASK   0x00000038
+
+// IM bits
+#define CYGHWR_HAL_LM3S_UART_IM_RXIM              BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_IM_TXIM              BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_IM_RTIM              BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_IM_FEIM              BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_IM_PEIM              BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_IM_BEIM              BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_IM_OEIM              BIT_(10)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_UART_RIS_RXRIS            BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_RIS_TXRIS            BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_RIS_RTRIS            BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_RIS_FERIS            BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_RIS_PERIS            BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_RIS_BERIS            BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_RIS_OERIS            BIT_(10)
+
+// MIS bits
+#define CYGHWR_HAL_LM3S_UART_MIS_RXMIS            BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_MIS_TXMIS            BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_MIS_RTMIS            BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_MIS_FEMIS            BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_MIS_PEMIS            BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_MIS_BEMIS            BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_MIS_OEMIS            BIT_(10)
+
+// ICR bits
+#define CYGHWR_HAL_LM3S_UART_ICR_RXIC             BIT_(4)
+#define CYGHWR_HAL_LM3S_UART_ICR_TXIC             BIT_(5)
+#define CYGHWR_HAL_LM3S_UART_ICR_RTIC             BIT_(6)
+#define CYGHWR_HAL_LM3S_UART_ICR_FEIC             BIT_(7)
+#define CYGHWR_HAL_LM3S_UART_ICR_PEIC             BIT_(8)
+#define CYGHWR_HAL_LM3S_UART_ICR_BEIC             BIT_(9)
+#define CYGHWR_HAL_LM3S_UART_ICR_OEIC             BIT_(10)
+
+// UARTO shall be connected to PortA 0/1 on all device
+#ifndef CYGHWR_HAL_LM3S_UART0_TX
+# define CYGHWR_HAL_LM3S_UART0_TX                 CYGHWR_HAL_LM3S_GPIO( A, 0, PERIPH, NONE, NONE, DISABLE )
+#endif
+#ifndef CYGHWR_HAL_LM3S_UART0_RX
+# define CYGHWR_HAL_LM3S_UART0_RX                 CYGHWR_HAL_LM3S_GPIO( A, 1, PERIPH, NONE, NONE, DISABLE )
+#endif
+#ifndef CYGHWR_HAL_LM3S_P_UART0_GPIO
+# define CYGHWR_HAL_LM3S_P_UART0_GPIO             CYGHWR_HAL_LM3S_P_GPIOA
+#endif
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_lm3s_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+#endif
+
+//=============================================================================
+// ADCs
+
+#ifdef CYGHWR_HAL_LM3S_ADC0_CHAN
+
+#define CYGHWR_HAL_LM3S_ADC_ACTSS                 0x0
+#define CYGHWR_HAL_LM3S_ADC_RIS                   0x4
+#define CYGHWR_HAL_LM3S_ADC_IMR                   0x8
+#define CYGHWR_HAL_LM3S_ADC_ISCR                  0xc
+#define CYGHWR_HAL_LM3S_ADC_OSR                   0x10
+#define CYGHWR_HAL_LM3S_ADC_EMUX                  0x14
+#define CYGHWR_HAL_LM3S_ADC_USR                   0x18
+#define CYGHWR_HAL_LM3S_ADC_SSPRI                 0x20
+#define CYGHWR_HAL_LM3S_ADC_PSSI                  0x28
+#define CYGHWR_HAL_LM3S_ADC_SAC                   0x30
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX0               0x40
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0               0x44
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO0              0x48
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO0_SR           0x4c
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX1               0x60
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL1               0x64
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO1              0x68
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO1_SR           0x6c
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX2               0x80
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL2               0x84
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO2              0x88
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO2_SR           0x8c
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX3               0xa0
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL3               0xa4
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO3              0xa8
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO3_SR           0xac
+#define CYGHWR_HAL_LM3S_ADC_TMLB                  0x100
+
+#define CYGHWR_HAL_LM3S_ADC_SAMPLE_SIZE           10
+
+// Active Sample Sequencer
+#define CYGHWR_HAL_LM3S_ADC_ACTSS_ASEN(__x)       VALUE_(((__x)&3),1)
+
+// Raw Interrupt Status
+#define CYGHWR_HAL_LM3S_ADC_RIS_INR(__x)          VALUE_(((__x)&3),1)
+
+// Interrupt Mask Register
+#define CYGHWR_HAL_LM3S_ADC_IMR_MASK(__x)         VALUE_(((__x)&3),1)
+
+// Interrupt Status and Clear Register
+#define CYGHWR_HAL_LM3S_ADC_ISCR_IN(__x)          VALUE_(((__x)&3),1)
+
+// Overflow Status Register
+#define CYGHWR_HAL_LM3S_ADC_OSR_OV(__x)           VALUE_(((__x)&3),1)
+
+// Event Multiplexer Select
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_CTRL(__x)     VALUE_((((__x)&3)<<2),0)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_AC0(__x)      VALUE_((((__x)&3)<<2),1)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_EXT(__x)      VALUE_((((__x)&3)<<2),4)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_TIMER(__x)    VALUE_((((__x)&3)<<2),5)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM0(__x)     VALUE_((((__x)&3)<<2),6)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM1(__x)     VALUE_((((__x)&3)<<2),7)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_PWM2(__x)     VALUE_((((__x)&3)<<2),8)
+#define CYGHWR_HAL_LM3S_ADC_EMUX_EM_ALWS(__x)     VALUE_((((__x)&3)<<2),15)
+
+// Underflow Status
+#define CYGHWR_HAL_LM3S_ADC_USR_UV(__x)           VALUE_(((__x)&3),1)
+
+// Sample Sequence Priority
+#define CYGHWR_HAL_LM3S_ADC_SSPRI_SS(__x, __y)    VALUE_((((__x)&3)<<2),(__y)&3)
+
+// Processor Sample Sequence Initiate
+#define CYGHWR_HAL_LM3S_ADC_PSSI_SS(__x)          VALUE_(((__x)&3),1)
+
+// Sample Averaging Control
+#define CYGHWR_HAL_LM3S_ADC_SAC_NO_OVER           0x0
+#define CYGHWR_HAL_LM3S_ADC_SAC_2X                0x1
+#define CYGHWR_HAL_LM3S_ADC_SAC_4X                0x2
+#define CYGHWR_HAL_LM3S_ADC_SAC_8X                0x3
+#define CYGHWR_HAL_LM3S_ADC_SAC_16X               0x4
+#define CYGHWR_HAL_LM3S_ADC_SAC_32X               0x5
+#define CYGHWR_HAL_LM3S_ADC_SAC_64X               0x6
+
+// Sample Sequence Input Multiplexer Select 0
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX0_V(_p_, _x_)   VALUE_((((_x_)&3)<<2),_p_)
+#define CYGHWR_HAL_LM3S_ADC_SS_MUX0_M(_x_)        VALUE_((((_x_)&3)<<2), 0x3)
+
+// Sample Sequence Control 0
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D0            BIT_(0)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END0          BIT_(1)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE0           BIT_(2)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS0           BIT_(3)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D1            BIT_(4)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END1          BIT_(5)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE1           BIT_(6)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS1           BIT_(7)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D2            BIT_(8)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END2          BIT_(9)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE2           BIT_(10)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS2           BIT_(11)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D3            BIT_(12)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END3          BIT_(13)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE3           BIT_(14)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS3           BIT_(15)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D4            BIT_(16)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END4          BIT_(17)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE4           BIT_(18)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS4           BIT_(19)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D5            BIT_(20)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END5          BIT_(21)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE5           BIT_(22)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS5           BIT_(23)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D6            BIT_(24)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END6          BIT_(25)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE6           BIT_(26)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS6           BIT_(27)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D7            BIT_(28)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END7          BIT_(29)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE7           BIT_(30)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS7           BIT_(31)
+
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_MASK(_x_)     VALUE_((((_x_)&3)<<2), 0x15)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_D(_x_)        VALUE_((((_x_)&3)<<2), 0x1)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_END(_x_)      VALUE_((((_x_)&3)<<2), 0x2)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_IE(_x_)       VALUE_((((_x_)&3)<<2), 0x4)
+#define CYGHWR_HAL_LM3S_ADC_SS_CTL0_TS(_x_)       VALUE_((((_x_)&3)<<2), 0x8)
+
+// Sequence FIFO Status
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_TPTR       0x0
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_HPTR       0x0
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_EMPTY      BIT_(8)
+#define CYGHWR_HAL_LM3S_ADC_SS_FIFO_SR_FULL       BIT_(12)
+
+#endif // CYGHWR_HAL_LM3S_ADC0_CHAN
+
+
+//=============================================================================
+// SSI interface register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_SSI_CHAN
+
+#define CYGHWR_HAL_LM3S_SSI_CR0                   0x000
+#define CYGHWR_HAL_LM3S_SSI_CR1                   0x004
+#define CYGHWR_HAL_LM3S_SSI_DR                    0x008
+#define CYGHWR_HAL_LM3S_SSI_SR                    0x00C
+#define CYGHWR_HAL_LM3S_SSI_CPSR                  0x010
+#define CYGHWR_HAL_LM3S_SSI_IM                    0x014
+#define CYGHWR_HAL_LM3S_SSI_RIS                   0x018
+#define CYGHWR_HAL_LM3S_SSI_MIS                   0x01c
+#define CYGHWR_HAL_LM3S_SSI_ICR                   0x020
+#define CYGHWR_HAL_LM3S_SSI_PID4                  0xfd0
+#define CYGHWR_HAL_LM3S_SSI_PID5                  0xfd4
+#define CYGHWR_HAL_LM3S_SSI_PID6                  0xfd8
+#define CYGHWR_HAL_LM3S_SSI_PID7                  0xfdc
+#define CYGHWR_HAL_LM3S_SSI_PID0                  0xfe0
+#define CYGHWR_HAL_LM3S_SSI_PID1                  0xfe4
+#define CYGHWR_HAL_LM3S_SSI_PID2                  0xfe8
+#define CYGHWR_HAL_LM3S_SSI_PID3                  0xfec
+#define CYGHWR_HAL_LM3S_SSI_PCID0                 0xff0
+#define CYGHWR_HAL_LM3S_SSI_PCID1                 0xff4
+#define CYGHWR_HAL_LM3S_SSI_PCID2                 0xff8
+#define CYGHWR_HAL_LM3S_SSI_PCID3                 0xffc
+
+
+// CR0 bits
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_4BIT          VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_5BIT          VALUE_(0, 0x4)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_6BIT          VALUE_(0, 0x5)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_7BIT          VALUE_(0, 0x6)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_8BIT          VALUE_(0, 0x7)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_9BIT          VALUE_(0, 0x8)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_10BIT         VALUE_(0, 0x9)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_11BIT         VALUE_(0, 0xa)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_12BIT         VALUE_(0, 0xb)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_13BIT         VALUE_(0, 0xc)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_14BIT         VALUE_(0, 0xd)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_15BIT         VALUE_(0, 0xe)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_16BIT         VALUE_(0, 0xf)
+#define CYGHWR_HAL_LM3S_SSI_CR0_DSS_MASK          0x0000000f
+#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_FSPIFF        VALUE_(4, 0x0)
+#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_TISSFF        VALUE_(4, 0x1)
+#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_MFF           VALUE_(4, 0x2)
+#define CYGHWR_HAL_LM3S_SSI_CR0_FRF_MASK          0x00000030
+#define CYGHWR_HAL_LM3S_SSI_CR0_SPO               BIT_(6)
+#define CYGHWR_HAL_LM3S_SSI_CR0_SPH               BIT_(7)
+#define CYGHWR_HAL_LM3S_SSI_CR0_SCR(__x)          VALUE_(8, ((__x)&0xff))
+
+// CR1 bits
+#define CYGHWR_HAL_LM3S_SSI_CR1_LBM               BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_CR1_SSE               BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_CR1_MS                BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_CR1_SOD               BIT_(3)
+
+// SR bits
+#define CYGHWR_HAL_LM3S_SSI_SR_TFE                BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_SR_TNF                BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_SR_RNE                BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_SR_RFF                BIT_(3)
+#define CYGHWR_HAL_LM3S_SSI_SR_BSY                BIT_(4)
+
+// IM bits
+#define CYGHWR_HAL_LM3S_SSI_IM_RORIM              BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_IM_RTIM               BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_IM_RXIM               BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_IM_TXIM               BIT_(3)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_SSI_RIS_RORRIS            BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_RIS_RTRIS             BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_RIS_RXRIS             BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_RIS_TXRIS             BIT_(3)
+
+// MIS bits
+#define CYGHWR_HAL_LM3S_SSI_MIS_RORMIS            BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_MIS_RTMIS             BIT_(1)
+#define CYGHWR_HAL_LM3S_SSI_MIS_RXMIS             BIT_(2)
+#define CYGHWR_HAL_LM3S_SSI_MIS_TXMIS             BIT_(3)
+
+// ICR bits
+#define CYGHWR_HAL_LM3S_SSI_ICR_RORIC             BIT_(0)
+#define CYGHWR_HAL_LM3S_SSI_ICR_RTIC              BIT_(1)
+
+#endif // CYGHWR_HAL_LM3S_SSI_CHAN
+
+//=============================================================================
+// PWM register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_PWM_CHAN
+
+#define CYGHWR_HAL_LM3S_PWM_CTL                   0x000
+#define CYGHWR_HAL_LM3S_PWM_SYNC                  0x004
+#define CYGHWR_HAL_LM3S_PWM_ENABLE                0x008
+#define CYGHWR_HAL_LM3S_PWM_INVERT                0x00c
+#define CYGHWR_HAL_LM3S_PWM_FAULT                 0x010
+#define CYGHWR_HAL_LM3S_PWM_INTEN                 0x014
+#define CYGHWR_HAL_LM3S_PWM_RIS                   0x018
+#define CYGHWR_HAL_LM3S_PWM_ISC                   0x01c
+#define CYGHWR_HAL_LM3S_PWM_STATUS                0x020
+
+#define CYGHWR_HAL_LM3S_PWM0_CTL                  0x040
+#define CYGHWR_HAL_LM3S_PWM0_INTEN                0x044
+#define CYGHWR_HAL_LM3S_PWM0_RIS                  0x048
+#define CYGHWR_HAL_LM3S_PWM0_ISC                  0x04c
+#define CYGHWR_HAL_LM3S_PWM0_LOAD                 0x050
+#define CYGHWR_HAL_LM3S_PWM0_COUNT                0x054
+#define CYGHWR_HAL_LM3S_PWM0_CMPA                 0x058
+#define CYGHWR_HAL_LM3S_PWM0_CMPB                 0x05c
+#define CYGHWR_HAL_LM3S_PWM0_GENA                 0x060
+#define CYGHWR_HAL_LM3S_PWM0_GENB                 0x064
+#define CYGHWR_HAL_LM3S_PWM0_DBCTL                0x068
+#define CYGHWR_HAL_LM3S_PWM0_DBRISE               0x06c
+#define CYGHWR_HAL_LM3S_PWM0_DBFALL               0x070
+
+#define CYGHWR_HAL_LM3S_PWM1_CTL                  0x080
+#define CYGHWR_HAL_LM3S_PWM1_INTEN                0x084
+#define CYGHWR_HAL_LM3S_PWM1_RIS                  0x088
+#define CYGHWR_HAL_LM3S_PWM1_ISC                  0x08c
+#define CYGHWR_HAL_LM3S_PWM1_LOAD                 0x090
+#define CYGHWR_HAL_LM3S_PWM1_COUNT                0x094
+#define CYGHWR_HAL_LM3S_PWM1_CMPA                 0x098
+#define CYGHWR_HAL_LM3S_PWM1_CMPB                 0x09c
+#define CYGHWR_HAL_LM3S_PWM1_GENA                 0x0a0
+#define CYGHWR_HAL_LM3S_PWM1_GENB                 0x0a4
+#define CYGHWR_HAL_LM3S_PWM1_DBCTL                0x0a8
+#define CYGHWR_HAL_LM3S_PWM1_DBRISE               0x0ac
+#define CYGHWR_HAL_LM3S_PWM1_DBFALL               0x0b0
+
+#define CYGHWR_HAL_LM3S_PWM2_CTL                  0x0c0
+#define CYGHWR_HAL_LM3S_PWM2_INTEN                0x0c4
+#define CYGHWR_HAL_LM3S_PWM2_RIS                  0x0c8
+#define CYGHWR_HAL_LM3S_PWM2_ISC                  0x0cc
+#define CYGHWR_HAL_LM3S_PWM2_LOAD                 0x0d0
+#define CYGHWR_HAL_LM3S_PWM2_COUNT                0x0d4
+#define CYGHWR_HAL_LM3S_PWM2_CMPA                 0x0d8
+#define CYGHWR_HAL_LM3S_PWM2_CMPB                 0x0dc
+#define CYGHWR_HAL_LM3S_PWM2_GENA                 0x0e0
+#define CYGHWR_HAL_LM3S_PWM2_GENB                 0x0e4
+#define CYGHWR_HAL_LM3S_PWM2_DBCTL                0x0e8
+#define CYGHWR_HAL_LM3S_PWM2_DBRISE               0x0ec
+#define CYGHWR_HAL_LM3S_PWM2_DBFALL               0x0f0
+
+
+// CTL bits
+#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC0            BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC1            BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_CTL_GSYNC2            BIT_(2)
+
+// SYNC bits
+#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC0            BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC1            BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_SYNC_SYNC2            BIT_(2)
+
+// ENABLE bits
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM0           BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM1           BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM2           BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM3           BIT_(3)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM4           BIT_(4)
+#define CYGHWR_HAL_LM3S_PWM_ENABLE_PWM5           BIT_(5)
+
+// INVERT bits
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM0           BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM1           BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM2           BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM3           BIT_(3)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM4           BIT_(4)
+#define CYGHWR_HAL_LM3S_PWM_INVERT_PWM5           BIT_(5)
+
+// FAULT bits
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM0            BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM1            BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM2            BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM3            BIT_(3)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM4            BIT_(4)
+#define CYGHWR_HAL_LM3S_PWM_FAULT_PWM5            BIT_(5)
+
+// INTEN bits
+#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM0            BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM1            BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_INTEN_PWM2            BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_INTEN_FAULT           BIT_(16)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_PWM_RIS_PWM0              BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_RIS_PWM1              BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_RIS_PWM2              BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_RIS_FAULT             BIT_(16)
+
+// ISC bits
+#define CYGHWR_HAL_LM3S_PWM_ISC_PWM0              BIT_(0)
+#define CYGHWR_HAL_LM3S_PWM_ISC_PWM1              BIT_(1)
+#define CYGHWR_HAL_LM3S_PWM_ISC_PWM2              BIT_(2)
+#define CYGHWR_HAL_LM3S_PWM_ISC_FAULT             BIT_(16)
+
+// STATUS bits
+#define CYGHWR_HAL_LM3S_PWM_STATUS_FAULT          BIT_(0)
+
+// PWMx CTL Bits
+#define CYGHWR_HAL_LM3S_PWMx_CTL_ENABLE           BIT_(0)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_MODE             BIT_(1)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_DEBUG            BIT_(2)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_LOAD_UPD         BIT_(3)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_CMPA_UPD         BIT_(4)
+#define CYGHWR_HAL_LM3S_PWMx_CTL_CMPB_UPD         BIT_(5)
+
+// PWMx INTEN Bits
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CNT_ZERO       BIT_(0)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CNT_LOAD       BIT_(1)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPA_UP        BIT_(2)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPA_DOWN      BIT_(3)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPB_UP        BIT_(4)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_CMPB_DOWN      BIT_(5)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CNT_ZERO  BIT_(8)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CNT_LOAD  BIT_(9)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPA_UP   BIT_(10)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPA_DOWN BIT_(11)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPB_UP   BIT_(12)
+#define CYGHWR_HAL_LM3S_PWMx_INTEN_TRIG_CMPB_DOWN BIT_(13)
+
+// PWMx RIS Bits
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CNT_ZERO         BIT_(0)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CNT_LOAD         BIT_(1)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPA_UP          BIT_(2)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPA_DOWN        BIT_(3)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPB_UP          BIT_(4)
+#define CYGHWR_HAL_LM3S_PWMx_RIS_CMPB_DOWN        BIT_(5)
+
+// PWMx ISC Bits
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CNT_ZERO         BIT_(0)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CNT_LOAD         BIT_(1)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPA_UP          BIT_(2)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPA_DOWN        BIT_(3)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPB_UP          BIT_(4)
+#define CYGHWR_HAL_LM3S_PWMx_ISC_CMPB_DOWN        BIT_(5)
+
+// PWMx GENA Bits
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_NONE   VALUE_(0, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_INVS   VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_SET0   VALUE_(0, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_SET1   VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_ZERO_MASK   0x00000003
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_NONE   VALUE_(2, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_INVS   VALUE_(2, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_SET0   VALUE_(2, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_SET1   VALUE_(2, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_ACT_LOAD_MASK   0x0000000c
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_NONE    VALUE_(4, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_INVS    VALUE_(4, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_SET0    VALUE_(4, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_SET1    VALUE_(4, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_UP_MASK    0x00000030
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_NONE  VALUE_(6, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_INVS  VALUE_(6, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_SET0  VALUE_(6, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_SET1  VALUE_(6, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPA_DOWN_MASK  0x000000c0
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_NONE    VALUE_(8, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_INVS    VALUE_(8, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_SET0    VALUE_(8, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_SET1    VALUE_(8, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_UP_MASK    0x00000300
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_NONE  VALUE_(10, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_INVS  VALUE_(10, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_SET0  VALUE_(10, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_SET1  VALUE_(10, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENA_CMPB_DOWN_MASK  0x00000c00
+
+// PWMx GENB Bits
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_NONE   VALUE_(0, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_INVS   VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_SET0   VALUE_(0, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_SET1   VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_ZERO_MASK   0x00000003
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_NONE   VALUE_(2, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_INVS   VALUE_(2, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_SET0   VALUE_(2, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_SET1   VALUE_(2, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_ACT_LOAD_MASK   0x0000000c
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_NONE    VALUE_(4, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_INVS    VALUE_(4, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_SET0    VALUE_(4, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_SET1    VALUE_(4, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_UP_MASK    0x00000030
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_NONE  VALUE_(6, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_INVS  VALUE_(6, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_SET0  VALUE_(6, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_SET1  VALUE_(6, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPA_DOWN_MASK  0x000000c0
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_NONE    VALUE_(8, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_INVS    VALUE_(8, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_SET0    VALUE_(8, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_SET1    VALUE_(8, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_UP_MASK    0x00000300
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_NONE  VALUE_(10, 0x0)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_INVS  VALUE_(10, 0x1)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_SET0  VALUE_(10, 0x2)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_SET1  VALUE_(10, 0x3)
+#define CYGHWR_HAL_LM3S_PWMx_GENB_CMPB_DOWN_MASK  0x00000c00
+
+// PWMx DBCTL Bits
+#define CYGHWR_HAL_LM3S_PWMx_DBCTL_ENABLE         BIT_(0)
+
+#endif // CYGHWR_HAL_LM3S_PWM_CHAN
+
+
+//=============================================================================
+// Global Timers register definitions.
+
+#define CYGHWR_HAL_LM3S_GPTIM_CFG                 0x000
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR                0x004
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR                0x008
+#define CYGHWR_HAL_LM3S_GPTIM_CTL                 0x00c
+#define CYGHWR_HAL_LM3S_GPTIM_IMR                 0x018
+#define CYGHWR_HAL_LM3S_GPTIM_RIS                 0x01C
+#define CYGHWR_HAL_LM3S_GPTIM_MIS                 0x020
+#define CYGHWR_HAL_LM3S_GPTIM_ICR                 0x024
+#define CYGHWR_HAL_LM3S_GPTIM_TAILR               0x028
+#define CYGHWR_HAL_LM3S_GPTIM_TBILR               0x02c
+#define CYGHWR_HAL_LM3S_GPTIM_TAMATCHR            0x030
+#define CYGHWR_HAL_LM3S_GPTIM_TBMATCHR            0x034
+#define CYGHWR_HAL_LM3S_GPTIM_TAPR                0x038
+#define CYGHWR_HAL_LM3S_GPTIM_TBPR                0x03c
+#define CYGHWR_HAL_LM3S_GPTIM_TAPMR               0x040
+#define CYGHWR_HAL_LM3S_GPTIM_TBPMR               0x044
+#define CYGHWR_HAL_LM3S_GPTIM_TAR                 0x048
+#define CYGHWR_HAL_LM3S_GPTIM_TBR                 0x04c
+
+// CFG bits
+#define CYGHWR_HAL_LM3S_GPTIM_CFG_32BIT           VALUE_(0, 0x0)
+#define CYGHWR_HAL_LM3S_GPTIM_CFG_32BIT_RTC       VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_CFG_16BIT           VALUE_(0, 0x4)
+#define CYGHWR_HAL_LM3S_GPTIM_CFG_MASK            0x00000007
+
+// TAMR bits
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_ONE_SHOT       VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_PERIODIC       VALUE_(0, 0x2)
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_CAPTURE        VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_MASK           0x00000003
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_TACMR          BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_TAMR_TAAMS          BIT_(3)
+
+// TBMR bits
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_ONE_SHOT       VALUE_(0, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_PERIODIC       VALUE_(0, 0x2)
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_CAPTURE        VALUE_(0, 0x3)
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_MASK           0x00000003
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_TBCMR          BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_TBMR_TBAMS          BIT_(3)
+
+// CTL bits
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEN            BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TASTALL         BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_POS     VALUE_(2, 0x0)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_NEG     VALUE_(2, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAEVENT_BOTH    VALUE_(2, 0x3)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_RTCEN           BIT_(4)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAOTE           BIT_(5)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TAPWML          BIT_(6)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEN            BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBSTALL         BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_POS     VALUE_(10, 0x0)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_NEG     VALUE_(10, 0x1)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBEVENT_BOTH    VALUE_(10, 0x3)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBOTE           BIT_(13)
+#define CYGHWR_HAL_LM3S_GPTIM_CTL_TBPWML          BIT_(14)
+
+// IMR bits
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_TATOIM          BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_CAMIM           BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_CAEIM           BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_RTCIM           BIT_(3)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_TBTOIM          BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_CBMIM           BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_IMR_CBEIM           BIT_(10)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_TATORIS         BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_CAMRIS          BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_CAERIS          BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_RTCRIS          BIT_(3)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_TBTORIS         BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_CBMRIS          BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_RIS_CBERIS          BIT_(10)
+
+// MIS bits
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_TATOMIS         BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_CAMMIS          BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_CAEMIS          BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_RTCMIS          BIT_(3)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_TBTOMIS         BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_CBMMIS          BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_MIS_CBEMIS          BIT_(10)
+
+// ICR bits
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_TATOCINT        BIT_(0)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_CAMCINT         BIT_(1)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_CAECINT         BIT_(2)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_RTCCINT         BIT_(3)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_TBTOCINT        BIT_(8)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_CBMCINT         BIT_(9)
+#define CYGHWR_HAL_LM3S_GPTIM_ICR_CBECINT         BIT_(10)
+
+cyg_uint32 hal_lm3s_timer_clock( void );
+
+#ifndef __ASSEMBLER__
+
+__externC cyg_uint32 hal_stellaris_lm3s_timer_clock( CYG_ADDRESS base );
+
+#endif
+
+
+//=============================================================================
+// I2C register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_I2C_CHAN
+
+#define CYGHWR_HAL_LM3S_I2C_MSA                   0x000
+#define CYGHWR_HAL_LM3S_I2C_MCS                   0x004
+#define CYGHWR_HAL_LM3S_I2C_MDR                   0x008
+#define CYGHWR_HAL_LM3S_I2C_MTPR                  0x00c
+#define CYGHWR_HAL_LM3S_I2C_MIMR                  0x010
+#define CYGHWR_HAL_LM3S_I2C_MRIS                  0x014
+#define CYGHWR_HAL_LM3S_I2C_MMIS                  0x018
+#define CYGHWR_HAL_LM3S_I2C_MICR                  0x01c
+#define CYGHWR_HAL_LM3S_I2C_MCR                   0x020
+
+#define CYGHWR_HAL_LM3S_I2C_SOAR                  0x000
+#define CYGHWR_HAL_LM3S_I2C_SCSR                  0x004
+#define CYGHWR_HAL_LM3S_I2C_SDR                   0x008
+#define CYGHWR_HAL_LM3S_I2C_SIMR                  0x00c
+#define CYGHWR_HAL_LM3S_I2C_SRIS                  0x010
+#define CYGHWR_HAL_LM3S_I2C_SMIS                  0x014
+#define CYGHWR_HAL_LM3S_I2C_SICR                  0x018
+
+// MSA bits
+#define CYGHWR_HAL_LM3S_I2C_MSA_RS                BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_MSA_SA(__x)           VALUE_(1, __x)
+
+// MCS bits
+#define CYGHWR_HAL_LM3S_I2C_MCS_BUSY              BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_MCS_ERR               BIT_(1)
+#define CYGHWR_HAL_LM3S_I2C_MCS_ADRACK            BIT_(2)
+#define CYGHWR_HAL_LM3S_I2C_MCS_DATACK            BIT_(3)
+#define CYGHWR_HAL_LM3S_I2C_MCS_ARBLST            BIT_(4)
+#define CYGHWR_HAL_LM3S_I2C_MCS_IDLE              BIT_(5)
+#define CYGHWR_HAL_LM3S_I2C_MCS_BUSBSY            BIT_(6)
+
+#define CYGHWR_HAL_LM3S_I2C_MCS_RUN               BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_MCS_START             BIT_(1)
+#define CYGHWR_HAL_LM3S_I2C_MCS_STOP              BIT_(2)
+#define CYGHWR_HAL_LM3S_I2C_MCS_ACK               BIT_(3)
+
+// MIMR bits
+#define CYGHWR_HAL_LM3S_I2C_MIMR_IM               BIT_(0)
+
+// MRIS bits
+#define CYGHWR_HAL_LM3S_I2C_MRIS_RIS              BIT_(0)
+
+// MMIS bits
+#define CYGHWR_HAL_LM3S_I2C_MMIS_MIS              BIT_(0)
+
+// MICR bits
+#define CYGHWR_HAL_LM3S_I2C_MICR_IC               BIT_(0)
+
+// MCR bits
+#define CYGHWR_HAL_LM3S_I2C_MCR_LPBK              BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_MCR_MFE               BIT_(4)
+#define CYGHWR_HAL_LM3S_I2C_MCR_SFE               BIT_(5)
+
+// SCSR bits
+#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_RREQ        BIT_(0)
+#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_TREQ        BIT_(1)
+#define CYGHWR_HAL_LM3S_I2C_SCSR_READ_FBR         BIT_(2)
+
+#define CYGHWR_HAL_LM3S_I2C_SCSR_WRITE_DA         BIT_(0)
+
+// SIMR bits
+#define CYGHWR_HAL_LM3S_I2C_SIMR_DATAIM           BIT_(0)
+
+// SRIS bits
+#define CYGHWR_HAL_LM3S_I2C_SRIS_DATARIS          BIT_(0)
+
+// SMIS bits
+#define CYGHWR_HAL_LM3S_I2C_SMIS_DATAMIS          BIT_(0)
+
+// SICR bits
+#define CYGHWR_HAL_LM3S_I2C_SICR_DATAMIC          BIT_(0)
+
+__externC cyg_uint32 hal_lm3s_i2c_clock( void );
+
+#endif // CYGHWR_HAL_LM3S_I2C_CHAN
+
+
+//=============================================================================
+// AC register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_AC_CHAN
+
+#define CYGHWR_HAL_LM3S_AC_MIS                    0x000
+#define CYGHWR_HAL_LM3S_AC_RIS                    0x004
+#define CYGHWR_HAL_LM3S_AC_INTEN                  0x008
+#define CYGHWR_HAL_LM3S_AC_REFCTL                 0x010
+#define CYGHWR_HAL_LM3S_AC_STAT0                  0x020
+#define CYGHWR_HAL_LM3S_AC_CTL0                   0x024
+#define CYGHWR_HAL_LM3S_AC_STAT1                  0x040
+#define CYGHWR_HAL_LM3S_AC_CTL1                   0x044
+#define CYGHWR_HAL_LM3S_AC_STAT2                  0x060
+#define CYGHWR_HAL_LM3S_AC_CTL2                   0x064
+
+// MIS bits
+#define CYGHWR_HAL_LM3S_AC_MIS_IN0                BIT_(0)
+#define CYGHWR_HAL_LM3S_AC_MIS_IN1                BIT_(1)
+#define CYGHWR_HAL_LM3S_AC_MIS_IN2                BIT_(2)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_AC_RIS_IN0                BIT_(0)
+#define CYGHWR_HAL_LM3S_AC_RIS_IN1                BIT_(1)
+#define CYGHWR_HAL_LM3S_AC_RIS_IN2                BIT_(2)
+
+// INTEN bits
+#define CYGHWR_HAL_LM3S_AC_INTEN_IN0              BIT_(0)
+#define CYGHWR_HAL_LM3S_AC_INTEN_IN1              BIT_(1)
+#define CYGHWR_HAL_LM3S_AC_INTEN_IN2              BIT_(2)
+
+// REFCTL bits
+#define CYGHWR_HAL_LM3S_AC_REFCTL_RNG             BIT_(8)
+#define CYGHWR_HAL_LM3S_AC_REFCTL_EN              BIT_(9)
+
+// STAT0, STAT1 and STAT2 bits
+#define CYGHWR_HAL_LM3S_AC_STATx_OVAL             BIT_(1)
+
+// CTL0, CTL1 anf CTL2 bits
+#define CYGHWR_HAL_LM3S_AC_CTLx_CINV              BIT_(1)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_LEV_SENSE    VALUE_(2, 0x0)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_FALL_EDGE    VALUE_(2, 0x1)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_RISE_EDGE    VALUE_(2, 0x2)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISEN_BOTH_EDGE    VALUE_(2, 0x3)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ISLVAL            BIT_(4)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_PIN_VAL     VALUE_(9, 0x0)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_PIN_VAL_C0  VALUE_(9, 0x1)
+#define CYGHWR_HAL_LM3S_AC_CTLx_ASRCP_IVOLTREF    VALUE_(9, 0x2)
+
+#endif // CYGHWR_HAL_LM3S_AC_CHAN
+
+
+//=============================================================================
+// QEI register definitions.
+
+#ifdef CYGHWR_HAL_LM3S_QEI_CHAN
+
+#define CYGHWR_HAL_LM3S_QEI_CTL                   0x000
+#define CYGHWR_HAL_LM3S_QEI_STAT                  0x004
+#define CYGHWR_HAL_LM3S_QEI_POS                   0x008
+#define CYGHWR_HAL_LM3S_QEI_MAXPOS                0x00c
+#define CYGHWR_HAL_LM3S_QEI_LOAD                  0x010
+#define CYGHWR_HAL_LM3S_QEI_TIME                  0x014
+#define CYGHWR_HAL_LM3S_QEI_COUNT                 0x018
+#define CYGHWR_HAL_LM3S_QEI_SPEED                 0x01c
+#define CYGHWR_HAL_LM3S_QEI_INTEN                 0x020
+#define CYGHWR_HAL_LM3S_QEI_RIS                   0x024
+#define CYGHWR_HAL_LM3S_QEI_ISC                   0x028
+
+// CTL bits
+#define CYGHWR_HAL_LM3S_QEI_CTL_EN                BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_CTL_SWAP              BIT_(1)
+#define CYGHWR_HAL_LM3S_QEI_CTL_SIGMODE           BIT_(2)
+#define CYGHWR_HAL_LM3S_QEI_CTL_CAPMODE           BIT_(3)
+#define CYGHWR_HAL_LM3S_QEI_CTL_RESMODE           BIT_(4)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELEN             BIT_(5)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_1          VALUE_(6, 0x0)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_2          VALUE_(6, 0x1)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_4          VALUE_(6, 0x2)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_8          VALUE_(6, 0x3)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_16         VALUE_(6, 0x4)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_32         VALUE_(6, 0x5)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_64         VALUE_(6, 0x6)
+#define CYGHWR_HAL_LM3S_QEI_CTL_VELDIV_128        VALUE_(6, 0x7)
+#define CYGHWR_HAL_LM3S_QEI_CTL_INVA              BIT_(9)
+#define CYGHWR_HAL_LM3S_QEI_CTL_INVB              BIT_(10)
+#define CYGHWR_HAL_LM3S_QEI_CTL_INVI              BIT_(11)
+#define CYGHWR_HAL_LM3S_QEI_CTL_SATLLEN           BIT_(12)
+
+// STAT bits
+#define CYGHWR_HAL_LM3S_QEI_STAT_ERR              BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_STAT_DIR              BIT_(1)
+
+// INTEN bits
+#define CYGHWR_HAL_LM3S_QEI_INTEN_INTINDEX        BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_INTEN_INTTIMER        BIT_(1)
+#define CYGHWR_HAL_LM3S_QEI_INTEN_INTDIR          BIT_(2)
+#define CYGHWR_HAL_LM3S_QEI_INTEN_INTERROR        BIT_(3)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_QEI_RIS_INTINDEX          BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_RIS_INTTIMER          BIT_(1)
+#define CYGHWR_HAL_LM3S_QEI_RIS_INTDIR            BIT_(2)
+#define CYGHWR_HAL_LM3S_QEI_RIS_INTERROR          BIT_(3)
+
+// ISC bits
+#define CYGHWR_HAL_LM3S_QEI_ISC_INTINDEX          BIT_(0)
+#define CYGHWR_HAL_LM3S_QEI_ISC_INTTIMER          BIT_(1)
+#define CYGHWR_HAL_LM3S_QEI_ISC_INTDIR            BIT_(2)
+#define CYGHWR_HAL_LM3S_QEI_ISC_INTERROR          BIT_(3)
+
+#endif // CYGHWR_HAL_LM3S_QEI_CHAN
+
+
+//=============================================================================
+// Flash controller
+
+#define CYGHWR_HAL_LM3S_FMC_FMA                   0x000
+#define CYGHWR_HAL_LM3S_FMC_FMD                   0x004
+#define CYGHWR_HAL_LM3S_FMC_FMC                   0x008
+#define CYGHWR_HAL_LM3S_FMC_FCRIS                 0x00c
+#define CYGHWR_HAL_LM3S_FMC_FCIM                  0x010
+#define CYGHWR_HAL_LM3S_FMC_FCMISC                0x014
+
+// Key value
+#define CYGHWR_HAL_LM3S_FMC_WRKEY                 0xA4420000
+
+// FMC bits
+#define CYGHWR_HAL_LM3S_FMC_FMC_WRITE             BIT_(0)
+#define CYGHWR_HAL_LM3S_FMC_FMC_ERASE             BIT_(1)
+#define CYGHWR_HAL_LM3S_FMC_FMC_MERASE            BIT_(2)
+#define CYGHWR_HAL_LM3S_FMC_FMC_COMT              BIT_(3)
+
+// RIS bits
+#define CYGHWR_HAL_LM3S_FMC_FCRIS_ARIS            BIT_(0)
+#define CYGHWR_HAL_LM3S_FMC_FCRIS_PRIS            BIT_(1)
+
+// IM bits
+#define CYGHWR_HAL_LM3S_FMC_FCIM_AMASK            BIT_(0)
+#define CYGHWR_HAL_LM3S_FMC_FCIM_PMASK            BIT_(1)
+
+// MISC bits
+#define CYGHWR_HAL_LM3S_FMC_FCMISC_AMASK          BIT_(0)
+#define CYGHWR_HAL_LM3S_FMC_FCMISC_PMASK          BIT_(0)
+
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_IO_H
+// EOF of var_io.h
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/include/variant.inc b/ecos/packages/hal/cortexm/lm3s/var/current/include/variant.inc
new file mode 100644
index 0000000..415ebf5
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/include/variant.inc
@@ -0,0 +1,54 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2010-11-23
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_lm3s.h>
+
+//==========================================================================
+// EOF variant.inc
+
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/lm3s/var/current/src/hal_diag.c
new file mode 100644
index 0000000..2ddb570
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/src/hal_diag.c
@@ -0,0 +1,406 @@
+//=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2010
+// 2011, Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   original: nickg, ccoutand: updated for Stellaris HAL
+// Date:        2011-01-18
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>        // Base types
+#include <cyg/infra/cyg_trac.h>        // Tracing
+
+#include <cyg/hal/hal_arch.h>          // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>            // IO macros
+#include <cyg/hal/hal_if.h>            // interface API
+#include <cyg/hal/hal_intr.h>          // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>          // Helper functions
+#include <cyg/hal/drv_api.h>           // CYG_ISR_HANDLED
+
+#include <cyg/hal/var_io.h>            // USART registers
+
+//-----------------------------------------------------------------------------
+typedef struct {
+    cyg_uint32      uart;
+    CYG_ADDRESS     base;
+    cyg_int32       msec_timeout;
+    int             isr_vector;
+    cyg_uint32      rxpin;
+    cyg_uint32      txpin;
+    cyg_uint32      baud_rate;
+    int             irq_state;
+} channel_data_t;
+
+static channel_data_t lm3s_ser_channels[] = {
+#if CYGINT_HAL_CORTEXM_LM3S_UART0>0
+    {0, CYGHWR_HAL_LM3S_UART0, 1000, CYGNUM_HAL_INTERRUPT_UART0,
+     CYGHWR_HAL_LM3S_UART0_RX, CYGHWR_HAL_LM3S_UART0_TX},
+#endif
+#if CYGINT_HAL_CORTEXM_LM3S_UART1>0
+    {1, CYGHWR_HAL_LM3S_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1,
+     CYGHWR_HAL_LM3S_UART1_RX, CYGHWR_HAL_LM3S_UART1_TX},
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void
+hal_lm3s_serial_init_channel(void *__ch_data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = chan->base;
+    cyg_uint32      lcrh,
+                    ctl;
+
+    // Disable UART
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl);
+    ctl &= ~(CYGHWR_HAL_LM3S_UART_CTL_UARTEN |
+             CYGHWR_HAL_LM3S_UART_CTL_TXE | CYGHWR_HAL_LM3S_UART_CTL_RXE);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl);
+
+    // Enable the PIO lines for the serial channel
+    CYGHWR_HAL_LM3S_GPIO_SET(chan->rxpin);
+    CYGHWR_HAL_LM3S_GPIO_SET(chan->txpin);
+
+    // Set up Baud rate
+    chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
+    hal_lm3s_uart_setbaud(base, chan->baud_rate);
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, 0);
+
+    // 8 bits - 1 stop - Enable FIFO
+    lcrh = CYGHWR_HAL_LM3S_UART_LCRH_WLEN(3) | CYGHWR_HAL_LM3S_UART_LCRH_FEN;
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_LCRH, lcrh);
+
+    // Enable the UART
+    ctl = (CYGHWR_HAL_LM3S_UART_CTL_UARTEN |
+           CYGHWR_HAL_LM3S_UART_CTL_TXE | CYGHWR_HAL_LM3S_UART_CTL_RXE);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_CTL, ctl);
+}
+
+void
+hal_lm3s_serial_putc(void *__ch_data, char c)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      sr;
+
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, sr);
+    } while ((sr & CYGHWR_HAL_LM3S_UART_FR_TXFE) == 0);
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_DR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+hal_lm3s_serial_getc_nonblock(void *__ch_data, cyg_uint8 *ch)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      fr;
+    cyg_uint32      c;
+
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_FR, fr);
+
+    if ((fr & CYGHWR_HAL_LM3S_UART_FR_RXFE))
+        return false;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_DR, c);
+
+    *ch = (cyg_uint8)c;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return true;
+}
+
+cyg_uint8
+hal_lm3s_serial_getc(void *__ch_data)
+{
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    while (!hal_lm3s_serial_getc_nonblock(__ch_data, &ch))
+        continue;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return ch;
+}
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+hal_lm3s_serial_write(void *__ch_data, const cyg_uint8 *__buf,
+                      cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        hal_lm3s_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+hal_lm3s_serial_read(void *__ch_data, cyg_uint8 *__buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        *__buf++ = hal_lm3s_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+hal_lm3s_serial_getc_timeout(void *__ch_data, cyg_uint8 *ch)
+{
+    int             delay_count;
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_bool        res;
+
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 100;     // delay in 10 us steps
+
+    for (;;) {
+        res = hal_lm3s_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(10);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return res;
+}
+
+static int
+hal_lm3s_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    int             ret = 0;
+    cyg_uint32      im;
+
+    va_list         ap;
+
+    CYGARC_HAL_SAVE_GP();
+
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im);
+        im |= CYGHWR_HAL_LM3S_UART_IM_RXIM;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        HAL_READ_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im);
+        im &= ~CYGHWR_HAL_LM3S_UART_IM_RXIM;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IM, im);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        {
+            va_list         ap;
+
+            va_start(ap, __func);
+
+            ret = chan->msec_timeout;
+            chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+            va_end(ap);
+        }
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        hal_lm3s_uart_setbaud(base, chan->baud_rate);
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+
+    va_end(ap);
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return ret;
+}
+
+static int
+hal_lm3s_serial_isr(void *__ch_data, int *__ctrlc,
+                    CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+
+    if (hal_lm3s_serial_getc_nonblock(__ch_data, &ch)) {
+        if (cyg_hal_is_break((char *)&ch, 1))
+            *__ctrlc = 1;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return 1;
+}
+
+static void
+hal_lm3s_serial_init(void)
+{
+    hal_virtual_comm_table_t *comm;
+    int             cur;
+    int             i;
+
+    cur =
+        CYGACC_CALL_IF_SET_CONSOLE_COMM
+        (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    for (i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; i++) {
+        hal_lm3s_serial_init_channel(&lm3s_ser_channels[i]);
+
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &lm3s_ser_channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, hal_lm3s_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, hal_lm3s_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, hal_lm3s_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, hal_lm3s_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, hal_lm3s_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_lm3s_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_lm3s_serial_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+
+# if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    // Set debug channel baud rate if different
+    lm3s_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate(&lm3s_ser_channels
+                     [CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]);
+# endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int      initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    hal_lm3s_serial_init();
+}
+
+#endif // ifdef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void
+hal_lm3s_diag_init(void)
+{
+    hal_lm3s_serial_init(&lm3s_ser_channels
+                         [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+void
+hal_lm3s_diag_putc(char c)
+{
+    hal_lm3s_serial_putc(&lm3s_ser_channels
+                         [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8
+hal_lm3s_diag_getc(void)
+{
+    return
+        hal_lm3s_serial_getc(&lm3s_ser_channels
+                             [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+#endif // ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//-----------------------------------------------------------------------------
+// EOF hal_diag.c
diff --git a/ecos/packages/hal/cortexm/lm3s/var/current/src/lm3s_misc.c b/ecos/packages/hal/cortexm/lm3s/var/current/src/lm3s_misc.c
new file mode 100644
index 0000000..291b3e5
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lm3s/var/current/src/lm3s_misc.c
@@ -0,0 +1,328 @@
+//==========================================================================
+//
+//      lm3s_misc.c
+//
+//      Stellaris Cortex-M3 variant HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ccoutand
+// Date:         2011-01-18
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>        // Tracing macros
+#include <cyg/infra/cyg_ass.h>         // Assertion macros
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_if.h>
+
+//==========================================================================
+// Initialization
+//
+__externC void  hal_start_clocks(void);
+
+// Clock computation must be done per Variant basis
+cyg_uint32      hal_cortexm_systick_clock;
+cyg_uint32      hal_lm3s_sysclk;
+
+
+void
+hal_variant_init(void)
+{
+#if !defined(CYG_HAL_STARTUP_RAM)
+    hal_start_clocks();
+#endif
+
+    // All LM3S devices use PORTA 0/1 for UART0
+#if CYGINT_HAL_CORTEXM_LM3S_UART0>0
+    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0, 1);
+    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0_GPIO, 1);
+#endif
+
+#if CYGINT_HAL_CORTEXM_LM3S_UART1>0
+
+# ifdef CYGHWR_HAL_LM3S_P_UART1_GPIO
+    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1, 1);
+    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1_GPIO, 1);
+# else
+#  error "Variant/Platform does not specify UART1 GPIO Port"
+# endif
+
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//==========================================================================
+// GPIO support
+//
+// These functions provide configuration and IO for GPIO pins.
+//
+
+__externC void
+hal_lm3s_gpio_set(cyg_uint32 pin)
+{
+    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
+    cyg_uint32      bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
+    cyg_uint32      cm = CYGHWR_HAL_LM3S_GPIO_CFG(pin);
+    cyg_uint32      mode = CYGHWR_HAL_LM3S_GPIO_MODE(pin);
+    cyg_uint32      irq = CYGHWR_HAL_LM3S_GPIO_IRQ(pin);
+    cyg_uint32      st = CYGHWR_HAL_LM3S_GPIO_STRENGTH(pin);
+    cyg_uint32      reg,
+                    dir,
+                    im,
+                    dr2r,
+                    dr4r,
+                    dr8r;
+
+    if (pin == CYGHWR_HAL_LM3S_GPIO_NONE)
+        return;
+
+    /*
+     *  Handle IO mode settings
+     */
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, reg);
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, dir);
+
+    HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg & ~(bit)));
+    if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_IN)
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir & ~(bit)));
+    else if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_OUT)
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir | bit));
+    else
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg | bit));
+
+    /*
+     *  Handle IO configuration
+     */
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, reg);
+    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP ||
+        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP ||
+        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg | bit));
+    } else
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg & ~(bit)));
+
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, reg);
+    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLUP ||
+        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg | bit));
+    } else
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg & ~(bit)));
+
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, reg);
+    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLDOWN ||
+        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg | bit));
+    } else
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg & ~(bit)));
+
+    /*
+     *  Handle IO strength
+     */
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, dr2r);
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, dr4r);
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, dr8r);
+    if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_2_MA) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r | bit));
+    } else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_4_MA) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r | bit));
+    } else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_8_MA) {
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit)));
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r | bit));
+    }
+
+    /*
+     *  Handle interrupt settings
+     */
+    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, im);
+    HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im & ~(bit)));
+    if (irq != CYGHWR_HAL_LM3S_GPIO_IRQ_DISABLE) {
+        HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, reg);
+
+        if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL ||
+            irq == CYGHWR_HAL_LM3S_GPIO_IRQ_HIGH_LEVEL)
+            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg | bit));
+        else
+            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg & ~(bit)));
+
+        HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, reg);
+        if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_BOTH_EDGES) {
+            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg | bit));
+        } else {
+            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg & ~(bit)));
+
+            HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV, reg);
+            if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL ||
+                irq == CYGHWR_HAL_LM3S_GPIO_IRQ_FALLING_EDGE)
+                HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV,
+                                 (reg & ~(bit)));
+            else
+                HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV,
+                                 (reg | bit));
+        }
+
+        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im | bit));
+    }
+}
+
+__externC void
+hal_lm3s_gpio_out(cyg_uint32 pin, int val)
+{
+    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
+    int             bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
+
+    port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2));
+
+    HAL_WRITE_UINT32(port, (val ? bit : 0));
+}
+
+__externC void
+hal_lm3s_gpio_in(cyg_uint32 pin, int *val)
+{
+    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
+    int             bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
+    cyg_uint32      pd;
+
+    port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2));
+
+    HAL_READ_UINT32(port, pd);
+    *val = pd;
+}
+
+
+//==========================================================================
+// Peripheral support
+//
+
+__externC void
+hal_lm3s_periph_set(cyg_uint32 periph, cyg_uint32 on_off)
+{
+    cyg_uint32      reg;
+
+    if (CYGHWR_HAL_LM3S_PERIPH_GC0 & periph) {
+        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg);
+        if (on_off)
+            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0);
+        else
+            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0);
+        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg);
+    }
+
+    if (CYGHWR_HAL_LM3S_PERIPH_GC1 & periph) {
+        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg);
+        if (on_off)
+            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1);
+        else
+            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1);
+        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg);
+    }
+
+    if (CYGHWR_HAL_LM3S_PERIPH_GC2 & periph) {
+        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg);
+        if (on_off)
+            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2);
+        else
+            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2);
+        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg);
+    }
+
+}
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current APB clock settings.
+//
+
+__externC void
+hal_lm3s_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)
+{
+    cyg_uint32      int_div,
+                    frac_div;
+
+    int_div = ((((hal_cortexm_systick_clock << 3) / baud) + 1) >> 1);
+
+    frac_div = int_div % 64;
+    int_div = int_div >> 6;
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IBRD, int_div);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_FBRD, frac_div);
+}
+
+
+//==========================================================================
+// I2C clock rate
+//
+__externC cyg_uint32
+hal_lm3s_i2c_clock(void)
+{
+    return hal_lm3s_sysclk;
+}
+
+//==========================================================================
+// Timer clock rate
+//
+__externC cyg_uint32
+hal_lm3s_timer_clock(void)
+{
+    return hal_lm3s_sysclk;
+}
+
+//==========================================================================
+// EOF lm3s_misc_misc.c
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog
new file mode 100644
index 0000000..81d7195
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog
@@ -0,0 +1,43 @@
+2012-01-16  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.h:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.ldi:
+	Recognize In Application Programming (IAP) SRAM field
+	and Valid User Code and Code Read Protection FLASH fields
+	Reported by Bernard Fouch� [ Bugzilla 1001395 ] [Bugzilla 1001443 ]
+
+2010-12-12  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.h:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.ldi:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/lpc1766stk_misc.c:
+	New package -- Olimex LPC1766STK board.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl
new file mode 100644
index 0000000..8ed6ac6
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl
@@ -0,0 +1,416 @@
+##==========================================================================
+##
+##      hal_cortexm_lpc17xx_lpc1766stk.cdl
+##
+##      Cortex-M Olimex LPC-1766STK platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ilijak
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LPC17XX_LPC1766STK {
+    display       "Olimex LPC-1700STK Board HAL"
+    parent        CYGPKG_HAL_CORTEXM_LPC17XX
+    define_header hal_cortexm_lpc17xx_lpc1766stk.h
+    include_dir   cyg/hal
+    hardware
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    implements    CYGINT_IO_SERIAL_LPC24XX_UART0
+    implements    CYGINT_IO_SERIAL_LPC24XX_UART1
+
+    description   "
+        The Olimex LPC-1766STK HAL package provides the support needed
+        to run eCos on the LPC-1766STK board. Also this package can be
+        used for other boards that employ a controller from LPC 176x
+        or LPC 175x families. Use 'LPC17xx member in use' to pick up
+        your device."
+
+    compile       lpc1766stk_misc.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+                   (1 == CYGHWR_DEVS_ETH_PHY_KS8721) }
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_lpc17xx.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Olimex LPC-1766STK\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value { "ROM" }
+        legal_values  { "ROM" }
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            'ROM' startup builds a stand-alone application which will
+            be put into internal flash."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_IAP {
+        display "Reserve RAM for IAP (Bytes)"
+        flavor data
+        legal_values { 0 32 }
+        default_value 32
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display       "Memory layout"
+        flavor        data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_lpc" . CYGHWR_HAL_CORTEXM_LPC17XX  . "_rom" :
+                        "undefined" }
+        description   "
+            Combination of 'Startup type' and 'LPC17xx member in use'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display       "Memory layout linker script fragment"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated   { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display       "Memory layout header file"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated    { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ {
+        display       "CPU xtal frequency"
+        parent        CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING
+        flavor        data
+        default_value { 12000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_MAX_CLOCK_SPEED {
+        display       "Max. CPU clock speed"
+        parent        CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING
+        flavor        data
+        calculated    { (CYGHWR_HAL_CORTEXM_LPC17XX == "1759") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769") ?  120000000 :
+            100000000 }
+        requires      { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <=
+            ((CYGHWR_HAL_CORTEXM_LPC17XX == "1759") ||
+             (CYGHWR_HAL_CORTEXM_LPC17XX == "1769") ?  120000000 :
+             100000000) }
+        description   "
+            Highest internal core frequency is dependent on selected
+            chip. "
+    }
+
+    # Both UARTs 0 and 1 are available for diagnostic/debug use.
+    implements CYGINT_HAL_LPC17XX_UART0
+    implements CYGINT_HAL_LPC17XX_UART1
+
+    implements      CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+    implements      CYGINT_IO_SERIAL_LINE_STATUS_HW
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display       "Number of communication channels on the board"
+        flavor        data
+        calculated    2
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display       "Debug serial port"
+        active_if     CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor        data
+        legal_values  0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value 0
+        description   "
+            The Olimex LPC1766STK board has two serial ports. This
+            option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display       "Diagnostic serial port"
+        active_if     CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor        data
+        legal_values  0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value 0
+        description   "
+            The Olimex LPC1766STK has two serial ports. This option
+            chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port
+            if the diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console
+            port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_HAL_LPC_EMAC_RAM_AHB {
+        display       "Ethernet controller AHB SRAM"
+        flavor        none
+        active_if     CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        parent        CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        description   "
+            AHB SRAM allocated for Ethernet controller."
+
+        cdl_option CYGHWR_HAL_LPC_EMAC_MEM_SECTION {
+            display       "Memory section for lwIP buffers."
+            flavor        data
+            default_value { "\".ahb_sram0\"" }
+            legal_values  { "\".ahb_sram0\"" "\".ahb_sram1\"" }
+            description   "
+                Select special section for lwIP p-buffers and heap and
+                provide section name."
+        }
+
+        cdl_option CYGHWR_HAL_LPC_EMAC_BLOCK_SIZE {
+            display       "Block size"
+            flavor        data
+            default_value 0x600
+        }
+    }
+
+    cdl_option CYGDAT_LWIP_MEM_SECTION_NAME {
+        display       "Memory section for lwIP buffers."
+        flavor        data
+        default_value { "\".ahb_sram0\"" }
+        legal_values  { "\".ahb_sram0\"" "\".ahb_sram1\"" }
+        active_if     CYGPKG_NET_LWIP
+        parent        CYGOPT_LWIP_MEM_PLF_SPEC
+        description   "
+            Select special section for lwIP p-buffers and heap and
+            provide section name."
+    }
+
+    cdl_component CYGOPT_LWIP_PLF_MEM_OPT {
+        display       "Platform related lwIP memory constrains"
+        flavor        none
+        no_define
+        active_if     CYGPKG_NET_LWIP
+        parent        CYGOPT_LWIP_MEM_PLF_SPEC
+        description   "
+            Some platform constrains, features and restrictions applied
+            to lwIP network stack."
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_SS0 {
+            display       "lwIP uses the same section as the ethernet controller"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_SS0)
+
+            active_if     CYGSEM_LWIP_MEM_SECTION
+            active_if     { CYGDAT_LWIP_MEM_SECTION_NAME == CYGHWR_HAL_LPC_EMAC_MEM_SECTION }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 1544 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 6 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 2 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 5 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 8 }
+
+            requires      { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 3 }
+        }
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_SS1 {
+            display       "lwIP uses different section than the ethernet controller"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_SS1)
+
+            active_if     CYGSEM_LWIP_MEM_SECTION
+            active_if     { CYGDAT_LWIP_MEM_SECTION_NAME != CYGHWR_HAL_LPC_EMAC_MEM_SECTION }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 1600 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  9 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 8 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 10 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 13 }
+
+            requires      { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 4 }
+        }
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_NSS {
+            display       "lwIP does not use a special section"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_NSS)
+
+            active_if     !CYGSEM_LWIP_MEM_SECTION
+
+            requires      { CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE == 1024 }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 884 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 5 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 2 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 5 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 7 }
+
+            requires { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 4 }
+        }
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display       "Global build options"
+        flavor        none
+        parent        CYGPKG_NONE
+        description   "
+            Global build options including control over compiler flags,
+            linker flags and choice of toolchain."
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display       "Global command prefix"
+            flavor        data
+            no_define
+            default_value { "arm-eabi" }
+            description   "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display       "Global compiler flags"
+            flavor        data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which
+                are used to compile all packages by default. Individual
+                packages may define options which override these global
+                flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display       "Global linker flags"
+            flavor        data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global
+                flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on
+            the board, and this ROM monitor may process exceptions or
+            interrupts generated from the application. This enables
+            features such as utilizing a separate interrupt stack when
+            exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the
+            encoding of diagnostic output, or the overriding of hardware
+            interrupt vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This
+            is the most basic support which is likely to be common to
+            most implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included
+            in the ROM monitor or boot ROM."
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_LPC1766STK_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        no_define
+        calculated    1
+        active_if     CYGBLD_BUILD_COMMON_GDB_STUBS
+        requires      { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description   "
+            This component causes the ELF image generated by the build
+            process to be converted to S-Record and binary files."
+    }
+}
+
+# EOF hal_cortexm_lpc17xx_lpc1766stk.cdl
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h
new file mode 100644
index 0000000..37c509c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h
@@ -0,0 +1,30 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x10000000)
+#define CYGMEM_REGION_ram_SIZE (0x00008000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE-CYGHWR_HAL_CORTEXM_LPC17XX_IAP)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ahb_sram_bank0 (0x2007C000)
+#define CYGMEM_REGION_ahb_sram_bank0_SIZE (0x00004000)
+#define CYGMEM_REGION_ahb_sram_bank0_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ahb_sram_bank1 (0x20080000)
+#define CYGMEM_REGION_ahb_sram_bank1_SIZE (0x00004000)
+#define CYGMEM_REGION_ahb_sram_bank1_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi
new file mode 100644
index 0000000..26c8376
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi
@@ -0,0 +1,49 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x10000000, LENGTH = 0x00008000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE-CYGHWR_HAL_CORTEXM_LPC17XX_IAP
+    ahb_sram_bank0  : ORIGIN = 0x2007C000, LENGTH = 0x00004000
+    ahb_sram_bank1  : ORIGIN = 0x20080000, LENGTH = 0x00004000
+    flash : ORIGIN = 0x00000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(lpc17xx_misc, flash, 0x00000020, LMA_EQ_VMA)
+    
+    // LPC17xx Code Read Protection field. Must be present at 0x000002FC
+    // Warning: Code Read Protection field or moving it to
+    //          other location may lock LPC17xx controller.
+    // See src/lpc17xx_mis.c for definition
+
+    .lpc17xxcrp 0x2FC : { KEEP (*(.lpc17xxcrp)) } > flash
+    
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (ahb_sram0, ahb_sram_bank0, 0x2007C000 (NOLOAD), LMA_EQ_VMA)
+    USER_SECTION (ahb_sram1, ahb_sram_bank1, 0x20080000 (NOLOAD), LMA_EQ_VMA)
+    SECTION_data (ram, 0x10000400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x10000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x10000000 + 1024*32-CYGHWR_HAL_CORTEXM_LPC17XX_IAP;
+
+
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h
new file mode 100644
index 0000000..dc0c228
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributor(s): ilijak
+// Date:        2010-12-29
+// Purpose:     LPC1766STK platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_ARCH_H
+// End of plf_arch.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h
new file mode 100644
index 0000000..cbcc469
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2010-12-29
+// Purpose:     LPC1766STK platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_INTR_H
+// End of plf_intr.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h
new file mode 100644
index 0000000..a9f9794
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h
@@ -0,0 +1,92 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-01-02
+// Purpose:     LPC1766STK platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+#if (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 20000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM20MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 40000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM40MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 60000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM60MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 80000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM80MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 100000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM100MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 120000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM120MHZ)
+#else
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIMSAFE)
+#endif
+
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_IO_H
+// End of plf_io.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c
new file mode 100644
index 0000000..1d8e105
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c
@@ -0,0 +1,256 @@
+//==========================================================================
+//
+//      lpc1766stk_misc.c
+//
+//      Cortex-M3 LPC1766STK HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2010-12-22
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>        // tracing macros
+#include <cyg/infra/cyg_ass.h>         // assertion macros
+
+#include <cyg/hal/hal_arch.h>          // HAL header
+#include <cyg/hal/hal_intr.h>          // HAL header
+static inline void hal_gpio_init(void);
+
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void
+hal_system_init(void)
+{
+#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_SRAM)
+    hal_gpio_init();
+#endif
+
+#if defined(CYG_HAL_STARTUP_ROM)
+    {
+        // Set flash accelerator according to CPU clock speed.
+        cyg_uint32      regval;
+        HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                        CYGHWR_HAL_LPC17XX_REG_FLASHCFG, regval);
+        regval &= ~CYGHWR_HAL_LPC17XX_REG_FLTIM_MASK;
+        regval |= CYGHWR_HAL_LPC17XX_REG_FLASHTIM;
+        HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                         CYGHWR_HAL_LPC17XX_REG_FLASHCFG, regval);
+    }
+#endif
+}
+
+
+//===========================================================================
+// hal_gpio_init
+//===========================================================================
+static inline void
+hal_gpio_init(void)
+{
+    // Enable UART0 and UART1 (has wired flow control and line status lines)
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL0,
+                               (1 /* TXD0 */  << 4) |
+                               (1 /* RXD0 */  << 6) |
+                               (1 /* TXD1 */  << 30)
+        );
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL1,
+                               (1 /* RXD1 */  << 0) |
+                               (1 /* CTS1 */  << 2) |
+                               (1 /* DCD1 */  << 4) |
+                               (1 /* DSR1 */  << 6) |
+                               (1 /* DTR1 */  << 8) |
+                               (1 /* RTS1 */  << 12)
+        );
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL2, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL4, 0);
+#if 0 // not used
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL5, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL6, 0);
+#endif
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL7, 0);
+#if 0 // not used
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL8, 0);
+#endif
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL9, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL10, 0);
+}
+
+
+//==========================================================================
+
+__externC void
+hal_platform_init(void)
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS     start;             // Region start address
+    CYG_ADDRESS     end;               // End address (last byte)
+} hal_data_access[] = {
+    {
+    // Main RAM (On-chip SRAM in code area)
+    CYGMEM_REGION_ram, CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - 1},
+#ifdef CYGMEM_REGION_ahb_sram_bank0
+    {
+    // On-chip AHB SRAM bank 0
+    CYGMEM_REGION_ahb_sram_bank0, CYGMEM_REGION_ahb_sram_bank0 + CYGMEM_REGION_ahb_sram_bank0_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_ahb_sram_bank1
+    {
+    // On-chip AHB SRAM bank 1
+    CYGMEM_REGION_ahb_sram_bank1, CYGMEM_REGION_ahb_sram_bank1 + CYGMEM_REGION_ahb_sram_bank1_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_flash
+    {
+    // On-chip flash
+    CYGMEM_REGION_flash, CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_rom
+    {
+    // External flash
+    CYGMEM_REGION_rom, CYGMEM_REGION_rom + CYGMEM_REGION_rom_SIZE - 1},
+#endif
+    {
+    0xE0000000, 0x00000000 - 1},       // Cortex-M peripherals
+    {
+    0x40000000, 0x60000000 - 1},       // Chip specific peripherals
+};
+
+__externC int
+cyg_hal_stub_permit_data_access(CYG_ADDRESS addr, cyg_uint32 count)
+{
+    int             i;
+
+    for (i = 0; i < sizeof(hal_data_access) / sizeof(hal_data_access[0]); i++) {
+        if ((addr >= hal_data_access[i].start) &&
+            (addr + count) <= hal_data_access[i].end)
+            return true;
+    }
+
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the main (S)RAM and peripheral (AHB) SRAM banks.
+
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_ahb_sram_bank0
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_ahb_sram_bank0;
+        *end =
+            (unsigned char *)(CYGMEM_REGION_ahb_sram_bank0 +
+                              CYGMEM_REGION_ahb_sram_bank0_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_ahb_sram_bank1
+# ifndef CYGMEM_REGION_ahb_sram_bank0
+    case 1:
+# else
+    case 2:
+# endif
+        *start = (unsigned char *)CYGMEM_REGION_ahb_sram_bank1;
+        *end =
+            (unsigned char *)(CYGMEM_REGION_ahb_sram_bank1 +
+                              CYGMEM_REGION_ahb_sram_bank1_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+}
+
+#endif // CYGPKG_REDBOOT
+
+
+//==========================================================================
+// EOF lpc1766stk_misc.c
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/ChangeLog b/ecos/packages/hal/cortexm/lpc17xx/var/current/ChangeLog
new file mode 100644
index 0000000..dd49607
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/ChangeLog
@@ -0,0 +1,61 @@
+2012-01-24  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	Fix interrupt minimal priority calculation. [ Bugzilla 1001432 ]
+
+2012-01-16  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	* include/var_io.h:
+	* src/lpc17xx_misc.c:
+	Recognize Code Read Protection FLASH field
+	Reported by Bernard Fouch� [Bugzilla 1001443 ]
+
+2011-05-13  John Dallaway  <john@dallaway.org.uk>
+
+	* include/var_intr.h: Fix I2C interrupt definitions issue reported
+	by Pavel Glinskii. Also fix CYGNUM_HAL_INTERRUPT_NVIC_MAX from Ilija
+	Kocho.
+
+2011-03-14  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl: Do not implement the
+	CYGINT_PROFILE_HAL_TIMER interface at present.
+
+2010-12-10  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/var_arch.h:
+	* include/variant.inc:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* src/hal_diag.c:
+	* src/lpc17xx_misc.c:
+	New package -- NXP LPC17XX variant HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl b/ecos/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl
new file mode 100644
index 0000000..5baeb43
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl
@@ -0,0 +1,468 @@
+##==========================================================================
+##
+##      hal_cortexm_lpc17xx.cdl
+##
+##      Cortex-M LPC 1700 variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ilijak
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LPC17XX {
+    display       "Cortex-M3 LPC 17XX Variant"
+    parent        CYGPKG_HAL_CORTEXM
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_lpc17xx.h
+    description   "
+       This package provides generic support for the NXP Cortex-M based
+       LPC17xx microcontroller family.  It is also necessary to select
+       a variant and platform HAL package."
+
+    compile       hal_diag.c lpc17xx_misc.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M3" }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX {
+        display       "LPC17xx member in use"
+        flavor        data
+        default_value { "1766" }
+        legal_values  {
+            "1751" "1752"  "1754" "1756" "1758" "1759" "1763" "1764"
+            "1765" "1766" "1767" "1768" "1769" }
+        description   "
+            The LPC17xx has several variants, the main differences being
+            in the size of on-chip FLASH and SRAM and numbers of some
+            peripherals. This option allows the platform HAL to select
+            the specific microcontroller fitted."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU priority levels"
+        flavor        data
+        calculated    5
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M
+            CPU implements."
+    }
+
+    cdl_option CYGNUM_HAL_IRQ_PRIORITY_MIN {
+        display       "minimal interrupt priority"
+        flavor        data
+        no_define
+        calculated      0xFFFF&\
+              ((((1<<CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)-1)-1)\
+               <<8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING {
+        display       "Clocking"
+        flavor        none
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_MAIN_CLOCK {
+            display       "Main clock"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL {
+                display       "PLL multiplier"
+                flavor        data
+                legal_values  6 to 32767
+                default_value { 12 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV {
+                display       "PLL divider"
+                flavor        data
+                legal_values  1 to 32
+                default_value { 1 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_OUTPUT {
+                display       "PLL output (MHz)"
+                flavor        data
+                legal_values  275000000 to 550000000
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV }
+                description   "
+                    Normally the PLL output must be in the range of
+                    275MHz to 550MHz."
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED {
+                display       "CPU clock speed"
+                flavor        data
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV }
+                description   "
+                    The core CPU clock speed is the PLL output divided
+                    by the CPU clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV {
+                    display       "CPU clock divider"
+                    flavor        data
+                    legal_values  2 to 256
+                    default_value { 3 }
+                    description   "
+                        The CPU clock divider controls the division of
+                        the PLL output before it is used by the CPU. When
+                        the PLL is bypassed, the division may be by
+                        1. When the PLL is running, the output must be
+                        divided in order to bring the CPU clock frequency
+                        (CCLK) within operating limits. An 8 bit divider
+                        allows a range of options, including slowing
+                        CPU operation to a low rate for temporary power
+                        savings without turning off the PLL."
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_USB_CLOCK {
+            display       "USB clock"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL {
+                display       "PLL multiplier"
+                flavor        data
+                calculated    { 48000000 / CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV {
+                display       "PLL divider"
+                flavor         data
+                legal_values  1 2 3 4
+                default_value { 2 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_OUTPUT {
+                display       "PLL output (MHz)"
+                flavor        data
+                legal_values  156000000 to 320000000
+                calculated    { 2 * 48000000 *  CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV }
+                description   "
+                    Normally the PLL output must be in the range of
+                    156MHz to 320MHz."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_USB_CLOCK_SPEED {
+                display       "USB clock speed"
+                flavor        data
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV }
+                description   "
+                    The USB clock speed is the PLL1 output."
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT {
+            display       "Clock-out option"
+            flavor        bool
+            default_value 0
+
+            description   "
+                This option enables clock output and selects clock source
+                and divider."
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SET {
+                display       "Clock out register setting"
+                flavor        data
+                calculated { (CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SRC |
+                              ((CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_DIV
+                               - (1 && CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT)) << 4) |
+                              (CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT ? 0x100 : 0x0 ))
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL {
+                display       "Clock-out source selector"
+                flavor        data
+                legal_values  { "CPU clock" "Main osc." "RC osc." "USB clock" "RTC osc." }
+                default_value { "CPU clock" }
+                description   "
+                    Select clock out source."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SRC {
+                display       "Clock-out source"
+                flavor        data
+                legal_values  0 1 2 3 4
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "CPU clock" ? 0 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "Main osc." ? 1 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "RC osc."   ? 2 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "USB clock" ? 3 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "RTC osc."  ? 4 :
+                    0
+                }
+                description   "
+                    Clock-out source index."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_DIV {
+                display       "Clock-out divider"
+                flavor        data
+                legal_values  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+                default_value { 10 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_PER_CLK {
+            display       "Peripherial clocking"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_LPC_RTC_32768HZ {
+                display      "RTC uses 32768 Hz clock"
+                flavor       bool
+                calculated   1
+                description  "
+                    This option has to be defined for LPC microcontrollers
+                    which RTC clock has no other clocking option than
+                    RTC 32768 Hz oscilator."
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK {
+                display       "CAN clock speed"
+                flavor        data
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK_DIV }
+                description   "
+                    The CAN clock speed is the CPU clock output divided
+                    by the CAN clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK_DIV {
+                    display       "CAN clock divider"
+                    flavor        data
+                    legal_values  { 1 2 4 6 }
+                    default_value { 2 }
+                    description   "
+                        This divider selects the peripheral clock for
+                        both CAN channels. The divider divides the CPU
+                        clock to get the clock for the CAN peripherals."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK {
+                display       "ADC clock speed"
+                flavor        data
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK_DIV }
+                description   "
+                    The ADC clock speed is the CPU clock output divided
+                    by the ADC clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK_DIV {
+                    display       "ADC clock divider"
+                    flavor        data
+                    legal_values  { 1 2 4 8 }
+                    default_value { 2 }
+                    description   "
+                        This divider selects the peripheral clock for
+                        on-chip ADC. The ADC clock is the input clock
+                        of the ADC peripheral."
+                }
+            }
+
+            for { set ::channel 0 } { $::channel < 3 } { incr ::channel } {
+                cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK {
+                    display       "I2C channel [set ::channel] clock speed"
+                    flavor        data
+                    calculated    CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED / \
+                          CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK_DIV
+                    description   "
+                        The I2C clock speed is the CPU clock output
+                        divided by the I2C clock divider."
+
+                    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK_DIV {
+                        display       "I2C channel [set ::channel] clock divider"
+                        flavor        data
+                        legal_values  { 1 2 4 8 }
+                        default_value { 2 }
+                        description   "
+                            This divider selects the peripheral clock
+                            for I2C channel [set ::channel]. The divider
+                            divides the CPU clock to get the clock for
+                            the I2C peripheral."
+                    }
+                }
+            }
+        }
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    CYGNUM_HAL_IRQ_PRIORITY_MIN
+        description   "
+            Set clock ISR priority to lowest priority."
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "
+                The period defined here is something of a fake, it is
+                expressed in terms of a notional 1MHz clock. The value
+                actually installed in the hardware is calculated from
+                the current settings of the clock generation hardware."
+        }
+    }
+
+    cdl_option CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION {
+        display "Utilize \".lpc17xx_misc\" section for HAL"
+        flavor bool
+        default_value { CYG_HAL_STARTUP == "ROM" }
+        active_if { CYG_HAL_STARTUP == "ROM" }
+        description "
+        Kinetis use FLASH location  0x2fc for FLASH Code Read Protection.
+        This leaves FLASH area below 0x2fc
+            out of standard linker sections. Special section
+            \".lpc17xx_misc\" provides linker access to this area.
+            Setting this option instructs linker to place some HAL
+            (variant/platform) \"misc.\" functions in this area."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART0 {
+        display      "Platform has UART0 serial port"
+        description  "
+            The platform has a socket on UART0."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART1 {
+        display       "Platform has UART1 serial port"
+        description   "
+            The platform has a socket on UART1."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART2 {
+        display       "Platform has UART2 serial port"
+        description   "
+            The platform has a socket on UART2."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART3 {
+        display       "Platform has UART3 serial port"
+        description   "
+            The platform has a socket on UART3."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_ENET {
+        display       "LPC 17xx Ethernet check"
+        flavor        bool
+        no_define
+        parent        CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        calculated    {
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1766") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1758") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1764") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1767") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1768") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769")
+        }
+        requires {
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1766") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1758") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1764") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1767") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1768") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769")
+        }
+        description   "
+            Check whether the chip has Ethernet controler."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_LPC17XX_OPTIONS {
+        display       "Build options"
+        flavor        none
+        description   "
+              Package specific build options including control over
+              compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_LPC17XX_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the LPC17xx variant HAL package. These flags
+                are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_LPC17XX_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the LPC17xx variant HAL package. These flags
+                are removed from the set of global flags if present."
+        }
+    }
+}
+
+# EOF hal_cortexm_lpc17xx.cdl
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h
new file mode 100644
index 0000000..169f109
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h
@@ -0,0 +1,110 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: 
+// Date:         2004-07-23
+// Purpose:      Cache control API
+// Description:  The NXP LPC17XX CPU family does not require cache control.
+//               File is kept empty.
+//
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h
new file mode 100644
index 0000000..7d409aa
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h
@@ -0,0 +1,89 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.                  
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2008-07-30
+// Purpose:        HAL diagnostics
+// Description: 
+// Usage:          #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+# define HAL_DIAG_INIT()          hal_if_diag_init()
+# define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+# define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void  hal_plf_diag_init(void);
+__externC void  hal_plf_diag_putc(char);
+__externC cyg_uint8 hal_plf_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_plf_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc()
+# endif
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_DIAG_H
+// End of hal_diag.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h
new file mode 100644
index 0000000..56a624a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h
@@ -0,0 +1,204 @@
+#ifndef CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+#define CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+//=============================================================================
+//
+//      lpc17xx_misc.h
+//
+//      HAL misc variant support code for NCP LPC17xx header file
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    andyj 
+// Contributors: jani, ilijak
+// Date:         2010-12-29
+// Purpose:      LPC17XX specific miscellaneous support header file
+// Description: 
+// Usage:        #include <cyg/hal/lpc17xx_misc.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Function to obtain the current processor clock settings
+// Use PCLK identifiers below
+//
+externC cyg_uint32 hal_lpc_get_pclk(cyg_uint32 pclk_id);
+#define CYG_HAL_CORTEXM_LPC17XX_PCLK(_pclkid_) hal_lpc_get_pclk(_pclkid_)
+
+//-----------------------------------------------------------------------------
+// Identifiers for peripheral clock. Use these identifiers with the function
+// hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCLK_WDT    0
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCLK_UART0  3
+#define CYNUM_HAL_LPC17XX_PCLK_UART1  4
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_PWM0   5
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCLK_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCLK_SPI    8
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_RTC    9
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_SSP1   10
+#define CYNUM_HAL_LPC17XX_PCLK_DAC    11
+#define CYNUM_HAL_LPC17XX_PCLK_ADC    12
+#define CYNUM_HAL_LPC17XX_PCLK_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCLK_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCLK_ACF    15
+#define CYNUM_HAL_LPC17XX_PCLK_QEI    16
+#define CYNUM_HAL_LPC17XX_PCLK_GPIO   17
+#define CYNUM_HAL_LPC17XX_PCLK_PCB    18
+#define CYNUM_HAL_LPC17XX_PCLK_I2C1   19
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_SSP0   21
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCLK_UART2  24
+#define CYNUM_HAL_LPC17XX_PCLK_UART3  25
+#define CYNUM_HAL_LPC17XX_PCLK_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCLK_I2S    27
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_MCI    28
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_RIT    29
+#define CYNUM_HAL_LPC17XX_PCLK_SYSCON 30
+#define CYNUM_HAL_LPC17XX_PCLK_MC     31
+
+
+//-----------------------------------------------------------------------------
+// Function to enable/disable power for certain peripheral
+// Use PCONP identifiers from below
+//
+externC void hal_lpc_set_power(cyg_uint8 pconp_id, int on);
+#define CYG_HAL_CORTEXM_LPC17XX_SET_POWER(_pconp_id_, _on_) \
+        hal_lpc_set_power((_pconp_id_), (_on_))
+
+
+//-----------------------------------------------------------------------------
+// Identifiers for power control, hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCONP_UART0  3
+#define CYNUM_HAL_LPC17XX_PCONP_UART1  4
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_PWM0   5
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCONP_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCONP_SPI    8
+#define CYNUM_HAL_LPC17XX_PCONP_RTC    9
+#define CYNUM_HAL_LPC17XX_PCONP_SSP1   10
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_EMC    11
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_ADC    12
+#define CYNUM_HAL_LPC17XX_PCONP_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCONP_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCONP_GPIO   15
+#define CYNUM_HAL_LPC17XX_PCONP_RIT    16
+#define CYNUM_HAL_LPC17XX_PCONP_MCPWM  17
+#define CYNUM_HAL_LPC17XX_PCONP_QEI    18
+#define CYNUM_HAL_LPC17XX_PCONP_I2C1   19
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_LCD    20
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_SSP0   21
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCONP_UART2  24
+#define CYNUM_HAL_LPC17XX_PCONP_UART3  25
+#define CYNUM_HAL_LPC17XX_PCONP_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCONP_I2S    27
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_SDC    28
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_GPDMA  29
+#define CYNUM_HAL_LPC17XX_PCONP_ENET   30
+#define CYNUM_HAL_LPC17XX_PCONP_USB    31
+
+
+//-----------------------------------------------------------------------------
+// Configure pin function
+//
+externC void hal_lpc_set_pin_function(cyg_uint8 port, cyg_uint8 pin,
+                                  cyg_uint8 function);
+#define CYG_HAL_CORTEXM_LPC17XX_PIN_CFG(_port_, _pin_, _func_) \
+                hal_lpc_set_pin_function((_port_), (_pin_), (_func_))
+
+
+//-----------------------------------------------------------------------------
+// Macros to derive the baudrate divider values for the internal UARTs
+// The LPC17xx family supports different baudrate clocks for each single
+// UART. So we need a way to calculate the baudrate for each single UART
+// Now we rely on the fact that we use the same baudrate clock for all
+// UARTs and we query only UART0
+//-----------------------------------------------------------------------------
+
+#define CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(_pclkid_, baud) \
+                (CYG_HAL_CORTEXM_LPC17XX_PCLK(_pclkid_)/((baud)*16))
+
+//-----------------------------------------------------------------------------
+// LPC17XX platform reset (watchdog resets the board)
+//-----------------------------------------------------------------------------
+#if 0
+externC void hal_lpc_watchdog_reset(void);
+
+#define HAL_PLATFORM_RESET() hal_lpc_watchdog_reset()
+#define HAL_PLATFORM_RESET_ENTRY 0
+#endif
+
+
+//-----------------------------------------------------------------------------
+// Compatibility layer for LPC2xxx device drivers
+//-----------------------------------------------------------------------------
+#define CYNUM_HAL_LPC24XX_PCLK_UART0 CYNUM_HAL_LPC17XX_PCLK_UART0
+#define CYNUM_HAL_LPC24XX_PCLK_UART1 CYNUM_HAL_LPC17XX_PCLK_UART1
+#define CYNUM_HAL_LPC24XX_PCLK_UART2 CYNUM_HAL_LPC17XX_PCLK_UART2
+#define CYNUM_HAL_LPC24XX_PCLK_UART3 CYNUM_HAL_LPC17XX_PCLK_UART3
+
+#define CYG_HAL_ARM_LPC24XX_BAUD_GENERATOR(_pclkid_, baud) \
+            CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(_pclkid_, baud)
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+// End of lpc17xx_misc.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h
new file mode 100644
index 0000000..e30e1af
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:jskov, gthomas, jlarmour
+// Date:        2008-07-30
+// Purpose:     Platform HAL stub support for STM32 variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+#include <cyg/hal/cortexm_stub.h>       // architecture stub support
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h
new file mode 100644
index 0000000..cbf21e3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h
@@ -0,0 +1,61 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      STM32 variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Purpose:      LPC17XX variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_ARCH_H
+// End of var_arch.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h
new file mode 100644
index 0000000..b2ebe90
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h
@@ -0,0 +1,120 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for LPC17XX variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Date:          2010-12-29
+// Purpose:       Define Interrupt support
+// Description:   The interrupt specifics for NXP LPC17XX variants are
+//                defined here.
+//              
+// Usage:         #include <cyg/hal/var_intr.h>
+//                However applications should include using <cyg/hal/hal_intr.h>
+//                instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_WD      (0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER0  (1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER1  (2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER2  (3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER3  (4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART0   (5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART1   (6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART2   (7+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART3   (8+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM1    (9+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0    (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1    (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C2    (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_SPI     (13+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SSP0    (14+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SSP1    (15+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_PLL0    (16+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RTCDEV  (17+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_EINT0   (18+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT1   (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT2   (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT3   (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AD      (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_BOD     (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_USB     (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN     (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA     (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2S     (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ETH     (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RITINT  (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MCPWM   (30+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_QENC    (31+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PLL1    (32+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_USBAI   (33+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CANWAKE (34+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_CANWAKE)
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX            CYGNUM_HAL_INTERRUPT_CANWAKE
+#define CYGNUM_HAL_ISR_COUNT          (CYGNUM_HAL_ISR_MAX+1)
+
+#define CYGNUM_HAL_VSR_MIN            0
+
+#ifndef CYGNUM_HAL_VSR_MAX
+# define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+
+#define CYGNUM_HAL_VSR_COUNT          (CYGNUM_HAL_VSR_MAX+1)
+
+//==========================================================================
+// Interrupt mask and config for variant-specific devices
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h
new file mode 100644
index 0000000..4e01dd3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h
@@ -0,0 +1,413 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                  
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Original data: Uwe Kindler ( LPC24XX port )
+// Date:          2010-12-22
+// Purpose:       LPC17XX variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Peripherals
+
+//=============================================================================
+// Cortex-M architecture register
+
+// VTOR setting
+#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM               BIT_(28)
+#endif
+
+//---------------------------------------------------------------------------
+// Utilize LPC17xx flash between startup vectors and 0x2fc
+// for misc funtions.
+#ifdef CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION
+# define CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR \
+         CYGBLD_ATTRIB_SECTION(".lpc17xx_misc")
+#else
+# define CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+#endif
+
+__externC const cyg_uint32* hal_lpc17xx_crp_p(void);
+
+// LPC System Control Block
+#define CYGHWR_HAL_LPC17XX_REG_SCB_BASE                 0x400FC000
+
+// Flash accelerator
+#define CYGHWR_HAL_LPC17XX_REG_FLASHCFG                 0x0000
+#define CYGHWR_HAL_LPC17XX_REG_FLTSET(__tim)            (__tim << 12)
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM20MHZ               0x0
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM40MHZ               0x1
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM60MHZ               0x2
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM80MHZ               0x3
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM100MHZ              0x4
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM120MHZ              0x4
+#define CYGHWR_HAL_LPC17XX_REG_FLTIMSAFE                0x5
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM_MASK               CYGHWR_HAL_LPC17XX_REG_FLTSET(0x0f)
+
+// PLL. Registers are offsets from base of this subsystem
+#define CYGHWR_HAL_LPC17XX_REG_PLL0CON                  0x0080
+#define CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE              (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC              (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0CFG                  0x0084
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT                 0x0088
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLE            (1<<24)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC            (1<<25)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLOCK           (1<<26)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0FEED                 0x008C
+
+#define CYGHWR_HAL_LPC17XX_REG_PLL1CON                  0x00A0
+#define CYGHWR_HAL_LPC17XX_REG_PLL1CFG                  0x00A4
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT                 0x00A8
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLE            (1<<8)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLC            (1<<9)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLOCK           (1<<10)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1FEED                 0x00AC
+
+// Clock source selection register
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL                0x010C
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_IRC            0x00
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_MAIN           0x01
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_RTC            0x10
+
+#define CYGHWR_HAL_LPC17XX_REG_CCLKCFG                  0x0104
+#define CYGHWR_HAL_LPC17XX_REG_USBCLKCFG                0x0108
+/* #define CYGHWR_HAL_LPC17XX_REG_IRCTRIM                  0x01A4 */
+#define CYGHWR_HAL_LPC17XX_REG_PCLKSEL0                 0x01A8
+#define CYGHWR_HAL_LPC17XX_REG_PCLKSEL1                 0x01AC
+#define CYGHWR_HAL_LPC17XX_REG_INTWAKE                  0x0144
+
+// Power Control
+#define CYGHWR_HAL_LPC17XX_REG_PCON                     0x00C0
+#define CYGHWR_HAL_LPC17XX_REG_PCON_IDL                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_PCON_PD                  (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP                    0x00C4
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM0               (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM1               (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT0               (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT1               (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_PWM0               (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_PWM1               (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C0               (1<<7)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SPI                (1<<8)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_RTC                (1<<9)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SSP1               (1<<10)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_EMC                (1<<11)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_AD                 (1<<12)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_CAN1               (1<<13)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_CAN2               (1<<14)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C1               (1<<19)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_LCD                (1<<20)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SSP0               (1<<21)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM2               (1<<22)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM3               (1<<23)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT2               (1<<24)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT3               (1<<25)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C2               (1<<26)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2S                (1<<27)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SD                 (1<<28)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_DMA                (1<<29)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_ENET               (1<<30)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_USB                (1<<31)
+
+// Utility
+#define CYGHWR_HAL_LPC17XX_REG_CLKOUTCFG                0x01C8
+
+// System control and status register
+#define CYGHWR_HAL_LPC17XX_REG_SCS                      0x01A0
+#define CYGHWR_HAL_LPC17XX_REG_SCS_OSCEN                0x20
+#define CYGHWR_HAL_LPC17XX_REG_SCS_OSCSTAT              0x40
+
+
+//=============================================================================
+// Pin Connect Block (PIN)
+
+#define CYGHWR_HAL_LPC17XX_REG_PIN_BASE                  0x4002C000
+
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL0                   0x000
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL1                   0x004
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL2                   0x008
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL3                   0x00C
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL4                   0x010
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL5                   0x014
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL6                   0x018
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL7                   0x01C
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL8                   0x020
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL9                   0x024
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL10                  0x028
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL11                  0x02C
+
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE0                  0x040
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE1                  0x044
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE2                  0x048
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE3                  0x04C
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE4                  0x050
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE5                  0x054
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE6                  0x058
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE7                  0x05C
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE8                  0x060
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE9                  0x064
+
+#define CYGHWR_HAL_LPC17XX_PIN_SET(_reg, _func) \
+            HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + _reg, _func)
+
+#define CYGHWR_HAL_LPC17XX_PIN_GET(_reg, _dst) \
+            HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + _reg, _dst)
+
+//=============================================================================
+// UARTs (Ux)
+
+#define CYGHWR_HAL_LPC17XX_REG_UART0_BASE                0x4000C000
+#define CYGHWR_HAL_LPC17XX_REG_UART1_BASE                0x40010000
+#define CYGHWR_HAL_LPC17XX_REG_UART2_BASE                0x40098000
+#define CYGHWR_HAL_LPC17XX_REG_UART3_BASE                0x4009C000
+
+// Registers are offsets from base for each UART
+#define CYGHWR_HAL_LPC17XX_REG_UxRBR                     0x0000 // DLAB=0 read
+#define CYGHWR_HAL_LPC17XX_REG_UxTHR                     0x0000 // DLAB=0 write
+#define CYGHWR_HAL_LPC17XX_REG_UxDLL                     0x0000 // DLAB=1 r/w
+#define CYGHWR_HAL_LPC17XX_REG_UxIER                     0x0004 // DLAB=0
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT          (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_THRE_INT            (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_RXLS_INT            (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_U1IER_RXMS_INT            (1<<3) // U1 only
+#define CYGHWR_HAL_LPC17XX_REG_UxDLM                     0x0004 // DLAB=1
+
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR                     0x0008 // read
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR0                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR1                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR2                (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR3                (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_FIFOS               (0xB0)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR                     0x0008 // write
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_FIFO_ENA            (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_FIFO_RESET       (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_TX_FIFO_RESET       (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_0        (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_1        (0x40)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_2        (0x80)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_3        (0xB0)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR                     0x000C
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_5       (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_6       (0x01)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_7       (0x02)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_8       (0x03)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_1              (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_2              (0x04)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ENA          (0x08)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ODD          (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_EVEN         (0x10)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ONE          (0x20)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ZERO         (0x30)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_BREAK_ENA           (0x40)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_DLAB                (0x80)
+
+// Modem Control Register is UART1 only
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR                     0x0010
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_DTR                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_RTS                 (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_LOOPBACK            (1<<4)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR                     0x0014
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_RDR                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_OE                  (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_PE                  (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_FE                  (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_BI                  (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_THRE                (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_TEMT                (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_RX_FIFO_ERR         (1<<7)
+
+// Modem Status Register is UART1 only
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR                     0x0018
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DCTS                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DDSR                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_RI_FALL             (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DDCD                (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_CTS                 (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DSR                 (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_RI                  (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DCD                 (1<<7)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxSCR                     0x001C
+#define CYGHWR_HAL_LPC17XX_REG_UxACR                     0x0020
+#define CYGHWR_HAL_LPC17XX_REG_U3ICR                     0x0024
+#define CYGHWR_HAL_LPC17XX_REG_UxFDR                     0x0028
+#define CYGHWR_HAL_LPC17XX_REG_UxTER                     0x0030
+
+// RTC
+#define CYGHWR_HAL_LPC17XX_REG_RTC_BASE                   0x40024000
+#define CYGARC_HAL_LPC2XXX_REG_RTC_BASE  CYGHWR_HAL_LPC17XX_REG_RTC_BASE
+
+// Registers are offsets from base of this subsystem
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR                    0x0000
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR_CIF                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR_ALF                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTC                    0x0004
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR                    0x0008
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR_CLKEN              (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR_CTCRST             (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CIIR                   0x000C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_AMR                    0x0010
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME0                 0x0014
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME1                 0x0018
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME2                 0x001C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_SEC                    0x0020
+#define CYGHWR_HAL_LPC17XX_REG_RTC_MIN                    0x0024
+#define CYGHWR_HAL_LPC17XX_REG_RTC_HOUR                   0x0028
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOM                    0x002C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOW                    0x0030
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOY                    0x0034
+#define CYGHWR_HAL_LPC17XX_REG_RTC_MONTH                  0x0038
+#define CYGHWR_HAL_LPC17XX_REG_RTC_YEAR                   0x003C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALSEC                  0x0060
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALMIN                  0x0064
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALHOUR                 0x0068
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOM                  0x006C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOW                  0x0070
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOY                  0x0074
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALMON                  0x0078
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALYEAR                 0x007C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_PREINT                 0x0080
+#define CYGHWR_HAL_LPC17XX_REG_RTC_PREFRAC                0x0084
+
+// Ethernet (EMAC)
+#define CYGHWR_HAL_LPC17XX_REG_EMAC_BASE                0x50000000
+
+// End Peripherals
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_plf_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+//-----------------------------------------------------------------------------
+// Configure pin function
+//
+__externC void  hal_set_pin_function(cyg_uint8 port, cyg_uint8 pin,
+                                     cyg_uint8 function);
+
+//-----------------------------------------------------------------------------
+// Function to enable/disable power for certain peripheral
+// Use PCONP identifiers from below
+//
+externC void hal_lpc_set_power(cyg_uint8 pconp_id, int on);
+
+
+//-----------------------------------------------------------------------------
+// Identifiers for power control, hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCONP_UART0  3
+#define CYNUM_HAL_LPC17XX_PCONP_UART1  4
+#define CYNUM_HAL_LPC17XX_PCONP_PWM0   5
+#define CYNUM_HAL_LPC17XX_PCONP_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCONP_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCONP_SPI    8
+#define CYNUM_HAL_LPC17XX_PCONP_RTC    9
+#define CYNUM_HAL_LPC17XX_PCONP_SSP1   10
+#define CYNUM_HAL_LPC17XX_PCONP_EMC    11
+#define CYNUM_HAL_LPC17XX_PCONP_ADC    12
+#define CYNUM_HAL_LPC17XX_PCONP_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCONP_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCONP_I2C1   19
+#define CYNUM_HAL_LPC17XX_PCONP_LCD    20
+#define CYNUM_HAL_LPC17XX_PCONP_SSP0   21
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCONP_UART2  24
+#define CYNUM_HAL_LPC17XX_PCONP_UART3  25
+#define CYNUM_HAL_LPC17XX_PCONP_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCONP_I2S    27
+#define CYNUM_HAL_LPC17XX_PCONP_SDC    28
+#define CYNUM_HAL_LPC17XX_PCONP_GPDMA  29
+#define CYNUM_HAL_LPC17XX_PCONP_ENET   30
+#define CYNUM_HAL_LPC17XX_PCONP_USB    31
+
+#endif // ifndef __ASSEMBLER__
+
+
+//-----------------------------------------------------------------------------
+// LPC2xxx compatibility block
+// These definitions enable reusing of compatible LPC2xxx devs.
+
+// UART
+#define CYGARC_HAL_LPC24XX_REG_UART0_BASE CYGHWR_HAL_LPC17XX_REG_UART0_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART1_BASE CYGHWR_HAL_LPC17XX_REG_UART1_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART2_BASE CYGHWR_HAL_LPC17XX_REG_UART2_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART3_BASE CYGHWR_HAL_LPC17XX_REG_UART3_BASE
+
+// RTC
+#define CYGARC_HAL_LPC2XXX_REG_RTC_BASE  CYGHWR_HAL_LPC17XX_REG_RTC_BASE
+
+// Ethernet (EMAC)
+#define CYGARC_HAL_LPC2XXX_REG_EMAC_BASE CYGHWR_HAL_LPC17XX_REG_EMAC_BASE
+
+// System Control Block
+#define CYGARC_HAL_LPC24XX_REG_SCB_BASE      CYGHWR_HAL_LPC17XX_REG_SCB_BASE
+
+// Power Control
+#define CYGARC_HAL_LPC24XX_REG_PCONP         CYGHWR_HAL_LPC17XX_REG_PCONP
+#define CYGARC_HAL_LPC24XX_REG_PCONP_ENET    CYGHWR_HAL_LPC17XX_REG_PCONP_ENET
+
+// Pin Connect Block (PIN)
+#define CYGARC_HAL_LPC24XX_REG_PIN_BASE      CYGHWR_HAL_LPC17XX_REG_PIN_BASE
+#define CYGARC_HAL_LPC24XX_REG_PINSEL2       CYGHWR_HAL_LPC17XX_REG_PINSEL2
+#define CYGARC_HAL_LPC24XX_REG_PINSEL3       CYGHWR_HAL_LPC17XX_REG_PINSEL3
+
+// End of LPC2xxx device compatibiliy block.
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_IO_H
+// End of var_io.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc
new file mode 100644
index 0000000..d509d5c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc
@@ -0,0 +1,53 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2010-12-25
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+
+//==========================================================================
+// EOF variant.inc
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c
new file mode 100644
index 0000000..5c8f144
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c
@@ -0,0 +1,402 @@
+//=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2010  Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, jani, ilijak
+// Contributors: jskov, gthomas
+// Date:         2010-12-15
+// Purpose:      HAL diagnostic output
+// Description:  Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>        // base types
+#include <cyg/infra/cyg_trac.h>        // tracing
+
+#include <cyg/hal/hal_arch.h>          // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>            // IO macros
+#include <cyg/hal/hal_if.h>            // interface API
+#include <cyg/hal/hal_intr.h>          // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>          // Helper functions
+#include <cyg/hal/drv_api.h>           // CYG_ISR_HANDLED
+
+#include <cyg/hal/var_io.h>            // USART registers
+#include <cyg/hal/lpc17xx_misc.h>      // peripheral identifiers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32      uart;
+    CYG_ADDRESS     base;
+    cyg_int32       msec_timeout;
+    int             isr_vector;
+    int             baud_rate;
+    cyg_uint8       periph_id;
+    int             irq_state;
+} channel_data_t;
+
+static channel_data_t lpc17xx_ser_channels[] = {
+#if CYGINT_HAL_LPC17XX_UART0>0
+    {0,
+     CYGHWR_HAL_LPC17XX_REG_UART0_BASE,
+     1000,
+     CYGNUM_HAL_INTERRUPT_UART0,
+     CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD,
+     CYNUM_HAL_LPC17XX_PCLK_UART0},
+#endif
+#if CYGINT_HAL_LPC17XX_UART1>0
+    {1,
+     CYGHWR_HAL_LPC17XX_REG_UART1_BASE,
+     1000,
+     CYGNUM_HAL_INTERRUPT_UART1,
+     CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD,
+     CYNUM_HAL_LPC17XX_PCLK_UART1}
+#endif
+};
+
+#define HAL_PLF_SER_CHANNELS lpc17xx_ser_channels
+
+
+//===========================================================================
+// Initialize diagnostic serial channel
+//===========================================================================
+static void
+hal_plf_serial_init_channel(void *__ch_data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = chan->base;
+
+    hal_plf_uart_setbaud(base, chan->baud_rate);
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_8 |
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_1);
+
+    // Reset and enable FIFO
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxFCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_FIFO_ENA |
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_FIFO_RESET |
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_TX_FIFO_RESET);
+}
+
+
+//===========================================================================
+// Write single character
+//===========================================================================
+void
+hal_plf_serial_putc(void *__ch_data, char c)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      sr;
+
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLSR, sr);
+    } while ((sr & CYGHWR_HAL_LPC17XX_REG_UxLSR_THRE) == 0);
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxTHR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+hal_plf_serial_getc_nonblock(void *__ch_data, cyg_uint8 *ch)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      sr;
+    cyg_uint32      c;
+
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLSR, sr);
+
+    if ((sr & CYGHWR_HAL_LPC17XX_REG_UxLSR_RDR) == 0)
+        return false;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxRBR, c);
+
+    *ch = (cyg_uint8)c;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return true;
+}
+
+cyg_uint8
+hal_plf_serial_getc(void *__ch_data)
+{
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    while (!hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return ch;
+}
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+hal_plf_serial_write(void *__ch_data, const cyg_uint8 *__buf,
+                     cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+hal_plf_serial_read(void *__ch_data, cyg_uint8 *__buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        *__buf++ = hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+hal_plf_serial_getc_timeout(void *__ch_data, cyg_uint8 *ch)
+{
+    int             delay_count;
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_bool        res;
+
+    CYGARC_HAL_SAVE_GP();
+
+    // Delay in 10 us steps
+    delay_count = chan->msec_timeout * 100;
+
+    while(true) {
+        res = hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(10);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return res;
+}
+
+static int
+hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    int             ret = 0;
+
+    va_list         ap;
+
+    CYGARC_HAL_SAVE_GP();
+
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxIER,
+                         CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxIER,
+                         CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        {
+            va_list         ap;
+
+            va_start(ap, __func);
+
+            ret = chan->msec_timeout;
+            chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+            va_end(ap);
+        }
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        hal_plf_uart_setbaud(base, chan->baud_rate);
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+hal_plf_serial_isr(void *__ch_data, int *__ctrlc,
+                   CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+
+    if (hal_plf_serial_getc_nonblock(__ch_data, &ch)) {
+        if (cyg_hal_is_break((char *)&ch, 1))
+            *__ctrlc = 1;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return 1;
+}
+
+static void
+hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t *comm;
+    int             cur;
+    int             i;
+
+    cur =
+        CYGACC_CALL_IF_SET_CONSOLE_COMM
+        (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    for (i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; i++) {
+        hal_plf_serial_init_channel(&lpc17xx_ser_channels[i]);
+
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc17xx_ser_channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, hal_plf_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, hal_plf_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, hal_plf_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, hal_plf_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, hal_plf_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_plf_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_plf_serial_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+
+    // Set debug channel baud rate if different
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    lpc17xx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate(&lpc17xx_ser_channels
+                     [CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]);
+#endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int      initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    hal_plf_serial_init();
+}
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void
+hal_plf_diag_init(void)
+{
+    hal_plf_serial_init(&lpc17xx_ser_channels
+                        [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+void
+hal_plf_diag_putc(char c)
+{
+    hal_plf_serial_putc(&lpc17xx_ser_channels
+                        [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8
+hal_plf_diag_getc(void)
+{
+    return
+        hal_plf_serial_getc(&lpc17xx_ser_channels
+                            [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+#endif // if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c b/ecos/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c
new file mode 100644
index 0000000..bb31257
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c
@@ -0,0 +1,430 @@
+//==========================================================================
+//
+//      lpc17xx_misc.c
+//
+//      Cortex-M LPC17XX HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2010-12-12
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>        // tracing macros
+#include <cyg/infra/cyg_ass.h>         // assertion macros
+
+#include <cyg/hal/hal_arch.h>          // HAL header
+#include <cyg/hal/hal_intr.h>          // HAL header
+#include <cyg/hal/hal_if.h>            // HAL header
+
+#include <cyg/hal/lpc17xx_misc.h>
+
+
+//===========================================================================
+//                               DEFINES
+//===========================================================================
+
+cyg_uint32      hal_lpc17xx_sysclk;
+cyg_uint32      hal_cortexm_systick_clock;
+
+cyg_uint32      hal_get_lpc_cpu_clock(void);
+
+void            hal_start_clocks(void);
+
+void            hal_lpc_start_main_clock(void);
+void            hal_lpc_start_usb_clock(void);
+#if defined(CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT)
+void            hal_lpc_clock_out(void);
+#endif
+//==========================================================================
+
+#ifdef CYG_HAL_STARTUP_ROM
+
+//===========================================================================
+// LPC17xx Code Read Protection field field
+//===========================================================================
+
+// Note: LPC17xx Code Read Protection field field must be present in
+//       LPC17xx flash image and ocupy a word at 0x000002FC
+
+// For ".lpc17xx_crp" section definition see MLT files.
+
+const cyg_uint32 LPC17XX_CRP __attribute__((section(".lpc17xxcrp"), used)) = 0xFFFFFFFF;
+
+#endif // CYG_HAL_STARTUP_ROM
+
+const cyg_uint32* hal_lpc17xx_crp_p(void)
+{
+    return &LPC17XX_CRP;
+}
+
+void
+hal_variant_init(void)
+{
+#if 1                                  /* !defined(CYG_HAL_STARTUP_RAM) */
+    hal_start_clocks();
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//==========================================================================
+// Setup up system clocks
+//
+// Set up clocks from configuration. In the future this should be extended so
+// that clock rates can be changed at runtime.
+
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_start_clocks(void)
+{
+    // Main clock - for everything except USB
+    hal_lpc_start_main_clock();
+
+    // USB clock
+    hal_lpc_start_usb_clock();
+
+#if defined CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+    hal_lpc_clock_out();
+#endif
+}
+
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_start_main_clock(void)
+{
+    CYG_ADDRESS     scb_base_p;
+    cyg_uint32      regval;
+
+    scb_base_p = CYGHWR_HAL_LPC17XX_REG_SCB_BASE;
+
+    HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    if (regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC) {
+
+        // Enable PLL, disconnected
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                         CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+    }
+    // Disable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON, 0x00);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Enables main oscillator and wait until it is usable
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_SCS,
+                     CYGHWR_HAL_LPC17XX_REG_SCS_OSCEN);
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_SCS, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_SCS_OSCSTAT));
+
+
+    // Select main OSC, 12MHz, as the PLL clock source
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL,
+                     CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_MAIN);
+
+    // Configure PLL multiplier and pre divider according to configuration
+    // values
+    regval = ((CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL - 1) |
+              (CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV - 1) << 16);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CFG, regval);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Enable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Set CPU clock divider
+    regval = CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV - 1;
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_CCLKCFG, regval);
+
+    // Check lock bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLOCK));
+
+    // Connect CPU clock
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE |
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Check connect bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC));
+
+    // Calculate system clock from configuration
+    hal_lpc17xx_sysclk = CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED;
+    hal_cortexm_systick_clock = hal_lpc17xx_sysclk;
+}
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_start_usb_clock(void)
+{
+    CYG_ADDRESS     scb_base_p;
+    cyg_uint32      regval;
+
+    scb_base_p = CYGHWR_HAL_LPC17XX_REG_SCB_BASE;
+
+    // Configure PLL multiplier and pre divider according to
+    // configuration values
+    regval = ((CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL - 1) |
+              (CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV - 1) << 5);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CFG, regval);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    // Enable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLOCK));
+
+    // Connect USB clock
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE |
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    // Check connect bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLC));
+}
+
+#ifdef CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_clock_out(void)
+{
+    cyg_uint32      regval;
+
+    CYGHWR_HAL_LPC17XX_PIN_GET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, regval);
+    regval &= ~0x00c00000;
+    regval |= 0x00400000;
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, regval);
+
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                     CYGHWR_HAL_LPC17XX_REG_CLKOUTCFG,
+                     CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SET);
+}
+#endif // CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+
+
+cyg_uint32
+hal_lpc_get_cpu_clock(void)
+{
+    cyg_uint32      regval,
+                    pll0stat_div,
+                    pll0stat_mul,
+                    cclkcfg;
+
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_PLL0STAT, pll0stat_div);
+    pll0stat_mul = ((pll0stat_div >> 16) & 0xff) + 1;
+    pll0stat_div = 2 * ((pll0stat_div & 0x7fff) + 1);
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_CCLKCFG, cclkcfg);
+    cclkcfg = (cclkcfg & 0xff) + 1;
+
+    regval =
+        CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ * pll0stat_div / pll0stat_mul /
+        cclkcfg;
+
+    return regval;
+}
+
+
+//===========================================================================
+// Get peripheral clock for a certain peripheral
+//===========================================================================
+cyg_uint32
+hal_lpc_get_pclk(cyg_uint32 pclk_id)
+{
+    static const cyg_uint8 divider_tbl[4] = {
+        4, 1, 2, 8
+    };
+    cyg_uint32      pclkselreg;
+    cyg_uint32      regval;
+    cyg_uint8       divider;
+
+    CYG_ASSERT(pclk_id >= CYNUM_HAL_LPC17XX_PCLK_WDT &&
+               pclk_id <= CYNUM_HAL_LPC17XX_PCLK_SYSCON,
+               "Invalid peripheral clock ID");
+
+    // Decide if we need PCLKSEL0 or PCLKSEL1
+    pclkselreg = ((pclk_id <= CYNUM_HAL_LPC17XX_PCLK_ACF) ?
+                  CYGHWR_HAL_LPC17XX_REG_PCLKSEL0 :
+                  CYGHWR_HAL_LPC17XX_REG_PCLKSEL1);
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+    regval = (regval >> ((pclk_id & 0xF) << 1)) & 0x03;
+    divider = divider_tbl[regval];
+    if ((8 == divider) && (pclk_id >= CYNUM_HAL_LPC17XX_PCLK_CAN1)
+        && (pclk_id <= CYNUM_HAL_LPC17XX_PCLK_ACF)) {
+        divider = 6;
+    }
+    return CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED / divider;
+}
+
+
+//===========================================================================
+// Set peripheral clock
+//===========================================================================
+void
+hal_lpc_set_pclk(cyg_uint32 peripheral_id, cyg_uint8 divider)
+{
+    static const cyg_uint8 clock_tbl[5] = {
+        0x01,                          // divider 1
+        0x02,                          // divider 2
+        0x00,                          // divider 4
+        0x03,                          // divider 6
+        0x03                           // divider 8
+    };
+    cyg_uint32      clock;
+    cyg_uint32      pclkselreg;
+    cyg_uint32      regval;
+
+    CYG_ASSERT(peripheral_id >= CYNUM_HAL_LPC17XX_PCLK_WDT &&
+               peripheral_id <= CYNUM_HAL_LPC17XX_PCLK_SYSCON,
+               "Invalid peripheral clock ID");
+    CYG_ASSERT(divider <= 8, "Wrong peripheral clock divider value");
+
+    // Decide if we need PCLKSEL0 or PCLKSEL1
+    pclkselreg = (peripheral_id <= CYNUM_HAL_LPC17XX_PCLK_ACF) ?
+        CYGHWR_HAL_LPC17XX_REG_PCLKSEL0 : CYGHWR_HAL_LPC17XX_REG_PCLKSEL1;
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+    clock = clock_tbl[divider >> 1];
+    regval &= ~(0x03 << ((peripheral_id & 0xF) << 1));
+    regval |= (clock << ((peripheral_id & 0xF) << 1));
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+}
+
+
+//===========================================================================
+// Set pin function
+//===========================================================================
+void
+hal_lpc_set_pin_function(cyg_uint8 port, cyg_uint8 pin, cyg_uint8 function)
+{
+    cyg_uint32      regval;
+    cyg_uint8       pinsel_reg = port << 1;
+
+    CYG_ASSERT(port <= 4, "Port value out of bounds");
+    CYG_ASSERT(pin <= 31, "Pin value out of bounds");
+    CYG_ASSERT(function <= 3, "Invalid function value");
+
+    pinsel_reg += (pin > 15) ? 1 : 0;
+    pinsel_reg <<= 2;
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + pinsel_reg, regval);
+    regval &= ~(0x03 << ((pin & 0xF) << 1));
+    regval |= (function << ((pin & 0xF) << 1));
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + pinsel_reg, regval);
+}
+
+//===========================================================================
+// Enable/Disable power for certain peripheral
+//===========================================================================
+void
+hal_lpc_set_power(cyg_uint8 pconp_id, int on)
+{
+    cyg_uint32      regval;
+
+    CYG_ASSERT(pconp_id >= CYNUM_HAL_LPC17XX_PCONP_TIMER0 &&
+               pconp_id <= CYNUM_HAL_LPC17XX_PCONP_USB,
+               "Invalid peripheral power ID");
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_PCONP, regval);
+    if (on) {
+        regval |= (0x01 << pconp_id);
+    } else {
+        regval &= ~(0x01 << pconp_id);
+    }
+
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                     CYGHWR_HAL_LPC17XX_REG_PCONP, regval);
+}
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current APB clock settings.
+
+void
+hal_plf_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)
+{
+    cyg_uint32      periph_id = CYNUM_HAL_LPC17XX_PCLK_UART0;
+    cyg_uint16      divider;
+
+    if (CYGHWR_HAL_LPC17XX_REG_UART1_BASE == base)
+        periph_id = CYNUM_HAL_LPC17XX_PCLK_UART1;
+    divider = CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(periph_id, baud);
+    // Set baudrate
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_DLAB);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxDLM, divider >> 8);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxDLL, divider & 0xFF);
+}
+
+//==========================================================================
+// EOF lpc17xx_misc.c
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog
new file mode 100644
index 0000000..3e7d64d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog
@@ -0,0 +1,170 @@
+2012-04-20  Ilija Stanislevik  <ilijas@siva.mk>
+
+	* src/stm3210e_eval_eth_enc424j600.c: New file, initialization
+	of optional enc424j600 ethernet over SPI.
+
+	* include/plf_io.h: Add macro for initialization of optional
+	enc424j600 ethernet over SPI.
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Add component
+	enc424j600 ethernet over SPI.
+
+2012-03-23  James Smith  <jsmith@ecoscentric.com>
+
+	* include/plf_io.h: Update GPIO pin definitions to use new PIN
+	wrapper macros. Update to use common SPEED_SPI name for SPI pin
+	speed selection.
+
+2012-02-29  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm3210e_eval_flash.c: Flash structure needs to be "const"
+	to match header.
+
+2012-01-12  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/plf_io.h: Add SPI and I2C pin and DMA definitions.
+
+2011-12-20  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Just set a requires on
+	RedBoot's number of memory segments to be 2 rather than using a
+	non-configurable option.
+
+2011-12-08  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Indicate to new STM32 variant
+	HAL CDL that this is an F103ZE processor.
+
+2011-01-27  Nick Garnett  <nickg@ecoscentric.com>
+
+	* misc/redboot_JTAG.ecm:
+	* misc/redboot_ROM.ecm: Define CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES
+	to take on-chip flash out of FIS control.
+
+2011-01-01  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl
+	(CYGHWR_HAL_CORTEXM_STM32_FLASH): Should be on by default if generic flash
+	active in configuration.
+
+2010-08-29  John Dallaway  <john@dallaway.org.uk>
+
+	* misc/redboot_JTAG.ecm, misc/redbooot_ROM.ecm:
+	Inhibit the FIS directory entry for RedBoot and management of the
+	internal flash. Issues reported by Carlo Caione.
+
+2009-11-09  Ross Younger  <wry@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Add 
+	  CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_{ADD,REMOVE},
+	  default to -Werror.
+
+2009-07-02  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm3210e_eval_misc.c (hal_system_init): Adjust clock enables
+	in line with changes to bit definitions.
+
+2009-02-04  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi:
+	Add .sram section to linker scripts.
+
+2009-02-07  Chris Holgate  <chris@zynaptic.com>
+
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
+	Modified SRAM section so that initialisation data is placed in ROM.
+
+2009-01-31  Bart Veer <bartv@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: update compiler flags for gcc 4.x
+
+2008-12-10  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Switch value for
+	CYGHWR_MEMORY_LAYOUT to calculated, so that changes to startup
+	type are correctly propagated.
+
+2008-11-20  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Remove doc link
+	to doc that doesn't exist.
+
+2008-11-19  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi (hal_startup_stack):
+	Adjust initial stack to top of external SRAM.
+
+2008-10-28  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h:	
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h: Adjust top of
+	RAM to 1MB.
+	
+2008-10-10  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h:	
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h:
+	Update RAM/SRAM upper limits to account for interrupt/init
+	stack.
+
+	* src/stm3210e_eval_flash.c: Use generic null functions for
+	external flash lock operations.
+
+2008-10-06  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3210e_eval.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/stm3210e_eval_misc.c:
+	* src/stm3210e_eval_flash.c:
+	* misc/redboot_ROM.ecm:
+	* misc/redboot_JTAG.ecm:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h:
+	New package -- ST STM3210E EVAL board HAL.
+	
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl
new file mode 100644
index 0000000..103c61d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl
@@ -0,0 +1,485 @@
+##==========================================================================
+##
+##      hal_cortexm_stm32_stm3210e_eval.cdl
+##
+##      Cortex-M STM3210E EVAL platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2008, 2012 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    nickg
+## Date:         2008-07-30
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL {
+    display       "ST STM3210E EVAL Development Board HAL"
+    parent        CYGPKG_HAL_CORTEXM_STM32
+    requires      { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_F1 == "F103ZE" }
+    define_header hal_cortexm_stm32_stm3210e_eval.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The STM3210E EVAL HAL package provides the support needed to run
+        eCos on the ST STM3210E EVAL board."
+
+    compile       stm3210e_eval_misc.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm3210e_eval.h>"
+	puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"ST STM3210E EVAL\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"RAM"}
+        legal_values  {"RAM" "SRAM" "ROM" "JTAG"}
+	no_define
+	define -file system.h CYG_HAL_STARTUP
+        description   "
+            When targetting the ST STM3210E EVAL board it is possible to
+            build the system for either RAM bootstrap or ROM bootstrap.
+            Select 'RAM' when building programs to load into RAM using onboard
+            debug software such as RedBoot or eCos GDB stubs.  Select 'ROM'
+            when building a stand-alone application which will be put
+            into ROM. The 'JTAG' type allows programs to be downloaded using a
+            JTAG debugger such as a BDI3000 or PEEDI. The 'SRAM' type allows
+            programs to be downloaded via a JTAG debugger into on-chip SRAM."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "RAM" ) ? 
+                        (CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM ?
+                        "cortexm_stm3210e_eval_extrabaseram" : "cortexm_stm3210e_eval_ram")      :
+                        (CYG_HAL_STARTUP == "SRAM") ? "cortexm_stm3210e_eval_sram"     :
+                        (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm3210e_eval_rom"      :
+                        (CYG_HAL_STARTUP == "JTAG") ? "cortexm_stm3210e_eval_jtag"     :
+                                                      "undefined" }
+
+        cdl_option CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM {
+            display       "Additional reserved space at base of RAM"
+            flavor        booldata
+            default_value 0
+            active_if     {CYG_HAL_STARTUP == "RAM"}
+            legal_values  0 to 0x80000
+            description   "
+                If you are using a RedBoot with additional components enabled,
+                such as networking, RedBoot may be occupying additional RAM.
+                In such cases, an eCos application loaded by RedBoot must
+                reserve additional space at the base of RAM to accommodate
+                RedBoot's extra RAM requirements. This option, specified in
+                bytes, allows the amount of extra reserved space to be
+                increased beyond the default."
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+                display "Memory layout linker script fragment"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+                display "Memory layout header file"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_H
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK {
+        display         "Input Clock frequency"
+        flavor          data
+        default_value   8000000
+        legal_values    0 to 1000000000
+        description     "Main clock input."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_STM32_FLASH {
+        display         "Flash support"
+        parent          CYGPKG_IO_FLASH
+        active_if       CYGPKG_IO_FLASH
+        compile         -library=libextras.a stm3210e_eval_flash.c
+        default_value   1
+        description     "Control flash device support for STM3210E-EVAL board."
+    
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL {
+            display         "Internal flash support"
+            default_value   1
+            description     "This option enables support for the internal flash device."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR {
+            display         "External NOR flash support"
+            default_value   1
+            description     "This option enables support for the external NOR flash device."
+        }
+
+    }
+
+    # Both UARTs 0 and 1 are available for diagnostic/debug use.
+    implements CYGINT_HAL_STM32_UART0
+    implements CYGINT_HAL_STM32_UART1
+
+    implements      CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+    implements      CYGINT_IO_SERIAL_LINE_STATUS_HW
+    
+    
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   2
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The ST STM3210E EVAL board has two serial ports. This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    0
+         description      "
+            The ST STM3210E EVAL has two serial ports. This option
+            chooses which port will be used for diagnostic output."
+     }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            RedBoot usess polling to transfer data over this port and
+            might not be able to keep up with baud rates above the
+            default, particularly when doing XYZmodem downloads. The
+            interrupt-driven device driver is able to handle these
+            baud rates, so any high speed application transfers should
+            use that instead.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            RedBoot usess polling to transfer data over this port and
+            might not be able to keep up with baud rates above the
+            default, particularly when doing XYZmodem downloads. The
+            interrupt-driven device driver is able to handle these
+            baud rates, so any high speed application transfers should
+            use that instead.
+            Note: this should match the value chosen for the console port if the
+            console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_STM32_SPIETH_CONTROLLER {
+        display       "STM3210E support for ENC424J600 SPI ethernet"
+        parent        CYGPKG_DEVS_ETH_ENC424J600
+        active_if     CYGPKG_DEVS_ETH_ENC424J600
+        compile       stm3210e_eval_eth_enc424j600.c
+        flavor        none
+        no_define
+
+        description   "
+            Support for ENC424J600 with STM3210E EVAL board."
+            
+        cdl_option CYGNUM_ETH_SPIETH_HAL_INTERRUPT_VECTOR { 
+            display       "Interrupt vector calculated from pin"
+            parent        CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR
+            flavor        data
+            no_define
+            calculated    { "CYGNUM_HAL_INTERRUPT_EXTI" . CYGHWR_HAL_SPIETH_INTERRUPT_PIN } 
+            active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED 
+            description   "
+                Interrupt vector corresponding with external interrupt line used for
+                enc424j600.
+                This value is automatically calculated from CYGHWR_HAL_SPIETH_INTERRUPT_PIN.
+                "
+        } 
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS {
+            display       "SPI bus"
+            flavor        data
+            requires      { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 1) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1 }
+            requires      { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 2) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2 }
+            requires      { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 3) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3 }
+            requires      (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE==50)
+            legal_values  { 1 2 3 } 
+            default_value 1
+            description   "
+                Select which SPI bus of the STM32 the SPI Ethernet controller
+                is connected to."
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_CS {
+            display       "Chip select index"
+            flavor        data
+            default_value 0
+            legal_values  0 to 99
+            description   "
+                Enter the index into the array of chip selects to be used as
+                the chip select for the external Ethernet
+                controller connected to the SPI bus. The list of possible chip
+                selects for the selected SPI bus is defined in the STM32 SPI
+                driver's configuration, for example for SPI bus 1:
+                CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS."
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT {
+            display       "Interrupt pin port"
+            active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED 
+            flavor        data
+            legal_values  { "\'A\'" "\'B\'" "\'C\'" "\'D\'" "\'E\'" "\'F\'" "\'G\'" }
+            default_value {"\'G\'"}
+            description   "
+               This selects the GPIO port associated with the interrupt pin
+               connected to the external Ethernet controller."
+        }
+        
+        cdl_option CYGHWR_HAL_SPIETH_INTERRUPT_PIN {
+            display       "Interrupt pin number"
+            active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED 
+            flavor        data
+            legal_values  0 to 15
+            default_value 15
+            description   "
+               This selects the pin number within the GPIO port associated with
+               the interrupt pin connected to the external Ethernet controller."
+        }
+
+        cdl_option CYGNUM_HAL_SPIETH_INTERRUPT_PRIORITY {
+            display       "Interrupt priority"
+            active_if     CYGINT_IO_ETH_INT_SUPPORT_REQUIRED 
+            flavor        data
+            legal_values  { 0xe0 0xd0 0xc0 0xb0 0xa0 0x90 0x80
+                            0x70 0x60 0x50 0x40 0x30 0x20 0x10 0x00}
+            default_value 0xe0
+            description   "
+               Enter the interrupt priority used for the interrupt
+               connected to the external Ethernet controller. A
+               lower number means a higher priority."
+        }
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_OPTIONS {
+        display "stm3210e HAL build options"
+                flavor  none
+                description   "
+                        Package specific build options including control over
+                        compiler flags used only in building this HAL."
+
+                cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_ADD {
+                        display "Additional compiler flags"
+                        flavor  data
+                        no_define
+                        default_value { "-Werror" }
+                        description   "
+                                This option modifies the set of compiler flags
+                                for building this HAL. These flags are used
+                                in addition to the set of global flags."
+                        }
+                cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_REMOVE {
+                        display "Suppressed compiler flags"
+                        flavor  data
+                        no_define
+                        default_value { "" }
+                        description   "
+                                This option modifies the set of compiler flags
+                                for building this HAL. These flags are
+                                removed from the set of global flags if
+                                present."
+                }
+        }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        requires { CYGNUM_REDBOOT_FLASH_BASE == 0x64000000 }
+        requires { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 2 }
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary images"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to binary image formats suitable for ROM programming."
+
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_STM3210E_EVAL_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O binary $< $@
+        }
+
+        description "This component causes the ELF image generated by the
+                     build process to be converted to S-Record and binary
+                     files."
+    }
+}
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h
new file mode 100644
index 0000000..cb67af0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi
new file mode 100644
index 0000000..a1e5775
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+    rom   : ORIGIN = 0x64000000, LENGTH = 0x01000000
+    ram   : ORIGIN = 0x68000000, LENGTH = 0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, 0x20000400, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x68008000+CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x68100000;
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h
new file mode 100644
index 0000000..62aa297
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h
@@ -0,0 +1,15 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi
new file mode 100644
index 0000000..d72db27
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi
@@ -0,0 +1,37 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+    rom   : ORIGIN = 0x64000000, LENGTH = 0x01000000
+    ram   : ORIGIN = 0x68000000, LENGTH = 0x00100000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, 0x20000400, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x68000000, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*64;
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h
new file mode 100644
index 0000000..cb67af0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi
new file mode 100644
index 0000000..11b1ab9
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+    rom   : ORIGIN = 0x64000000, LENGTH = 0x01000000
+    ram   : ORIGIN = 0x68000000, LENGTH = 0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, 0x20000400, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x68008000, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x68100000;
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h
new file mode 100644
index 0000000..93f4f59
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h
@@ -0,0 +1,24 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00080000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x64000000)
+#define CYGMEM_REGION_rom_SIZE (0x01000000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi
new file mode 100644
index 0000000..0a17ecc
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi
@@ -0,0 +1,38 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+    rom   : ORIGIN = 0x64000000, LENGTH = 0x01000000
+    ram   : ORIGIN = 0x68000000, LENGTH = 0x00100000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, 0x20000400, FOLLOWING (.got))
+    SECTION_data (ram, 0x68000000, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20000000 + 1024*64;
+
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h
new file mode 100644
index 0000000..1ed517d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x68000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi
new file mode 100644
index 0000000..c533b38
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00080000
+    rom   : ORIGIN = 0x64000000, LENGTH = 0x01000000
+    ram   : ORIGIN = 0x68000000, LENGTH = 0x00100000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram, 0x20000400, LMA_EQ_VMA)
+    SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x20010000;
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_arch.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_arch.h
new file mode 100644
index 0000000..ab15b99
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM3210E EVAL platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_intr.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_intr.h
new file mode 100644
index 0000000..f447f8c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM3210E EVAL platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h
new file mode 100644
index 0000000..2cc5bb4
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h
@@ -0,0 +1,165 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM3210E EVAL platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h>
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+#define HAL_AM29XXXXX_UNCACHED_ADDRESS(__addr) (__addr)
+
+//=============================================================================
+// I2C busses and devices
+
+# define HAL_I2C_EXPORTED_DEVICES                                       \
+    __externC cyg_i2c_bus                  hal_stm32_i2c_bus1;          \
+    __externC cyg_i2c_device               hal_stm32_i2c_temperature;
+
+
+//=============================================================================
+// I2C bus pin configurations
+
+#if defined(CYGHWR_HAL_STM32_I2C1_REMAP)
+#define CYGHWR_HAL_STM32_I2C1_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  8, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C1_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  9, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#else
+#define CYGHWR_HAL_STM32_I2C1_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  6, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C1_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  7, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#endif
+
+#define CYGHWR_HAL_STM32_I2C1_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 6, 0, M2P )
+#define CYGHWR_HAL_STM32_I2C1_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 7, 0, P2M )
+
+
+#define CYGHWR_HAL_STM32_I2C2_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, NA, OPENDRAIN, NA, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C2_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, NA, OPENDRAIN, NA, AT_LEAST(50) )
+
+#define CYGHWR_HAL_STM32_I2C2_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 4, 0, M2P )
+#define CYGHWR_HAL_STM32_I2C2_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 5, 0, P2M )
+
+//=============================================================================
+// SPI bus pin configurations
+
+// NOTE: The SPEED_SPI manifest is declared by the device driver
+// (e.g. "devs/spi/cortexm/stm32/<vsn>/src/spi_stm32.c") and is not
+// currently defined in a header.
+
+#ifndef CYGHWR_HAL_STM32_SPI1_REMAP
+#define CYGHWR_HAL_STM32_SPI1_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  5, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  6, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI1_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  7, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG      0
+#else
+#define CYGHWR_HAL_STM32_SPI1_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  3, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  4, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI1_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG      CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP
+#endif
+
+#define CYGHWR_HAL_STM32_SPI1_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 3, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI1_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 2, 0, P2M )
+
+
+#define CYGHWR_HAL_STM32_SPI2_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 13, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI2_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B, 14, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI2_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 15, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG      0
+
+#define CYGHWR_HAL_STM32_SPI2_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 5, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI2_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 4, 0, P2M )
+
+
+
+#ifndef CYGHWR_HAL_STM32_SPI3_REMAP
+#define CYGHWR_HAL_STM32_SPI3_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  3, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  4, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI3_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG      0
+#else
+#define CYGHWR_HAL_STM32_SPI3_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C, 11, NA, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI3_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, NA, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG      CYGHWR_HAL_STM32_AFIO_MAPR_SPI3_RMP
+#endif
+
+#define CYGHWR_HAL_STM32_SPI3_DMA_TX            CYGHWR_HAL_STM32_DMA( 2, 2, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI3_DMA_RX            CYGHWR_HAL_STM32_DMA( 2, 1, 0, P2M )
+
+
+//=============================================================================
+// Optional enc424j600 Ethernet over SPI
+
+#ifdef CYGPKG_DEVS_ETH_ENC424J600
+struct cyg_netdevtab_entry;
+__externC void cyg_devs_cortexm_stm3210e_enc424j600_init( struct cyg_netdevtab_entry * );
+#define CYG_DEVS_ETH_ENC424J600_PLF_INIT( _tab_ ) \
+			cyg_devs_cortexm_stm3210e_enc424j600_init( _tab_ )
+
+#endif
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm
new file mode 100644
index 0000000..b7080cb
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm
@@ -0,0 +1,99 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value JTAG
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT {
+    user_value 0
+};
+
+cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST {
+    user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES {
+    user_value 1 "0x08000000"
+};
+
+
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm
new file mode 100644
index 0000000..a0e2f0f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm
@@ -0,0 +1,98 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT {
+    user_value 0
+};
+
+cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST {
+    user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+
+cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES {
+    user_value 1 "0x08000000"
+};
+
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c
new file mode 100644
index 0000000..85551e8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c
@@ -0,0 +1,148 @@
+/*==========================================================================
+//
+//      stm3210e_eval_eth_enc424j600.c
+//
+//      Setup for optional enc424j600 Ethernet over SPI
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Ilija Stanislevik
+// Date:         2012-04-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/io/spi.h>
+#include <cyg/io/spi_stm32.h>
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+#include <cyg/io/eth/enc424j600_eth.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+// Set to: 1 for diagnostic printouts; 0 for no diagnostic printouts.
+#define DEBUG_ENC424J600_PLATFORM_INIT 0
+
+// SPI device for communication with enc424j600 Ethernet chip
+#define TRANS8B            false
+#define CLK_IDLE_LOW        0
+#define CLK_PHASE_RISING    0
+
+#define AUX_SPI_CORTEXM_STM32_DEVICE(_name_, _bus_)     \
+    CYG_DEVS_SPI_CORTEXM_STM32_DEVICE(                  \
+        _name_##_spi,                                   \
+        _bus_,                                          \
+        CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_CS,         \
+        TRANS8B,                                        \
+        CLK_IDLE_LOW,                                   \
+        CLK_PHASE_RISING,                               \
+        14000000,                                       \
+        1,                                              \
+        1,                                              \
+        1                                               \
+    )
+
+AUX_SPI_CORTEXM_STM32_DEVICE
+(
+    CYGDAT_IO_ETH_ENC424J600_NAME,
+    CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS
+);
+
+// Code to initialize enc424j600 driver data structure.
+
+void cyg_devs_cortexm_stm3210e_enc424j600_init( struct cyg_netdevtab_entry * netdevtab_entry)
+{
+    struct eth_drv_sc *eth_inst = NULL;          // pointer to device instance
+    enc424j600_priv_data_t *eth_inst_pd = NULL;  // device's private data
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+    cyg_uint32 cr;
+    cyg_uint32 backupr;
+#endif
+
+//  Assign SPI device to Ethernet device.
+    eth_inst = netdevtab_entry->device_instance;
+    eth_inst_pd = (enc424j600_priv_data_t *)eth_inst->driver_private;
+
+#if DEBUG_ENC424J600_PLATFORM_INIT & 1
+    diag_printf("%s(): Assigning SPI device to Ethernet device %s.\n",__FUNCTION__, netdevtab_entry->name);
+#endif
+    eth_inst_pd->spi_service_device = (cyg_spi_device *) &CYGDAT_IO_ETH_ENC424J600_NAME_spi_stm32;
+
+#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+
+// Interrupt output from enc424j600 is connected to one of the pins from ports A-G.
+// Here this pin is marshaled to External Interrupt Controller (EXTI).
+
+#define ENC424J600_INTERRUPT_SOURCE_PIN  CYGHWR_HAL_SPIETH_INTERRUPT_PIN
+#define ENC424J600_EXTICR                ((ENC424J600_INTERRUPT_SOURCE_PIN / 4) * 4 + 8)
+#define ENC424J600_SHIFT_VALUE           ((ENC424J600_INTERRUPT_SOURCE_PIN % 4) * 4)
+
+#if DEBUG_ENC424J600_PLATFORM_INIT & 1
+    diag_printf("%s(): Mapping external interrupt from P%c%d.\n",__FUNCTION__,
+                CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT,
+                ENC424J600_INTERRUPT_SOURCE_PIN);
+#endif
+
+    // Is AFIO clock enabled?
+    HAL_READ_UINT32(CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB2ENR , backupr );
+    if (0 == (backupr & BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO)))
+    {
+        CYGHWR_HAL_STM32_CLOCK_ENABLE(CYGHWR_HAL_STM32_CLOCK(APB2,AFIO));
+    }
+
+    // Modify External Interrupt Control Register
+    HAL_READ_UINT32(CYGHWR_HAL_STM32_AFIO + ENC424J600_EXTICR , cr );
+    cr |= ((cyg_uint32)0xf << ENC424J600_SHIFT_VALUE);
+    cr &= (((cyg_uint32)(CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT - 'A')
+                            << ENC424J600_SHIFT_VALUE) & 0xffff);
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_AFIO + ENC424J600_EXTICR , cr );
+
+    // Restore AFIO clock
+    if (0 == (backupr & BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO)))
+    {
+        CYGHWR_HAL_STM32_CLOCK_DISABLE(CYGHWR_HAL_STM32_CLOCK(APB2,AFIO));
+    }
+
+#endif  //  #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
+}
+
+//==========================================================================
+// EOF stm3210e_eval_eth_enc424j600.c
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c
new file mode 100644
index 0000000..e0c244e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c
@@ -0,0 +1,115 @@
+/*==========================================================================
+//
+//      stm3210e_eval_flash.c
+//
+//      Cortex-M3 STM3210E EVAL Flash setup
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/io/flash.h>
+#include <cyg/io/flash_dev.h>
+#include <cyg/hal/hal_io.h>
+
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL
+//--------------------------------------------------------------------------
+// Internal flash
+
+#include <cyg/io/stm32_flash.h>
+
+const cyg_stm32_flash_dev hal_stm32_flash_priv;
+
+CYG_FLASH_DRIVER(hal_stm32_flash,
+                 &cyg_stm32_flash_funs,
+                 0,
+                 0x08000000,
+                 0,
+                 0,
+                 0,
+                 &hal_stm32_flash_priv
+);
+
+#endif // CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR
+//--------------------------------------------------------------------------
+// There is a Spansion S29GL128P90FFIR20 or a NUMONYX equivalent.
+// These are AMD compatible and with CFI can all be handled by the AMD
+// driver.
+
+
+#include <cyg/io/am29xxxxx_dev.h>
+
+static const CYG_FLASH_FUNS(hal_stm3210e_flash_amd_funs,
+                            &cyg_am29xxxxx_init_cfi_16,
+                            &cyg_flash_devfn_query_nop,
+                            &cyg_am29xxxxx_erase_16,
+                            &cyg_am29xxxxx_program_16,
+                            (int (*)(struct cyg_flash_dev*, const cyg_flashaddr_t, void*, size_t))0,
+                            &cyg_flash_devfn_lock_nop,
+                            &cyg_flash_devfn_unlock_nop);
+
+static const cyg_am29xxxxx_dev hal_stm3210e_flash_priv;
+
+CYG_FLASH_DRIVER(hal_stm3210e_flash,
+                 &hal_stm3210e_flash_amd_funs,
+                 0,
+                 0x64000000,
+                 0,
+                 0,
+                 hal_stm3210e_flash_priv.block_info,
+                 &hal_stm3210e_flash_priv);
+
+#endif // CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR
+
+//--------------------------------------------------------------------------
+// EOF stm3210e_eval_flash.c
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c
new file mode 100644
index 0000000..52fa886
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c
@@ -0,0 +1,256 @@
+/*==========================================================================
+//
+//      stm3210e_eval_misc.c
+//
+//      Cortex-M3 STM3210E EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables. 
+
+__externC void hal_system_init( void )
+{
+    CYG_ADDRESS base;
+    
+#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM)
+    
+    // Enable peripheral clocks in RCC
+
+    base = CYGHWR_HAL_STM32_RCC;
+    
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHBENR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FSMC)  |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FLITF) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_SRAM)  );
+
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB2ENR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG) );
+
+    // Set all unused GPIO lines to input with pull down to prevent
+    // them floating and annoying any external hardware.
+
+    base = CYGHWR_HAL_STM32_GPIOA;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );
+    
+    base = CYGHWR_HAL_STM32_GPIOB;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );
+    
+    base = CYGHWR_HAL_STM32_GPIOC;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );
+    
+    // Set up GPIO lines for external bus
+
+    base = CYGHWR_HAL_STM32_GPIOD;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bb44bb );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb );
+
+    base = CYGHWR_HAL_STM32_GPIOE;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0xbbbbb4bb );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb );
+
+    base = CYGHWR_HAL_STM32_GPIOF;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbb4444 );
+
+    base = CYGHWR_HAL_STM32_GPIOG;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x44444bb4 );
+
+    
+    // Set up FSMC NOR/SRAM bank 2 for NOR Flash
+
+    base = CYGHWR_HAL_STM32_FSMC;
+
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001059 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x10000705 );
+
+    // Set up FSMC NOR/SRAM bank 3 for SRAM
+
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR3, 0x00001011 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR3, 0x00000200 );
+
+#endif
+
+    // Enable flash prefetch buffer and set latency to 2 wait states.
+    {
+        cyg_uint32 acr;
+        
+        base = CYGHWR_HAL_STM32_FLASH;
+
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTBE;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(2);
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+    }
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct
+{
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // External SRAM
+#ifdef CYGMEM_REGION_sram    
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash    
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+#ifdef CYGMEM_REGION_rom    
+    { CYGMEM_REGION_rom,        CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1      },      // External flash
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // STM32 peripherals
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ )
+    {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#elif defined(CYGMEM_REGION_xram)
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_xram;
+        *end = (unsigned char *)(CYGMEM_REGION_xram + CYGMEM_REGION_xram_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+
+//==========================================================================
+// EOF stm3210e_eval_misc.c
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog
new file mode 100644
index 0000000..9ccd105
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog
@@ -0,0 +1,42 @@
+2013-08-09  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_stm32_stm32f4discovery.cdl: Merge CDL goal
+	expressions to avoid confusing the eCos Configuration Tool during
+	initial inference of STM32 variant HAL options.
+
+2013-06-09  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_stm32_stm32f4discovery.cdl,
+	include/plf_arch.h, include/plf_intr.h, include/plf_io.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h,
+	include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi,
+	src/stm32f4discovery_flash.c, src/stm32f4discovery_misc.c,
+	tests/gpio.c, misc/openocd-misc.cfg, doc/stm32f4discovery.sgml:
+	New STM32F4-Discovery platform HAL package. Derived from
+	STM32x0G-EVAL platform HAL package.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl
new file mode 100644
index 0000000..e367003
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl
@@ -0,0 +1,289 @@
+##==========================================================================
+##
+##      hal_cortexm_stm32_stm32f4discovery.cdl
+##
+##      Cortex-M STM32F4-Discovery platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2013 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    jld
+## Based on:     stm32x0g_eval CDL by jlarmour
+## Date:         2013-06-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY {
+    display       "STMicroelectronics STM32F4-Discovery board HAL"
+    parent        CYGPKG_HAL_CORTEXM_STM32
+
+    requires      { CYGHWR_HAL_CORTEXM == "M4" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" &&
+                    CYGHWR_HAL_CORTEXM_STM32_F4 == "F407VG" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSE" }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 8 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 336 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 2 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 7 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 }
+
+    include_dir   cyg/hal
+    hardware
+    doc           ref/hal-cortexm-stm32f4discovery-part.html
+    description   "
+        The STM32F4-Discovery HAL package provides the support needed to run
+        eCos on the STMicroelectronics STM32F4-Discovery board."
+
+    compile       stm32f4discovery_misc.c
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"STMicroelectronics STM32F4-Discovery\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    # use UART4 at PC10,11 for diagnostic I/O (named UART3 in the STM32 variant HAL)
+    implements CYGINT_HAL_STM32_UART3
+
+    implements CYGINT_HAL_FPV4_SP_D16
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"JTAG"}
+        legal_values  {"JTAG" "ROM"}
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            Select 'JTAG' when building applications to download into on-chip RAM
+            using the on-board ST-LINK/V2 serial wire debugging interface. Select
+            'ROM' when building an application which will be written to on-chip
+            Flash memory for immediate execution on system reset."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "ROM"    ) ? "cortexm_stm32f4discovery_rom"      :
+                        (CYG_HAL_STARTUP == "JTAG"   ) ? "cortexm_stm32f4discovery_jtag"     :
+                                                         "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+                display "Memory layout linker script fragment"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+                display "Memory layout header file"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_H
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK {
+        display         "Input clock frequency"
+        flavor          data
+        default_value   8000000
+        legal_values    0 to 1000000000
+        description     "Main clock input."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES {
+        display         "Flash read wait states"
+        flavor          data
+        default_value   5
+        legal_values    0 to 7
+        description     "
+            This option gives the number of wait states to use for accessing
+            the flash for reads. The correct setting for this value depends
+            on both the CPU clock (HCLK) frequency and the voltage. Consult
+            the STM32 Flash programming manual (PM0059) for appropriate
+            values for different clock speeds or voltages. The default of
+            5 reflects a supply voltage of 3.3V and HCLK of 168MHz."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH {
+        display         "Flash driver support"
+        parent          CYGPKG_IO_FLASH
+        active_if       CYGPKG_IO_FLASH
+        compile         -library=libextras.a stm32f4discovery_flash.c
+        default_value   1
+        description     "Control flash device support for STM32F4-Discovery board."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        calculated       0
+        description      "
+            The STM32F4-Discovery board has one serial port enabled. This option
+            informs the rest of the system which port will be used to connect
+            to a host running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         calculated       0
+         description      "
+            The STM32F4-Discovery board has one serial port enabled. This option
+            informs the rest of the system which port will be used for
+            diagnostic output."
+     }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option controls the default baud rate used for the
+            console connection."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "Debug serial port baud rate"
+        flavor        data
+        calculated    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_OPTIONS {
+        display "STM32F4-Discovery HAL build options"
+        flavor  none
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this HAL package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "-Werror" }
+            description   "
+                This option modifies the set of compiler flags
+                for building this HAL. These flags are used
+                in addition to the set of global flags."
+        }
+        cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags
+                for building this HAL. These flags are
+                removed from the set of global flags if
+                present."
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_TESTS {
+        display "STM32F4-Discovery tests"
+        flavor  data
+        no_define
+        calculated { "tests/gpio" }
+        description   "
+            This option specifies the set of tests for the STM32F4-Discovery HAL."
+    }
+
+}
+
+# EOF hal_cortexm_stm32_stm32f4discovery.cdl
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml
new file mode 100644
index 0000000..67295cb
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml
@@ -0,0 +1,215 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     stm32f4discovery.sgml                                       -->
+<!--                                                                 -->
+<!--     STM32F4-Discovery platform HAL documentation                -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2003, 2004, 2008, 2013 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   jld                                                -->
+<!-- Based on:    M5272C3 documentation by bartv                     -->
+<!-- Date:        2013-06-07                                         -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<part id="hal-cortexm-stm32f4discovery-part"><title>STMicroelectronics STM32F4-Discovery Board Support</title>
+
+<refentry id="cortexm-stm32f4discovery">
+  <refmeta>
+    <refentrytitle>Overview</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>eCos Support for the STMicroelectronics STM32F4-Discovery Board</refname>
+    <refpurpose>Overview</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-description"><title>Description</title>
+    <para>
+The STMicroelectronics STM32F4-Discovery board has an STM32F407VGT6 Cortex-M4F processor,
+192KiB of on-chip SRAM, 1MiB of on-chip flash memory, plus motion and audio sensors, an
+audio DAC and a connector for the on-chip USB peripheral. The board also
+features an ST-LINK/V2 serial wire debug (SWD) interface.
+    </para>
+    <para>
+For typical eCos development the ST-LINK/V2 interface is connected via USB to a host
+computer running the OpenOCD on-chip debug tool. OpenOCD provides a GDB server enabling
+the download and debuging of eCos applications via the GDB debugger.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-hardware"><title>Supported Hardware</title>
+    <para>
+By default, eCos will use the 128KiB of contiguous on-chip SRAM, accessible
+at location 0x20000000. On-chip flash memory at 0x08000000 can be optionally
+used for bootable application code. A further 64KiB of core coupled memory (CCM)
+is mapped to location 0x10000000. This memory is not used by eCos but may be used
+for application-defined static data structures such as thread stacks which require no
+initialization other than that performed during eCos startup and application
+execution. Data structures may be assigned to the <varname>.ccm</varname> section
+within CCM memory using the eCos <varname>CYGBLD_ATTRIB_SECTION</varname> macro. For example:
+    </para>
+    <programlisting>char thread_stack[4096] CYGBLD_ATTRIB_SECTION(".ccm");</programlisting>
+    <para>
+There is a serial driver <varname>CYGPKG_IO_SERIAL_CORTEXM_STM32</varname>
+which supports all on-chip UARTs. However, there are no RS232 drivers or
+serial connectors on the board. STM32 UART4 (named UART3 in the eCos serial driver) is
+enabled for use as a diagnostics channel.
+    </para>
+    <para>
+The GPIO ports are enabled and manipulated only as needed
+to access UART4, the LEDs and the push button. eCos does not
+enable the remaining on-chip peripherals.
+    </para>
+  </refsect1>
+  <refsect1 id="cortexm-stm32f4discovery-tools"><title>Tools</title>
+    <para>
+The STM32F4-Discovery board port is intended to work with GNU tools
+configured for an arm-eabi target. The original porting work was performed using
+binutils 2.18.50.20080513, arm-eabi-gcc 4.3.2, arm-eabi-gdb 7.4.1 and OpenOCD 0.6.1.
+    </para>
+  </refsect1>
+</refentry>
+
+<refentry id="cortexm-stm32f4discovery-setup">
+  <refmeta>
+    <refentrytitle>Setup</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>Setup</refname>
+    <refpurpose>Preparing for eCos Development with the STM32F4-Discovery board</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-overview"><title>Overview</title>
+    <para>
+In a typical development environment the STM32F4-Discovery board is halted
+on reset using OpenOCD communicating via the ST-LINK/V2 SWD interface. eCos
+applications are configured for JTAG startup, then downloaded to the board
+and executed via the arm-eabi-gdb debugger.
+    </para>
+    <para>
+OpenOCD may be configured for use with the STM32F4-Discovery board using the
+board configuration script <filename>stm32f4discovery.cfg</filename> provided with the tool.
+It is also necessary to define a handler for GDB attach events which will halt the board. A
+suitable OpenOCD script is provided at <filename>misc/openocd-misc.cfg</filename> in the
+STM32F4-Discovery platform HAL package. Both scripts may be specified on the OpenOCD
+command line.
+    </para>
+  </refsect1>
+  <refsect1 id="cortexm-stm32f4discovery-config-diagnostic"><title>Diagnostic output</title>
+    <para>
+For diagnostic output, a SparkFun FTDI 3.3v Basic Breakout board or similar
+may be connected to UART4 of the STM32F4-Discovery board using jumper wires as follows:
+    </para>
+    <informaltable frame="all">
+        <tgroup cols="3" colsep="1" rowsep="1" align="left">
+            <thead>
+	        <row>
+                    <entry>Function</entry>
+                    <entry>STM32F4-Discovery header</entry>
+                    <entry>SparkFun FTDI breakout board socket</entry>
+                </row>
+            </thead>
+            <tbody>
+	        <row>
+                    <entry>UART4 Tx</entry>
+                    <entry>PC10</entry>
+                    <entry>RXI</entry>
+                </row>
+                <row>
+                    <entry>Ground</entry>
+                    <entry>GND</entry>
+                    <entry>GND</entry>
+                </row>
+            </tbody>
+        </tgroup>
+    </informaltable>
+    <para>
+The UART is configured at 115200 baud by default and runs with 8 bits,
+no parity, and 1 stop bit. The baud rate can be changed via the
+configuration option <varname>CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD</varname>.
+    </para>
+  </refsect1>
+</refentry>
+
+<refentry id="cortexm-stm32f4discovery-config">
+  <refmeta>
+    <refentrytitle>Configuration</refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname>Configuration</refname>
+    <refpurpose>Platform-specific Configuration Options</refpurpose>
+  </refnamediv>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-overview"><title>Overview</title>
+    <para>
+The STM32F4-Discovery platform HAL package is loaded automatically when eCos is
+configured for an STM32F4-Discovery target. It should never be necessary to load
+this package explicitly. Unloading of the package should only occur as a result
+of switching target hardware.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-startup"><title>Startup</title>
+    <para>
+The STM32F4-Discovery platform HAL package supports two startup types which may be
+selected using the configuration option <varname>CYG_HAL_STARTUP</varname>:
+    </para>
+    <variablelist>
+      <varlistentry>
+        <term>JTAG</term>
+        <listitem><para>
+This is the startup type which is normally used during application
+development. <application>arm-eabi-gdb</application> is used to download a JTAG
+startup application into memory via OpenOCD and the ST-LINK/V2 SWD debug interface.
+eCos startup code will perform all necessary hardware initialization.
+        </para></listitem>
+      </varlistentry>
+      <varlistentry>
+        <term>ROM</term>
+        <listitem><para>
+This startup type can be used for finished applications which will
+be programmed into flash at location 0x08000000. It can also be used for
+debugging larger applications which do not fit in available SRAM. The
+application must be programmed to flash using the ST-LINK tool before debugging commences.
+eCos startup code will perform all necessary hardware initialization.
+        </para></listitem>
+      </varlistentry>
+    </variablelist>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-flash"><title>Flash Driver</title>
+    <para>
+The platform HAL package contains flash driver support. This support may be
+activated by loading the eCos flash I/O infrastructure package <varname>CYGPKG_IO_FLASH</varname>.
+    </para>
+  </refsect1>
+
+  <refsect1 id="cortexm-stm32f4discovery-config-clock"><title>System Clock</title>
+    <para>
+By default the system clock interrupts once every 10ms, corresponding
+to a 100Hz clock. This period can be modified using the configuration option
+<varname>CYGNUM_HAL_RTC_PERIOD</varname>.
+    </para>
+  </refsect1>
+</refentry>
+
+</part>
+
+<!-- EOF stm32f4discovery.sgml -->
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h
new file mode 100644
index 0000000..63fb7bc
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi
new file mode 100644
index 0000000..9b1c4eb
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (ccm, ccm, 0x10000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h
new file mode 100644
index 0000000..63fb7bc
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi
new file mode 100644
index 0000000..fcf96e7
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi
@@ -0,0 +1,43 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+}
+
+hal_vsr_table = 0x20000000;
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    USER_SECTION (ccm, ccm, 0x10000000, LMA_EQ_VMA)
+    SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, hal_virtual_vector_table_end, FOLLOWING (.got))
+    SECTION_data (ram, ALIGN( 0x8), FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h
new file mode 100644
index 0000000..c643a40
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Based on:    stm32x0g_eval overrides by nickg
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h
new file mode 100644
index 0000000..48da0a8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Based on:    stm32x0g_eval overrides by nickg
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h
new file mode 100644
index 0000000..8f5eb5a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h
@@ -0,0 +1,67 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jld
+// Date:        2013-06-06
+// Purpose:     STM32F4-Discovery platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+// User LEDs and button
+
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED1 CYGHWR_HAL_STM32_PIN_OUT( D, 12, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED2 CYGHWR_HAL_STM32_PIN_OUT( D, 13, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED3 CYGHWR_HAL_STM32_PIN_OUT( D, 14, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_LED4 CYGHWR_HAL_STM32_PIN_OUT( D, 15, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32F4DISCOVERY_BTN1 CYGHWR_HAL_STM32_PIN_IN( A, 0, NONE )
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg
new file mode 100644
index 0000000..a2d204b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg
@@ -0,0 +1,54 @@
+##==========================================================================
+##
+##      openocd-misc.cfg
+##
+##      Cortex-M STM32F4-Discovery OpenOCD miscellaneous definitions
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2013 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    jld
+## Date:         2013-06-09
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+gdb_memory_map disable
+stm32f4x.cpu configure -event gdb-attach {
+    reset init
+}
+
+# EOF openocd-misc.cfg
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c
new file mode 100644
index 0000000..5c5a7a0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c
@@ -0,0 +1,65 @@
+/*==========================================================================
+//
+//      stm32f4discovery_flash.c
+//
+//      Cortex-M4 STM32F4-Discovery Flash setup
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Based on:     stm32x0g_eval flash setup by jlarmour
+// Date:         2013-06-06
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <cyg/io/flash_dev.h>
+#include <cyg/io/stm32_flash.h>
+
+CYG_FLASH_DRIVER(hal_stm32_flash,
+                 &cyg_stm32_flash_funs,
+                 0,
+                 0x08000000,
+                 0,
+                 0,
+                 0,
+                 &hal_stm32_flash_priv
+);
+
+//--------------------------------------------------------------------------
+// EOF stm32f4discovery_flash.c
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c
new file mode 100644
index 0000000..8f3f5f0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c
@@ -0,0 +1,147 @@
+/*==========================================================================
+//
+//      stm32f4discovery_misc.c
+//
+//      Cortex-M4 STM32F4-Discovery HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011, 2012, 2013 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Based on:     stm32x0g_eval misc setup by jlarmour
+// Date:         2013-06-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>
+
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_if.h>
+
+//==========================================================================
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+#if (CYGNUM_CALL_IF_TABLE_SIZE > 64)
+// We force a compilation error for this fatal condition since run-time asserts
+// may not be enabled for the build.
+#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated"
+#endif
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void hal_system_init( void )
+{
+    CYG_ADDRESS base;
+
+    // Enable CCM clock and any required GPIO ports in RCC
+    base = CYGHWR_HAL_STM32_RCC;
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) );
+
+    // Set unused lines on enabled GPIO ports to input with pull down
+
+    // GPIO Port A - setup PA0 for button, PA9 for LED, PA13,14 for SWD
+    base = CYGHWR_HAL_STM32_GPIOA;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x82A8AAA8 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x28040000 );
+
+    // GPIO Port C - setup PC10,11 for RS232 (UART4)
+    base = CYGHWR_HAL_STM32_GPIOC;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA0AAAAA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A00000 );
+
+    // GPIO Port D - setup PD5,12,13,14,15 for LEDs
+    base = CYGHWR_HAL_STM32_GPIOD;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA2AA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x55000400 );
+
+    // Enable flash prefetch buffer, cacheability and set latency to 2 wait states
+    // Latency has to be set before clock is switched to a higher speed
+    {
+        cyg_uint32 acr;
+
+        base = CYGHWR_HAL_STM32_FLASH;
+
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES);
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+    }
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+#ifdef CYGDBG_USE_ASSERTS
+    __externC char __sram_data_start[];
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    // Check the number of VSRs matches the linker script. We can do this
+    // because we intend the VV table to follow the VSR table with no gaps.
+    CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+    // Now check the declared start of SRAM data follows the VV table end
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4,
+                "VV table size does not match sram space" );
+#else
+    // Check the VSR table fits below declared start of SRAM data
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+#endif
+}
+
+//==========================================================================
+// EOF stm32f4discovery_misc.c
diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c
new file mode 100644
index 0000000..766691b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c
@@ -0,0 +1,73 @@
+/*=============================================================================
+//
+//      gpio.c
+//
+//      Test for STM32F4-Discovery GPIO
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jld
+// Date:         2013-06-07
+//              
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <cyg/infra/testcase.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/var_io.h>
+
+externC void cyg_start(void) {
+    int b, n;
+    CYG_TEST_INIT();
+    CYG_TEST_INFO( "Starting STM32F4-Discovery GPIO test" );
+    CYG_TEST_INFO( "Press and hold user button for slow LED count" );
+    for ( n = 0; n < 0x100; n++ ) {
+    	// display least significant 4 bits of count on user LEDs
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED1, 0 != (n & 0x1) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED2, 0 != (n & 0x2) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED3, 0 != (n & 0x4) );
+        CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED4, 0 != (n & 0x8) );
+        // extend delay from 125ms to 500ms when user button pressed
+        CYGHWR_HAL_STM32_GPIO_IN( CYGHWR_HAL_STM32F4DISCOVERY_BTN1, &b );
+        HAL_DELAY_US( 125000 * (1 + ( (b & 1) * 3) ) );
+    }
+    CYG_TEST_PASS_FAIL( 1, "STM32F4-Discovery GPIO test" );
+    CYG_TEST_FINISH( "STM32F4-Discovery GPIO test" );
+}
+
+//=============================================================================
+// EOF gpio.c
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog
new file mode 100644
index 0000000..8683a0f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog
@@ -0,0 +1,199 @@
+2013-04-06  Jerzy Dyrda  <jerzdy@gmail.com>
+
+	* cdl/hal_cortexm_stm32_stm32x0g_eval.cdl: Fix PHY name and
+	added defualt Ethernet interface.
+	* src/stm32x0g_eval_misc.c: Enabled clock for PHY. [ Bugzilla 1001219 ]
+
+2013-03-09  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* misc/redboot_ROM_FPU.ecm: Add ECM for RedBoot with FPU support.
+
+2012-12-01  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_stm32_stm32x0g_eval.cdl: Implement CYGINT_HAL_FPV4_SP_D16.
+	[Bugzilla 1001607]
+
+2012-03-29  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi:
+	Correct number of VSR table entries.
+	* src/stm32x0g_eval_misc.c (hal_platform_init): Add assertion checks
+	that layout of vector tables at bottom of SRAM is what it should be.
+
+2012-03-29  James Smith  <jsmith@ecoscentric.com>
+
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi:
+	Provide hal_virtual_vector_table_end symbol to allow the
+	SECTION_sram pre-allocation to be minimised to the actual platform
+	requirements.
+
+	* src/stm32x0g_eval_misc.c: Provide #error check on linker script
+	hardwired CYGNUM_CALL_IF_TABLE_SIZE assumption.
+
+2012-03-23  James Smith  <jsmith@ecoscentric.com>
+
+	* include/plf_io.h: Update GPIO pin definitions to use new PIN
+	wrapper macros. Update the I2C lines to specify PULLUP.
+
+2012-03-22  James Smith  <jsmith@ecoscentric.com>
+
+	* include/plf_io.h (CYGHWR_HAL_STM32_ETH_MII_*): Platform specific
+	ethernet pin manifests updated to use new GPIO PIN macros.
+
+2012-03-15  James Smith  <jsmith@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32_stm32x0g_eval.cdl:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h:
+	* include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi:
+	* src/stm32x0g_eval_flash.c:
+	* src/stm32x0g_eval_misc.c:
+	* src/stm32x0g_eval_spi.c:
+	Rename platform from the name "stm3220g_eval" to the generic name
+	"stm32x0g_eval". This is to make it clear that the platform
+	supports both the F2 (STM3220G-EVAL) and F4 (STM3240G-EVAL)
+	platforms. This rename includes renaming of the relevant support
+	source files.
+
+	* include/plf_io.h (HAL_I2C_EXPORTED_DEVICES): Declare I2C bus1
+	for on-board M24C64 device.
+
+2012-02-08  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl
+	(CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL_SPI): This should now be a component
+	since it has no children. Also make description match configuration (Aardvark
+	expected to be on bus 2).
+
+2012-02-05  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* misc/redboot_JTAG.ecm, misc/redboot_ROM.ecm: Build in inferences
+	so there's no output on import.
+	* misc/redboot_RAM.ecm: New file. For completeness and to make it
+	easier for RedBoot to update itself.
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Make comment description of
+	UART selection and naming clearer.
+
+2012-01-31  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* include/plf_io.h: Prototype hal_stm3220_led() for setting board LEDs.
+	* src/stm3220g_eval_misc.c: Choose correct board SRAM memory timings.
+
+2012-01-13  Nick Garnett  <nickg@ecoscentric.com>
+
+	* misc/redboot_ROM.ecm:
+	* misc/redboot_JTAG.ecm: Add CYGPKG_IO_WALLCLOCK package to enable
+	date command for setting on-chip RTC.
+
+2012-01-12  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Add SPI and I2C
+	configuration options.
+
+	* include/plf_io.h: Add SPI and I2C pin and DMA stream definitions.
+
+	* src/stm3220g_eval_spi.c: Add SPI device definition for aardvark
+	board.
+
+2011-12-20  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Just set a requires on
+	RedBoot's number of memory segments to be 2 rather than using a
+	non-configurable option.
+
+2011-12-15  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl
+	(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES): New option. Configures
+	Flash wait states.
+	(CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL_ETH0): New component. Holds
+	options and CDL to configure ethernet support.
+	Change default baud rate to 115200.
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.h: Add definitions for
+	sram and flash regions.
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_ram.h: Add definitions for
+	flash region.
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_sram.h: Ditto. Also fix
+	external SRAM address.
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_sram.ldi: Fix external SRAM
+	address.
+	* include/plf_io.h: Provide platform specific ethernet pin mappings.
+	(CYGHWR_HAL_STM32_ETH_CONFIGURE_MCO): New macro used to configure MCO1
+	as PHY clock.
+	* misc/redboot_JTAG.ecm, misc/redboot_ROM.ecm: Don't disable
+	CYGOPT_REDBOOT_FIS_REDBOOT nor CYGOPT_REDBOOT_FIS_REDBOOT_POST - there
+	is only one flash here and it does contain RedBoot.
+	* src/stm3220g_eval_flash.c: No longer define private flash structure
+	here. Internal flash support is no longer an option in this file if this
+	file is used at all.
+	* src/stm3220g_eval_misc.c (hal_system_init): Clear FSMC reset bit after
+	reset otherwise it stays there.
+	Configure USART4 TX/RX on PC10/11 otherwise RedBoot can get confused.
+	Set Flash wait states as per configuration.
+	(cyg_plf_memory_segment): Allow for renaming of external SRAM region to
+	xram.
+
+2011-12-12  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Set PLLQ.
+
+2011-12-08  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32_stm3220g_eval.cdl:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.ldi:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_ram.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_ram.ldi:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_rom.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_romint.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_romint.ldi:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_rom.ldi:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_sram.h:
+	* include/pkgconf/mlt_cortexm_stm3220g_eval_sram.ldi:
+	* misc/redboot_JTAG.ecm:
+	* misc/redboot_ROM.ecm:
+	* src/stm3220g_eval_flash.c:
+	* src/stm3220g_eval_misc.c:
+	New package -- ST STM3220G EVAL board HAL. Derived from STM3210E HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl
new file mode 100644
index 0000000..dcc2fd2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl
@@ -0,0 +1,473 @@
+##==========================================================================
+##
+##      hal_cortexm_stm32_stm32x0g_eval.cdl
+##
+##      Cortex-M STM32X0G EVAL platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    jlarmour
+## Based on:     stm3210e CDL by nickg
+## Date:         2011-11-10
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL {
+    display       "ST STM32x0G-EVAL (STM32 20-21-45-46 G-EVAL) Development Board HAL"
+    parent        CYGPKG_HAL_CORTEXM_STM32
+    requires      { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4"))  }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? (CYGHWR_HAL_CORTEXM_STM32_F2 == "F207IG") : (CYGHWR_HAL_CORTEXM_STM32_F4 == "F407IG") }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM == "M3") }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM == "M4") }
+    # 25MHz crystal feeds HSE
+    # From STM32F4xx Rev A System Clock Configuration v1.0.1
+    #   SYSCLK          120MHz    168MHz
+    #   ------          ------    ------
+    #   HSE             25MHz     25MHz		fixed input crystal on board : CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK
+    #   PLL_M           25        25		(6bits) main divisor
+    #   PLL_N           240       336		(9bits) main multiplier
+    #   PLL_P           2         2		(2bits) derived from PLL_N : used for SYSCLK (must not exceed F2:120 or F4:168)
+    #   PLL_Q           5         7		(4bits) derived from PLL_N : used for USB OTG FS, SDIO and RNG (must be >= 2)
+    #   AHB Prescaler   1         1
+    #   SYSCLK		120MHz	  168MHz	(((HSE / PLL_M) * PLL_N) / PLL_P)
+    #   HCLK            120MHz    168MHz	(SYSCLK / AHB Prescaler)
+    #   APB1 Prescaler  4         4
+    #   PCLK1		30MHz	  42MHz		(HCLK / APB1 Prescaler)
+    #   APB2 Prescaler  2         2
+    #	PCLK2		60MHz	  84MHz		(HCLK / APB2 Prescaler)
+    #
+    # Must use HSE for the PLL settings below
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSE" }
+    # F2:
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 15) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 288) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 4) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 10) }
+    # F4:
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 25) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 336) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 2) }
+    requires      { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 7) }
+    # Common:
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 }
+    requires      { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 }
+
+#    define_header hal_cortexm_stm32_stm32x0g_eval.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The STM32x0G EVAL HAL package provides the support needed to run
+        eCos on the ST STM32 20-21-45-46 G-EVAL board."
+
+    compile       stm32x0g_eval_misc.c
+
+    cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL {
+        display "Platform definitions for STM3220G-EVAL (F2) board."
+	active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2" }
+        no_define
+	calculated 1
+        define_proc {
+            puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+            puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>"
+            puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>"
+            puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3\""
+            puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"ST STM3220G-EVAL\""
+            puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3240G_EVAL {
+        display "Platform definitions for STM3240G-EVAL (F4) board."
+	active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" }
+        no_define
+	calculated 1
+        define_proc {
+            puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+            puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>"
+            puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>"
+            puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+            puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"ST STM3240G-EVAL\""
+            puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        }
+        implements    CYGINT_HAL_FPV4_SP_D16
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"RAM"}
+        legal_values  {"RAM" "SRAM" "ROM" "ROMINT" "JTAG"}
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            When targetting the ST STM32X0G EVAL board it is possible to
+            build the system for either RAM bootstrap or ROM bootstrap.
+            Select 'RAM' when building programs to load into RAM using onboard
+            debug software such as RedBoot or eCos GDB stubs.  Select 'ROM'
+            when building a stand-alone application which will be put
+            into ROM. The 'JTAG' type allows programs to be downloaded using a
+            JTAG debugger such as a BDI3000 or PEEDI. The 'SRAM' type allows
+            programs to be downloaded via a JTAG debugger into on-chip SRAM.
+            The 'ROMINT' type supports applications with code in on-chip flash
+            and data/bss in on-chip SRAM, ignoring the external SRAM."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "RAM"    ) ? "cortexm_stm32x0g_eval_ram"      :
+                        (CYG_HAL_STARTUP == "SRAM"   ) ? "cortexm_stm32x0g_eval_sram"     :
+                        (CYG_HAL_STARTUP == "ROM"    ) ? "cortexm_stm32x0g_eval_rom"      :
+                        (CYG_HAL_STARTUP == "ROMINT" ) ? "cortexm_stm32x0g_eval_romint"   :
+                        (CYG_HAL_STARTUP == "JTAG"   ) ? "cortexm_stm32x0g_eval_jtag"     :
+                                                         "undefined" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+                display "Memory layout linker script fragment"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+                display "Memory layout header file"
+                flavor data
+                no_define
+                define -file system.h CYGHWR_MEMORY_LAYOUT_H
+                calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK {
+        display         "Input Clock frequency"
+        flavor          data
+        default_value   25000000
+        legal_values    0 to 1000000000
+        description     "Main clock input."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES {
+        display         "Flash read wait states"
+        flavor          data
+        default_value   { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? 3 : 5 }
+        legal_values    0 to 7
+        description     "
+            This option gives the number of wait states to use for accessing
+            the flash for reads. The correct setting for this value depends
+            on both the CPU clock (HCLK) frequency and the voltage. Consult
+            the STM32 Flash programming manual (PM0059) for appropriate
+            values for different clock speeds or voltages. The default of
+            3 reflects a supply voltage of 3.3V and HCLK of 120MHz."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH {
+        display         "Flash driver support"
+        parent          CYGPKG_IO_FLASH
+        active_if       CYGPKG_IO_FLASH
+        compile         -library=libextras.a stm32x0g_eval_flash.c
+        default_value   1
+        description     "Control flash device support for STM32X0G-EVAL board."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_ETH0 {
+        display       "STM32 Ethernet support"
+        description   "
+            Hardware specifics for the ethernet interface provided on the
+            STM32X0G-EVAL board."
+        parent        CYGPKG_IO_ETH_DRIVERS
+        active_if     CYGPKG_IO_ETH_DRIVERS
+        default_value 1
+        requires      CYGPKG_DEVS_ETH_CORTEXM_STM32
+        requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+                         (1 == CYGHWR_DEVS_ETH_PHY_DP8384X) }
+        requires      { is_active(CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) implies \
+                            (CYGHWR_DEVS_ETH_CORTEXM_STM32_PHY_CLK_MCO == CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) }
+        requires      { "MII" == CYGSEM_DEVS_ETH_CORTEXM_STM32_INTF }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO {
+            display         "Use MCO as PHY clock"
+            default_value   1
+            description     "
+                The STM32X0G can use the MCO clock signals as the 25MHz clock for
+                the PHY, or it can use the onboard 25MHz crystal at X1, depending
+                on the setting of jumper J5. This option should be set to reflect
+                the J5 setting."
+        }
+    }
+
+    implements CYGINT_HAL_VIRTUAL_VECTOR_VPRINTF
+
+    # The 9-pin D connector is connected to PC10 and PC11, which are connected to
+    # USART3 or UART4 depending on pin config. The main difference between these
+    # ports is that UART4 doesn't support hardware flow control. This board doesn't
+    # have the flow control lines hooked up anyway, so to save having to fiddle
+    # with ignoring the flow control lines on USART3, we choose to use UART4.
+    # Note that this is UART4 in STM32 speak (counting from 1), but the STM32 port
+    # uses the name UART3 for it (counting from 0). Hrm.
+    implements CYGINT_HAL_STM32_UART3
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        calculated       0
+        description      "
+            The ST STM32X0G EVAL board has one serial port. This option
+            informs the rest of the system which port will be used to connect
+            to a host running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         calculated       0
+         description      "
+            The ST STM32X0G EVAL has one serial port. This option
+            informs the rest of the system which port will be used for
+            diagnostic output."
+     }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            RedBoot usess polling to transfer data over this port and
+            might not be able to keep up with baud rates above the
+            default, particularly when doing XYZmodem downloads. The
+            interrupt-driven device driver is able to handle these
+            baud rates, so any high speed application transfers should
+            use that instead.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        # Only one channel on this board so:
+        requires      { CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD == CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            RedBoot usess polling to transfer data over this port and
+            might not be able to keep up with baud rates above the
+            default, particularly when doing XYZmodem downloads. The
+            interrupt-driven device driver is able to handle these
+            baud rates, so any high speed application transfers should
+            use that instead.
+            Note: this should match the value chosen for the console port if the
+            console and GDB port are the same."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_OPTIONS {
+        display "STM32X0G HAL build options"
+                flavor  none
+                description   "
+                        Package specific build options including control over
+                        compiler flags used only in building this HAL."
+
+                cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_CFLAGS_ADD {
+                        display "Additional compiler flags"
+                        flavor  data
+                        no_define
+                        default_value { "-Werror" }
+                        description   "
+                                This option modifies the set of compiler flags
+                                for building this HAL. These flags are used
+                                in addition to the set of global flags."
+                        }
+                cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_CFLAGS_REMOVE {
+                        display "Suppressed compiler flags"
+                        flavor  data
+                        no_define
+                        default_value { "" }
+                        description   "
+                                This option modifies the set of compiler flags
+                                for building this HAL. These flags are
+                                removed from the set of global flags if
+                                present."
+                }
+        }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMINT" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 2) }
+        requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 3) }
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary images"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to binary image formats suitable for ROM programming."
+
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_STM32X0G_EVAL_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        active_if CYGBLD_BUILD_COMMON_GDB_STUBS
+        no_define
+        calculated 1
+        requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMINT" }
+
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+                <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O binary $< $@
+        }
+
+        description "This component causes the ELF image generated by the
+                     build process to be converted to S-Record and binary
+                     files."
+    }
+}
+
+# EOF hal_cortexm_stm32_stm32x0g_eval.cdl
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h
new file mode 100644
index 0000000..e3f51d7
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x64000000)
+#define CYGMEM_REGION_ram_SIZE (0x00200000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi
new file mode 100644
index 0000000..03cbd9a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi
@@ -0,0 +1,50 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ram   : ORIGIN = 0x64000000, LENGTH = 0x00200000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x64000000, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h
new file mode 100644
index 0000000..1ce0565
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h
@@ -0,0 +1,28 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00020000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x64000000)
+#define CYGMEM_REGION_ram_SIZE (0x00200000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi
new file mode 100644
index 0000000..ea212a1
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi
@@ -0,0 +1,50 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00020000
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ram   : ORIGIN = 0x64000000, LENGTH = 0x00200000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// External SRAM is 2MB
+hal_startup_stack = 0x64200000;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_sram (sram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x64008000, LMA_EQ_VMA)
+    SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h
new file mode 100644
index 0000000..e3f51d7
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x64000000)
+#define CYGMEM_REGION_ram_SIZE (0x00200000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi
new file mode 100644
index 0000000..c5c7c5f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi
@@ -0,0 +1,51 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ram   : ORIGIN = 0x64000000, LENGTH = 0x00200000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, hal_virtual_vector_table_end, FOLLOWING (.got))
+    SECTION_data (ram, 0x64000000, FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h
new file mode 100644
index 0000000..d265178
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x20000000)
+#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_xram (0x64000000)
+#define CYGMEM_REGION_xram_SIZE (0x00200000)
+#define CYGMEM_REGION_xram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi
new file mode 100644
index 0000000..cdfa7eb
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi
@@ -0,0 +1,50 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram   : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    xram  : ORIGIN = 0x64000000, LENGTH = 0x00200000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA)
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (ram, hal_virtual_vector_table_end, FOLLOWING (.got))
+    SECTION_data (ram, ALIGN( 0x8), FOLLOWING (.sram))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h
new file mode 100644
index 0000000..99dcbe9
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h
@@ -0,0 +1,28 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x20000000)
+#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGMEM_REGION_ccm (0x10000000)
+#define CYGMEM_REGION_ccm_SIZE (0x00010000)
+#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGMEM_REGION_flash (0x08000000)
+#define CYGMEM_REGION_flash_SIZE (0x00100000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x64000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi
new file mode 100644
index 0000000..05d2bc3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi
@@ -0,0 +1,51 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram  : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+    flash : ORIGIN = 0x08000000, LENGTH = 0x00100000
+    ram   : ORIGIN = 0x64000000, LENGTH = 0x00200000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    ccm   : ORIGIN = 0x10000000, LENGTH = 0x00010000
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+}
+
+
+hal_vsr_table = 0x20000000;
+// 97 or 98 entries in this VSR table depending on the processor family
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+hal_virtual_vector_table = hal_vsr_table + 97*4;
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+hal_virtual_vector_table = hal_vsr_table + 98*4;
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4;
+#else // zero size virtual vector table
+hal_virtual_vector_table_end = hal_virtual_vector_table;
+#endif
+
+// SRAM is 128k.
+hal_startup_stack = 0x20000000 + 1024*128;
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (sram, hal_virtual_vector_table_end, LMA_EQ_VMA)
+    SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h
new file mode 100644
index 0000000..1800e7f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM32X0G EVAL platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h
new file mode 100644
index 0000000..644590f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM32X0G EVAL platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h
new file mode 100644
index 0000000..3f15576
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h
@@ -0,0 +1,171 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM32X0G EVAL platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+// Board LEDs
+
+#define CYGHWR_HAL_STM32X0G_LED1   CYGHWR_HAL_STM32_PIN_OUT( G, 6, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32X0G_LED2   CYGHWR_HAL_STM32_PIN_OUT( G, 8, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32X0G_LED3   CYGHWR_HAL_STM32_PIN_OUT( I, 9, PUSHPULL, NONE, LOW )
+#define CYGHWR_HAL_STM32X0G_LED4   CYGHWR_HAL_STM32_PIN_OUT( C, 7, PUSHPULL, NONE, LOW )
+
+// A convenience function to set LEDs. Lowest 4 bits of 'c' correspond to the 4 LEDs.
+__externC void hal_stm32x0_led(char c);
+
+//=============================================================================
+// Custom Ethernet pin mappings
+
+#define CYGHWR_HAL_STM32_ETH_MII_TX_CRS         CYGHWR_HAL_STM32_PIN_ALTFN_IN(  H,  2, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_COL            CYGHWR_HAL_STM32_PIN_ALTFN_IN(  H,  3, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_RXD2           CYGHWR_HAL_STM32_PIN_ALTFN_IN(  H,  6, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_RXD3           CYGHWR_HAL_STM32_PIN_ALTFN_IN(  H,  7, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD3           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  8, 11, PUSHPULL,  NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_RX_ER          CYGHWR_HAL_STM32_PIN_ALTFN_IN(  I, 10, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_TX_EN          CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 11, 11, PUSHPULL,  NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD0           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 13, 11, PUSHPULL,  NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD1           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 14, 11, PUSHPULL,  NONE, AT_LEAST(50) )
+// NOTE: CYGHWR_HAL_STM32_ETH_MII_PPS_OUT not defined
+
+#define CYGHWR_HAL_STM32_ETH_CONFIGURE_MCO()                            \
+  CYG_MACRO_START                                                       \
+  cyg_uint32 cfgr;                                                      \
+  HAL_READ_UINT32( CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); \
+  cfgr &= ~CYGHWR_HAL_STM32_RCC_CFGR_MCO1_MASK;                          \
+  cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE;                           \
+  cfgr &= ~CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_MASK;                       \
+  cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1;                          \
+  HAL_WRITE_UINT32( CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); \
+  CYG_MACRO_END
+  
+//=============================================================================
+// GPIO pin and DMA definitions for each SPI bus
+
+// NOTE: The SPEED_SPI manifest is declared by the device driver
+// (e.g. "devs/spi/cortexm/stm32/<vsn>/src/spi_stm32.c") and is not
+// currently defined in a header.
+
+#ifndef CYGHWR_HAL_STM32_SPI1_REMAP
+#define CYGHWR_HAL_STM32_SPI1_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  5, 5, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  6, 5, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI1_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  7, 5, PUSHPULL, NONE, SPEED_SPI )
+#else
+#define CYGHWR_HAL_STM32_SPI1_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  3, 5, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI1_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  4, 5, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI1_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, 5, PUSHPULL, NONE, SPEED_SPI )
+#endif
+#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG      0
+
+#define CYGHWR_HAL_STM32_SPI1_DMA_TX            CYGHWR_HAL_STM32_DMA( 2, 3, 3, M2P )
+#define CYGHWR_HAL_STM32_SPI1_DMA_RX            CYGHWR_HAL_STM32_DMA( 2, 0, 3, P2M )
+
+
+
+#define CYGHWR_HAL_STM32_SPI2_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( I, 1, 5, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI2_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  I, 2, 5, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI2_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( I, 3, 5, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG      0
+
+#define CYGHWR_HAL_STM32_SPI2_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 4, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI2_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 3, 0, P2M )
+
+
+    
+#ifndef CYGHWR_HAL_STM32_SPI3_REMAP
+#define CYGHWR_HAL_STM32_SPI3_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  3, 6, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  4, 6, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI3_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, 6, PUSHPULL, NONE, SPEED_SPI )
+#else
+#define CYGHWR_HAL_STM32_SPI3_SCK               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 6, PUSHPULL, NONE, SPEED_SPI )
+#define CYGHWR_HAL_STM32_SPI3_MISO              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C, 11, 6, NA,       PULLUP )
+#define CYGHWR_HAL_STM32_SPI3_MOSI              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, 6, PUSHPULL, NONE, SPEED_SPI )
+#endif
+#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG      0
+
+#define CYGHWR_HAL_STM32_SPI3_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 2, 0, M2P )
+#define CYGHWR_HAL_STM32_SPI3_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 0, 0, P2M )
+
+
+//=============================================================================
+// GPIO pin and DMA definitions for each I2C bus
+
+#define CYGHWR_HAL_STM32_I2C1_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  6, 4, OPENDRAIN, PULLUP, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C1_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  9, 4, OPENDRAIN, PULLUP, AT_LEAST(50) )
+
+#define CYGHWR_HAL_STM32_I2C1_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 7, 1, M2P )
+#define CYGHWR_HAL_STM32_I2C1_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 5, 1, P2M )
+
+#define CYGHWR_HAL_STM32_I2C2_SCL               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, 4, OPENDRAIN, PULLUP, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_I2C2_SDA               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, 4, OPENDRAIN, PULLUP, AT_LEAST(50) )
+
+#define CYGHWR_HAL_STM32_I2C2_DMA_TX            CYGHWR_HAL_STM32_DMA( 1, 7, 7, M2P )
+#define CYGHWR_HAL_STM32_I2C2_DMA_RX            CYGHWR_HAL_STM32_DMA( 1, 3, 7, P2M )
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm
new file mode 100644
index 0000000..fd2f9e5
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm
@@ -0,0 +1,87 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value JTAG
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    inferred_value ROM
+};
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm
new file mode 100644
index 0000000..19a5583
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm
@@ -0,0 +1,83 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value RAM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm
new file mode 100644
index 0000000..5c92419
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm
@@ -0,0 +1,87 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    inferred_value ROM
+};
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm
new file mode 100644
index 0000000..14652a8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm
@@ -0,0 +1,95 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    template    redboot ;
+
+    package CYGPKG_IO_FLASH current ;
+};
+
+cdl_component CYGHWR_HAL_CORTEXM_FPU {
+    user_value 1
+};
+
+cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH {
+    user_value ALL
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES {
+    user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+     user_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGDBG_HAL_CRCTABLE_LOCATION {
+    inferred_value ROM
+};
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c
new file mode 100644
index 0000000..ed513c5
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c
@@ -0,0 +1,68 @@
+/*==========================================================================
+//
+//      stm32x0g_eval_flash.c
+//
+//      Cortex-M3 STM32X0G EVAL Flash setup
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Date:         2011-12-12
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <cyg/io/flash_dev.h>
+
+//--------------------------------------------------------------------------
+// Internal flash
+
+#include <cyg/io/stm32_flash.h>
+
+CYG_FLASH_DRIVER(hal_stm32_flash,
+                 &cyg_stm32_flash_funs,
+                 0,
+                 0x08000000,
+                 0,
+                 0,
+                 0,
+                 &hal_stm32_flash_priv
+);
+
+//--------------------------------------------------------------------------
+// EOF stm32x0g_eval_flash.c
diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c
new file mode 100644
index 0000000..84a5a0a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c
@@ -0,0 +1,404 @@
+/*==========================================================================
+//
+//      stm32x0g_eval_misc.c
+//
+//      Cortex-M3/-M4 STM32X0G EVAL HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011, 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour based on stm3210e by nickg
+// Date:         2008-07-30
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include CYGHWR_MEMORY_LAYOUT_H         // Memory regions
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+//==========================================================================
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+#if (CYGNUM_CALL_IF_TABLE_SIZE > 64)
+// We force a compilation error for this fatal condition since run-time asserts
+// may not be enabled for the build.
+#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated"
+#endif
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void hal_system_init( void )
+{
+    CYG_ADDRESS base;
+
+    // Enable peripheral clocks in RCC
+
+    base = CYGHWR_HAL_STM32_RCC;
+
+    // All GPIO ports
+    // FIXME: this should be done in variant HAL at point of gpio_set
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR,
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) // enable CCM clock
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) |
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH) |
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI) );
+
+    // Enable FSMC
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3ENR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) );
+
+#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM)
+
+    // Reset FSMC in case it was already enabled. This should set
+    // all regs back to default documented values, so we don't need
+    // to do any precautionary resets.
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR,
+                     BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) );
+    // Bring out of reset:
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR, 0 );
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO)
+    // Use HSE clock as the MCO1 clock signals for PHY
+    {
+        cyg_uint32 acr;
+
+        HAL_READ_UINT32(base + CYGHWR_HAL_STM32_RCC_CFGR, acr);
+        acr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE |
+            CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1;
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_STM32_RCC_CFGR, acr);
+    }
+#endif
+
+    // Set all unused GPIO lines to input with pull down to prevent
+    // them floating and annoying any external hardware.
+
+    // GPIO Ports C..I reset GPIOx_MODER to 0x00000000
+    // GPIO Ports A..I reset GPIOx_OTYPER to 0x00000000
+    // CPIO Ports A,C..I reset GPIOx_OSPEEDR to 0x00000000
+    // GPIO Ports C..I reset GPIOx_PUPDR to 0x00000000
+
+    // GPIO Port A resets GPIOA_MODER to 0xA8000000
+    // GPIO Port A resets GPIOA_PUPDR to 0x64000000
+    // GPIO Port A keeps the default JTAG pins on PA13,14,15
+    base = CYGHWR_HAL_STM32_GPIOA;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x02AAAAAA );
+
+    // GPIO Port B resets GPIOB_MODER to 0x00000280
+    // GPIO Port B resets GPIOB_OSPEEDR to 0x000000C0
+    // GPIO Port B resets GPIOB_PUPDR to 0x00000100
+    // GPIO Port B keeps the default JTAG pins on PB3,4
+    base = CYGHWR_HAL_STM32_GPIOB;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAA82A );
+
+    // GPIO Port C - setup PC7 for LED4 as GPIO out, RS232 (USART4) on PC10,11.
+    // Rest stay default, with pulldowns on all except PC14,15 (OSC32)
+    // just in case that is important.
+
+    base = CYGHWR_HAL_STM32_GPIOC;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00008800 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x0A0A2AAA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A04000 );
+
+    // GPIO Port D - setup FSMC for SRAM (PD0-1,3-15) and MicroSDcard (PD2) alternate functions
+    base = CYGHWR_HAL_STM32_GPIOD;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xCCCCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAAAAAA );
+    // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
+
+    // GPIO Port E - setup FSMC alternate function. PE0-1,3-4,7-15.
+    // But not PE5 (A21), PE6(A22), PE2(A23) which are not connected to SRAM.
+    base = CYGHWR_HAL_STM32_GPIOE;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xC00CC0CC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00002820 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAA828A );
+    // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
+
+    // GPIO Port F - setup FSMC alternate function. PF0-5,12-15.
+    // But not PF6-11 which aren't connected to SRAM.
+    base = CYGHWR_HAL_STM32_GPIOF;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCC0000 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA000 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAA000AAA );
+    // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
+
+    // GPIO Port G - setup FSMC alternate function. PG0-5,9,10.
+    // Other FSMC pins not connected to SRAM.
+    // LED1 is PG6, LED2 is PG8, so set as GPIO out.
+    base = CYGHWR_HAL_STM32_GPIOG;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00000CC0 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA808000 );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00291AAA );
+    // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
+
+    // GPIO Port H stays default, with pulldowns on all except PH0,1 (OSC) just in case that is important.
+    base = CYGHWR_HAL_STM32_GPIOH;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAAAA0 );
+
+    // GPIO Port I - setup PI9 for LED3 as GPIO out, rest stay default, with pulldowns
+    base = CYGHWR_HAL_STM32_GPIOI;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAA2AAAA );
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00040000 );
+
+
+    // Set up FSMC NOR/SRAM bank 2 for SRAM
+
+    base = CYGHWR_HAL_STM32_FSMC;
+
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+    // NOTEs:
+    // - The "STM32 20-21-45-46 G-EVAL" boards we have are populated with the
+    //   IS61WV102416BLL-10MLI part and not the Cypress CY7C1071DV33 part.
+    // - The F4[01][57]xx devices can operate upto 168MHz (or 144MHz) so maximum HCLK
+    //   timing of 6ns (or 6.94444ns).
+    //
+    // NOTE: The code does NOT set BWTR2 for SRAM write-cycle timing (so will be
+    // the default reset value of 0x0FFFFFFF) since BCRx:EXTMOD bit is NOT set.
+
+    // TODO:IMPROVE: Derive values based on CLK settings. The following "fixed"
+    // values are based on a 168MHz SYSCLK:
+
+    // BCR2 = MBKEN | MWID=0b01 (16bits) | WREN
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001015 );
+
+    // BTR2:
+    //   ADDSET=3 (3 HCLK cycles)
+    //   ADDHLD=0 (SRAM:do not care)
+    //   DATAST=6 (6 HCLK cycles)
+    //   BUSTURN=1 (1 HCLK cycle)
+    //   CLKDIV=0 (SRAM:do not care)
+    //   DATLAT=0 (SRAM:do not care)
+    //   ACCMOD=0 (access mode A)
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00010603 );
+#else // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001011 );
+    // SRAM timings for the fitted CY7C1071DV33-12BAXI async SRAM
+    // We could try and make this depend on hclk as it should, but that's
+    // probably overkill for now. With an hclk of 120MHz, each hclk period
+    // is 8.33ns, so we just use that. This might mean being slightly
+    // suboptimal at lower configured hclk speeds.
+    // It's tricky to get the waveforms in the STM32 FSMC docs and the SRAM
+    // datasheet, to match up, so there's a small amount of guess work involved
+    // here. From the SRAM datasheet, ADDSET should be at least 7ns (tHZWE), and
+    // DATAST should be at least 9ns (tPWE) plus one HCLK (from Fig 397 in FSMC
+    // docs showing Mode 1 write accesses). This gives ADDSET=1 and
+    // DATAST=3.
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00000301 );
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2
+
+    // Enable flash prefetch buffer, cacheability and set latency to 2 wait states.
+    // Latency has to be set before clock is switched to a higher speed.
+    {
+        cyg_uint32 acr;
+
+        base = CYGHWR_HAL_STM32_FLASH;
+
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN;
+        acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES);
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
+    }
+}
+
+//==========================================================================
+
+// Set LEDs 1-4 to lowest 4 bits of supplied char.
+__externC void hal_stm32x0_led(char c)
+{
+    CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED1, 0 != (c&1) );
+    CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED2, 0 != (c&2) );
+    CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED3, 0 != (c&4) );
+    CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED4, 0 != (c&8) );
+}
+
+//==========================================================================
+
+__externC void hal_platform_init( void )
+{
+#ifdef CYGDBG_USE_ASSERTS
+    __externC char __sram_data_start[];
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    // Check the number of VSRs matches the linker script. We can do this
+    // because we intend the VV table to follow the VSR table with no gaps.
+    CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+    // Now check the declared start of SRAM data follows the VV table end
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4,
+                "VV table size does not match sram space" );
+#else
+    // Check the VSR table fits below declared start of SRAM data
+    CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4,
+                "VSR table size does not match" );
+#endif
+    hal_stm32x0_led(1);
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct
+{
+    CYG_ADDRESS         start;          // Region start address
+    CYG_ADDRESS         end;            // End address (last byte)
+} hal_data_access[] =
+{
+    { CYGMEM_REGION_ram,        CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1      },      // External SRAM
+#ifdef CYGMEM_REGION_sram
+    { CYGMEM_REGION_sram,       CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1    },      // On-chip SRAM
+#endif
+#ifdef CYGMEM_REGION_flash
+    { CYGMEM_REGION_flash,      CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1  },      // On-chip flash
+#endif
+    { 0xE0000000,               0x00000000-1                                    },      // Cortex-M peripherals
+    { 0x40000000,               0x60000000-1                                    },      // STM32 peripherals
+    { 0xA0000000,               0xA0001000-1                                    },      // FSMC control
+#ifdef CYGMEM_REGION_ccm
+    { CYGMEM_REGION_ccm,        CYGMEM_REGION_ccm+CYGMEM_REGION_ccm_SIZE-1      },      // On-chip (close-coupled) SRAM
+#endif
+};
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
+{
+    int i;
+    for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ )
+    {
+        if( (addr >= hal_data_access[i].start) &&
+            (addr+count) <= hal_data_access[i].end)
+            return true;
+    }
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the on-chip SRAM and external SRAM.
+
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_sram
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_sram;
+        *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
+        break;
+#elif defined(CYGMEM_REGION_xram)
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_xram;
+        *end = (unsigned char *)(CYGMEM_REGION_xram + CYGMEM_REGION_xram_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_ccm
+    case 2:
+        *start = (unsigned char *)CYGMEM_REGION_ccm;
+        *end = (unsigned char *)(CYGMEM_REGION_ccm + CYGMEM_REGION_ccm_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+} // cyg_plf_memory_segment()
+
+#endif // CYGPKG_REDBOOT
+
+
+//==========================================================================
+// EOF stm32x0g_eval_misc.c
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/ChangeLog b/ecos/packages/hal/cortexm/stm32/var/current/ChangeLog
new file mode 100644
index 0000000..acc15b3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/ChangeLog
@@ -0,0 +1,406 @@
+2014-02-28  John Dallaway  <john@dallaway.org.uk>
+
+	* src/stm32_misc.c: Ensure TIM2 clock enabled when profiling.
+	[Bugzilla 1001953]
+
+2013-04-06  Jerzy Dyrda  <jerzdy@gmail.com>
+
+	* include/var_io_eth.h: 
+	* include/var_io.h: Update ETH macros for F4 device. [ Bugzilla 1001219 ]
+
+2013-01-19  John Dallaway  <john@dallaway.org.uk>
+
+	* include/var_io.h: Fix CYGHWR_HAL_STM32_UART6 definition.
+
+2012-04-23  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_pins.h (CYGHWR_HAL_STM32_PIN_IN): Removed
+	spurious parameter since the API for this macro should match the
+	F2/F4 (HIPERFORMANCE) definition.
+
+	* include/var_io_eth.h: Update F1 ETH_MII
+	CYGHWR_HAL_STM32_PIN_IN() usage to reflect correct API.
+
+2012-04-13  Christophe Coutand  <ecos@hotmail.co.uk>
+
+	* include/var_io.h:
+	Added definitions, CYGHWR_HAL_STM32_USB_CLOCK, 
+	CYGHWR_HAL_STM32_CAN1_CLOCK and CYGHWR_HAL_STM32_CAN2_CLOCK 
+
+2012-03-27  James Smith  <jsmith@ecoscentric.com>
+
+	* tests/timers.c (TIMER_PRI): Add macro and manifests to allow
+	easy manipulation of the base and delta between the timer
+	priorities being tested.
+
+2012-03-23  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_usart.h: Provide common/shared UART pin
+	definitions for F1, F2 and F4 devices using the new PIN wrapper
+	macros. The RTS pin definitions for all STM32F families now use
+	GPIO output since the driver uses software controlled
+	RTS. Previously the F2/F4 defined the RTS pins as ALTFN.
+
+	* include/var_io.h: Provide common/shared ADC pin definitions for
+	F1, F2 and F4 devices using the new PIN_ANALOG() wrapper macro.
+
+	* include/var_io_eth.h: Provide common MII pin definitions using
+	the new PIN wrapper macros. Also remove MII_REMAP which was
+	incorrectly using the wrong manifests (STM3210C-EVAL networking
+	would not work) since decision taken that "plf_io.h" should
+	contain board specific I/O pin mapping.
+
+	* cdl/hal_cortexm_stm32.cdl: Remove CYGPKG_HAL_STM32_ETH and
+	sub-option CYGHWR_HAL_STM32_ETH_MII_REMAP since ethernet pin
+	mapping now present in platform specific "plf_io.h" header.
+
+2012-03-22  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_pins.h: Provide "common" wrapper macros
+	CYGHWR_HAL_STM32_PIN_OUT, CYGHWR_HAL_STM32_PIN_ALTFN_OUT,
+	CYGHWR_HAL_STM32_PIN_IN, CYGHWR_HAL_STM32_PIN_ALTFN_IN and
+	CYGHWR_HAL_STM32_PIN_ANALOG for defining I/O pins to allow the
+	same (where applicable) source calls to be used regardless of
+	whether the target is F1 or HIPERFORMANCE (F2/F4).
+
+	* cdl/hal_cortexm_stm32.cdl: Remove CYGPKG_HAL_STM32_ETH and
+	sub-option CYGHWR_HAL_STM32_ETH_MII_REMAP since ethernet pin
+	mapping now present in platform specific "plf_io.h" header.
+
+2012-03-21  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_pins.h: Provide similar support for F1 family
+	devices as available for F2/F4 family devices by adding AT_LEAST
+	and AT_MOST macros for specifying OUTPUT pin speed limits, and
+	providing generic LOW, MED and FAST manifests to hide the actual
+	device speed.
+
+	* src/stm32_misc.c (hal_stm32_gpio_set): Use
+	CYGHWR_HAL_STM32_GPIO_CNFMODE_SET macro instead of explicit
+	bitmask manipulation for seeting F1 CRL/CRH.
+
+2012-03-15  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm32_misc.c:
+	* src/stm32_dma.c:
+	* src/hal_diag.c:
+	* include/var_io_usart.h:
+	* include/var_io_pins.h:
+	* include/var_io_eth.h:
+	* include/var_io.h:
+	* include/var_intr.h:
+	* include/var_dma.h: Use HIPERFORMANCE manifest to add support for
+	F4 devices.
+
+	* cdl/hal_cortexm_stm32.cdl: Many minor changes to support
+	Cortex-M4 and STM32F4 devices.
+
+	* tests/timers.c (timers): Add TIM8_UP_TIM13 to the set of timers
+	tested for those platforms where it is defined.
+
+2012-03-13  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io.h (HAL_AARDVARK_CHECK_I2C): Macro for specific
+	STM32 F1 devices that suffer from an I2C/FSMC errata to allow the
+	Aardvark test cases to operate. Added STM32F4 RTC manifests.
+
+2012-02-28  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm32_dma.c (hal_stm32_dma_disable): Add new function to
+	allow temporary disable of DMA stream for circular mode
+	configurations.
+
+	* include/var_dma.h: Added prototype for newly added
+	hal_stm32_dma_disable() function.
+
+2012-02-28  James Smith  <jsmith@ecoscentric.com>
+
+	* src/stm32_dma.c (hal_stm32_dma_isr): Do not disable the stream
+	when configured for circular mode.
+
+2012-02-24  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io.h: Provide manifests covering STM32F2 ADC
+	support.
+
+	* include/var_intr.h: Provide explicit DMA2 CH4 and CH5 manifests
+	for non-connectivity devices (e.g. STM3210E-EVAL target).
+
+	* include/var_dma.h:
+	* src/stm32_dma.c (hal_stm32_dma_configure_circular): Provide
+	function to enable/disable DMA circular mode, and provide
+	prototype in header and documentation.
+
+2012-02-17  James Smith  <jsmith@ecoscentric.com>
+
+	* include/var_io_pins.h: Fix F2 MODE_SET and OSPEED_SET macros to
+	correctly mask register field bits.
+
+2012-01-20  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_intr.h (CYGNUM_HAL_VSR_MAX): Reverse an earlier
+	change to this value.
+
+2012-01-13  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_io.h: Add shifts for RTC TR and DR register fields.
+
+2012-01-12  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_intr.h: Reorganize vectors 43-49 so they are defined
+	correctly for F2 devices.
+
+	* include/var_io.h: Tidy up DMA defines. Move I2C and SPI pin and
+	DMA channel definitions out to platform HALs.
+
+	* include/var_io_pins.h (CYGHWR_HAL_STM32_GPIO_PUPD_SET): Fix
+	buglet in register clear code.
+
+	* cdl/hal_cortexm_stm32.cdl:
+	* include/var_dma.h:
+	* src/stm32_dma.c: Add DMA API.
+
+2011-12-15  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl (CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY):
+	Rather than list every F2 part, just say all F2 since we don't yet know
+	of F2 parts that don't have connectivity.
+	(CYGHWR_HAL_STM32_ETH_MII_REMAP): Allow pin remapping to be configurable
+	as a standard setting, alternate mapping, or provided by the platform.
+	* include/var_io.h: Add MCO1_MASK/MCO2_MASK and
+	MCO1PRE_MASK/MCO2PRE_MASK defns. Add CYGHWR_HAL_STM32_FLASH_CR_PSIZE()
+	to make flash parallelism easier to set.
+	* include/var_io_eth.h: Fix MACMIIAR_CR_MASK define.
+	Allow specification (and checking) of MACMIIAR_CR to set MDC clock
+	according to defined MHz ranges - this allows it to vary between
+	processors.
+	Support above CYGHWR_HAL_STM32_ETH_MII_REMAP changes.
+	Add alternate mappings for F2 eth pins (although it's a different
+	subset to F1.
+
+2011-12-12  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* src/stm32_misc.c (hal_start_clocks): Remove unnecessary fiddling
+	after RCC reset. Avoid overflow from PLL multiplier. Handle PLLQ
+	and RTCPRE on F2.
+
+	* include/var_io.h (CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE): Add set macro
+	separate from mask.
+
+	* cdl/hal_cortexm_stm32.cdl: Improve clock option descriptions. Add
+	CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV.
+
+2011-12-08  Jonathan Larmour  <jifl@eCosCentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl: Add selections for processors in F2
+	family, and allow discrimination between those and F1.
+	* include/var_intr.h: Modify and add to interrupt list for F2.
+	(HAL_VAR_INTERRUPT_{MASK,UNMASK,ACKNOWLEDGE,CONFIGURE ): Update
+	EXTI interrupts that need special mapping for F2.
+	* include/var_io.h: Many additions and changes for F2. To avoid
+	an unmanageable size, split out GPIO/pin config, USART and ETH
+	peripheral definitions into new files.
+	* include/var_io_pins.h: New file for GPIO and pin configuration.
+	* include/var_io_usart.h: New file for USART definitions.
+	* include/var_io_eth.h: New file for Ethernet peripheral definitions.
+	* src/hal_diag.c: Allow for new style pin remapping used by F2
+	while still allowing F1 to work.
+	Support USART6 (which we call UART5).
+	(hal_stm32_serial_init_channel): Only use AFIO on F1.
+	* src/stm32_misc.c (hal_stm32_gpio_{set,out,in}): Support new GPIO
+	pin setting.
+	(hal_stm32_uart_setbaud): Support UART6 (called UART5 in CDL).
+	(hal_enable_profile_timer): Ensure timer peripheral (defaulting to TIM6)
+	has its clock enabled.
+
+2011-10-07  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_io.h: Separate FSMC and ETH register definitions,
+	which seem to have got a little mixed together at some point.
+
+2011-02-03  Alan Bowman  <alan.bowman@datong.co.uk>
+
+	* include/var_io.h: Fix CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_*
+	definitions. [ Bugzilla 1001137 ]
+
+2011-01-21  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* src/stm32_misc.c (hal_start_clocks): Added optional calculation of
+	hal_cortexm_systick_clock when 'internal' clock source is selected.
+
+2011-01-13  John Dallaway  <john@dallaway.org.uk>
+
+	* src/stm32_misc.c: Implement a profiling timer on TIM2.
+	* cdl/hal_cortexm_stm32.cdl: Add CDL option to enable the profiling
+	timer.
+
+2011-01-13  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_misc.c (hal_start_clocks): Correct bit clear operation
+	when disabling external clock.
+
+2009-10-26  Ross Younger  <wry@ecoscentric.com>
+
+	* include/var_io.h: Minor corrections to the FSMC register defs.
+
+2009-10-22  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl:
+	* include/var_io.h: Add remap configuration for SPI busses.
+
+2009-08-10  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* include/var_io.h: Added more register definitions for FSMC
+
+2009-07-02  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl: Add remap configuration for UARTS.
+
+	* include/var_io.h (CYGHWR_HAL_STM32_AFIO_CLOCK): Add AFIO clock control.
+	(CYGHWR_HAL_STM32_UART*_REMAP_CONFIG): Add remap support for UARTS.
+
+	* src/hal_diag.c (channel_data_t, hal_stm32_serial_init_channel):
+	Add support for UART remapping.
+
+2009-06-29  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_io.h (CYGHWR_HAL_STM32_ETH): Add support for
+	ethernet device on connectivity line devices.
+	Add device clock control support.
+
+	* include/var_intr.h:
+	* cdl/hal_cortexm_stm32.cdl: Add support for connectivity line
+	devices.
+
+	* src/stm32_misc.c (hal_variant_init): Remove default enable of
+	all device clocks.
+	(hal_stm32_clock_enable, hal_stm32_clock_disable): Add routines to
+	enable individual device clocks.
+
+	* src/hal_diag.c (stm32_ser_channels)
+	(hal_stm32_serial_init_channel): Add clock enable support.
+
+2009-04-17  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* src/hal_diag.c (hal_stm32_serial_getc_timeout): Fix for higher
+	baudrates. The original version lost bytes due to the long
+	timeout.
+
+2009-03-23  Nick Garnett  <nickg@ecoscentric.com>
+
+	* src/stm32_misc.c (hal_variant_init): Add write to AHBENR
+	register to enable all AHB based devices.
+
+	* include/var_io.h (CYGHWR_HAL_STM32_IWDG_*): Add defines for
+	independent watchdog.
+
+2009-02-27  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* include/var_io.h:
+	Add mask for CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE.
+	Fixed CYGHWR_HAL_STM32_RTC_CRL_ALRF.
+	Add register definitions for ADC.
+	Add additional timer registers.
+	* src/stm32_mis.c:
+	Moved system clock initialization into it's own function, so it can
+	be called after wakeup from sleep modes.
+	Added hal_stm32_timer_clock() to get current clock of timers.
+
+2009-02-10  Chris Holgate  <chris@zynaptic.com>
+
+	* include/var_io.h: Add mask for CYGHWR_HAL_STM32_AFIO_MAPR_SWJ.
+
+2009-02-04  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_intr.h: Various fixes to allow external interrupts
+	to work.
+
+	* include/var_io.h: Add AFIO, DMA, SPI and USB definitions.
+
+	* src/stm32_misc.c (hal_stm32_gpio_set): Refetch bit number for
+	setting pullup/down.
+
+2008-11-24  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_intr.h (CYGNUM_HAL_INTERRUPT_DMA1_CHX): Rename DMA0
+	to DMA1 to match ST's numbering elsewhere.
+
+	* include/var_io.h (CYGHWR_HAL_STM32_GPIO_CFG): Remove PULLUP bit
+	from mask. Previous addition was incorrect.
+
+2008-11-24  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* include/var_io.h: Corrected capitalisation.
+	
+2008-11-12  Simon Kallweit  <simon.kallweit@intefo.ch>
+
+	* include/var_io.h: Changed CYGHWR_HAL_STM32_BD_UNPROTECT to
+	CYGHWR_HAL_STM32_BD_PROTECT, inverting the argument.
+	* src/stm32_misc.c: Changed hal_stm32_bd_unprotect() to
+	hal_stm32_bd_protect(), inverting the argument.
+
+2008-11-11  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_io.h: Add power control definitions.
+
+	* src/stm32_misc.c (hal_stm32_bd_unprotect): Add this function to
+	control backup domain write protection.
+
+2008-10-14  Nick Garnett  <nickg@ecoscentric.com>
+
+	* tests/timers.c: Add ifdefs to avoid compiling tests when not all
+	packages or components are present.
+
+2008-10-10  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl: Only build tests if the kernel is present.
+
+	* include/var_io.h (CYGHWR_HAL_STM32_GPIO_CFG): Add PULLUP bit to mask.
+
+	* tests/timers.c (timers_test): Terminate with PASS_FINISH rather
+	than just FINISH.
+
+2008-10-08  Nick Garnett  <nickg@ecoscentric.com>
+
+	* include/var_intr.h (CYGNUM_HAL_ISR_MAX, CYGNUM_HAL_VSR_MAX): Fix
+	definition of these values.
+
+	* tests/timers.c: Fix to run for maximum duration of 2 minutes.
+
+2008-10-06  Nick Garnett  <nickg@ecoscentric.com>
+
+	* cdl/hal_cortexm_stm32.cdl:
+	* include/variant.inc:
+	* include/var_arch.h:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* src/hal_diag.c:
+	* src/stm32_misc.c:
+	New package -- ST STM32 variant HAL.	
+	
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011, 2013, 2014 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl b/ecos/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl
new file mode 100644
index 0000000..97b2dee
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl
@@ -0,0 +1,480 @@
+##==========================================================================
+##
+##      hal_cortexm_stm32.cdl
+##
+##      Cortex-M STM32 variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2008, 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    nickg
+## Contributors: jld
+## Date:         2008-07-30
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_STM32 {
+    display       "Cortex-M3/-M4 STM32 Variant"
+    parent        CYGPKG_HAL_CORTEXM
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_stm32.h
+    description   "
+        This package provides generic support for the ST Cortex-M based STM32
+        microcontroller family.
+        It is also necessary to select a variant and platform HAL package."
+
+    compile       hal_diag.c stm32_misc.c stm32_dma.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+    implements    CYGINT_PROFILE_HAL_TIMER
+
+    requires      { (CYGHWR_HAL_CORTEXM == "M3") || (CYGHWR_HAL_CORTEXM == "M4") }
+
+    cdl_component CYGHWR_HAL_CORTEXM_STM32_SELECTION {
+        display          "STM32 processor selection"
+        no_define
+        flavor           none
+        description      "
+            The options within this component allow you to select which STM32
+            processor is in use."
+
+
+    cdl_option CYGHWR_HAL_CORTEXM_STM32 {
+            display          "STM32 processor variant in use"
+        flavor           data
+            default_value    { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1") ? CYGHWR_HAL_CORTEXM_STM32_F1 : \
+                               (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? CYGHWR_HAL_CORTEXM_STM32_F2 : \
+			       CYGHWR_HAL_CORTEXM_STM32_F4 }
+            # At some point we'll add the L1, etc. here.
+        description      "The STM32 has several variants, the main differences
+                          being in the size of on-chip FLASH and SRAM
+                          and numbers of some peripherals. This option
+                          allows the platform HAL to select the specific
+                          microcontroller fitted."
+    }
+                          
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_FAMILY {
+            display          "Processor family in use"
+            flavor           data
+            default_value    { "F1" }
+            legal_values     { "F1" "F2" "F4" }
+	    # NOTE: F1/F2 imply CYGHWR_HAL_CORTEXM_M3 and F4 implies CYGHWR_HAL_CORTEXM_M4
+            description      "
+                Which family of STM32 processors is in use. This will
+                usually be the leading part of the processor model name."
+        }
+
+	# NOTE: This allows later L1 support to still select "FAMILY_HIPERFORMANCE" if the I/O is the same:
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE {
+            display     "Part belongs to ST Hi-Performance family"
+	    active_if   { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") }
+	    calculated  { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") }
+            description "
+	        Indicates that this part conforms to the I/O
+		definitions for the Hi-Performance family of
+		devices. Currently this includes the STM32 F2 and F4
+		devices."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_F1 {
+            display          "F1 processor family selection"
+            flavor           data
+            active_if        { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" }
+            default_value    {"F103ZE"}
+            legal_values     {"F103RC" "F103VC" "F103ZC"
+                              "F103RD" "F103VD" "F103ZD"
+                              "F103RE" "F103VE" "F103ZE"
+                              "F105R8" "F105V8"
+                              "F105RB" "F105VB"
+                              "F105RC" "F105VC"
+                              "F107RB" "F107VB"
+                              "F107RC" "F107VC"
+                             }
+            requires         { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F1 }
+            description "
+                This option specifies which member of the STM32F1 family is
+                in use."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_F2 {
+            display          "F2 processor family selection"
+            flavor           data
+            active_if        { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2" }
+            default_value    {"F207IG"}
+            legal_values     {"F205RB" "F205RC" "F205RE" "F205RF" "F205RG"
+                              "F205VB" "F205VC" "F205VE" "F205VF" "F205VG"
+                              "F205ZB" "F205ZC" "F205ZE" "F205ZF" "F205ZG"
+                              "F207VB" "F207VC" "F207VE" "F207VF" "F207VG"
+                              "F207ZB" "F207ZC" "F207ZE" "F207ZF" "F207ZG"
+                              "F207IB" "F207IC" "F207IE" "F207IF" "F207IG"
+                             }
+            requires         { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F2 }
+            description "
+                This option specifies which member of the STM32F2 family is
+                in use."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_F4 {
+            display          "F4 processor family selection"
+            flavor           data
+            active_if        { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" }
+            default_value    {"F407IG"}
+            # NOTEs: The "F4xxxE" parts have 512MB on-chip flash and
+            # the "F4xxxG" parts have 1MB on-chip flash. The "F41xxx"
+            # parts have CRYPTO support.
+            legal_values     {"F405RG" "F405VG" "F405ZG"
+                              "F415RG" "F415VG" "F415ZG"
+                              "F407IG" "F407VG" "F407ZG"
+                              "F407IE" "F407VE" "F407ZE"
+                              "F417IG" "F417VG" "F417ZG"
+                              "F417IE" "F417VE" "F417ZE"
+                             }
+            requires         { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F4 }
+            description "
+                This option specifies which member of the STM32F4 family is
+                in use."
+        }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY {
+        display         "Part belongs to connectivity family"
+        default_value   { (CYGHWR_HAL_CORTEXM_STM32 == "F105R8") || (CYGHWR_HAL_CORTEXM_STM32 == "F105V8") ||
+                          (CYGHWR_HAL_CORTEXM_STM32 == "F105RB") || (CYGHWR_HAL_CORTEXM_STM32 == "F105VB") ||
+                          (CYGHWR_HAL_CORTEXM_STM32 == "F105RC") || (CYGHWR_HAL_CORTEXM_STM32 == "F105VC") ||
+                          (CYGHWR_HAL_CORTEXM_STM32 == "F107RB") || (CYGHWR_HAL_CORTEXM_STM32 == "F107VB") ||
+                          (CYGHWR_HAL_CORTEXM_STM32 == "F107RC") || (CYGHWR_HAL_CORTEXM_STM32 == "F107VC") ||
+                          (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4")
+                        }
+        description     "Indicates that this part belongs to the connectivity
+                         family of devices. These have slightly different interrupt
+                         and GPIO layouts to the original STM32 F103 devices."
+    }
+    
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display         "CPU priority levels"
+        flavor          data
+        calculated      4
+        description     "This option defines the number of bits used to
+                         encode the exception priority levels that this
+                         variant of the Cortex-M CPU implements."
+    }
+
+    
+   
+    cdl_component CYGHWR_HAL_CORTEXM_STM32_CLOCK {
+        display         "Clock setup calculations"
+        flavor          none
+        no_define
+        
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE {
+            display         "PLL input source"
+            flavor          data
+            default_value   { "HSE" }
+            legal_values    { "HSI" "HSE" }
+            description     "
+                This sets whether the PLL will be driven by the external
+                high-speed clock (HSE), or internal high-speed clock (HSI)."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV {
+            display         "PLL pre-divider"
+            flavor          data
+            default_value   1
+            legal_values    1 to 63
+            requires        { !CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV <= 2) }
+            requires        { (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV <= 16) }
+            requires        { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") && (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSI")) implies \
+                                  (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 2) }
+            requires        { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV >= 2) }
+            description     "
+               This option corresponds to the divider used before input to the PLL.
+               On non-connectivity parts, you can only divide by 2 or 1. On other
+               F1 parts, if using HSI as the clock source, then that is automatically
+               divided by 2. If using HSE as the clock source, then this value corresponds
+               to the PREDIV1 field of register RCC_CFGR2. On F2 and F4 parts, this value
+               corresponds to the PLLM field of RCC_PLLCFGR."
+        }
+
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL {
+            display         "PLL multiplier"
+            flavor          data
+            default_value   9
+            legal_values    2 to 432
+            requires        { (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL <= 16) }
+            requires        { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL <= 432) }
+            description     "
+                This value is used to multiply up the PLL input. On the F1 it corresponds
+                to the PLLMUL field of RCC_CFGR. On the F2 and F4 it corresponds to the PLLN
+                field of RCC_PLLCFGR."
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV {
+            display         "SYSCLK divider"
+            flavor          data
+            active_if       { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) }
+            default_value   4
+            legal_values    { 2 4 6 8 }
+            description     "
+                This value is used to divide down the PLL output for use as
+                the SYSCLK clock. This corresponds to the PLLP field of
+                RCC_PLLCFGR"
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV {
+            display         "HCLK divider"
+            flavor          data
+            default_value   1
+            legal_values    { 1 2 4 8 16 64 128 256 512 }
+            description     "Divider for AHB"
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV {
+            display         "PCLK1 divider"
+            flavor          data
+            default_value   2
+            legal_values    { 1 2 4 8 16 }
+            description     "Divider for APB1"
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV {
+            display         "PCLK2 divider"
+            flavor          data
+            default_value   1
+            legal_values    { 1 2 4 8 16 }
+            description     "Divider for APB2"
+        }
+
+        cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV {
+            display         "PLLQ divider"
+            flavor          data
+            active_if       { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) }
+            default_value   10
+            legal_values    4 to 15
+            description     "
+               This PLL divider is used in the F2 and F4 families to divide down the
+               PLL output clock (VCO clock) for use by the USB OTG FS, SDIO
+               and RNG peripherals. USB OTG FS requires a 48MHz clock and
+               other peripherals require a clock no greater than 48MHz."
+        }
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    0xE0
+        description   "Set clock ISR priority to lowest priority."
+    }
+        
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "The period defined here is something of a fake, it is expressed
+                           in terms of a notional 1MHz clock. The value actually installed
+                           in the hardware is calculated from the current settings of the
+                           clock generation hardware."
+        }
+    }
+
+    
+    cdl_interface CYGINT_HAL_STM32_UART0 {
+        display     "Platform has UART0 serial port"
+        description "The platform has a socket on UART0."
+    }
+
+    cdl_interface CYGINT_HAL_STM32_UART1 {
+        display     "Platform has UART1 serial port"
+        description "The platform has a socket on UART1."
+    }
+
+    cdl_interface CYGINT_HAL_STM32_UART2 {
+        display     "Platform has UART2 serial port"
+        description "The platform has a socket on UART2."
+    }
+
+    cdl_interface CYGINT_HAL_STM32_UART3 {
+        display     "Platform has UART3 serial port"
+        description "The platform has a socket on UART3."
+    }
+
+    cdl_interface CYGINT_HAL_STM32_UART4 {
+        display     "Platform has UART4 serial port"
+        description "The platform has a socket on UART4."
+    }
+    
+    cdl_interface CYGINT_HAL_STM32_UART5 {
+        display     "Platform has UART5 serial port"
+        description "The platform has a socket on UART5."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_UART0_REMAP {
+        display       "Remap UART0 (USART1) pins"
+        default_value 0
+
+        description   "Remap UART0 (USART1) to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_UART1_REMAP {
+        display       "Remap UART1 (USART2) pins"
+        default_value 0
+
+        description   "Remap UART1 (USART2) to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_UART2_REMAP {
+        display       "Remap UART2 (USART3) pins"
+        flavor        data
+        default_value { "NONE" }
+        legal_values  { "NONE" "PARTIAL" "FULL" }
+
+        description   "Remap UART2 (USART3) to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_I2C1_REMAP {
+        display       "Remap I2C bus 1 pins"
+        default_value 0
+
+        description   "Remap I2C bus 1 to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_SPI1_REMAP {
+        display       "Remap SPI bus 1 pins"
+        active_if     CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+        default_value 0
+
+        description   "Remap SPI bus 1 to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware."
+    }
+
+    cdl_option CYGHWR_HAL_STM32_SPI3_REMAP {
+        display       "Remap SPI bus 3 pins"
+        active_if     CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+        default_value 0
+
+        description   "Remap SPI bus 3 to alternate set of pins.
+                       This will usually be set by the platform
+                       HAL to reflect the configuration of the hardware.
+                       This option is only available on connectivity line
+                       devices."
+    }
+
+    cdl_option CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER {
+        display       "Use TIM2 for gprof profiling"
+        active_if     CYGPKG_PROFILE_GPROF
+        flavor        bool
+        default_value 1
+        implements    CYGINT_PROFILE_HAL_TIMER
+        implements    CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED
+        description   "
+            The STM32 variant HAL can provide support for gprof-based
+            profiling. This uses timer TIM2 to generate regular interrupts,
+            and the interrupt handler records the PC at the time of the
+            interrupt. Disable this option if you wish to provide
+            an alternative profiling timer implementation."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_STM32_OPTIONS {
+        display "Build options"
+        flavor  none
+        description   "
+	    Package specific build options including control over
+	    compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_STM32_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the STM32 variant HAL package. These flags are used
+                in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_STM32_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the STM32 variant HAL package. These flags are removed from
+                the set of global flags if present."
+        }
+    }
+
+    cdl_option CYGPKG_HAL_CORTEXM_STM32_TESTS {
+        display "STM32 tests"
+        active_if      CYGPKG_KERNEL
+        flavor  data
+        no_define
+        calculated { "tests/timers" }
+        description   "
+            This option specifies the set of tests for the STM32 HAL."
+    }
+    
+}
+
+# EOF hal_cortexm_stm32.cdl
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h
new file mode 100644
index 0000000..0a19bc9
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h
@@ -0,0 +1,194 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: 
+// Date:         2004-07-23
+// Purpose:      Cache control API
+// Description:  The macros defined here provide the HAL APIs for handling
+//               cache control operations.
+//
+//               For the STM32, these are empty macros as there
+//               is no cache.
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+// Data cache
+//#define HAL_DCACHE_SIZE                 0    // Size of data cache in bytes
+//#define HAL_DCACHE_LINE_SIZE            0    // Size of a data cache line
+//#define HAL_DCACHE_WAYS                 0    // Associativity of the cache
+
+// Instruction cache
+//#define HAL_ICACHE_SIZE                 0    // Size of cache in bytes
+//#define HAL_ICACHE_LINE_SIZE            0    // Size of a cache line
+//#define HAL_ICACHE_WAYS                 0    // Associativity of the cache
+
+//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+
+//#define HAL_DCACHE_WRITETHRU_MODE       0
+//#define HAL_DCACHE_WRITEBACK_MODE       1
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h
new file mode 100644
index 0000000..207930b
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h
@@ -0,0 +1,91 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     HAL diagnostics
+// Description: 
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#define HAL_DIAG_INIT()          hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void hal_stm32_diag_init(void);
+__externC void hal_stm32_diag_putc(char);
+__externC cyg_uint8 hal_stm32_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_stm32_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_stm32_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_stm32_diag_getc()
+# endif
+
+#endif
+
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h
new file mode 100644
index 0000000..d1d9db3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:jskov, gthomas, jlarmour
+// Date:        2008-07-30
+// Purpose:     Platform HAL stub support for STM32 variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/cortexm_stub.h>           // architecture stub support
+
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h
new file mode 100644
index 0000000..1bc50a2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h
@@ -0,0 +1,61 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      STM32 variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Purpose:      STM32 variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h
new file mode 100644
index 0000000..dc4089f
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h
@@ -0,0 +1,146 @@
+#ifndef CYGONCE_HAL_VAR_DMA_H
+#define CYGONCE_HAL_VAR_DMA_H
+//=============================================================================
+//
+//      var_dma.h
+//
+//      STM32 DMA support
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2011-12-07
+// Purpose:     STM32 DMA support
+// Description: 
+// Usage:       #include <cyg/hal/var_dma.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_stm32.h>
+
+#include <cyg/hal/drv_api.h>
+
+//=============================================================================
+// DMA stream descriptors
+
+#define CYGHWR_HAL_STM32_DMA_MODE_P2M           0
+#define CYGHWR_HAL_STM32_DMA_MODE_M2P           1
+#define CYGHWR_HAL_STM32_DMA_MODE_M2M           2
+
+
+// DMA descriptor. Packs interrupt vector, controller, stream and
+// channel IDs together with the mode into a 32 bit descriptor.
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_DMA( __ctlr, __stream, __chan, __mode )        \
+    (((CYGNUM_HAL_INTERRUPT_DMA##__ctlr##_CH##__stream)<<16) |         \
+     ((CYGHWR_HAL_STM32_DMA_MODE_##__mode)<<12) |                       \
+     ((__chan)<<8) | ((__stream)<<4) | ((__ctlr)<<0))
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_DMA( __ctlr, __stream, __chan, __mode )        \
+    (((CYGNUM_HAL_INTERRUPT_DMA##__ctlr##_STR##__stream)<<16) |         \
+     ((CYGHWR_HAL_STM32_DMA_MODE_##__mode)<<12) |                       \
+     ((__chan)<<8) | ((__stream)<<4) | ((__ctlr)<<0))
+#else
+#error "Undefined STM32 family"
+#endif
+
+#define CYGHWR_HAL_STM32_DMA_INTERRUPT( __desc )  (((__desc)>>16)&0xFFFF)
+#define CYGHWR_HAL_STM32_DMA_MODE( __desc )       (((__desc)>>12)&0xF)
+#define CYGHWR_HAL_STM32_DMA_CHANNEL( __desc )    (((__desc)>>8)&0xF)
+#define CYGHWR_HAL_STM32_DMA_STREAM( __desc )     (((__desc)>>4)&0xF)
+#define CYGHWR_HAL_STM32_DMA_CONTROLLER( __desc ) (((__desc)>>0)&0xF)
+
+//=============================================================================
+// API
+
+#ifndef __ASSEMBLER__
+
+typedef struct hal_stm32_dma_stream hal_stm32_dma_stream;
+
+typedef void hal_stm32_dma_callback( hal_stm32_dma_stream *stream, cyg_uint32 count, CYG_ADDRWORD data );
+
+struct hal_stm32_dma_stream
+{
+    // These fields need to be initialized before calling
+    // hal_stm32_dma_init(). This can usually be done statically, when
+    // defining an containing data structure.
+    
+    cyg_uint32                  desc;           // stream descriptor
+    hal_stm32_dma_callback      *callback;      // Callback function
+    CYG_ADDRWORD                data;           // Client private data
+
+    
+    // Runtime data
+    
+    CYG_ADDRWORD                ctlr;           // Controller base address
+    CYG_ADDRWORD                stream;         // Stream/channel index
+
+    cyg_uint32                  ccr;            // Channel control register value
+    cyg_bool                    active;         // Channel active
+    cyg_uint32                  count;          // Bytes left to transfer
+    
+    cyg_interrupt               interrupt;      // DMA interrupt object
+    cyg_handle_t                handle;         // Interrupt handle
+};
+
+
+__externC void hal_stm32_dma_init( hal_stm32_dma_stream *stream, int pri );
+
+__externC void hal_stm32_dma_delete( hal_stm32_dma_stream *stream );
+
+__externC void hal_stm32_dma_disable( hal_stm32_dma_stream *stream );
+
+__externC void hal_stm32_dma_poll( hal_stm32_dma_stream *stream );
+
+__externC void hal_stm32_dma_configure( hal_stm32_dma_stream *stream, int tfr_size,
+                                        cyg_bool no_minc, cyg_bool polled  );
+
+__externC void hal_stm32_dma_configure_circular( hal_stm32_dma_stream *stream,
+                                                 cyg_bool enable);
+
+__externC void hal_stm32_dma_start( hal_stm32_dma_stream *stream, void *memory,
+                                    CYG_ADDRESS peripheral, cyg_uint32 size );
+
+__externC void hal_stm32_dma_show( hal_stm32_dma_stream *stream );
+
+#endif // __ASSEMBLER__
+
+#endif // CYGONCE_HAL_VAR_DMA_H
+//-----------------------------------------------------------------------------
+// end of var_dma.h
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h
new file mode 100644
index 0000000..05835f9
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h
@@ -0,0 +1,427 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for STM32 variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-10-06
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for ST STM32 variants are
+//               defined here.
+//              
+// Usage:        #include <cyg/hal/var_intr.h>
+//               However applications should include using <cyg/hal/hal_intr.h>
+//               instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+
+#define CYGNUM_HAL_INTERRUPT_WWDG               ( 0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PVD                ( 1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TAMPER             ( 2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TAMP_STAMP         ( 2+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name - also timestamps
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGNUM_HAL_INTERRUPT_RTC_GLOBAL         ( 3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGNUM_HAL_INTERRUPT_RTC_WKUP           ( 3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#define CYGNUM_HAL_INTERRUPT_FLASH              ( 4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RCC                ( 5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EXTI0              ( 6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EXTI1              ( 7+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EXTI2              ( 8+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EXTI3              ( 9+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_EXTI4              (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH1           (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR0          (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH2           (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR1          (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH3           (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR2          (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH4           (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR3          (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH5           (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR4          (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH6           (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR5          (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA1_CH7           (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR6          (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_ADC1_2             (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 only has ADC1+2
+#define CYGNUM_HAL_INTERRUPT_ADC1_2_3           (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has ADC1+2+3
+#define CYGNUM_HAL_INTERRUPT_ADC                (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // More generic name
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGNUM_HAL_INTERRUPT_USB_HP             (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#define CYGNUM_HAL_INTERRUPT_CAN1_TX            (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGNUM_HAL_INTERRUPT_USB_LP             (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#define CYGNUM_HAL_INTERRUPT_CAN1_RX0           (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN1_RX1           (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN1_SCE           (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EXTI9_5            (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM1_BRK           (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM1_BRK_TIM9      (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM9
+#define CYGNUM_HAL_INTERRUPT_TIM1_UP            (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM1_UP_TIM10      (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM10
+#define CYGNUM_HAL_INTERRUPT_TIM1_TRG           (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM1_TRG_COM_TIM11 (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM11
+#define CYGNUM_HAL_INTERRUPT_TIM1_CC            (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM2               (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM3               (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_TIM4               (30+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1_EV            (31+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1_EE            (32+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C2_EV            (33+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C2_EE            (34+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SPI1               (35+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SPI2               (36+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART1              (37+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART2              (38+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART3              (39+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_EXTI15_10          (40+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RTC_ALARM          (41+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGNUM_HAL_INTERRUPT_USB_WAKEUP         (42+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGNUM_HAL_INTERRUPT_OTG_FS_WKUP        (42+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#ifndef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGNUM_HAL_INTERRUPT_TIM8_BRK           (43+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM8_UP            (44+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM8_TRG           (45+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM8_CC            (46+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGNUM_HAL_INTERRUPT_ADC3               (47+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#define CYGNUM_HAL_INTERRUPT_FSMC               (48+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SDIO               (49+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#else
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGNUM_HAL_INTERRUPT_TIM8_BRK_TIM12     (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM12
+#define CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13      (44+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM13
+#define CYGNUM_HAL_INTERRUPT_TIM8_TRG_COM_TIM14 (45+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM13
+#define CYGNUM_HAL_INTERRUPT_TIM8_CC            (46+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA1_STR7          (47+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_FSMC               (48+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SDIO               (49+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#endif
+#endif
+
+#define CYGNUM_HAL_INTERRUPT_TIM5               (50+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SPI3               (51+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART4              (52+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART5              (53+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM6               (54+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIM6_DAC           (54+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because also DAC1+2 underrun
+#define CYGNUM_HAL_INTERRUPT_TIM7               (55+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH1           (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR0          (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH2           (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR1          (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH3           (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR2          (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+
+#ifndef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+# error Support does not yet exist for F2 or F4 without connectivity
+#endif
+
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH4           (59+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH5           (CYGNUM_HAL_INTERRUPT_DMA2_CH4) // As per RM0008 datasheet 3.3.6 note
+
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX           (59+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#else
+
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH4           (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR3          (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+
+#define CYGNUM_HAL_INTERRUPT_DMA2_CH5           (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR4          (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams
+#define CYGNUM_HAL_INTERRUPT_ETH                (61+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ETH_WAKEUP         (62+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN2_TX            (63+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN2_RX0           (64+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN2_RX1           (65+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN2_SCE           (66+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGNUM_HAL_INTERRUPT_USB_FS             (67+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX           (67+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGNUM_HAL_INTERRUPT_OTG_FS             (67+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR5          (68+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR6          (69+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA2_STR7          (70+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART6              (71+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C3_EV            (72+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C3_ER            (73+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_OTG_HS_EP1_OUT     (74+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_OTG_HS_EP1_IN      (75+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_OTG_HS_WKUP        (76+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_OTG_HS             (77+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DCMI               (78+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CRYP               (79+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_HASH_RNG           (80+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+# define CYGNUM_HAL_INTERRUPT_HASH_FPU          (81+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+# define CYGNUM_HAL_INTERRUPT_NVIC_MAX          (81+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+# define CYGNUM_HAL_INTERRUPT_NVIC_MAX          (80+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#else
+# error "Support does not yet exist for this FAMILY_HIPERFORMANCE configuration"
+#endif
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#endif // ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+
+#define CYGNUM_HAL_INTERRUPT_EXTI5              ( 1+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI6              ( 2+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI7              ( 3+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI8              ( 4+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI9              ( 5+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI10             ( 6+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI11             ( 7+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI12             ( 8+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI13             ( 9+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI14             (10+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#define CYGNUM_HAL_INTERRUPT_EXTI15             (11+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+
+#define CYGNUM_HAL_ISR_MIN                     0
+#define CYGNUM_HAL_ISR_MAX                     CYGNUM_HAL_INTERRUPT_EXTI15
+#define CYGNUM_HAL_ISR_COUNT                   (CYGNUM_HAL_ISR_MAX + 1)
+
+#define CYGNUM_HAL_VSR_MIN                     0
+#ifndef CYGNUM_HAL_VSR_MAX
+#define CYGNUM_HAL_VSR_MAX                     (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+#define CYGNUM_HAL_VSR_COUNT                   (CYGNUM_HAL_VSR_MAX+1)
+
+//==========================================================================
+// Interrupt mask and config for variant-specific devices
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                  \
+    case CYGNUM_HAL_INTERRUPT_PVD:                                      \
+        __v =  16;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_RTC_ALARM:                                \
+        __v =  17;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_USB_WAKEUP:                               \
+        __v =  18;                                                      \
+        break;
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                  \
+    case CYGNUM_HAL_INTERRUPT_PVD:                                      \
+        __v =  16;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_RTC_ALARM:                                \
+        __v =  17;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_OTG_FS_WKUP:                              \
+        __v =  18;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_ETH_WAKEUP:                               \
+        __v =  19;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_OTG_HS_WKUP:                              \
+        __v =  20;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_TAMP_STAMP:                               \
+        __v =  21;                                                      \
+        break;                                                          \
+    case CYGNUM_HAL_INTERRUPT_RTC_WKUP:                                 \
+        __v =  22;                                                      \
+        break;
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define HAL_VAR_INTERRUPT_MASK( __vector )                              \
+{                                                                       \
+    cyg_int32 __v = -1;                                                 \
+                                                                        \
+    switch( __vector )                                                  \
+    {                                                                   \
+    case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4:       \
+        __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0;                    \
+        break;                                                          \
+                                                                        \
+    case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9:       \
+        __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
+        break;                                                          \
+                                                                        \
+    case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15:     \
+        __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
+        break;                                                          \
+                                                                        \
+    HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                      \
+    }                                                                   \
+                                                                        \
+    if( __v >= 0 )                                                      \
+    {                                                                   \
+        cyg_uint32 __imr;                                               \
+        HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \
+        __imr &= ~CYGHWR_HAL_STM32_EXTI_BIT(__v);                       \
+        HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \
+    }                                                                   \
+}
+
+#define HAL_VAR_INTERRUPT_UNMASK( __vector )                            \
+{                                                                       \
+    cyg_int32 __v = -1;                                                 \
+                                                                        \
+    switch( __vector )                                                  \
+    {                                                                   \
+    case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4:       \
+        __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0;                    \
+        break;                                                          \
+                                                                        \
+    case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9:       \
+        __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;                \
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(CYGNUM_HAL_INTERRUPT_EXTI9_5-CYGNUM_HAL_INTERRUPT_EXTERNAL), \
+                          CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI9_5-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \
+        break;                                                          \
+                                                                        \
+    case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15:     \
+        __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;                \
+        HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL), \
+                          CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \
+        break;                                                          \
+                                                                        \
+    HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                      \
+    }                                                                   \
+                                                                        \
+    if( __v >= 0 )                                                      \
+    {                                                                   \
+        cyg_uint32 __imr;                                               \
+        HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \
+        __imr |= CYGHWR_HAL_STM32_EXTI_BIT(__v);                        \
+        HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \
+    }                                                                   \
+}
+
+#define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) CYG_EMPTY_STATEMENT
+
+#define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector )                       \
+{                                                                       \
+    cyg_int32 __v = -1;                                                 \
+                                                                        \
+    switch( __vector )                                                  \
+    {                                                                   \
+    case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4:       \
+        __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0;                    \
+        break;                                                          \
+                                                                        \
+    case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9:       \
+        __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
+        break;                                                          \
+                                                                        \
+    case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15:     \
+        __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
+        break;                                                          \
+                                                                        \
+    HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                      \
+    }                                                                   \
+                                                                        \
+    if( __v >= 0 )                                                      \
+    {                                                                   \
+        cyg_uint32 __bit = CYGHWR_HAL_STM32_EXTI_BIT(__v);              \
+        HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_PR, __bit ); \
+    }                                                                   \
+}
+
+#define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up )          \
+{                                                                       \
+    cyg_int32 __v = -1;                                                 \
+                                                                        \
+    switch( __vector )                                                  \
+    {                                                                   \
+    case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4:       \
+        __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0;                    \
+        break;                                                          \
+                                                                        \
+    case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9:       \
+        __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
+        break;                                                          \
+                                                                        \
+    case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15:     \
+        __v =  __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5;               \
+        break;                                                          \
+                                                                        \
+    HAL_VAR_PERIPH_EXTI_MAP_FAMILY                                      \
+    }                                                                   \
+                                                                        \
+    if(( __v >= 0 ) && !(__level) )                                     \
+    {                                                                   \
+        cyg_uint32 __base = CYGHWR_HAL_STM32_EXTI;                      \
+        cyg_uint32 __rtsr, __ftsr;                                      \
+        cyg_uint32 __bit = CYGHWR_HAL_STM32_EXTI_BIT(__v);              \
+        HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __rtsr );   \
+        HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_FTSR, __ftsr );   \
+        if( __up ) __rtsr |= __bit, __ftsr &= ~__bit;                   \
+        else __ftsr |= __bit, __rtsr &= ~__bit;                         \
+        HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __rtsr );  \
+        HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_FTSR, __ftsr );  \
+    }                                                                   \
+}
+
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h
new file mode 100644
index 0000000..b947bf5
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h
@@ -0,0 +1,1931 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     STM32 variant specific registers
+// Description:
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_stm32.h>
+
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Peripherals
+
+#define CYGHWR_HAL_STM32_TIM2           0x40000000
+#define CYGHWR_HAL_STM32_TIM3           0x40000400
+#define CYGHWR_HAL_STM32_TIM4           0x40000800
+#define CYGHWR_HAL_STM32_TIM5           0x40000C00
+#define CYGHWR_HAL_STM32_TIM6           0x40001000
+#define CYGHWR_HAL_STM32_TIM7           0x40001400
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_TIM12          0x40001800
+#define CYGHWR_HAL_STM32_TIM13          0x40001C00
+#define CYGHWR_HAL_STM32_TIM14          0x40002000
+#endif
+#define CYGHWR_HAL_STM32_RTC            0x40002800
+#define CYGHWR_HAL_STM32_WWDG           0x40002C00
+#define CYGHWR_HAL_STM32_IWDG           0x40003000
+#define CYGHWR_HAL_STM32_SPI2           0x40003800
+#define CYGHWR_HAL_STM32_SPI3           0x40003C00
+#define CYGHWR_HAL_STM32_UART2          0x40004400
+#define CYGHWR_HAL_STM32_UART3          0x40004800
+#define CYGHWR_HAL_STM32_UART4          0x40004C00
+#define CYGHWR_HAL_STM32_UART5          0x40005000
+#define CYGHWR_HAL_STM32_I2C1           0x40005400
+#define CYGHWR_HAL_STM32_I2C2           0x40005800
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_USB            0x40005C00
+#define CYGHWR_HAL_STM32_USB_CAN_SRAM   0x40006000
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_I2C3           0x40005C00
+#endif
+#define CYGHWR_HAL_STM32_BXCAN1         0x40006400
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_BXCAN2         0x40006800
+#endif
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_BKP            0x40006C00
+#endif
+#define CYGHWR_HAL_STM32_PWR            0x40007000
+#define CYGHWR_HAL_STM32_DAC            0x40007400
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_AFIO           0x40010000
+#define CYGHWR_HAL_STM32_EXTI           0x40010400
+#define CYGHWR_HAL_STM32_GPIOA          0x40010800
+#define CYGHWR_HAL_STM32_GPIOB          0x40010C00
+#define CYGHWR_HAL_STM32_GPIOC          0x40011000
+#define CYGHWR_HAL_STM32_GPIOD          0x40011400
+#define CYGHWR_HAL_STM32_GPIOE          0x40011800
+#define CYGHWR_HAL_STM32_GPIOF          0x40011C00
+#define CYGHWR_HAL_STM32_GPIOG          0x40012000
+#define CYGHWR_HAL_STM32_ADC1           0x40012400
+#define CYGHWR_HAL_STM32_ADC2           0x40012800
+#define CYGHWR_HAL_STM32_TIM1           0x40012C00
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_TIM1           0x40010000
+#define CYGHWR_HAL_STM32_PWM1           0x40010000
+#define CYGHWR_HAL_STM32_TIM8           0x40010400
+#define CYGHWR_HAL_STM32_PWM2           0x40010400
+#define CYGHWR_HAL_STM32_UART1          0x40011000
+#define CYGHWR_HAL_STM32_UART6          0x40011400
+#define CYGHWR_HAL_STM32_ADC1           0x40012000
+#define CYGHWR_HAL_STM32_ADC2           CYGHWR_HAL_STM32_ADC1 + 0x0100
+#define CYGHWR_HAL_STM32_ADC3           CYGHWR_HAL_STM32_ADC1 + 0x0200
+#define CYGHWR_HAL_STM32_ADC_COMMON     CYGHWR_HAL_STM32_ADC1 + 0x0300
+#define CYGHWR_HAL_STM32_SDIO           0x40012C00
+#endif
+#define CYGHWR_HAL_STM32_SPI1           0x40013000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_TIM8           0x40013400
+#define CYGHWR_HAL_STM32_UART1          0x40013800
+#define CYGHWR_HAL_STM32_ADC3           0x40013C00
+#define CYGHWR_HAL_STM32_SDIO           0x40018000
+#define CYGHWR_HAL_STM32_DMA1           0x40020000
+#define CYGHWR_HAL_STM32_DMA2           0x40020400
+#define CYGHWR_HAL_STM32_RCC            0x40021000
+#define CYGHWR_HAL_STM32_FLASH          0x40022000
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_SYSCFG         0x40013800
+#define CYGHWR_HAL_STM32_EXTI           0x40013C00
+#define CYGHWR_HAL_STM32_TIM9           0x40014000
+#define CYGHWR_HAL_STM32_TIM10          0x40014400
+#define CYGHWR_HAL_STM32_TIM11          0x40014800
+#define CYGHWR_HAL_STM32_GPIOA          0x40020000
+#define CYGHWR_HAL_STM32_GPIOB          0x40020400
+#define CYGHWR_HAL_STM32_GPIOC          0x40020800
+#define CYGHWR_HAL_STM32_GPIOD          0x40020C00
+#define CYGHWR_HAL_STM32_GPIOE          0x40021000
+#define CYGHWR_HAL_STM32_GPIOF          0x40021400
+#define CYGHWR_HAL_STM32_GPIOG          0x40021800
+#define CYGHWR_HAL_STM32_GPIOH          0x40021C00
+#define CYGHWR_HAL_STM32_GPIOI          0x40022000
+#endif
+#define CYGHWR_HAL_STM32_CRC            0x40023000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC            0x40023800
+#define CYGHWR_HAL_STM32_FLASH          0x40023C00
+#define CYGHWR_HAL_STM32_BKPSRAM        0x40024000
+#define CYGHWR_HAL_STM32_DMA1           0x40026000
+#define CYGHWR_HAL_STM32_DMA2           0x40026400
+#endif
+#define CYGHWR_HAL_STM32_ETH            0x40028000
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_USB_OTG_HS     0x40040000
+#endif
+#define CYGHWR_HAL_STM32_USB_OTG_FS     0x50000000
+#define CYGHWR_HAL_STM32_OTG            CYGHWR_HAL_STM32_USB_OTG_FS // compatibility define. Deprecated.
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_DCMI           0x50050000
+#define CYGHWR_HAL_STM32_CRYP           0x50060000
+#define CYGHWR_HAL_STM32_HASH           0x50060400
+#define CYGHWR_HAL_STM32_RNG            0x50060800
+#endif
+#define CYGHWR_HAL_STM32_FSMC           0xA0000000
+
+//=============================================================================
+// Device signature and ID registers
+
+#define CYGHWR_HAL_STM32_DEV_SIG                0x1FFFF7E0
+#define CYGHWR_HAL_STM32_DEV_SIG_RSIZE(__s)     (((__s)>>16)&0xFFFF)
+#define CYGHWR_HAL_STM32_DEV_SIG_FSIZE(__s)     ((__s)&0xFFFF)
+
+#define CYGHWR_HAL_STM32_MCU_ID                 0xe0042000
+#define CYGHWR_HAL_STM32_MCU_ID_DEV(__x)        ((__x)&0xFFF)
+#define CYGHWR_HAL_STM32_MCU_ID_DEV_MEDIUM      0x410
+#define CYGHWR_HAL_STM32_MCU_ID_DEV_HIGH        0x414
+#define CYGHWR_HAL_STM32_MCU_ID_REV(__x)        (((__x)>>16)&0xFFFF)
+
+//=============================================================================
+// RCC
+//
+// Not all registers are described here
+
+#define CYGHWR_HAL_STM32_RCC_CR                 0x00
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_RCC_CFGR               0x04
+#define CYGHWR_HAL_STM32_RCC_CIR                0x08
+#define CYGHWR_HAL_STM32_RCC_APB2RSTR           0x0C
+#define CYGHWR_HAL_STM32_RCC_APB1RSTR           0x10
+#define CYGHWR_HAL_STM32_RCC_AHBENR             0x14
+#define CYGHWR_HAL_STM32_RCC_APB2ENR            0x18
+#define CYGHWR_HAL_STM32_RCC_APB1ENR            0x1C
+#define CYGHWR_HAL_STM32_RCC_BDCR               0x20
+#define CYGHWR_HAL_STM32_RCC_CSR                0x24
+# ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_AHBRSTR            0x28
+#define CYGHWR_HAL_STM32_RCC_CFGR2              0x2C
+# endif
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR            0x04
+#define CYGHWR_HAL_STM32_RCC_CFGR               0x08
+#define CYGHWR_HAL_STM32_RCC_CIR                0x0C
+#define CYGHWR_HAL_STM32_RCC_AHB1RSTR           0x10
+#define CYGHWR_HAL_STM32_RCC_AHB2RSTR           0x14
+#define CYGHWR_HAL_STM32_RCC_AHB3RSTR           0x18
+#define CYGHWR_HAL_STM32_RCC_APB1RSTR           0x20
+#define CYGHWR_HAL_STM32_RCC_APB2RSTR           0x24
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR            0x30
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR            0x34
+#define CYGHWR_HAL_STM32_RCC_AHB3ENR            0x38
+#define CYGHWR_HAL_STM32_RCC_APB1ENR            0x40
+#define CYGHWR_HAL_STM32_RCC_APB2ENR            0x44
+#define CYGHWR_HAL_STM32_RCC_AHB1LPENR          0x50
+#define CYGHWR_HAL_STM32_RCC_AHB2LPENR          0x54
+#define CYGHWR_HAL_STM32_RCC_AHB3LPENR          0x58
+#define CYGHWR_HAL_STM32_RCC_APB1LPENR          0x60
+#define CYGHWR_HAL_STM32_RCC_APB2LPENR          0x64
+#define CYGHWR_HAL_STM32_RCC_BDCR               0x70
+#define CYGHWR_HAL_STM32_RCC_CSR                0x74
+#endif
+
+#define CYGHWR_HAL_STM32_RCC_CR_HSION           BIT_(0)
+#define CYGHWR_HAL_STM32_RCC_CR_HSIRDY          BIT_(1)
+#define CYGHWR_HAL_STM32_RCC_CR_HSITRIM         MASK_(3,5)
+#define CYGHWR_HAL_STM32_RCC_CR_HSICAL          MASK_(8,8)
+#define CYGHWR_HAL_STM32_RCC_CR_HSEON           BIT_(16)
+#define CYGHWR_HAL_STM32_RCC_CR_HSERDY          BIT_(17)
+#define CYGHWR_HAL_STM32_RCC_CR_HSEBYP          BIT_(18)
+#define CYGHWR_HAL_STM32_RCC_CR_CSSON           BIT_(19)
+#define CYGHWR_HAL_STM32_RCC_CR_PLLON           BIT_(24)
+#define CYGHWR_HAL_STM32_RCC_CR_PLLRDY          BIT_(25)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_CR_PLLI2SON        BIT_(26)
+#define CYGHWR_HAL_STM32_RCC_CR_PLLI2SRDY       BIT_(27)
+#endif
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM(__m)  VALUE_(0,__m)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM_MASK  MASK_(0,6)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN(__n)  VALUE_(6,__n)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN_MASK  MASK_(6,9)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP(__p)  VALUE_(16,((__p)>>1)-1 )
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_2     VALUE_(16,0)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_4     VALUE_(16,1)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_6     VALUE_(16,2)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_8     VALUE_(16,3)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSI VALUE_(22,0)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSE VALUE_(22,1)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ(__q)  VALUE_(24,__q)
+#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ_MASK  MASK_(24,4)
+#endif
+
+#define CYGHWR_HAL_STM32_RCC_CFGR_SW_HSI        VALUE_(0,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_SW_HSE        VALUE_(0,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_SW_PLL        VALUE_(0,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_SW_XXX        VALUE_(0,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_HSI       VALUE_(2,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_HSE       VALUE_(2,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_PLL       VALUE_(2,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_XXX       VALUE_(2,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_1        VALUE_(4,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_2        VALUE_(4,8)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_4        VALUE_(4,9)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_8        VALUE_(4,10)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_16       VALUE_(4,11)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_64       VALUE_(4,12)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_128      VALUE_(4,13)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_256      VALUE_(4,14)
+#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_512      VALUE_(4,15)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1       VALUE_(8,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2       VALUE_(8,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4       VALUE_(8,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8       VALUE_(8,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16      VALUE_(8,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1       VALUE_(11,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2       VALUE_(11,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4       VALUE_(11,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8       VALUE_(11,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16      VALUE_(11,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_2      VALUE_(14,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_4      VALUE_(14,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_6      VALUE_(14,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_8      VALUE_(14,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_XXX    VALUE_(14,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSI    0
+#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE    BIT_(16)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_PREDIV1 BIT_(16)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE      BIT_(17)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PLLMUL(__x)   VALUE_(18,(__x)-2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_USBPRE        BIT_(22)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_NONE      VALUE_(24,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_SYSCLK    VALUE_(24,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_HSI       VALUE_(24,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_HSE       VALUE_(24,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL       VALUE_(24,7)
+# ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL2      VALUE_(24,8)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3_HALF VALUE_(24,9)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_XT1       VALUE_(24,10)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3      VALUE_(24,11)
+#define CYGHWR_HAL_STM32_RCC_CR_PLL2ON          BIT_(26)
+#define CYGHWR_HAL_STM32_RCC_CR_PLL2RDY         BIT_(27)
+# endif
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1       VALUE_(10,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2       VALUE_(10,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4       VALUE_(10,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8       VALUE_(10,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16      VALUE_(10,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1       VALUE_(13,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2       VALUE_(13,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4       VALUE_(13,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8       VALUE_(13,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16      VALUE_(13,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE(__x)   VALUE_(16,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE_MASK   MASK_(16,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_MASK     MASK_(21,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSI      VALUE_(21,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_LSE      VALUE_(21,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE      VALUE_(21,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_PLL      VALUE_(21,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_I2SSRC_PLLI2S VALUE_(23,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_I2SSRC_EXT    VALUE_(23,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_MASK  MASK_(24,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1     VALUE_(24,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_2     VALUE_(24,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_3     VALUE_(24,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_4     VALUE_(24,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_5     VALUE_(24,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_MASK  MASK_(27,3)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_1     VALUE_(27,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_2     VALUE_(27,4)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_3     VALUE_(27,5)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_4     VALUE_(27,6)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_5     VALUE_(27,7)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_MASK     MASK_(30,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_SYSCLK   VALUE_(30,0)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_PLLI2S   VALUE_(30,1)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_HSE      VALUE_(30,2)
+#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_PLL      VALUE_(30,3)
+#endif
+
+#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA1        (0)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA2        (1)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_SRAM        (2)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_FLITF       (4)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_CRC         (6)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_FSMC        (8)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_SDIO        (10)
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_AHBENR_OTGFS       (12)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMAC      (14)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACTX    (15)
+#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACRX    (16)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_RCC_AHBRSTR_OTGFSRST   BIT_(12)
+#define CYGHWR_HAL_STM32_RCC_AHBRSTR_ETHMACRST  BIT_(14)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_AHB1RSTR_ETHMACRST BIT_(25)
+#endif
+#endif
+
+// Note that the following are bit numbers, not masks. They should
+// either be used with the CYGHWR_HAL_STM32_CLOCK() macro or used to
+// shift a 1, perhaps using the BIT_() macro.
+//
+// Note that in the F2/F4 families, the bit positions in the LP registers are
+// the same.
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO       (0)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA       (2)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB       (3)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC       (4)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD       (5)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE       (6)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF       (7)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG       (8)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1       (9)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2       (10)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1       (11)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1       (12)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8       (13)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1      (14)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3       (15)
+
+
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2       (0)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3       (1)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4       (2)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5       (3)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6       (4)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7       (5)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG       (11)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2       (14)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3       (15)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2      (17)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3      (18)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4      (19)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5      (20)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1       (21)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2       (22)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_USB        (23)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1       (25)
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN2       (26)
+#endif
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_BKP        (27)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR        (28)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC        (29)
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1(__x)     VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV2(__x)     VALUE_(4,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PLL2MUL(__x)     VALUE_(8,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PLL3MUL(__x)     VALUE_(12,__x)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1SRC_HSE   0
+#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1SRC_PLL2  BIT_(16)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S2SRC_SYSCLK   0
+#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S2SRC_PLL3     BIT_(17)
+#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S3SRC_SYSCLK   0
+#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S3SRC_PLL3     BIT_(18)
+#endif
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA       (0)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB       (1)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC       (2)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD       (3)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE       (4)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF       (5)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG       (6)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH       (7)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI       (8)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_CRC        (12)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_BKPSRAM    (18)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN (20)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_DMA1       (21)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_DMA2       (22)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMAC     (25)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACTX   (26)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACRX   (27)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACPTP  (28)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_OTGHS      (29)
+#define CYGHWR_HAL_STM32_RCC_AHB1ENR_OTGHSULPI  (30)
+
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_DCMI        (0)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_CRYP        (4)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_HASH        (5)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_RNG         (6)
+#define CYGHWR_HAL_STM32_RCC_AHB2ENR_OTGFS       (7)
+
+#define CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC        (0)
+
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2        (0)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3        (1)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4        (2)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5        (3)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6        (4)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7        (5)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM12       (6)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM13       (7)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM14       (8)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG       (11)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2       (14)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3       (15)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2      (17)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3      (18)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4      (19)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5      (20)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1       (21)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2       (22)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C3       (23)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1       (25)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN2       (26)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR        (28)
+#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC        (29)
+
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1        (0)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8        (1)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1       (4)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART6       (5)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1        (8)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2        (9)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3       (10)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_SDIO       (11)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1       (12)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_SYSCFG     (14)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM9       (16)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM10      (17)
+#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM11      (18)
+
+#endif
+
+// The following encodes the control register and clock bit number
+// into a 32 bit descriptor.
+#define CYGHWR_HAL_STM32_CLOCK( __reg, __pin )                  \
+            ((CYGHWR_HAL_STM32_RCC_##__reg##ENR) |              \
+             ((CYGHWR_HAL_STM32_RCC_##__reg##ENR_##__pin)<<16))
+
+// Macros to extract encoded values.
+#define CYGHWR_HAL_STM32_CLOCK_REG( __desc ) ((__desc)&0xFF)
+#define CYGHWR_HAL_STM32_CLOCK_PIN( __desc ) (((__desc)>>16)&0xFF)
+
+// Functions and macros to enable/disable clocks.
+
+__externC void hal_stm32_clock_enable( cyg_uint32 desc );
+__externC void hal_stm32_clock_disable( cyg_uint32 desc );
+
+#define CYGHWR_HAL_STM32_CLOCK_ENABLE( __desc ) hal_stm32_clock_enable( __desc )
+#define CYGHWR_HAL_STM32_CLOCK_DISABLE( __desc ) hal_stm32_clock_disable( __desc )
+
+
+#define CYGHWR_HAL_STM32_RCC_BDCR_LSEON         BIT_(0)
+#define CYGHWR_HAL_STM32_RCC_BDCR_LSERDY        BIT_(1)
+#define CYGHWR_HAL_STM32_RCC_BDCR_LSEBYP        BIT_(2)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_NO     VALUE_(8,0)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSE    VALUE_(8,1)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSI    VALUE_(8,2)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_HSE    VALUE_(8,3)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_XXX    VALUE_(8,3)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCEN         BIT_(15)
+#define CYGHWR_HAL_STM32_RCC_BDCR_BDRST         BIT_(16)
+
+#define CYGHWR_HAL_STM32_RCC_CSR_LSION          BIT_(0)
+#define CYGHWR_HAL_STM32_RCC_CSR_LSIRDY         BIT_(1)
+#define CYGHWR_HAL_STM32_RCC_CSR_RMVF           BIT_(24)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_RCC_CSR_BORRSTF        BIT_(25)
+#endif
+#define CYGHWR_HAL_STM32_RCC_CSR_PINRSTF        BIT_(26)
+#define CYGHWR_HAL_STM32_RCC_CSR_PORRSTF        BIT_(27)
+#define CYGHWR_HAL_STM32_RCC_CSR_SFTRSTF        BIT_(28)
+#define CYGHWR_HAL_STM32_RCC_CSR_IWDGRSTF       BIT_(29)
+#define CYGHWR_HAL_STM32_RCC_CSR_WWDGRSTF       BIT_(30)
+#define CYGHWR_HAL_STM32_RCC_CSR_LPWRRSTF       BIT_(31)
+
+
+// Miscellaneous clock control bits
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_CLOCK_BKP              CYGHWR_HAL_STM32_CLOCK( APB1, BKP )
+#endif
+
+#define CYGHWR_HAL_STM32_CLOCK_PWR              CYGHWR_HAL_STM32_CLOCK( APB1, PWR )
+
+//=============================================================================
+// Realtime Clock
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_RTC_CRH                0x00
+#define CYGHWR_HAL_STM32_RTC_CRL                0x04
+#define CYGHWR_HAL_STM32_RTC_PRLH               0x08
+#define CYGHWR_HAL_STM32_RTC_PRLL               0x0C
+#define CYGHWR_HAL_STM32_RTC_DIVH               0x10
+#define CYGHWR_HAL_STM32_RTC_DIVL               0x14
+#define CYGHWR_HAL_STM32_RTC_CNTH               0x18
+#define CYGHWR_HAL_STM32_RTC_CNTL               0x1C
+#define CYGHWR_HAL_STM32_RTC_ALRH               0x20
+#define CYGHWR_HAL_STM32_RTC_ALRL               0x24
+
+// CRH fields
+
+#define CYGHWR_HAL_STM32_RTC_CRH_SECIE          BIT_(0)
+#define CYGHWR_HAL_STM32_RTC_CRH_ALRIE          BIT_(1)
+#define CYGHWR_HAL_STM32_RTC_CRH_OWIE           BIT_(2)
+
+// CRL fields
+
+#define CYGHWR_HAL_STM32_RTC_CRL_SECF           BIT_(0)
+#define CYGHWR_HAL_STM32_RTC_CRL_ALRF           BIT_(1)
+#define CYGHWR_HAL_STM32_RTC_CRL_OWF            BIT_(2)
+#define CYGHWR_HAL_STM32_RTC_CRL_RSF            BIT_(3)
+#define CYGHWR_HAL_STM32_RTC_CRL_CNF            BIT_(4)
+#define CYGHWR_HAL_STM32_RTC_CRL_RTOFF          BIT_(5)
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_RTC_TR                 0x00
+#define CYGHWR_HAL_STM32_RTC_DR                 0x04
+#define CYGHWR_HAL_STM32_RTC_CR                 0x08
+#define CYGHWR_HAL_STM32_RTC_ISR                0x0C
+#define CYGHWR_HAL_STM32_RTC_PRER               0x10
+#define CYGHWR_HAL_STM32_RTC_WUTR               0x14
+#define CYGHWR_HAL_STM32_RTC_CALIBR             0x18
+#define CYGHWR_HAL_STM32_RTC_ALRMAR             0x1C
+#define CYGHWR_HAL_STM32_RTC_ALRMBR             0x20
+#define CYGHWR_HAL_STM32_RTC_WPR                0x24
+#define CYGHWR_HAL_STM32_RTC_TSTR               0x30
+#define CYGHWR_HAL_STM32_RTC_TSDR               0x34
+#define CYGHWR_HAL_STM32_RTC_TAFCR              0x40
+#define CYGHWR_HAL_STM32_RTC_BKxR(_x)           (0x50 + 4*(_x))
+
+#define CYGHWR_HAL_STM32_RTC_TR_SU              MASK_(0,4)
+#define CYGHWR_HAL_STM32_RTC_TR_SU_SHIFT        0
+#define CYGHWR_HAL_STM32_RTC_TR_ST              MASK_(4,3)
+#define CYGHWR_HAL_STM32_RTC_TR_ST_SHIFT        4
+#define CYGHWR_HAL_STM32_RTC_TR_MNU             MASK_(8,4)
+#define CYGHWR_HAL_STM32_RTC_TR_MNU_SHIFT       8
+#define CYGHWR_HAL_STM32_RTC_TR_MNT             MASK_(12,3)
+#define CYGHWR_HAL_STM32_RTC_TR_MNT_SHIFT       12
+#define CYGHWR_HAL_STM32_RTC_TR_HU              MASK_(16,4)
+#define CYGHWR_HAL_STM32_RTC_TR_HU_SHIFT        16
+#define CYGHWR_HAL_STM32_RTC_TR_HT              MASK_(20,2)
+#define CYGHWR_HAL_STM32_RTC_TR_HT_SHIFT        20
+#define CYGHWR_HAL_STM32_RTC_TR_AM              VALUE_(22, 0)
+#define CYGHWR_HAL_STM32_RTC_TR_PM              VALUE_(22, 1)
+
+#define CYGHWR_HAL_STM32_RTC_DR_DU              MASK_(0,4)
+#define CYGHWR_HAL_STM32_RTC_DR_DU_SHIFT        0
+#define CYGHWR_HAL_STM32_RTC_DR_DT              MASK_(4,2)
+#define CYGHWR_HAL_STM32_RTC_DR_DT_SHIFT        4
+#define CYGHWR_HAL_STM32_RTC_DR_MU              MASK_(8,4)
+#define CYGHWR_HAL_STM32_RTC_DR_MU_SHIFT        8
+#define CYGHWR_HAL_STM32_RTC_DR_MT              BIT_(12)
+#define CYGHWR_HAL_STM32_RTC_DR_MT_SHIFT        12
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_MON         VALUE_(13,1)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_TUE         VALUE_(13,2)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_WED         VALUE_(13,3)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_THU         VALUE_(13,4)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_FRI         VALUE_(13,5)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_SAT         VALUE_(13,6)
+#define CYGHWR_HAL_STM32_RTC_DR_WDU_SUN         VALUE_(13,7)
+#define CYGHWR_HAL_STM32_RTC_DR_YU              MASK_(16,4)
+#define CYGHWR_HAL_STM32_RTC_DR_YU_SHIFT        16
+#define CYGHWR_HAL_STM32_RTC_DR_YT              MASK_(20,4)
+#define CYGHWR_HAL_STM32_RTC_DR_YT_SHIFT        20
+
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_16      VALUE_(0,0)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_8       VALUE_(0,1)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_4       VALUE_(0,2)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_2       VALUE_(0,3)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_CK_SPRE VALUE_(0,4)
+#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_CK_SPRE_PLUS_216 VALUE_(0,6)
+#define CYGHWR_HAL_STM32_RTC_CR_TSEDGE          BIT_(3)
+#define CYGHWR_HAL_STM32_RTC_CR_REFCKON         BIT_(4)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_RTC_CR_BYPSHAD         BIT_(5)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGHWR_HAL_STM32_RTC_CR_FMT             BIT_(6)
+#define CYGHWR_HAL_STM32_RTC_CR_DCE             BIT_(7)
+#define CYGHWR_HAL_STM32_RTC_CR_ALRAE           BIT_(8)
+#define CYGHWR_HAL_STM32_RTC_CR_ALRBE           BIT_(9)
+#define CYGHWR_HAL_STM32_RTC_CR_WUTE            BIT_(10)
+#define CYGHWR_HAL_STM32_RTC_CR_TSE             BIT_(11)
+#define CYGHWR_HAL_STM32_RTC_CR_ALRAIE          BIT_(12)
+#define CYGHWR_HAL_STM32_RTC_CR_ALRBIE          BIT_(13)
+#define CYGHWR_HAL_STM32_RTC_CR_WUTIE           BIT_(14)
+#define CYGHWR_HAL_STM32_RTC_CR_TSIE            BIT_(15)
+#define CYGHWR_HAL_STM32_RTC_CR_ADD1H           BIT_(16)
+#define CYGHWR_HAL_STM32_RTC_CR_SUB1H           BIT_(17)
+#define CYGHWR_HAL_STM32_RTC_CR_BKP             BIT_(18)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_RTC_CR_COSEL           BIT_(19)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#define CYGHWR_HAL_STM32_RTC_CR_POL             BIT_(20)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_DISABLE    VALUE_(21, 0)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_ALRAOE     VALUE_(21, 1)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_ALRBOE     VALUE_(21, 2)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_WUOE       VALUE_(21, 3)
+#define CYGHWR_HAL_STM32_RTC_CR_OSEL_COE        BIT_(23)
+
+#define CYGHWR_HAL_STM32_RTC_ISR_ALRAWF         BIT_(0)
+#define CYGHWR_HAL_STM32_RTC_ISR_ALRBWF         BIT_(1)
+#define CYGHWR_HAL_STM32_RTC_ISR_WUTWF          BIT_(2)
+#define CYGHWR_HAL_STM32_RTC_ISR_INITS          BIT_(4)
+#define CYGHWR_HAL_STM32_RTC_ISR_RSF            BIT_(5)
+#define CYGHWR_HAL_STM32_RTC_ISR_INITF          BIT_(6)
+#define CYGHWR_HAL_STM32_RTC_ISR_INIT           BIT_(7)
+#define CYGHWR_HAL_STM32_RTC_ISR_ALRAF          BIT_(8)
+#define CYGHWR_HAL_STM32_RTC_ISR_ALRBF          BIT_(9)
+#define CYGHWR_HAL_STM32_RTC_ISR_WUTF           BIT_(10)
+#define CYGHWR_HAL_STM32_RTC_ISR_TSF            BIT_(11)
+#define CYGHWR_HAL_STM32_RTC_ISR_TSOVF          BIT_(12)
+#define CYGHWR_HAL_STM32_RTC_ISR_TAMP1F         BIT_(13)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_S      MASK_(0,13)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_RTC_ISR_SHPF           BIT_(3)
+#define CYGHWR_HAL_STM32_RTC_ISR_TAMP2F         BIT_(14)
+#define CYGHWR_HAL_STM32_RTC_ISR_RECALPF        BIT_(16)
+#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_S      MASK_(0,15)
+#endif
+#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_A      MASK_(16,7)
+
+// RTC_WUTR defines omitted
+// RTC_CALIBR defines omitted
+// RTC_ALRMAR defines omitted
+// RTC_ALRMBR defines omitted
+
+#define CYGHWR_HAL_STM32_RTC_WPR_KEY            MASK_(0,8)
+#define CYGHWR_HAL_STM32_RTC_WPR_KEY1           0xCA
+#define CYGHWR_HAL_STM32_RTC_WPR_KEY2           0x53
+
+// RTC_TSTR defines omitted, but layout identical to RTC_TR
+// RTC_TSDR defines omitted, but layout identical to RTC_DR except for omission of year fields
+// RTC_TAFCR defines omitted
+// No relevant RTC_BKPxR defines.
+
+// RCC clock is selected within wallclock driver, so no define here.
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+
+//=============================================================================
+// System configuration controller - F2 and F4 only
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+// Register offsets
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP          0x00
+#define CYGHWR_HAL_STM32_SYSCFG_PMC             0x04
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR1         0x08
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR2         0x0C
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR3         0x10
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR4         0x14
+#define CYGHWR_HAL_STM32_SYSCFG_CMPCR           0x20
+
+// Register definitions
+
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_MAINFLASH VALUE_(0,0)
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_SYSFLASH  VALUE_(0,1)
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_FSMC1     VALUE_(0,2)
+#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_SRAM      VALUE_(0,3)
+
+#define CYGHWR_HAL_STM32_SYSCFG_PMC_MII          VALUE_(23,0)
+#define CYGHWR_HAL_STM32_SYSCFG_PMC_RMII         VALUE_(23,1)
+
+// FIXME: The below EXTI bits should be merged with the F1 defines in
+// var_io_pins.h to provide a common interface
+
+// The following macro allows the four EXTICR registers to be indexed
+// as CYGHWR_HAL_STM32_SYSCFG_EXTICR(1) to CYGHWR_HAL_STM32_SYSCFG_EXTICR(4)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICR(__x)      (4*((__x)-1)+0x08)
+
+// The following macros are used to generate the bitfields for setting up
+// external interrupts.  For example, CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTC(12)
+// will generate the bitfield which when ORed into the EXTICR4 register will
+// set up C12 as the external interrupt pin for the EXTI12 interrupt.
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTH(__x) VALUE_(4*((__x)&3),7)
+#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_MASK(__x)  VALUE_(4*((__x)&3),0xF)
+
+#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_CMP_DIS      VALUE_(0,0)
+#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_CMP_ENA      VALUE_(0,1)
+#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_READY        BIT_(8)
+
+// SYSCFG clock control
+
+#define CYGHWR_HAL_STM32_SYSCFG_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, SYSCFG )
+
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+
+//=============================================================================
+// External interrupt controller
+
+#define CYGHWR_HAL_STM32_EXTI_IMR               0x00
+#define CYGHWR_HAL_STM32_EXTI_EMR               0x04
+#define CYGHWR_HAL_STM32_EXTI_RTSR              0x08
+#define CYGHWR_HAL_STM32_EXTI_FTSR              0x0C
+#define CYGHWR_HAL_STM32_EXTI_SWIER             0x10
+#define CYGHWR_HAL_STM32_EXTI_PR                0x14
+
+#define CYGHWR_HAL_STM32_EXTI_BIT(__b)          BIT_(__b)
+
+//=============================================================================
+// GPIO ports and pin configuration. Include separate header file for this
+// to avoid this header getting unmanageable.
+#include <cyg/hal/var_io_pins.h>
+
+//=============================================================================
+// DMA controller register definitions.
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_DMA_ISR                0x00
+#define CYGHWR_HAL_STM32_DMA_IFCR               0x04
+
+#define CYGHWR_HAL_STM32_DMA_ISR_REG(__chan)    CYGHWR_HAL_STM32_DMA_ISR
+#define CYGHWR_HAL_STM32_DMA_IFCR_REG(__chan)   CYGHWR_HAL_STM32_DMA_IFCR
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_DMA_LISR               0x00
+#define CYGHWR_HAL_STM32_DMA_HISR               0x04
+#define CYGHWR_HAL_STM32_DMA_LIFCR              0x08
+#define CYGHWR_HAL_STM32_DMA_HIFCR              0x0C
+
+#define CYGHWR_HAL_STM32_DMA_ISR_REG(__stream)  ((__stream)>3 ?               \
+                                                 CYGHWR_HAL_STM32_DMA_HISR :  \
+                                                 CYGHWR_HAL_STM32_DMA_LISR)
+#define CYGHWR_HAL_STM32_DMA_IFCR_REG(__stream) ((__stream)>3 ?               \
+                                                 CYGHWR_HAL_STM32_DMA_HIFCR : \
+                                                 CYGHWR_HAL_STM32_DMA_LIFCR)
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+
+// The following macros allow access to the per-channel DMA registers, indexed
+// by channel number. For F1 parts there is no concept of a stream - each entry
+// has a fixed relationship to the corresponding channel.
+// Valid channel/stream numbers are 1 to 7 for DMA1 and 1 to 5 for DMA2 on F1
+// parts, 1 to 7 for DMA2 streams on F2/F4 parts.
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_DMA_CCR(__x)           (0x14*(__x)-0x0C)
+#define CYGHWR_HAL_STM32_DMA_CNDTR(__x)         (0x14*(__x)-0x08)
+#define CYGHWR_HAL_STM32_DMA_CPAR(__x)          (0x14*(__x)-0x04)
+#define CYGHWR_HAL_STM32_DMA_CMAR(__x)          (0x14*(__x))
+
+#define CYGHWR_HAL_STM32_DMA_ISR_GIF(__x)       BIT_(4*(__x)-4)
+#define CYGHWR_HAL_STM32_DMA_ISR_TCIF(__x)      BIT_(4*(__x)-3)
+#define CYGHWR_HAL_STM32_DMA_ISR_HTIF(__x)      BIT_(4*(__x)-2)
+#define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x)      BIT_(4*(__x)-1)
+#define CYGHWR_HAL_STM32_DMA_ISR_MASK(__x)      VALUE_(4*(__x)-4,0xF)
+
+#define CYGHWR_HAL_STM32_DMA_IFCR_CGIF(__x)     BIT_(4*(__x)-4)
+#define CYGHWR_HAL_STM32_DMA_IFCR_CTCIF(__x)    BIT_(4*(__x)-3)
+#define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x)    BIT_(4*(__x)-2)
+#define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x)    BIT_(4*(__x)-1)
+#define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x)     VALUE_(4*(__x)-4,0xF)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_DMA_SCR(__x)           (0x18*(__x)+0x10)
+#define CYGHWR_HAL_STM32_DMA_SNDTR(__x)         (0x18*(__x)+0x14)
+#define CYGHWR_HAL_STM32_DMA_SPAR(__x)          (0x18*(__x)+0x18)
+#define CYGHWR_HAL_STM32_DMA_SM0AR(__x)         (0x18*(__x)+0x1C)
+#define CYGHWR_HAL_STM32_DMA_SM1AR(__x)         (0x18*(__x)+0x20)
+#define CYGHWR_HAL_STM32_DMA_SFCR(__x)          (0x18*(__x)+0x24)
+
+// For now at least we implement an identity mapping between
+// streams and channels.
+#define CYGHWR_HAL_STM32_DMA_CCR(__x)           CYGHWR_HAL_STM32_DMA_SCR(__x)
+#define CYGHWR_HAL_STM32_DMA_CNDTR(__x)         CYGHWR_HAL_STM32_DMA_SNDTR(__x)
+#define CYGHWR_HAL_STM32_DMA_CPAR(__x)          CYGHWR_HAL_STM32_DMA_SPAR(__x)
+#define CYGHWR_HAL_STM32_DMA_CMAR(__x)          CYGHWR_HAL_STM32_DMA_SM0AR(__x)
+#define CYGHWR_HAL_STM32_DMA_CM0AR(__x)         CYGHWR_HAL_STM32_DMA_SM0AR(__x)
+#define CYGHWR_HAL_STM32_DMA_CM1AR(__x)         CYGHWR_HAL_STM32_DMA_SM1AR(__x)
+
+// This selects which region of an isr register to use for a stream
+#define CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x)  ( ((__x)&0x3) == 3 ? 22 : \
+                                               ((__x)&0x3) == 2 ? 16 : \
+                                               ((__x)&0x3) == 1 ? 6 : 0 )
+
+#define CYGHWR_HAL_STM32_DMA_ISR_FEIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) )
+#define CYGHWR_HAL_STM32_DMA_ISR_DMEIF(__x)     BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 2 )
+#define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 3 )
+#define CYGHWR_HAL_STM32_DMA_ISR_HTIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 4 )
+#define CYGHWR_HAL_STM32_DMA_ISR_TCIF(__x)      BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 5 )
+
+#define CYGHWR_HAL_STM32_DMA_ISR_MASK(__x)      VALUE_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x), 0x3f )
+
+// This selects which region of an ifcr register to use for a stream.
+// Happens to be laid out the same as the isr, so reuse.
+#define CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x)    CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x)
+
+#define CYGHWR_HAL_STM32_DMA_IFCR_CFEIF(__x)    BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) )
+#define CYGHWR_HAL_STM32_DMA_IFCR_CDMEIF(__x)   BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 2 )
+#define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x)    BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 3 )
+#define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x)    BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 4 )
+#define CYGHWR_HAL_STM32_DMA_IFCR_CTCIF(__x)    BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 5 )
+#define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x)     VALUE_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x), 0x3f )
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_DMA_CCR_EN             BIT_(0)
+#define CYGHWR_HAL_STM32_DMA_CCR_TCIE           BIT_(1)
+#define CYGHWR_HAL_STM32_DMA_CCR_HTIE           BIT_(2)
+#define CYGHWR_HAL_STM32_DMA_CCR_TEIE           BIT_(3)
+#define CYGHWR_HAL_STM32_DMA_CCR_DIR            BIT_(4)
+#define CYGHWR_HAL_STM32_DMA_CCR_CIRC           BIT_(5)
+#define CYGHWR_HAL_STM32_DMA_CCR_PINC           BIT_(6)
+#define CYGHWR_HAL_STM32_DMA_CCR_MINC           BIT_(7)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE8         VALUE_(8,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE16        VALUE_(8,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE32        VALUE_(8,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8         VALUE_(10,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16        VALUE_(10,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32        VALUE_(10,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PL(__x)        VALUE_(12,__x)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLLOW          VALUE_(12,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM       VALUE_(12,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH         VALUE_(12,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLMAX          VALUE_(12,3)
+#define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM        BIT_(14)
+
+// F2/F4 compatibility combinations to control transfer source/dest
+#define CYGHWR_HAL_STM32_DMA_CCR_P2MEM          0
+#define CYGHWR_HAL_STM32_DMA_CCR_MEM2P          CYGHWR_HAL_STM32_DMA_CCR_DIR
+
+// Clock enable bits
+
+#define CYGHWR_HAL_STM32_DMA1_CLOCK             CYGHWR_HAL_STM32_CLOCK( AHB, DMA1 )
+#define CYGHWR_HAL_STM32_DMA2_CLOCK             CYGHWR_HAL_STM32_CLOCK( AHB, DMA2 )
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_DMA_CCR_EN             BIT_(0)
+#define CYGHWR_HAL_STM32_DMA_CCR_DMEIE          BIT_(1)
+#define CYGHWR_HAL_STM32_DMA_CCR_TEIE           BIT_(2)
+#define CYGHWR_HAL_STM32_DMA_CCR_HTIE           BIT_(3)
+#define CYGHWR_HAL_STM32_DMA_CCR_TCIE           BIT_(4)
+#define CYGHWR_HAL_STM32_DMA_CCR_PFCTRL         BIT_(5)
+#define CYGHWR_HAL_STM32_DMA_CCR_P2MEM          VALUE_(6,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_MEM2P          VALUE_(6,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM        VALUE_(6,2)
+
+#define CYGHWR_HAL_STM32_DMA_CCR_CIRC           BIT_(8)
+#define CYGHWR_HAL_STM32_DMA_CCR_PINC           BIT_(9)
+#define CYGHWR_HAL_STM32_DMA_CCR_MINC           BIT_(10)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE8         VALUE_(11,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE16        VALUE_(11,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE32        VALUE_(11,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8         VALUE_(13,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16        VALUE_(13,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32        VALUE_(13,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PINCOS         BIT_(15)
+#define CYGHWR_HAL_STM32_DMA_CCR_PL(__x)        VALUE_(16,__x)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLLOW          VALUE_(16,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM       VALUE_(16,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH         VALUE_(16,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PLMAX          VALUE_(16,3)
+#define CYGHWR_HAL_STM32_DMA_CCR_DBM            BIT_(18)
+#define CYGHWR_HAL_STM32_DMA_CCR_CT             BIT_(19)
+#define CYGHWR_HAL_STM32_DMA_CCR_PBURST1        VALUE_(21,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_PBURST4        VALUE_(21,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_PBURST8        VALUE_(21,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_PBURST16       VALUE_(21,3)
+#define CYGHWR_HAL_STM32_DMA_CCR_MBURST1        VALUE_(23,0)
+#define CYGHWR_HAL_STM32_DMA_CCR_MBURST4        VALUE_(23,1)
+#define CYGHWR_HAL_STM32_DMA_CCR_MBURST8        VALUE_(23,2)
+#define CYGHWR_HAL_STM32_DMA_CCR_MBURST16       VALUE_(23,3)
+#define CYGHWR_HAL_STM32_DMA_CCR_CHSEL(__x)     VALUE_(25,__x)
+
+#define CYGHWR_HAL_STM32_DMA_FCR_FTH_QUARTER    VALUE_(0,0) // FIFO threshold selection
+#define CYGHWR_HAL_STM32_DMA_FCR_FTH_HALF       VALUE_(0,1)
+#define CYGHWR_HAL_STM32_DMA_FCR_FTH_3QUARTER   VALUE_(0,2)
+#define CYGHWR_HAL_STM32_DMA_FCR_FTH_FULL       VALUE_(0,3)
+#define CYGHWR_HAL_STM32_DMA_FCR_DMDIS          BIT_(2)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTQUARTER   VALUE_(3,0) // LT==less than
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTHALF      VALUE_(3,1)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_LT3QUARTER  VALUE_(3,2)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTFULL      VALUE_(3,3)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_EMPTY       VALUE_(3,4)
+#define CYGHWR_HAL_STM32_DMA_FCR_FS_FULL        VALUE_(3,5)
+#define CYGHWR_HAL_STM32_DMA_FCR_FEIE           BIT_(7)
+
+// Clock enable bits
+
+#define CYGHWR_HAL_STM32_DMA1_CLOCK             CYGHWR_HAL_STM32_CLOCK( AHB1, DMA1 )
+#define CYGHWR_HAL_STM32_DMA2_CLOCK             CYGHWR_HAL_STM32_CLOCK( AHB1, DMA2 )
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+//=============================================================================
+// UARTs
+// Include separate header file for this to avoid this header getting unmanageable.
+
+#include <cyg/hal/var_io_usart.h>
+
+//=============================================================================
+// ADCs
+
+#define CYGHWR_HAL_STM32_ADC_SR                 0x00
+#define CYGHWR_HAL_STM32_ADC_CR1                0x04
+#define CYGHWR_HAL_STM32_ADC_CR2                0x08
+#define CYGHWR_HAL_STM32_ADC_SMPR1              0x0C
+#define CYGHWR_HAL_STM32_ADC_SMPR2              0x10
+#define CYGHWR_HAL_STM32_ADC_JOFR(__x)          0x14 + ((__x) << 2)
+#define CYGHWR_HAL_STM32_ADC_HTR                0x24
+#define CYGHWR_HAL_STM32_ADC_LTR                0x28
+#define CYGHWR_HAL_STM32_ADC_SQR1               0x2C
+#define CYGHWR_HAL_STM32_ADC_SQR2               0x30
+#define CYGHWR_HAL_STM32_ADC_SQR3               0x34
+#define CYGHWR_HAL_STM32_ADC_JSQR               0x38
+#define CYGHWR_HAL_STM32_ADC_JDR(__x)           0x3C + ((__x) << 2)
+#define CYGHWR_HAL_STM32_ADC_DR                 0x4C
+
+// SR fields
+
+#define CYGHWR_HAL_STM32_ADC_SR_AWD             BIT_(0)
+#define CYGHWR_HAL_STM32_ADC_SR_EOC             BIT_(1)
+#define CYGHWR_HAL_STM32_ADC_SR_JEOC            BIT_(2)
+#define CYGHWR_HAL_STM32_ADC_SR_JSTRT           BIT_(3)
+#define CYGHWR_HAL_STM32_ADC_SR_STRT            BIT_(4)
+
+// CR1 fields
+
+#define CYGHWR_HAL_STM32_ADC_CR1_AWDCH(__x)     VALUE_(0,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR1_EOCIE          BIT_(5)
+#define CYGHWR_HAL_STM32_ADC_CR1_AWDIE          BIT_(6)
+#define CYGHWR_HAL_STM32_ADC_CR1_JEOCIE         BIT_(7)
+#define CYGHWR_HAL_STM32_ADC_CR1_SCAN           BIT_(8)
+#define CYGHWR_HAL_STM32_ADC_CR1_AWDSGL         BIT_(9)
+#define CYGHWR_HAL_STM32_ADC_CR1_JAUTO          BIT_(10)
+#define CYGHWR_HAL_STM32_ADC_CR1_DISCEN         BIT_(11)
+#define CYGHWR_HAL_STM32_ADC_CR1_JDISCEN        BIT_(12)
+#define CYGHWR_HAL_STM32_ADC_CR1_DISCNUM(__x)   VALUE_(13,(__x))
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_ADC_CR1_DUALMODE(__x)  VALUE_(16,(__x))
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#define CYGHWR_HAL_STM32_ADC_CR1_JAWDEN         BIT_(22)
+#define CYGHWR_HAL_STM32_ADC_CR1_AWDEN          BIT_(23)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_CR1_OVRIE          BIT_(26)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+
+
+// CR2 fields
+
+#define CYGHWR_HAL_STM32_ADC_CR2_ADON           BIT_(0)
+#define CYGHWR_HAL_STM32_ADC_CR2_CONT           BIT_(1)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_ADC_CR2_CAL            BIT_(2)
+#define CYGHWR_HAL_STM32_ADC_CR2_RSTCAL         BIT_(3)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#define CYGHWR_HAL_STM32_ADC_CR2_DMA            BIT_(8)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_CR2_DDS            BIT_(9)
+#define CYGHWR_HAL_STM32_ADC_CR2_EOCS           BIT_(10)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+#define CYGHWR_HAL_STM32_ADC_CR2_ALIGN          BIT_(11)
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_ADC_CR2_JEXTSEL(__x)   VALUE_(12,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_JEXTTRIG       BIT_(15)
+#define CYGHWR_HAL_STM32_ADC_CR2_EXTSEL(__x)    VALUE_(17,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_EXTTRIG        BIT_(20)
+#define CYGHWR_HAL_STM32_ADC_CR2_JSWSTART       BIT_(21)
+#define CYGHWR_HAL_STM32_ADC_CR2_SWSTART        BIT_(22)
+#define CYGHWR_HAL_STM32_ADC_CR2_TSVREFE        BIT_(23)
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_CR2_JEXTSEL(__x)   VALUE_(16,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_JEXTEN(__x)    VALUE_(20,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_JSWSTART       BIT_(22)
+#define CYGHWR_HAL_STM32_ADC_CR2_EXTSEL(__x)    VALUE_(24,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_EXTEN(__x)     VALUE_(28,(__x))
+#define CYGHWR_HAL_STM32_ADC_CR2_SWSTART        BIT_(30)
+#endif
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+// On F1 devices ADC1 and ADC3 have different external event sets for regular groups
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC1       (0)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC2       (1)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC3       (2)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM2_CC2       (3)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM3_TRGO      (4)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM4_CC4       (5)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM8_TRGO      (6) // For high- and XL-density devices
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_SWSTART        (7)
+
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM3_CC1       (0)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM2_CC3       (1)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM1_CC3       (2)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM8_CC1       (3)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM8_TRGO      (4)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM5_CC1       (5)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM5_CC3       (6)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_SWSTART        (7)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC1    (0)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC2    (1)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC3    (2)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC2    (3)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC3    (4)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC4    (5)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_TRGO   (6)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM3_CC1    (7)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM3_TRGO   (8)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM4_CC4    (9)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC1    (10)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC2    (11)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC3    (12)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM8_CC1    (13)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM8_TRGO   (14)
+#define CYGHWR_HAL_STM32_ADC_EXTSEL_EXTI        (15) // line 11
+
+#define CYGHWR_HAL_STM32_ADC_EXTEN_DISABLED     (0)
+#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_RISE    (1)
+#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_FALL    (2)
+#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_BOTH    (3)
+
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+// SMPRx fields
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+// F1 : SMPR1 17..10 : SMPR2 9..0
+#define CYGHWR_HAL_STM32_ADC_SMPR1_NUM_CHANNELS (8)
+#define CYGHWR_HAL_STM32_ADC_SMPR2_NUM_CHANNELS (10)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+// F2/F4 : SMPR1 18..10 : SMPR2 9..0
+#define CYGHWR_HAL_STM32_ADC_SMPR1_NUM_CHANNELS (9)
+#define CYGHWR_HAL_STM32_ADC_SMPR2_NUM_CHANNELS (10)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+#define CYGHWR_HAL_STM32_ADC_SMPRx_SMP(__x, __y) VALUE_((__x) * 3, (__y))
+
+// SQRx fields
+
+#define CYGHWR_HAL_STM32_ADC_SQR1_L(__x)        VALUE_(20, (__x))
+#define CYGHWR_HAL_STM32_ADC_SQRx_SQ(__x, __y)  VALUE_((__x) * 5, (__y))
+
+// JSQR fields
+
+#define CYGHWR_HAL_STM32_ADC_JSQR_SQ(__x, __y)  VALUE_((__x) * 5, (__y))
+
+// ADC GPIO pins
+
+// F1/F2/F4 GPIO inputs have 16 channels (0..15).
+// ADC1 has extra internal sources, which for F1 and HIPERFORMANCE (F2/F4)
+// devices respectively have 18 (0..17) and 19 (0..18) available sources.
+
+// Internal (non-GPIO) channels (ADC1 only):
+// - ADC1_IN16 temperature      F1/F2/F4
+// - ADC1_IN17 Vrefint          F1/F2/F4
+// - ADC1_IN18 Vbat             F2/F4
+
+#define CYGHWR_HAL_STM32_ADC123_IN0             CYGHWR_HAL_STM32_PIN_ANALOG( A, 0 )
+#define CYGHWR_HAL_STM32_ADC123_IN1             CYGHWR_HAL_STM32_PIN_ANALOG( A, 1 )
+#define CYGHWR_HAL_STM32_ADC123_IN2             CYGHWR_HAL_STM32_PIN_ANALOG( A, 2 )
+#define CYGHWR_HAL_STM32_ADC123_IN3             CYGHWR_HAL_STM32_PIN_ANALOG( A, 3 )
+
+#define CYGHWR_HAL_STM32_ADC12_IN4              CYGHWR_HAL_STM32_PIN_ANALOG( A, 4 )
+#define CYGHWR_HAL_STM32_ADC12_IN5              CYGHWR_HAL_STM32_PIN_ANALOG( A, 5 )
+#define CYGHWR_HAL_STM32_ADC12_IN6              CYGHWR_HAL_STM32_PIN_ANALOG( A, 6 )
+#define CYGHWR_HAL_STM32_ADC12_IN7              CYGHWR_HAL_STM32_PIN_ANALOG( A, 7 )
+
+#define CYGHWR_HAL_STM32_ADC12_IN8              CYGHWR_HAL_STM32_PIN_ANALOG( B, 0 )
+#define CYGHWR_HAL_STM32_ADC12_IN9              CYGHWR_HAL_STM32_PIN_ANALOG( B, 1 )
+
+#define CYGHWR_HAL_STM32_ADC3_IN4               CYGHWR_HAL_STM32_PIN_ANALOG( F, 6 )
+#define CYGHWR_HAL_STM32_ADC3_IN5               CYGHWR_HAL_STM32_PIN_ANALOG( F, 7 )
+#define CYGHWR_HAL_STM32_ADC3_IN6               CYGHWR_HAL_STM32_PIN_ANALOG( F, 8 )
+#define CYGHWR_HAL_STM32_ADC3_IN7               CYGHWR_HAL_STM32_PIN_ANALOG( F, 9 )
+#define CYGHWR_HAL_STM32_ADC3_IN8               CYGHWR_HAL_STM32_PIN_ANALOG( F, 10 )
+
+#define CYGHWR_HAL_STM32_ADC123_IN10            CYGHWR_HAL_STM32_PIN_ANALOG( C, 0 )
+#define CYGHWR_HAL_STM32_ADC123_IN11            CYGHWR_HAL_STM32_PIN_ANALOG( C, 1 )
+#define CYGHWR_HAL_STM32_ADC123_IN12            CYGHWR_HAL_STM32_PIN_ANALOG( C, 2 )
+#define CYGHWR_HAL_STM32_ADC123_IN13            CYGHWR_HAL_STM32_PIN_ANALOG( C, 3 )
+
+#define CYGHWR_HAL_STM32_ADC12_IN14             CYGHWR_HAL_STM32_PIN_ANALOG( C, 4 )
+#define CYGHWR_HAL_STM32_ADC12_IN15             CYGHWR_HAL_STM32_PIN_ANALOG( C, 5)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+// Following ADC3 channels not-mapped on F1 devices
+#define CYGHWR_HAL_STM32_ADC3_IN9        CYGHWR_HAL_STM32_GPIO_NONE
+#define CYGHWR_HAL_STM32_ADC3_IN14       CYGHWR_HAL_STM32_GPIO_NONE
+#define CYGHWR_HAL_STM32_ADC3_IN15       CYGHWR_HAL_STM32_GPIO_NONE
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC3_IN9        CYGHWR_HAL_STM32_PIN_ANALOG( F, 3 )
+#define CYGHWR_HAL_STM32_ADC3_IN14       CYGHWR_HAL_STM32_PIN_ANALOG( F, 4 )
+#define CYGHWR_HAL_STM32_ADC3_IN15       CYGHWR_HAL_STM32_PIN_ANALOG( F, 5 )
+#endif
+
+// ADC1 GPIO pin aliases
+
+#define CYGHWR_HAL_STM32_ADC1_IN0               CYGHWR_HAL_STM32_ADC123_IN0
+#define CYGHWR_HAL_STM32_ADC1_IN1               CYGHWR_HAL_STM32_ADC123_IN1
+#define CYGHWR_HAL_STM32_ADC1_IN2               CYGHWR_HAL_STM32_ADC123_IN2
+#define CYGHWR_HAL_STM32_ADC1_IN3               CYGHWR_HAL_STM32_ADC123_IN3
+#define CYGHWR_HAL_STM32_ADC1_IN4               CYGHWR_HAL_STM32_ADC12_IN4
+#define CYGHWR_HAL_STM32_ADC1_IN5               CYGHWR_HAL_STM32_ADC12_IN5
+#define CYGHWR_HAL_STM32_ADC1_IN6               CYGHWR_HAL_STM32_ADC12_IN6
+#define CYGHWR_HAL_STM32_ADC1_IN7               CYGHWR_HAL_STM32_ADC12_IN7
+#define CYGHWR_HAL_STM32_ADC1_IN8               CYGHWR_HAL_STM32_ADC12_IN8
+#define CYGHWR_HAL_STM32_ADC1_IN9               CYGHWR_HAL_STM32_ADC12_IN9
+#define CYGHWR_HAL_STM32_ADC1_IN10              CYGHWR_HAL_STM32_ADC123_IN10
+#define CYGHWR_HAL_STM32_ADC1_IN11              CYGHWR_HAL_STM32_ADC123_IN11
+#define CYGHWR_HAL_STM32_ADC1_IN12              CYGHWR_HAL_STM32_ADC123_IN12
+#define CYGHWR_HAL_STM32_ADC1_IN13              CYGHWR_HAL_STM32_ADC123_IN13
+#define CYGHWR_HAL_STM32_ADC1_IN14              CYGHWR_HAL_STM32_ADC12_IN14
+#define CYGHWR_HAL_STM32_ADC1_IN15              CYGHWR_HAL_STM32_ADC12_IN15
+
+// ADC2 GPIO pin aliases
+
+#define CYGHWR_HAL_STM32_ADC2_IN0               CYGHWR_HAL_STM32_ADC123_IN0
+#define CYGHWR_HAL_STM32_ADC2_IN1               CYGHWR_HAL_STM32_ADC123_IN1
+#define CYGHWR_HAL_STM32_ADC2_IN2               CYGHWR_HAL_STM32_ADC123_IN2
+#define CYGHWR_HAL_STM32_ADC2_IN3               CYGHWR_HAL_STM32_ADC123_IN3
+#define CYGHWR_HAL_STM32_ADC2_IN4               CYGHWR_HAL_STM32_ADC12_IN4
+#define CYGHWR_HAL_STM32_ADC2_IN5               CYGHWR_HAL_STM32_ADC12_IN5
+#define CYGHWR_HAL_STM32_ADC2_IN6               CYGHWR_HAL_STM32_ADC12_IN6
+#define CYGHWR_HAL_STM32_ADC2_IN7               CYGHWR_HAL_STM32_ADC12_IN7
+#define CYGHWR_HAL_STM32_ADC2_IN8               CYGHWR_HAL_STM32_ADC12_IN8
+#define CYGHWR_HAL_STM32_ADC2_IN9               CYGHWR_HAL_STM32_ADC12_IN9
+#define CYGHWR_HAL_STM32_ADC2_IN10              CYGHWR_HAL_STM32_ADC123_IN10
+#define CYGHWR_HAL_STM32_ADC2_IN11              CYGHWR_HAL_STM32_ADC123_IN11
+#define CYGHWR_HAL_STM32_ADC2_IN12              CYGHWR_HAL_STM32_ADC123_IN12
+#define CYGHWR_HAL_STM32_ADC2_IN13              CYGHWR_HAL_STM32_ADC123_IN13
+#define CYGHWR_HAL_STM32_ADC2_IN14              CYGHWR_HAL_STM32_ADC12_IN14
+#define CYGHWR_HAL_STM32_ADC2_IN15              CYGHWR_HAL_STM32_ADC12_IN15
+
+// ADC3 GPIO pin aliases
+
+#define CYGHWR_HAL_STM32_ADC3_IN0               CYGHWR_HAL_STM32_ADC123_IN0
+#define CYGHWR_HAL_STM32_ADC3_IN1               CYGHWR_HAL_STM32_ADC123_IN1
+#define CYGHWR_HAL_STM32_ADC3_IN2               CYGHWR_HAL_STM32_ADC123_IN2
+#define CYGHWR_HAL_STM32_ADC3_IN3               CYGHWR_HAL_STM32_ADC123_IN3
+// Inputs 4 - 9 are already defined
+#define CYGHWR_HAL_STM32_ADC3_IN10              CYGHWR_HAL_STM32_ADC123_IN10
+#define CYGHWR_HAL_STM32_ADC3_IN11              CYGHWR_HAL_STM32_ADC123_IN11
+#define CYGHWR_HAL_STM32_ADC3_IN12              CYGHWR_HAL_STM32_ADC123_IN12
+#define CYGHWR_HAL_STM32_ADC3_IN13              CYGHWR_HAL_STM32_ADC123_IN13
+// Inputs 14 - 15 are already defined
+
+// ADC Clock control pins
+
+#define CYGHWR_HAL_STM32_ADC1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, ADC1 )
+#define CYGHWR_HAL_STM32_ADC2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, ADC2 )
+#define CYGHWR_HAL_STM32_ADC3_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, ADC3 )
+
+// F2/F4 only: Common configuration registers based from CYGHWR_HAL_STM32_ADC_COMMON
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ADC_CSR  0x00
+#define CYGHWR_HAL_STM32_ADC_CCR  0x04
+#define CYGHWR_HAL_STM32_ADC_CDR  0x08
+
+// CSR
+#define CYGHWR_HAL_STM32_ADC_CSR_AWD            BIT_(0)
+#define CYGHWR_HAL_STM32_ADC_CSR_EOC            BIT_(1)
+#define CYGHWR_HAL_STM32_ADC_CSR_JEOC           BIT_(2)
+#define CYGHWR_HAL_STM32_ADC_CSR_JSTRT          BIT_(3)
+#define CYGHWR_HAL_STM32_ADC_CSR_STRT           BIT_(4)
+#define CYGHWR_HAL_STM32_ADC_CSR_OVR            BIT_(5)
+
+#define CYGHWR_HAL_STM32_ADC1_CSR_AWD            CYGHWR_HAL_STM32_ADC_CSR_AWD
+#define CYGHWR_HAL_STM32_ADC1_CSR_EOC            CYGHWR_HAL_STM32_ADC_CSR_EOC
+#define CYGHWR_HAL_STM32_ADC1_CSR_JEOC           CYGHWR_HAL_STM32_ADC_CSR_JEOC
+#define CYGHWR_HAL_STM32_ADC1_CSR_JSTRT          CYGHWR_HAL_STM32_ADC_CSR_JSTRT
+#define CYGHWR_HAL_STM32_ADC1_CSR_STRT           CYGHWR_HAL_STM32_ADC_CSR_STRT
+#define CYGHWR_HAL_STM32_ADC1_CSR_OVR            CYGHWR_HAL_STM32_ADC_CSR_OVR
+
+#define CYGHWR_HAL_STM32_ADC2_CSR_AWD            (CYGHWR_HAL_STM32_ADC_CSR_AWD << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_EOC            (CYGHWR_HAL_STM32_ADC_CSR_EOC << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_JEOC           (CYGHWR_HAL_STM32_ADC_CSR_JEOC << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_JSTRT          (CYGHWR_HAL_STM32_ADC_CSR_JSTRT << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_STRT           (CYGHWR_HAL_STM32_ADC_CSR_STRT << 8)
+#define CYGHWR_HAL_STM32_ADC2_CSR_OVR            (CYGHWR_HAL_STM32_ADC_CSR_OVR << 8)
+
+#define CYGHWR_HAL_STM32_ADC3_CSR_AWD            (CYGHWR_HAL_STM32_ADC_CSR_AWD << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_EOC            (CYGHWR_HAL_STM32_ADC_CSR_EOC << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_JEOC           (CYGHWR_HAL_STM32_ADC_CSR_JEOC << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_JSTRT          (CYGHWR_HAL_STM32_ADC_CSR_JSTRT << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_STRT           (CYGHWR_HAL_STM32_ADC_CSR_STRT << 16)
+#define CYGHWR_HAL_STM32_ADC3_CSR_OVR            (CYGHWR_HAL_STM32_ADC_CSR_OVR << 16)
+
+#define CYGHWR_HAL_STM32_ADC_CSR_ADC1(__csr) ((__csr) >> 0)
+#define CYGHWR_HAL_STM32_ADC_CSR_ADC2(__csr) ((__csr) >> 8)
+#define CYGHWR_HAL_STM32_ADC_CSR_ADC3(__csr) ((__csr) >> 16)
+
+// CCR
+#define CYGHWR_HAL_STM32_ADC_CCR_MULTI_XXX     VALUE_(0,0x1F)
+#define CYGHWR_HAL_STM32_ADC_CCR_DELAY_XXX     VALUE_(8,0xF)
+#define CYGHWR_HAL_STM32_ADC_CCR_DDS           BIT_(13)
+#define CYGHWR_HAL_STM32_ADC_CCR_DMA_XXX       VALUE_(14,0x3)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_2      VALUE_(16,0x0)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_4      VALUE_(16,0x1)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_6      VALUE_(16,0x2)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_8      VALUE_(16,0x3)
+#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_XXX    VALUE_(16,0x3)
+#define CYGHWR_HAL_STM32_ADC_CCR_VBATE         BIT_(22)
+#define CYGHWR_HAL_STM32_ADC_CCR_TSVREFE       BIT_(23)
+
+// CDR
+#define CYGHWR_HAL_STM32_ADC_CDR_DATA1_XXX    VALUE_(0,0xFFFF)
+#define CYGHWR_HAL_STM32_ADC_CDR_DATA2_XXX    VALUE_(16,0xFFFF)
+#endif
+
+//=============================================================================
+// SPI interface register definitions.
+
+#define CYGHWR_HAL_STM32_SPI_CR1                0x00
+#define CYGHWR_HAL_STM32_SPI_CR2                0x04
+#define CYGHWR_HAL_STM32_SPI_SR                 0x08
+#define CYGHWR_HAL_STM32_SPI_DR                 0x0C
+#define CYGHWR_HAL_STM32_SPI_CRCPR              0x10
+#define CYGHWR_HAL_STM32_SPI_RXCRCR             0x14
+#define CYGHWR_HAL_STM32_SPI_TXCRCR             0x18
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR            0x1C
+#define CYGHWR_HAL_STM32_SPI_I2SPR              0x20
+
+#define CYGHWR_HAL_STM32_SPI_CR1_CPHA           BIT_(0)
+#define CYGHWR_HAL_STM32_SPI_CR1_CPOL           BIT_(1)
+#define CYGHWR_HAL_STM32_SPI_CR1_MSTR           BIT_(2)
+#define CYGHWR_HAL_STM32_SPI_CR1_BR(__x)        VALUE_(3,(__x))
+#define CYGHWR_HAL_STM32_SPI_CR1_SPE            BIT_(6)
+#define CYGHWR_HAL_STM32_SPI_CR1_LSBFIRST       BIT_(7)
+#define CYGHWR_HAL_STM32_SPI_CR1_SSI            BIT_(8)
+#define CYGHWR_HAL_STM32_SPI_CR1_SSM            BIT_(9)
+#define CYGHWR_HAL_STM32_SPI_CR1_RXONLY         BIT_(10)
+#define CYGHWR_HAL_STM32_SPI_CR1_DFF            BIT_(11)
+#define CYGHWR_HAL_STM32_SPI_CR1_CRCNEXT        BIT_(12)
+#define CYGHWR_HAL_STM32_SPI_CR1_CRCEN          BIT_(13)
+#define CYGHWR_HAL_STM32_SPI_CR1_BIDIOE         BIT_(14)
+#define CYGHWR_HAL_STM32_SPI_CR1_BIDIMODE       BIT_(15)
+
+#define CYGHWR_HAL_STM32_SPI_CR2_RXDMAEN        BIT_(0)
+#define CYGHWR_HAL_STM32_SPI_CR2_TXDMAEN        BIT_(1)
+#define CYGHWR_HAL_STM32_SPI_CR2_SSOE           BIT_(2)
+#define CYGHWR_HAL_STM32_SPI_CR2_ERRIE          BIT_(5)
+#define CYGHWR_HAL_STM32_SPI_CR2_RXNEIE         BIT_(6)
+#define CYGHWR_HAL_STM32_SPI_CR2_TXEIE          BIT_(7)
+
+#define CYGHWR_HAL_STM32_SPI_SR_RXNE            BIT_(0)
+#define CYGHWR_HAL_STM32_SPI_SR_TXE             BIT_(1)
+#define CYGHWR_HAL_STM32_SPI_SR_CHSIDE          BIT_(2)
+#define CYGHWR_HAL_STM32_SPI_SR_UDR             BIT_(3)
+#define CYGHWR_HAL_STM32_SPI_SR_CRCERR          BIT_(4)
+#define CYGHWR_HAL_STM32_SPI_SR_MODF            BIT_(5)
+#define CYGHWR_HAL_STM32_SPI_SR_OVR             BIT_(6)
+#define CYGHWR_HAL_STM32_SPI_SR_BSY             BIT_(7)
+
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_CHLEN      BIT_(0)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN16   VALUE_(1,0)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN24   VALUE_(1,1)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN32   VALUE_(1,2)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_CKPOL      BIT_(3)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDPHL  VALUE_(4,0)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDMSB  VALUE_(4,1)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDLSB  VALUE_(4,2)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDPCM  VALUE_(4,3)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_PCMSYNC    BIT_(7)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGST   VALUE_(8,0)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGSR   VALUE_(8,1)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGMT   VALUE_(8,2)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGMR   VALUE_(8,3)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SE       BIT_(10)
+#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2MOD      BIT_(11)
+
+#define CYGHWR_HAL_STM32_SPI_I2SPR_I2SDIV(__x)  VALUE_(0,(__x))
+#define CYGHWR_HAL_STM32_SPI_I2SPR_ODD          BIT_(8)
+#define CYGHWR_HAL_STM32_SPI_I2SPR_MCKOE        BIT_(9)
+
+// Clock control definitions for each SPI bus
+
+#define CYGHWR_HAL_STM32_SPI1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, SPI1 )
+#define CYGHWR_HAL_STM32_SPI2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, SPI2 )
+#define CYGHWR_HAL_STM32_SPI3_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, SPI3 )
+
+//=============================================================================
+// I2C busses
+
+#define CYGHWR_HAL_STM32_I2C_CR1                0x00
+#define CYGHWR_HAL_STM32_I2C_CR2                0x04
+#define CYGHWR_HAL_STM32_I2C_OAR1               0x08
+#define CYGHWR_HAL_STM32_I2C_OAR2               0x0C
+#define CYGHWR_HAL_STM32_I2C_DR                 0x10
+#define CYGHWR_HAL_STM32_I2C_SR1                0x14
+#define CYGHWR_HAL_STM32_I2C_SR2                0x18
+#define CYGHWR_HAL_STM32_I2C_CCR                0x1C
+#define CYGHWR_HAL_STM32_I2C_TRISE              0x20
+
+#define CYGHWR_HAL_STM32_I2C_CR1_PE             BIT_(0)
+#define CYGHWR_HAL_STM32_I2C_CR1_SMBUS          BIT_(1)
+#define CYGHWR_HAL_STM32_I2C_CR1_SMBTYPE        BIT_(3)
+#define CYGHWR_HAL_STM32_I2C_CR1_ENARP          BIT_(4)
+#define CYGHWR_HAL_STM32_I2C_CR1_ENPEC          BIT_(5)
+#define CYGHWR_HAL_STM32_I2C_CR1_ENGC           BIT_(6)
+#define CYGHWR_HAL_STM32_I2C_CR1_NOSTRETCH      BIT_(7)
+#define CYGHWR_HAL_STM32_I2C_CR1_START          BIT_(8)
+#define CYGHWR_HAL_STM32_I2C_CR1_STOP           BIT_(9)
+#define CYGHWR_HAL_STM32_I2C_CR1_ACK            BIT_(10)
+#define CYGHWR_HAL_STM32_I2C_CR1_POS            BIT_(11)
+#define CYGHWR_HAL_STM32_I2C_CR1_PEC            BIT_(12)
+#define CYGHWR_HAL_STM32_I2C_CR1_ALERT          BIT_(13)
+#define CYGHWR_HAL_STM32_I2C_CR1_SWRST          BIT_(15)
+
+
+#define CYGHWR_HAL_STM32_I2C_CR2_FREQ(__x)      VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_I2C_CR2_FREQ_MASK      MASK_(0,6)
+#define CYGHWR_HAL_STM32_I2C_CR2_ITERREN        BIT_(8)
+#define CYGHWR_HAL_STM32_I2C_CR2_ITEVTEN        BIT_(9)
+#define CYGHWR_HAL_STM32_I2C_CR2_ITBUFEN        BIT_(10)
+#define CYGHWR_HAL_STM32_I2C_CR2_DMAEN          BIT_(11)
+#define CYGHWR_HAL_STM32_I2C_CR2_LAST           BIT_(12)
+
+// OAR1 and OAR2 omitted, we only support master mode
+
+#define CYGHWR_HAL_STM32_I2C_SR1_SB             BIT_(0)
+#define CYGHWR_HAL_STM32_I2C_SR1_ADDR           BIT_(1)
+#define CYGHWR_HAL_STM32_I2C_SR1_BTF            BIT_(2)
+#define CYGHWR_HAL_STM32_I2C_SR1_ADD10          BIT_(3)
+#define CYGHWR_HAL_STM32_I2C_SR1_STOPF          BIT_(4)
+#define CYGHWR_HAL_STM32_I2C_SR1_RxNE           BIT_(6)
+#define CYGHWR_HAL_STM32_I2C_SR1_TxE            BIT_(7)
+#define CYGHWR_HAL_STM32_I2C_SR1_BERR           BIT_(8)
+#define CYGHWR_HAL_STM32_I2C_SR1_ARLO           BIT_(9)
+#define CYGHWR_HAL_STM32_I2C_SR1_AF             BIT_(10)
+#define CYGHWR_HAL_STM32_I2C_SR1_OVR            BIT_(11)
+#define CYGHWR_HAL_STM32_I2C_SR1_PECERR         BIT_(12)
+#define CYGHWR_HAL_STM32_I2C_SR1_TIMEOUT        BIT_(14)
+#define CYGHWR_HAL_STM32_I2C_SR1_SMBALERT       BIT_(15)
+
+
+#define CYGHWR_HAL_STM32_I2C_SR2_MSL            BIT_(0)
+#define CYGHWR_HAL_STM32_I2C_SR2_BUSY           BIT_(1)
+#define CYGHWR_HAL_STM32_I2C_SR2_TRA            BIT_(2)
+#define CYGHWR_HAL_STM32_I2C_SR2_GENCALL        BIT_(4)
+#define CYGHWR_HAL_STM32_I2C_SR2_SMBDEFAULT     BIT_(5)
+#define CYGHWR_HAL_STM32_I2C_SR2_SMBHOST        BIT_(6)
+#define CYGHWR_HAL_STM32_I2C_SR2_DUALF          BIT_(7)
+#define CYGHWR_HAL_STM32_I2C_SR2_PEC            MASK_(7,8)
+
+#define CYGHWR_HAL_STM32_I2C_CCR_CCR(__x)       VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_I2C_CCR_CCR_MASK       MASK_(0,12)
+#define CYGHWR_HAL_STM32_I2C_CCR_DUTY_2         0
+#define CYGHWR_HAL_STM32_I2C_CCR_DUTY_16_9      BIT_(14)
+#define CYGHWR_HAL_STM32_I2C_CCR_STD            0
+#define CYGHWR_HAL_STM32_I2C_CCR_FAST           BIT_(15)
+
+#define CYGHWR_HAL_STM32_I2C_TRISE_VAL(__x)     VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_I2C_TRISE_MASK         MASK_(0,6)
+
+// Clock control definitions for each I2C bus
+
+#define CYGHWR_HAL_STM32_I2C1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, I2C1 )
+#define CYGHWR_HAL_STM32_I2C2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, I2C2 )
+
+
+//=============================================================================
+// USB interface register definitions.
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_USB_EP0R               0x00
+#define CYGHWR_HAL_STM32_USB_EP1R               0x04
+#define CYGHWR_HAL_STM32_USB_EP2R               0x08
+#define CYGHWR_HAL_STM32_USB_EP3R               0x0C
+#define CYGHWR_HAL_STM32_USB_EP4R               0x10
+#define CYGHWR_HAL_STM32_USB_EP5R               0x14
+#define CYGHWR_HAL_STM32_USB_EP6R               0x18
+#define CYGHWR_HAL_STM32_USB_EP7R               0x1C
+
+#define CYGHWR_HAL_STM32_USB_CNTR               0x40
+#define CYGHWR_HAL_STM32_USB_ISTR               0x44
+#define CYGHWR_HAL_STM32_USB_FNR                0x48
+#define CYGHWR_HAL_STM32_USB_DADDR              0x4C
+#define CYGHWR_HAL_STM32_USB_BTABLE             0x50
+
+// The following macro allows the USB endpoint registers to be indexed as
+// CYGHWR_HAL_STM32_USB_EPXR(0) to CYGHWR_HAL_STM32_USB_EPXR(7).
+#define CYGHWR_HAL_STM32_USB_EPXR(__x)          ((__x)*4)
+
+#define CYGHWR_HAL_STM32_USB_EPXR_EA(__x)       VALUE_(0,(__x))
+#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_DIS    VALUE_(4,0)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_STALL  VALUE_(4,1)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_NAK    VALUE_(4,2)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID  VALUE_(4,3)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK   VALUE_(4,3)
+#define CYGHWR_HAL_STM32_USB_EPXR_DTOGTX        BIT_(6)
+#define CYGHWR_HAL_STM32_USB_EPXR_SWBUFRX       BIT_(6)
+#define CYGHWR_HAL_STM32_USB_EPXR_CTRTX         BIT_(7)
+#define CYGHWR_HAL_STM32_USB_EPXR_EPKIND        BIT_(8)
+#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_BULK   VALUE_(9,0)
+#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_CTRL   VALUE_(9,1)
+#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_ISO    VALUE_(9,2)
+#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_INTR   VALUE_(9,3)
+#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_MASK   VALUE_(9,3)
+#define CYGHWR_HAL_STM32_USB_EPXR_SETUP         BIT_(11)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_DIS    VALUE_(12,0)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_STALL  VALUE_(12,1)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_NAK    VALUE_(12,2)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID  VALUE_(12,3)
+#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK   VALUE_(12,3)
+#define CYGHWR_HAL_STM32_USB_EPXR_DTOGRX        BIT_(14)
+#define CYGHWR_HAL_STM32_USB_EPXR_SWBUFTX       BIT_(14)
+#define CYGHWR_HAL_STM32_USB_EPXR_CTRRX         BIT_(15)
+
+#define CYGHWR_HAL_STM32_USB_CNTR_FRES          BIT_(0)
+#define CYGHWR_HAL_STM32_USB_CNTR_PDWN          BIT_(1)
+#define CYGHWR_HAL_STM32_USB_CNTR_LPMODE        BIT_(2)
+#define CYGHWR_HAL_STM32_USB_CNTR_FSUSP         BIT_(3)
+#define CYGHWR_HAL_STM32_USB_CNTR_RESUME        BIT_(4)
+#define CYGHWR_HAL_STM32_USB_CNTR_ESOFM         BIT_(8)
+#define CYGHWR_HAL_STM32_USB_CNTR_SOFM          BIT_(9)
+#define CYGHWR_HAL_STM32_USB_CNTR_RESETM        BIT_(10)
+#define CYGHWR_HAL_STM32_USB_CNTR_SUSPM         BIT_(11)
+#define CYGHWR_HAL_STM32_USB_CNTR_WKUPM         BIT_(12)
+#define CYGHWR_HAL_STM32_USB_CNTR_ERRM          BIT_(13)
+#define CYGHWR_HAL_STM32_USB_CNTR_PMAOVRM       BIT_(14)
+#define CYGHWR_HAL_STM32_USB_CNTR_CTRM          BIT_(15)
+
+#define CYGHWR_HAL_STM32_USB_ISTR_EPID(__x)     VALUE_(0,(__x))
+#define CYGHWR_HAL_STM32_USB_ISTR_EPID_MASK     MASK_(0,4)
+#define CYGHWR_HAL_STM32_USB_ISTR_DIR           BIT_(4)
+#define CYGHWR_HAL_STM32_USB_ISTR_ESOF          BIT_(8)
+#define CYGHWR_HAL_STM32_USB_ISTR_SOF           BIT_(9)
+#define CYGHWR_HAL_STM32_USB_ISTR_RESET         BIT_(10)
+#define CYGHWR_HAL_STM32_USB_ISTR_SUSP          BIT_(11)
+#define CYGHWR_HAL_STM32_USB_ISTR_WKUP          BIT_(12)
+#define CYGHWR_HAL_STM32_USB_ISTR_ERR           BIT_(13)
+#define CYGHWR_HAL_STM32_USB_ISTR_PMAOVR        BIT_(14)
+#define CYGHWR_HAL_STM32_USB_ISTR_CTR           BIT_(15)
+
+#define CYGHWR_HAL_STM32_USB_FNR_FN_MASK        MASK_(0,11)
+#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF0     VALUE_(11,0)
+#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF1     VALUE_(11,1)
+#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF2     VALUE_(11,2)
+#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOFN     VALUE_(11,3)
+#define CYGHWR_HAL_STM32_USB_FNR_LSOF_MASK      MASK_(11,2)
+#define CYGHWR_HAL_STM32_USB_FNR_LCK            BIT_(13)
+#define CYGHWR_HAL_STM32_USB_FNR_RXDM           BIT_(14)
+#define CYGHWR_HAL_STM32_USB_FNR_RXDP           BIT_(15)
+
+#define CYGHWR_HAL_STM32_USB_DADDR_ADD(__x)     VALUE_(0,(__x))
+#define CYGHWR_HAL_STM32_USB_DADDR_EF           BIT_(7)
+
+#define CYGHWR_HAL_STM32_USB_CLOCK              CYGHWR_HAL_STM32_CLOCK( APB1, USB )
+
+#endif // if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+// USB in F2/F4 parts is completely different. Definitions will be provided when implemented.
+
+//=============================================================================
+// Timers
+//
+// This currently only defines the basic registers and functionality
+// common to all timers.
+
+#define CYGHWR_HAL_STM32_TIM_CR1                0x00
+#define CYGHWR_HAL_STM32_TIM_CR2                0x04
+#define CYGHWR_HAL_STM32_TIM_DIER               0x0C
+#define CYGHWR_HAL_STM32_TIM_SR                 0x10
+#define CYGHWR_HAL_STM32_TIM_EGR                0x14
+#define CYGHWR_HAL_STM32_TIM_CCMR1              0x18
+#define CYGHWR_HAL_STM32_TIM_CCMR2              0x1C
+#define CYGHWR_HAL_STM32_TIM_CCER               0x20
+#define CYGHWR_HAL_STM32_TIM_CNT                0x24
+#define CYGHWR_HAL_STM32_TIM_PSC                0x28
+#define CYGHWR_HAL_STM32_TIM_ARR                0x2C
+#define CYGHWR_HAL_STM32_TIM_CCR1               0x34
+#define CYGHWR_HAL_STM32_TIM_CCR2               0x38
+#define CYGHWR_HAL_STM32_TIM_CCR3               0x3C
+#define CYGHWR_HAL_STM32_TIM_CCR4               0x40
+
+#define CYGHWR_HAL_STM32_TIM_CR1_CEN            BIT_(0)
+#define CYGHWR_HAL_STM32_TIM_CR1_UDIS           BIT_(1)
+#define CYGHWR_HAL_STM32_TIM_CR1_URS            BIT_(2)
+#define CYGHWR_HAL_STM32_TIM_CR1_OPM            BIT_(3)
+#define CYGHWR_HAL_STM32_TIM_CR1_DIR            BIT_(4)
+#define CYGHWR_HAL_STM32_TIM_CR1_ARPE           BIT_(7)
+#define CYGHWR_HAL_STM32_TIM_CR1_CKD_1          VALUE_(8,0)
+#define CYGHWR_HAL_STM32_TIM_CR1_CKD_2          VALUE_(8,1)
+#define CYGHWR_HAL_STM32_TIM_CR1_CKD_4          VALUE_(8,2)
+#define CYGHWR_HAL_STM32_TIM_CR1_CKD_XXX        VALUE_(8,3)
+
+#define CYGHWR_HAL_STM32_TIM_CR2_MMS_RESET      VALUE_(4,0)
+#define CYGHWR_HAL_STM32_TIM_CR2_MMS_ENABLE     VALUE_(4,1)
+#define CYGHWR_HAL_STM32_TIM_CR2_MMS_UPDATE     VALUE_(4,2)
+
+#define CYGHWR_HAL_STM32_TIM_DIER_UIE           BIT_(0)
+#define CYGHWR_HAL_STM32_TIM_DIER_UDE           BIT_(8)
+
+#define CYGHWR_HAL_STM32_TIM_SR_UIF             BIT_(0)
+
+#define CYGHWR_HAL_STM32_TIM_EGR_UG             BIT_(0)
+
+// Clock control pins
+#define CYGHWR_HAL_STM32_TIM1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, TIM1 )
+#define CYGHWR_HAL_STM32_TIM2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM2 )
+#define CYGHWR_HAL_STM32_TIM3_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM3 )
+#define CYGHWR_HAL_STM32_TIM4_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM4 )
+#define CYGHWR_HAL_STM32_TIM5_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM5 )
+#define CYGHWR_HAL_STM32_TIM6_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM6 )
+#define CYGHWR_HAL_STM32_TIM7_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, TIM7 )
+#define CYGHWR_HAL_STM32_TIM8_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, TIM8 )
+#if 0
+#define CYGHWR_HAL_STM32_TIM9_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, TIM9 )
+#define CYGHWR_HAL_STM32_TIM10_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, TIM10 )
+#define CYGHWR_HAL_STM32_TIM11_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, TIM11 )
+#define CYGHWR_HAL_STM32_TIM12_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, TIM12 )
+#define CYGHWR_HAL_STM32_TIM13_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, TIM13 )
+#define CYGHWR_HAL_STM32_TIM14_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, TIM14 )
+#endif
+
+#ifndef __ASSEMBLER__
+
+__externC cyg_uint32 hal_stm32_timer_clock( CYG_ADDRESS base );
+
+#endif
+
+//=============================================================================
+// Independent Watchdog
+
+#define CYGHWR_HAL_STM32_IWDG_KR                0x00
+#define CYGHWR_HAL_STM32_IWDG_PR                0x04
+#define CYGHWR_HAL_STM32_IWDG_RLR               0x08
+#define CYGHWR_HAL_STM32_IWDG_SR                0x0C
+
+#define CYGHWR_HAL_STM32_IWDG_KR_RESET          0xAAAA
+#define CYGHWR_HAL_STM32_IWDG_KR_ACCESS         0x5555
+#define CYGHWR_HAL_STM32_IWDG_KR_START          0xCCCC
+
+#define CYGHWR_HAL_STM32_IWDG_PR_4              0
+#define CYGHWR_HAL_STM32_IWDG_PR_8              1
+#define CYGHWR_HAL_STM32_IWDG_PR_16             2
+#define CYGHWR_HAL_STM32_IWDG_PR_32             3
+#define CYGHWR_HAL_STM32_IWDG_PR_64             4
+#define CYGHWR_HAL_STM32_IWDG_PR_128            5
+#define CYGHWR_HAL_STM32_IWDG_PR_256            6
+
+#define CYGHWR_HAL_STM32_IWDG_SR_PVU            BIT_(0)
+#define CYGHWR_HAL_STM32_IWDG_SR_RVU            BIT_(1)
+
+// Clock control
+
+//#define CYGHWR_HAL_STM32_IWDG_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, IWDG )
+
+
+//=============================================================================
+// Flash controller
+
+#define CYGHWR_HAL_STM32_FLASH_ACR              0x00
+#define CYGHWR_HAL_STM32_FLASH_KEYR             0x04
+#define CYGHWR_HAL_STM32_FLASH_OPTKEYR          0x08
+#define CYGHWR_HAL_STM32_FLASH_SR               0x0C
+#define CYGHWR_HAL_STM32_FLASH_CR               0x10
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_FLASH_AR               0x14
+#define CYGHWR_HAL_STM32_FLASH_OBR              0x1C
+#define CYGHWR_HAL_STM32_FLASH_WRPR             0x20
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_FLASH_OPTCR            0x14
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+// Key values
+
+#define CYGHWR_HAL_STM32_FLASH_KEYR_KEY1        0x45670123
+#define CYGHWR_HAL_STM32_FLASH_KEYR_KEY2        0xCDEF89AB
+
+// ACR fields
+
+#define CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(__x) VALUE_(0,__x)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_FLASH_ACR_HLFCYA       BIT_(3)
+#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTBE       BIT_(4)
+#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTBS       BIT_(5)
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN       BIT_(8)
+#define CYGHWR_HAL_STM32_FLASH_ACR_ICEN         BIT_(9)
+#define CYGHWR_HAL_STM32_FLASH_ACR_DCEN         BIT_(10)
+#define CYGHWR_HAL_STM32_FLASH_ACR_ICRST        BIT_(11)
+#define CYGHWR_HAL_STM32_FLASH_ACR_DCRST        BIT_(12)
+
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+// SR fields
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_FLASH_SR_BSY           BIT_(0)
+#define CYGHWR_HAL_STM32_FLASH_SR_PGERR         BIT_(2)
+#define CYGHWR_HAL_STM32_FLASH_SR_WRPRTERR      BIT_(4)
+#define CYGHWR_HAL_STM32_FLASH_SR_EOP           BIT_(5)
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_FLASH_SR_EOP           BIT_(0)
+#define CYGHWR_HAL_STM32_FLASH_SR_OPERR         BIT_(1)
+#define CYGHWR_HAL_STM32_FLASH_SR_WRPERR        BIT_(4)
+#define CYGHWR_HAL_STM32_FLASH_SR_PGAERR        BIT_(5)
+#define CYGHWR_HAL_STM32_FLASH_SR_PGPERR        BIT_(6)
+#define CYGHWR_HAL_STM32_FLASH_SR_PGSERR        BIT_(7)
+#define CYGHWR_HAL_STM32_FLASH_SR_BSY           BIT_(16)
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+// CR fields
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_FLASH_CR_PG            BIT_(0)
+#define CYGHWR_HAL_STM32_FLASH_CR_PER           BIT_(1)
+#define CYGHWR_HAL_STM32_FLASH_CR_MER           BIT_(2)
+#define CYGHWR_HAL_STM32_FLASH_CR_OPTPG         BIT_(4)
+#define CYGHWR_HAL_STM32_FLASH_CR_OPTER         BIT_(5)
+#define CYGHWR_HAL_STM32_FLASH_CR_STRT          BIT_(6)
+#define CYGHWR_HAL_STM32_FLASH_CR_LOCK          BIT_(7)
+#define CYGHWR_HAL_STM32_FLASH_CR_OPTWRE        BIT_(9)
+#define CYGHWR_HAL_STM32_FLASH_CR_ERRIE         BIT_(10)
+#define CYGHWR_HAL_STM32_FLASH_CR_EOPIE         BIT_(12)
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_FLASH_CR_PG            BIT_(0)
+#define CYGHWR_HAL_STM32_FLASH_CR_SER           BIT_(1)
+#define CYGHWR_HAL_STM32_FLASH_CR_MER           BIT_(2)
+#define CYGHWR_HAL_STM32_FLASH_CR_SNB(__x)      (((__x)&0xf) << 3)
+#define CYGHWR_HAL_STM32_FLASH_CR_SNB_MASK      MASK_(3,4)
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE(__x)    ( (__x) == 8 ? VALUE_(8,0) : \
+                                                  (__x) == 16 ? VALUE_(8,1) : \
+                                                  (__x) == 32 ? VALUE_(8,2) : \
+                                                  VALUE_(8,3) )
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_8       VALUE_(8,0)
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_16      VALUE_(8,1)
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_32      VALUE_(8,2)
+#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_64      VALUE_(8,3)
+#define CYGHWR_HAL_STM32_FLASH_CR_STRT          BIT_(16)
+#define CYGHWR_HAL_STM32_FLASH_CR_EOPIE         BIT_(24)
+#define CYGHWR_HAL_STM32_FLASH_CR_ERRIE         BIT_(25)
+#define CYGHWR_HAL_STM32_FLASH_CR_LOCK          BIT_(31)
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+// OBR fields
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_FLASH_OBR_OPTERR       BIT_(0)
+#define CYGHWR_HAL_STM32_FLASH_OBR_RDPRT        BIT_(1)
+#define CYGHWR_HAL_STM32_FLASH_OBR_WDG_SW       BIT_(2)
+#define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STOP    BIT_(3)
+#define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STDBY   BIT_(4)
+#endif
+
+// F2/F4 FLASH_OPTCR not defined as our flash driver doesn't use it.
+
+//=============================================================================
+// Power control
+
+#define CYGHWR_HAL_STM32_PWR_CR                 0x00
+#define CYGHWR_HAL_STM32_PWR_CSR                0x04
+
+// CR fields
+
+#define CYGHWR_HAL_STM32_PWR_CR_LPDS            BIT_(0)
+#define CYGHWR_HAL_STM32_PWR_CR_PDDS            BIT_(1)
+#define CYGHWR_HAL_STM32_PWR_CR_CWUF            BIT_(2)
+#define CYGHWR_HAL_STM32_PWR_CR_CSBF            BIT_(3)
+#define CYGHWR_HAL_STM32_PWR_CR_PVDE            BIT_(4)
+#define CYGHWR_HAL_STM32_PWR_CR_PLS_XXX         VALUE_(5,7)
+#define CYGHWR_HAL_STM32_PWR_CR_DBP             BIT_(8)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_PWR_CR_FPDS            BIT_(9)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_PWR_CR_VOS             BIT_(14)
+#endif // (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+// CSR fields
+
+#define CYGHWR_HAL_STM32_PWR_CSR_WUF            BIT_(0)
+#define CYGHWR_HAL_STM32_PWR_CSR_SBF            BIT_(1)
+#define CYGHWR_HAL_STM32_PWR_CSR_PVDO           BIT_(2)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_PWR_CSR_BRR            BIT_(3)
+#endif
+#define CYGHWR_HAL_STM32_PWR_CSR_EWUP           BIT_(8)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_PWR_CSR_BRE            BIT_(9)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+#define CYGHWR_HAL_STM32_PWR_CSR_VOSRDY         BIT_(14)
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+// Functions and macros to reset the backup domain as well as
+// enable/disable backup domain write protection.
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_stm32_bd_protect( int protect );
+
+#endif
+
+#define CYGHWR_HAL_STM32_BD_RESET()                                         \
+    CYG_MACRO_START                                                         \
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_RCC_BDCR,        \
+                     CYGHWR_HAL_STM32_RCC_BDCR_BDRST);                      \
+    HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_RCC_BDCR, 0);    \
+    CYG_MACRO_END
+
+#define CYGHWR_HAL_STM32_BD_PROTECT(__protect )                         \
+    hal_stm32_bd_protect( __protect )
+
+//=============================================================================
+// FSMC
+//
+// These registers are usually set up in hal_system_init() using direct
+// binary values. Hence we don't define all the fields here (of which
+// there are many).
+
+#define CYGHWR_HAL_STM32_FSMC_BCR1              0x00
+#define CYGHWR_HAL_STM32_FSMC_BTR1              0x04
+#define CYGHWR_HAL_STM32_FSMC_BCR2              0x08
+#define CYGHWR_HAL_STM32_FSMC_BTR2              0x0C
+#define CYGHWR_HAL_STM32_FSMC_BCR3              0x10
+#define CYGHWR_HAL_STM32_FSMC_BTR3              0x14
+#define CYGHWR_HAL_STM32_FSMC_BCR4              0x18
+#define CYGHWR_HAL_STM32_FSMC_BTR4              0x1C
+
+#define CYGHWR_HAL_STM32_FSMC_BWTR1             0x104
+#define CYGHWR_HAL_STM32_FSMC_BWTR2             0x10C
+#define CYGHWR_HAL_STM32_FSMC_BWTR3             0x114
+#define CYGHWR_HAL_STM32_FSMC_BWTR4             0x11C
+
+#define CYGHWR_HAL_STM32_FSMC_PCR2              0x60
+#define CYGHWR_HAL_STM32_FSMC_SR2               0x64
+#define CYGHWR_HAL_STM32_FSMC_PMEM2             0x68
+#define CYGHWR_HAL_STM32_FSMC_PATT2             0x6C
+#define CYGHWR_HAL_STM32_FSMC_ECCR2             0x74
+
+#define CYGHWR_HAL_STM32_FSMC_PCR3              0x80
+#define CYGHWR_HAL_STM32_FSMC_SR3               0x84
+#define CYGHWR_HAL_STM32_FSMC_PMEM3             0x88
+#define CYGHWR_HAL_STM32_FSMC_PATT3             0x8C
+#define CYGHWR_HAL_STM32_FSMC_ECCR3             0x94
+
+#define CYGHWR_HAL_STM32_FSMC_PCR4              0xA0
+#define CYGHWR_HAL_STM32_FSMC_SR4               0xA4
+#define CYGHWR_HAL_STM32_FSMC_PMEM4             0xA8
+#define CYGHWR_HAL_STM32_FSMC_PATT4             0xAC
+
+#define CYGHWR_HAL_STM32_FSMC_PIO4              0xB0
+
+#define CYGHWR_HAL_STM32_FSMC_BANK1_BASE        0x60000000
+#define CYGHWR_HAL_STM32_FSMC_BANK2_BASE        0x70000000
+#define CYGHWR_HAL_STM32_FSMC_BANK3_BASE        0x80000000
+#define CYGHWR_HAL_STM32_FSMC_BANK4_BASE        0x90000000
+
+#define CYGHWR_HAL_STM32_FSMC_BANK_CMD          0x10000
+#define CYGHWR_HAL_STM32_FSMC_BANK_ADDR         0x20000
+
+// PCR fields
+
+#define CYGHWR_HAL_STM32_FSMC_PCR_PWAITEN       BIT_(1)
+#define CYGHWR_HAL_STM32_FSMC_PCR_PBKEN         BIT_(2)
+#define CYGHWR_HAL_STM32_FSMC_PCR_PTYP_NAND     BIT_(3)
+#define CYGHWR_HAL_STM32_FSMC_PCR_PWID_8        VALUE_(4,0)
+#define CYGHWR_HAL_STM32_FSMC_PCR_PWID_16       VALUE_(4,1)
+#define CYGHWR_HAL_STM32_FSMC_PCR_ECCEN         BIT_(6)
+// FIXME: I don't see where ADLOW comes from? It's not in F1, F2 or F4. -Jifl
+#define CYGHWR_HAL_STM32_FSMC_PCR_ADLOW         BIT_(8)
+#define CYGHWR_HAL_STM32_FSMC_PCR_TCLR(__x)     VALUE_(9,__x)
+#define CYGHWR_HAL_STM32_FSMC_PCR_TAR(__x)      VALUE_(13,__x)
+#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_256     VALUE_(17,0)
+#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_512     VALUE_(17,1)
+#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_1024    VALUE_(17,2)
+#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_2048    VALUE_(17,3)
+#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_4096    VALUE_(17,4)
+#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_8192    VALUE_(17,5)
+
+// SR fields
+
+#define CYGHWR_HAL_STM32_FSMC_SR_IRS            BIT_(0)
+#define CYGHWR_HAL_STM32_FSMC_SR_ILS            BIT_(1)
+#define CYGHWR_HAL_STM32_FSMC_SR_IFS            BIT_(2)
+#define CYGHWR_HAL_STM32_FSMC_SR_IREN           BIT_(3)
+#define CYGHWR_HAL_STM32_FSMC_SR_ILEN           BIT_(4)
+#define CYGHWR_HAL_STM32_FSMC_SR_IFEN           BIT_(5)
+#define CYGHWR_HAL_STM32_FSMC_SR_FEMPT          BIT_(6)
+
+//=============================================================================
+// CAN
+//
+
+#define CYGHWR_HAL_STM32_CAN1_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, CAN1 )
+#define CYGHWR_HAL_STM32_CAN2_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB1, CAN2 )
+
+
+//=============================================================================
+// Ethernet MAC
+// Include separate header file for this to avoid this header getting unmanageable.
+
+#include <cyg/hal/var_io_eth.h>
+
+//==========================================================================
+
+#if (defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RC) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VC) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZC) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RD) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VD) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZD) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RE) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VE) || \
+     defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZE))
+// NOTE: From ST document ES0104 (STM32F101xC/D/E and STM32F103xC/D/E)
+// errata section 2.6.9 we cannot use FSMC and I2C1 at the same time.
+// For I2C1 support we are limited to on-chip SRAM/Flash execution and
+// must ensure that FSMC is disabled.
+# if (defined(CYG_HAL_STARTUP_SRAM) || \
+      defined(CYG_HAL_STARTUP_ROM) || \
+      defined(CYG_HAL_STARTUP_JTAG))
+#  define HAL_AARDVARK_CHECK_I2C( _i2cdev_ )                                   \
+     CYG_MACRO_START                                                           \
+     if ((_i2cdev_)->i2c_bus == &hal_stm32_i2c_bus1) {                         \
+         CYGHWR_HAL_STM32_CLOCK_DISABLE( CYGHWR_HAL_STM32_CLOCK( AHB, FSMC) ); \
+     }                                                                         \
+     CYG_MACRO_END
+# else // on this CPU we cannot use I2C1 since FSMC needed for the CYG_HAL_STARTUP type
+#  define HAL_AARDVARK_CHECK_I2C( _i2cdev_ )                                  \
+     CYG_MACRO_START                                                          \
+     if ((_i2cdev_)->i2c_bus == &hal_stm32_i2c_bus1) {                        \
+         CYG_TEST_FAIL_FINISH("Invalid CYG_HAL_STARTUP for I2C1 operations"); \
+     }                                                                        \
+     CYG_MACRO_END
+# endif
+#endif
+
+//==========================================================================
+
+#endif // CYGONCE_HAL_VAR_IO_H
+//-----------------------------------------------------------------------------
+// end of var_io.h
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h
new file mode 100644
index 0000000..a5ab5fa
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h
@@ -0,0 +1,490 @@
+#ifndef CYGONCE_HAL_VAR_IO_ETH_H
+#define CYGONCE_HAL_VAR_IO_ETH_H
+//=============================================================================
+//
+//      var_io_eth.h
+//
+//      Ethernet-specific variant definitions
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, jlarmour
+// Date:        2008-07-30
+// Purpose:     STM32 variant ETH specific registers
+// Description:
+// Usage:       Do not include this header file directly. Instead:
+//              #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#ifndef CYGONCE_HAL_VAR_IO_H
+# error Do not include var_io_eth.h directly, use var_io.h
+#endif
+
+
+//=============================================================================
+// Ethernet MAC
+//
+// Connectivity devices only
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+
+#define CYGHWR_HAL_STM32_ETH_MACCR              0x0000
+#define CYGHWR_HAL_STM32_ETH_MACFFR             0x0004
+#define CYGHWR_HAL_STM32_ETH_MACHTHR            0x0008
+#define CYGHWR_HAL_STM32_ETH_MACHTLR            0x000C
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR           0x0010
+#define CYGHWR_HAL_STM32_ETH_MACMIIDR           0x0014
+#define CYGHWR_HAL_STM32_ETH_MACFCR             0x0018
+#define CYGHWR_HAL_STM32_ETH_MACVLANTR          0x001C
+#define CYGHWR_HAL_STM32_ETH_MACRWUFFR          0x0028
+#define CYGHWR_HAL_STM32_ETH_MACPMTCSR          0x002C
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_MACDBGR            0x0034
+#endif
+#define CYGHWR_HAL_STM32_ETH_MACSR              0x0038
+#define CYGHWR_HAL_STM32_ETH_MACIMR             0x003C
+#define CYGHWR_HAL_STM32_ETH_MACA0HR            0x0040
+#define CYGHWR_HAL_STM32_ETH_MACA0LR            0x0044
+#define CYGHWR_HAL_STM32_ETH_MACA1HR            0x0048
+#define CYGHWR_HAL_STM32_ETH_MACA1LR            0x004C
+#define CYGHWR_HAL_STM32_ETH_MACA2HR            0x0050
+#define CYGHWR_HAL_STM32_ETH_MACA2LR            0x0054
+#define CYGHWR_HAL_STM32_ETH_MACA3HR            0x0058
+#define CYGHWR_HAL_STM32_ETH_MACA3LR            0x005C
+
+#define CYGHWR_HAL_STM32_ETH_MMCCR              0x0100
+#define CYGHWR_HAL_STM32_ETH_MMCRIR             0x0104
+#define CYGHWR_HAL_STM32_ETH_MMCTIR             0x0108
+#define CYGHWR_HAL_STM32_ETH_MMCRIMR            0x010C
+#define CYGHWR_HAL_STM32_ETH_MMCTIMR            0x0110
+#define CYGHWR_HAL_STM32_ETH_MMCTGFSCCR         0x014C
+#define CYGHWR_HAL_STM32_ETH_MMCTGFMSCCR        0x0150
+#define CYGHWR_HAL_STM32_ETH_MMCTGFCR           0x0168
+#define CYGHWR_HAL_STM32_ETH_MMCRFCECR          0x0194
+#define CYGHWR_HAL_STM32_ETH_MMCRFAECR          0x0198
+#define CYGHWR_HAL_STM32_ETH_MMCRGUFCR          0x01C4
+
+#define CYGHWR_HAL_STM32_ETH_PTPTSCR            0x0700
+#define CYGHWR_HAL_STM32_ETH_PTPSSIR            0x0704
+#define CYGHWR_HAL_STM32_ETH_PTPTSHR            0x0708
+#define CYGHWR_HAL_STM32_ETH_PTPTSLR            0x070C
+#define CYGHWR_HAL_STM32_ETH_PTPTSHUR           0x0710
+#define CYGHWR_HAL_STM32_ETH_PTPTSLUR           0x0714
+#define CYGHWR_HAL_STM32_ETH_PTPTSAR            0x0718
+#define CYGHWR_HAL_STM32_ETH_PTPTTHR            0x071C
+#define CYGHWR_HAL_STM32_ETH_PTPTTLR            0x0720
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_PTPTSSR            0x0728
+#endif
+
+#define CYGHWR_HAL_STM32_ETH_DMABMR             0x1000
+#define CYGHWR_HAL_STM32_ETH_DMATPDR            0x1004
+#define CYGHWR_HAL_STM32_ETH_DMARPDR            0x1008
+#define CYGHWR_HAL_STM32_ETH_DMARDLAR           0x100C
+#define CYGHWR_HAL_STM32_ETH_DMATDLAR           0x1010
+#define CYGHWR_HAL_STM32_ETH_DMASR              0x1014
+#define CYGHWR_HAL_STM32_ETH_DMAOMR             0x1018
+#define CYGHWR_HAL_STM32_ETH_DMAIER             0x101C
+#define CYGHWR_HAL_STM32_ETH_DMAMFBOCR          0x1020
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_DMARSWTR           0x1024
+#endif
+#define CYGHWR_HAL_STM32_ETH_DMACHTDR           0x1048
+#define CYGHWR_HAL_STM32_ETH_DMACHRDR           0x104C
+#define CYGHWR_HAL_STM32_ETH_DMACHTBAR          0x1050
+#define CYGHWR_HAL_STM32_ETH_DMACHRBAR          0x1054
+
+// MACCR
+
+#define CYGHWR_HAL_STM32_ETH_MACCR_RE           BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_MACCR_TE           BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_MACCR_DC           BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_MACCR_BL(__x)      VALUE_(6, __x)
+#define CYGHWR_HAL_STM32_ETH_MACCR_APCS         BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_MACCR_RD           BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_MACCR_IPCO         BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_MACCR_DM           BIT_(11)
+#define CYGHWR_HAL_STM32_ETH_MACCR_LM           BIT_(12)
+#define CYGHWR_HAL_STM32_ETH_MACCR_ROD          BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_MACCR_FES          BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_MACCR_CSD          BIT_(16)
+#define CYGHWR_HAL_STM32_ETH_MACCR_IFG(__x)     VALUE_(17, (96-(__x))/8 )
+#define CYGHWR_HAL_STM32_ETH_MACCR_JD           BIT_(22)
+#define CYGHWR_HAL_STM32_ETH_MACCR_WD           BIT_(23)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_MACCR_CSTF         BIT_(25)
+#endif
+
+// MACFFR
+
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PM          BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_HU          BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_HM          BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_DAIF        BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PAM         BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_BFD         BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_BLOCK   VALUE_(6,0)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_NOPAUSE VALUE_(6,1)
+#endif
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_ALL     VALUE_(6,2)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_FILTER  VALUE_(6,3)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_SAIF        BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_SAF         BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_HPF         BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_MACFFR_RA          BIT_(31)
+
+// MACHT* omitted
+
+// MACMIIAR
+
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MB        BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MW        BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(__x)   VALUE_(2,__x)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MASK   MASK_(2,4)
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 72)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2)
+# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 120)
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
+# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 168)
+#endif
+// This macro is shared between F1/F2/F4 families for now (despite
+// irrelevance for >72Mhz speed, but that's checked above) but it's
+// foreseeable that this could change for future products.
+# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ(_mhz)  (          \
+  ((_mhz) >= 150) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(4) :       \
+  ((_mhz) >= 100) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(1) :       \
+  ((_mhz) >= 60)  ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(0) :       \
+  ((_mhz) >= 35)  ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(3) :       \
+  /*((_mhz) >= 20)  ?*/ CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(2))
+
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MR(__x)   VALUE_(6,__x)
+#define CYGHWR_HAL_STM32_ETH_MACMIIAR_PA(__x)   VALUE_(11,__x)
+
+// MACFCR omitted
+// MACVLANTR omitted
+// MACRWUFFR omitted
+// MACPMTCSR omitted
+// MACDBGR (F2/F4 only) omitted
+
+// MACSR
+
+#define CYGHWR_HAL_STM32_ETH_MACSR_PMTS         BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_MACSR_MMCS         BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_MACSR_MMCRS        BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_MACSR_MMCTS        BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_MACSR_TSTS         BIT_(9)
+
+// MACIMR
+
+#define CYGHWR_HAL_STM32_ETH_MACIMR_PMTIM       BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_MACIMR_TSTIM       BIT_(9)
+
+// MMCR
+
+#define CYGHWR_HAL_STM32_ETH_MMCCR_CR           BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_CSR          BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_ROR          BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_MCF          BIT_(3)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_MCP          BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_MMCCR_MCFHP        BIT_(5)
+#endif
+
+// MMCRIR & MMCRIMR
+
+#define CYGHWR_HAL_STM32_ETH_MMCRIR_RFCES       BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_MMCRIR_RFAES       BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_MMCRIR_RGUFS       BIT_(17)
+
+// MMCTIR & MMCTIMR
+
+#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFSCS      BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFMSCS     BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFS        BIT_(21)
+
+// PTP* omitted
+
+// DMABMR
+
+#define CYGHWR_HAL_STM32_ETH_DMABMR_SR          BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_DA          BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_DSL(__x)    VALUE_(2,__x)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_PBL(__x)    VALUE_(8,__x)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_RTPR(__x)   VALUE_(14,(__x)-1)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_FB          BIT_(16)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_RDP(__x)    VALUE_(17,__x)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_USP         BIT_(23)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_FPM         BIT_(24)
+#define CYGHWR_HAL_STM32_ETH_DMABMR_AAB         BIT_(25)
+
+//DMASR
+
+#define CYGHWR_HAL_STM32_ETH_DMASR_TS           BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TPSS         BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TBUS         BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TJTS         BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_DMASR_ROS          BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TUS          BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RS           BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RBUS         BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RPSS         BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RWTS         BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_DMASR_ETS          BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_DMASR_FBES         BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_DMASR_ERS          BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_DMASR_AIS          BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_DMASR_NIS          BIT_(16)
+#define CYGHWR_HAL_STM32_ETH_DMASR_RPS          MASK_(17,3)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TPS          MASK_(20,3)
+#define CYGHWR_HAL_STM32_ETH_DMASR_EBS          MASK_(23,3)
+#define CYGHWR_HAL_STM32_ETH_DMASR_MMCS         BIT_(27)
+#define CYGHWR_HAL_STM32_ETH_DMASR_PMTS         BIT_(28)
+#define CYGHWR_HAL_STM32_ETH_DMASR_TSTS         BIT_(29)
+
+// DMAOMR
+
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_SR          BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_OSF         BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_RTC(__x)    VALUE_(3,__x)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_FUGF        BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_FEF         BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_ST          BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_TTC(__x)    VALUE_(14,__x)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_FTF         BIT_(20)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_TSF         BIT_(21)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_DFRF        BIT_(24)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_RSF         BIT_(25)
+#define CYGHWR_HAL_STM32_ETH_DMAOMR_DTCEFD      BIT_(26)
+
+// DMAIER
+
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TIE         BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TPSIE       BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TBUIE       BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TJTIE       BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_ROIE        BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_TUIE        BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_RIE         BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_RBUIE       BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_RPSIE       BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_RWTIE       BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_ETIE        BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_FBEIE       BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_ERIE        BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_AISE        BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_DMAIER_NISE        BIT_(16)
+
+// DMAFBOCR omitted
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC_MASK   MASK_(0,8)
+#define CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC(__x)   ((__x)& CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC_MASK)
+#endif
+
+// Transmit descriptor fields
+
+/*
+-----------------------------------------------------------------------
+TDES0|OWN(31)|CTRL[30:26]|Res[25:24]|CTRL[23:20]|Res[19:17]|Stat[16:0]|
+-----------------------------------------------------------------------
+TDES1|Res[31:29]| Buffer2 Len[28:16] | Res[15:13] | Buffer1 Len[12:0] |
+-----------------------------------------------------------------------
+TDES2|               Buffer1 Address [31:0]                           |
+-----------------------------------------------------------------------
+TDES3|               Buffer2 Address [31:0]                           |
+-----------------------------------------------------------------------
+*/
+
+// TDES0 register: DMA Tx descriptor status
+
+#define CYGHWR_HAL_STM32_ETH_TDES0_DB           BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_TDES0_UF           BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_TDES0_ED           BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CC           MASK_(3,4)
+#define CYGHWR_HAL_STM32_ETH_TDES0_VF           BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_TDES0_EC           BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_TDES0_LCO          BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_TDES0_NC           BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_TDES0_LCA          BIT_(11)
+#define CYGHWR_HAL_STM32_ETH_TDES0_IPE          BIT_(12)
+#define CYGHWR_HAL_STM32_ETH_TDES0_FF           BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_TDES0_JT           BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_TDES0_ES           BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_TDES0_IHE          BIT_(16)
+#define CYGHWR_HAL_STM32_ETH_TDES0_TTSS         BIT_(17)
+#define CYGHWR_HAL_STM32_ETH_TDES0_TCH          BIT_(20)
+#define CYGHWR_HAL_STM32_ETH_TDES0_TER          BIT_(21)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_DISA     VALUE_(22,0)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_H        VALUE_(22,1)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_HP       VALUE_(22,2)
+#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_HPP      VALUE_(22,3)
+#define CYGHWR_HAL_STM32_ETH_TDES0_TTSE         BIT_(25)
+#define CYGHWR_HAL_STM32_ETH_TDES0_DP           BIT_(26)
+#define CYGHWR_HAL_STM32_ETH_TDES0_DC           BIT_(27)
+#define CYGHWR_HAL_STM32_ETH_TDES0_FS           BIT_(28)
+#define CYGHWR_HAL_STM32_ETH_TDES0_LS           BIT_(29)
+#define CYGHWR_HAL_STM32_ETH_TDES0_IC           BIT_(30)
+#define CYGHWR_HAL_STM32_ETH_TDES0_OWN          BIT_(31)
+
+#define CYGHWR_HAL_STM32_ETH_TDES1_TBS1(__x)    (VALUE_(0,__x)&0x00001FFF)
+#define CYGHWR_HAL_STM32_ETH_TDES1_TBS2(__x)    (VALUE_(16,__x)&0x1FFF0000)
+
+// Receive descriptor fields
+
+/*
+-----------------------------------------------------------------------
+RDES0| OWN(31) |                Status [30:0]                         |
+-----------------------------------------------------------------------
+RDES1|DIC(31)|Res[30:29]|Not Used|CTRL[15:14]|Res(13)|Buffer Len[12:0]|
+-----------------------------------------------------------------------
+RDES2|                Buffer1 Address [31:0]                          |
+-----------------------------------------------------------------------
+RDES3|                      Not Used                                  |
+-----------------------------------------------------------------------
+*/
+
+// RDES0 register: DMA Rx descriptor status
+
+#define CYGHWR_HAL_STM32_ETH_RDES0_PCE          BIT_(0)
+#define CYGHWR_HAL_STM32_ETH_RDES0_CE           BIT_(1)
+#define CYGHWR_HAL_STM32_ETH_RDES0_DE           BIT_(2)
+#define CYGHWR_HAL_STM32_ETH_RDES0_RE           BIT_(3)
+#define CYGHWR_HAL_STM32_ETH_RDES0_RWT          BIT_(4)
+#define CYGHWR_HAL_STM32_ETH_RDES0_FT           BIT_(5)
+#define CYGHWR_HAL_STM32_ETH_RDES0_LCO          BIT_(6)
+#define CYGHWR_HAL_STM32_ETH_RDES0_IPHCE        BIT_(7)
+#define CYGHWR_HAL_STM32_ETH_RDES0_LS           BIT_(8)
+#define CYGHWR_HAL_STM32_ETH_RDES0_FS           BIT_(9)
+#define CYGHWR_HAL_STM32_ETH_RDES0_VLAN         BIT_(10)
+#define CYGHWR_HAL_STM32_ETH_RDES0_OE           BIT_(11)
+#define CYGHWR_HAL_STM32_ETH_RDES0_LE           BIT_(12)
+#define CYGHWR_HAL_STM32_ETH_RDES0_SAF          BIT_(13)
+#define CYGHWR_HAL_STM32_ETH_RDES0_DESCE        BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_RDES0_ES           BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_RDES0_FL(__x)      (((__x)>>16)&0x3FFF)
+#define CYGHWR_HAL_STM32_ETH_RDES0_AFM          BIT_(30)
+#define CYGHWR_HAL_STM32_ETH_RDES0_OWN          BIT_(31)
+
+// RDES1 register : DMA Rx descriptor control and buffer length
+
+#define CYGHWR_HAL_STM32_ETH_RDES1_RBS1(__x)    VALUE_(0,__x)
+#define CYGHWR_HAL_STM32_ETH_RDES1_RCH          BIT_(14)
+#define CYGHWR_HAL_STM32_ETH_RDES1_RER          BIT_(15)
+#define CYGHWR_HAL_STM32_ETH_RDES1_RBS2(__x)    VALUE_(16,__x)
+
+
+// GPIO pins
+
+// NOTE: The platform specific (re-)mapping of pins is provided in the relevant
+// target specific "plf_io.h" header file. These definitions just cover the
+// fixed mappings.
+
+// MCO1 clock to PHY
+#define CYGHWR_HAL_STM32_ETH_MCO                CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  8,  0, PUSHPULL,  NONE,     AT_LEAST(50) )
+
+// MII interface
+#define CYGHWR_HAL_STM32_ETH_MII_MDC            CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C,  1, 11, PUSHPULL,  NONE,     AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD2           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C,  2, 11, PUSHPULL,  NONE,     AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_MDIO           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  2, 11, PUSHPULL,  NONE,     AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TX_CLK         CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C,  3, 11, OPENDRAIN, FLOATING )
+#define CYGHWR_HAL_STM32_ETH_MII_RX_CLK         CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  1, 11, OPENDRAIN, FLOATING )
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+// MII interface
+#define CYGHWR_HAL_STM32_ETH_MII_TX_CRS         CYGHWR_HAL_STM32_PIN_IN( A,  0, FLOATING )
+#define CYGHWR_HAL_STM32_ETH_MII_COL            CYGHWR_HAL_STM32_PIN_IN( A,  3, FLOATING )
+#define CYGHWR_HAL_STM32_ETH_MII_RX_ER          CYGHWR_HAL_STM32_PIN_IN( B, 10, FLOATING )
+
+#define CYGHWR_HAL_STM32_ETH_MII_TX_EN          CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, 11, PUSHPULL, NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD0           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 12, 11, PUSHPULL, NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD1           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 13, 11, PUSHPULL, NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_PPS_OUT        CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  5, 11, PUSHPULL, NONE, AT_LEAST(50) )
+#define CYGHWR_HAL_STM32_ETH_MII_TXD3           CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  8, 11, PUSHPULL, NONE, AT_LEAST(50) )
+
+// RMII interface
+#define CYGHWR_HAL_STM32_ETH_RMII_MDC           CYGHWR_HAL_STM32_ETH_MII_MDC
+#define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK       CYGHWR_HAL_STM32_ETH_MII_RX_CLK
+#define CYGHWR_HAL_STM32_ETH_RMII_MDIO          CYGHWR_HAL_STM32_ETH_MII_MDIO
+#define CYGHWR_HAL_STM32_ETH_RMII_TX_EN         CYGHWR_HAL_STM32_ETH_MII_TX_EN
+#define CYGHWR_HAL_STM32_ETH_RMII_TXD0          CYGHWR_HAL_STM32_ETH_MII_TXD0
+#define CYGHWR_HAL_STM32_ETH_RMII_TXD1          CYGHWR_HAL_STM32_ETH_MII_TXD1
+#define CYGHWR_HAL_STM32_ETH_RMII_PPS_OUT       CYGHWR_HAL_STM32_ETH_MII_PPS_OUT
+
+// Clock controls
+
+#define CYGHWR_HAL_STM32_ETH_MAC_CLOCK          CYGHWR_HAL_STM32_CLOCK( AHB, ETHMAC )
+#define CYGHWR_HAL_STM32_ETH_TX_CLOCK           CYGHWR_HAL_STM32_CLOCK( AHB, ETHMACTX )
+#define CYGHWR_HAL_STM32_ETH_RX_CLOCK           CYGHWR_HAL_STM32_CLOCK( AHB, ETHMACRX )
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+// MII interface
+#define CYGHWR_HAL_STM32_ETH_MII_RX_DV          CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  7, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_RXD0           CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C,  4, 11, OPENDRAIN, NONE )
+#define CYGHWR_HAL_STM32_ETH_MII_RXD1           CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C,  5, 11, OPENDRAIN, NONE )
+
+// RMII interface
+#define CYGHWR_HAL_STM32_ETH_RMII_MDC           CYGHWR_HAL_STM32_ETH_MII_MDC
+#define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK       CYGHWR_HAL_STM32_ETH_MII_RX_CLK
+#define CYGHWR_HAL_STM32_ETH_RMII_MDIO          CYGHWR_HAL_STM32_ETH_MII_MDIO
+#define CYGHWR_HAL_STM32_ETH_RMII_CRS_DV        CYGHWR_HAL_STM32_ETH_MII_RX_DV
+#define CYGHWR_HAL_STM32_ETH_RMII_RXD0          CYGHWR_HAL_STM32_ETH_MII_RXD0
+#define CYGHWR_HAL_STM32_ETH_RMII_RXD1          CYGHWR_HAL_STM32_ETH_MII_RXD1
+#define CYGHWR_HAL_STM32_ETH_RMII_TX_EN         CYGHWR_HAL_STM32_ETH_MII_TX_EN
+#define CYGHWR_HAL_STM32_ETH_RMII_TXD0          CYGHWR_HAL_STM32_ETH_MII_TXD0
+#define CYGHWR_HAL_STM32_ETH_RMII_TXD1          CYGHWR_HAL_STM32_ETH_MII_TXD1
+#define CYGHWR_HAL_STM32_ETH_RMII_PPS_OUT       CYGHWR_HAL_STM32_ETH_MII_PPS_OUT
+
+// Clock controls
+
+#define CYGHWR_HAL_STM32_ETH_MAC_CLOCK          CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMAC )
+#define CYGHWR_HAL_STM32_ETH_TX_CLOCK           CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMACTX )
+#define CYGHWR_HAL_STM32_ETH_RX_CLOCK           CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMACRX )
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#endif // CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+
+#endif // CYGONCE_HAL_VAR_IO_ETH_H
+//-----------------------------------------------------------------------------
+// end of var_io_eth.h
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h
new file mode 100644
index 0000000..5ec9986
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h
@@ -0,0 +1,502 @@
+#ifndef CYGONCE_HAL_VAR_IO_PINS_H
+#define CYGONCE_HAL_VAR_IO_PINS_H
+//=============================================================================
+//
+//      var_io_pins.h
+//
+//      Pin configuration and GPIO definitions
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, jlarmour
+// Date:        2011-11-29
+// Purpose:     STM32 variant GPIO and pin configuration specific registers
+// Description: 
+// Usage:       Do not include this header file directly. Instead:
+//              #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#ifndef CYGONCE_HAL_VAR_IO_H
+# error Do not include var_io_pins.h directly, use var_io.h
+#endif
+
+//=============================================================================
+// GPIO ports - common manifests
+
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_NA (0) // Convenience define for ease of pin definitions (for F1 actually marks MODE as INPUT)
+
+//=============================================================================
+// GPIO ports - F1 family
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_GPIO_CRL               0x00
+#define CYGHWR_HAL_STM32_GPIO_CRH               0x04
+#define CYGHWR_HAL_STM32_GPIO_IDR               0x08
+#define CYGHWR_HAL_STM32_GPIO_ODR               0x0C
+#define CYGHWR_HAL_STM32_GPIO_BSRR              0x10
+#define CYGHWR_HAL_STM32_GPIO_BRR               0x14
+#define CYGHWR_HAL_STM32_GPIO_LCKR              0x18
+
+#define CYGHWR_HAL_STM32_GPIO_MODE_IN           VALUE_(0,0)     // Input mode
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ    VALUE_(0,1)     // Output mode, max 10MHz
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ     VALUE_(0,2)     // Output mode, max 2MHz
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ    VALUE_(0,3)     // Output mode, max 50MHz
+
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_LOW (CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_MED (CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_FAST (CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ)
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH (CYGHWR_HAL_STM32_GPIO_MODE_OUT_FAST) // F1 limited to 50MHz
+
+// The following allows compatible specification of speed with other parts
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_AT_LEAST(__mhz)  ( ((__mhz) <= 2) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ :   \
+                                                        ((__mhz) <= 10) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ : \
+                                                        ((__mhz) <= 50) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ : \
+                                                          CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH )
+
+#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_AT_MOST(__mhz)  ( ((__mhz) < 10) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ :   \
+                                                       ((__mhz) < 50) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ :  \
+                                                       ((__mhz) < 100) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ : \
+                                                         CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH )
+
+#define CYGHWR_HAL_STM32_GPIO_CNF_AIN           VALUE_(2,0)     // Analog input
+#define CYGHWR_HAL_STM32_GPIO_CNF_FIN           VALUE_(2,1)     // Floating input
+#define CYGHWR_HAL_STM32_GPIO_CNF_PULL          VALUE_(2,2)     // Input with pull up/down
+#define CYGHWR_HAL_STM32_GPIO_CNF_RESV          VALUE_(2,3)     // Reserved
+
+#define CYGHWR_HAL_STM32_GPIO_CNF_GPOPP         VALUE_(2,0)     // GP output push/pull
+#define CYGHWR_HAL_STM32_GPIO_CNF_GPOOD         VALUE_(2,1)     // GP output open drain
+#define CYGHWR_HAL_STM32_GPIO_CNF_AOPP          VALUE_(2,2)     // Alt output push/pull
+#define CYGHWR_HAL_STM32_GPIO_CNF_AOOD          VALUE_(2,3)     // Alt output open drain
+
+
+// Alternative, more readable, config names
+// Inputs
+#define CYGHWR_HAL_STM32_GPIO_CNF_ANALOG        CYGHWR_HAL_STM32_GPIO_CNF_AIN
+#define CYGHWR_HAL_STM32_GPIO_CNF_FLOATING      CYGHWR_HAL_STM32_GPIO_CNF_FIN
+#define CYGHWR_HAL_STM32_GPIO_CNF_PULLDOWN      (CYGHWR_HAL_STM32_GPIO_CNF_PULL)
+#define CYGHWR_HAL_STM32_GPIO_CNF_PULLUP        (CYGHWR_HAL_STM32_GPIO_CNF_PULL|CYGHWR_HAL_STM32_GPIO_PULLUP)
+// Outputs
+#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_GPOOD
+#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_PUSHPULL  CYGHWR_HAL_STM32_GPIO_CNF_GPOPP
+#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_AOOD
+#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_PUSHPULL  CYGHWR_HAL_STM32_GPIO_CNF_AOPP
+
+
+// This macro packs the port number, bit number, mode and
+// configuration for a GPIO pin into a single word. The packing puts
+// the mode and config in the ls 5 bits, the bit number in 16:20 and
+// the offset of the GPIO port from GPIOA in bits 8:15. The port, mode
+// and config are only specified using the last component of the names
+// to keep definitions short.
+
+#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __cnf )            \
+            ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) | \
+             (__bit<<16) |                                              \
+             (CYGHWR_HAL_STM32_GPIO_MODE_##__mode) |                    \
+             (CYGHWR_HAL_STM32_GPIO_CNF_##__cnf))
+
+// We treat the CNF and MODE fields as a single field to simplify the hardware register access. The CNFMODE fields are split across
+// two registers (CRL/CRH) so the passed __pin needs to be in the range 0..7
+#define CYGHWR_HAL_STM32_GPIO_CNFMODE_VAL(__pin, __cnfmode) ((__cnfmode) << ((__pin)<<2))
+#define CYGHWR_HAL_STM32_GPIO_CNFMODE_SET(__pin, __cnfmode, __reg) ((__reg) &= ~MASK_((__pin<<2),4), \
+                                                              (__reg) |= CYGHWR_HAL_STM32_GPIO_CNFMODE_VAL(__pin, __cnfmode))
+
+// Macros to extract encoded values
+#define CYGHWR_HAL_STM32_GPIO_PORT(__pin)       (CYGHWR_HAL_STM32_GPIOA+((__pin)&0x0000FF00))
+#define CYGHWR_HAL_STM32_GPIO_BIT(__pin)        (((__pin)>>16)&0x1F)
+#define CYGHWR_HAL_STM32_GPIO_CFG(__pin)        ((__pin)&0xF)
+#define CYGHWR_HAL_STM32_GPIO_PULLUP            BIT_(4)
+
+//=============================================================================
+// Alternate I/O configuration registers.
+
+#define CYGHWR_HAL_STM32_AFIO_EVCR              0x00
+#define CYGHWR_HAL_STM32_AFIO_MAPR              0x04
+#define CYGHWR_HAL_STM32_AFIO_EXTICR1           0x08
+#define CYGHWR_HAL_STM32_AFIO_EXTICR2           0x0C
+#define CYGHWR_HAL_STM32_AFIO_EXTICR3           0x10
+#define CYGHWR_HAL_STM32_AFIO_EXTICR4           0x14
+
+// The following macro allows the four EXTICR registers to be indexed
+// as CYGHWR_HAL_STM32_AFIO_EXTICR(1) to CYGHWR_HAL_STM32_AFIO_EXTICR(4)
+#define CYGHWR_HAL_STM32_AFIO_EXTICR(__x)       (4*((__x)-1)+0x08)
+
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PIN(__x)     VALUE_(0,(__x))
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTA        VALUE_(4,0) 
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTB        VALUE_(4,1) 
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTC        VALUE_(4,2) 
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTD        VALUE_(4,3) 
+#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTE        VALUE_(4,4)
+#define CYGHWR_HAL_STM32_AFIO_EVCR_EVOE         BIT_(7) 
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP     BIT_(0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_I2C1_RMP     BIT_(1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP     BIT_(2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP     BIT_(3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP  VALUE_(4,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP  VALUE_(4,1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP  VALUE_(4,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_NO_RMP  VALUE_(6,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_P1_RMP  VALUE_(6,1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_FL_RMP  VALUE_(6,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_NO_RMP  VALUE_(8,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P1_RMP  VALUE_(8,1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P2_RMP  VALUE_(8,2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_FL_RMP  VALUE_(8,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_NO_RMP  VALUE_(10,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_P2_RMP  VALUE_(10,2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_FL_RMP  VALUE_(10,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM4_RMP     BIT_(12)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_NO_RMP   VALUE_(13,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL1_RMP  VALUE_(13,2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL2_RMP  VALUE_(13,3)
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_PD01_RMP     BIT_(15)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM5CH4_RMP  BIT_(16)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EINJ_RMP BIT_(17)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EREG_RMP BIT_(18)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EINJ_RMP BIT_(19)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EREG_RMP BIT_(20)
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMP      BIT_(21)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN2_RMP     BIT_(22)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMII     BIT_(23)
+#endif
+
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_FULL     VALUE_(24,0)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_NORST    VALUE_(24,1)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPEN   VALUE_(24,2)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS  VALUE_(24,4)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK     VALUE_(24,7)
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI3_RMP     BIT_(28)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2ITR1_RMP BIT_(29)
+#define CYGHWR_HAL_STM32_AFIO_MAPR_PTP_PPS_RMP  BIT_(30)
+#endif
+
+// The following macros are used to generate the bitfields for setting up
+// external interrupts.  For example, CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(12)
+// will generate the bitfield which when ORed into the EXTICR4 register will
+// set up C12 as the external interrupt pin for the EXTI12 interrupt.
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6)
+#define CYGHWR_HAL_STM32_AFIO_EXTICRX_MASK(__x)  VALUE_(4*((__x)&3),0xF)
+
+// AFIO clock control
+
+#define CYGHWR_HAL_STM32_AFIO_CLOCK             CYGHWR_HAL_STM32_CLOCK( APB2, AFIO )
+
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+//=============================================================================
+// GPIO ports - F2/F4 family
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+// GPIO Register offsets.
+#define CYGHWR_HAL_STM32_GPIO_MODER                   0x00
+#define CYGHWR_HAL_STM32_GPIO_OTYPER                  0x04
+#define CYGHWR_HAL_STM32_GPIO_OSPEEDR                 0x08
+#define CYGHWR_HAL_STM32_GPIO_PUPDR                   0x0C
+#define CYGHWR_HAL_STM32_GPIO_IDR                     0x10
+#define CYGHWR_HAL_STM32_GPIO_ODR                     0x14
+#define CYGHWR_HAL_STM32_GPIO_BSRR                    0x18
+#define CYGHWR_HAL_STM32_GPIO_LCKR                    0x1C
+#define CYGHWR_HAL_STM32_GPIO_AFRL                    0x20
+#define CYGHWR_HAL_STM32_GPIO_AFRH                    0x24
+
+// A helper macro just to allow access to a particular register
+#define CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, __offset)  ((volatile cyg_uint32 *)( ((char*)__portbaseaddr) + __offset ))
+
+// GPIO port mode register. 
+#define CYGHWR_HAL_STM32_GPIO_MODE_GPIO_IN            (0)
+#define CYGHWR_HAL_STM32_GPIO_MODE_GPIO_OUT           (1)
+#define CYGHWR_HAL_STM32_GPIO_MODE_ALTFN              (2)
+#define CYGHWR_HAL_STM32_GPIO_MODE_ANALOG             (3)
+#define CYGHWR_HAL_STM32_GPIO_MODE_VAL(__pin, __mode) ((__mode) << ((__pin)<<1))
+#define CYGHWR_HAL_STM32_GPIO_MODE_SET(__pin, __mode, __reg) ((__reg) &= ~MASK_((__pin<<1),2), \
+                                                              (__reg) |= CYGHWR_HAL_STM32_GPIO_MODE_VAL(__pin, __mode))
+
+// GPIO port output type register.
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_PUSHPULL          (0)
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_OPENDRAIN         (1)
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_VAL(__pin, __otype)   VALUE_(__pin,__otype)
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_SET(__pin, __otype, __reg)   ((__reg) &= ~BIT_(__pin), \
+                                                                  (__reg) |= CYGHWR_HAL_STM32_GPIO_OTYPE_VAL(__pin, __otype))
+#define CYGHWR_HAL_STM32_GPIO_OTYPE_NA                (0) // Convenience define for ease of pin definitions
+
+// GPIO port output speed register.
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_LOW              (0)  // 2MHz
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ             (0)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_MED              (1)  // 25MHz
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ            (1)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_FAST             (2)  // 50MHz
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ            (2)
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH             (3)  // 100MHZ on 30pF, 80MHz on 15pF
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_BAL(__pin, __speed)  ((__speed) << ((__pin)<<1))
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_SET(__pin, __speed, __reg)  ((__reg) &= ~MASK_((__pin<<1),2), \
+                                                                  (__reg) |= CYGHWR_HAL_STM32_GPIO_OSPEED_BAL(__pin, __speed))
+
+// The following allows compatible specification of speed with other parts
+// which have different speed ranges e.g. F1
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_AT_LEAST(__mhz)  ( ((__mhz) <= 2) ? CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ :   \
+                                                        ((__mhz) <= 25) ? CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ : \
+                                                        ((__mhz) <= 50) ? CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ : \
+                                                        CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH )
+  
+#define CYGHWR_HAL_STM32_GPIO_OSPEED_AT_MOST(__mhz)  ( ((__mhz) < 25) ? CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ :   \
+                                                       ((__mhz) < 50) ? CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ :  \
+                                                       ((__mhz) < 100) ? CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ : \
+                                                       CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH )
+
+// GPIO port pull-up/pull-down register.
+#define CYGHWR_HAL_STM32_GPIO_PUPD_NONE               (0)
+#define CYGHWR_HAL_STM32_GPIO_PUPD_PULLUP             (1)
+#define CYGHWR_HAL_STM32_GPIO_PUPD_PULLDOWN           (2)
+#define CYGHWR_HAL_STM32_GPIO_PUPD_VAL(__pin, __pupd) ((__pupd) << ((__pin)<<1))
+#define CYGHWR_HAL_STM32_GPIO_PUPD_SET(__pin, __pupd, __reg) ((__reg) &= ~MASK_(((__pin)<<1),2), \
+                                                              (__reg) |= CYGHWR_HAL_STM32_GPIO_PUPD_VAL(__pin, __pupd))
+
+// GPIO port input data register.
+#define CYGHWR_HAL_STM32_GPIO_IDR_GET(__portbaseaddr, __pin, __val) \
+  ((__val) = ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_IDR) >> (__pin)) & 1)
+
+// GPIO port output data register.
+// Don't encourage setting it here. Use GPIO_BSRR instead for that.
+#define CYGHWR_HAL_STM32_GPIO_ODR_GET(__portbaseaddr, __pin, __val) \
+  ((__val) = ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_ODR) >> (__pin)) & 1)
+
+// GPIO port bit set/reset register.
+#define CYGHWR_HAL_STM32_GPIO_BSRR_SET(__portbaseaddr, __pin, __val) \
+  ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_BSRR) = (__val)?(1<<(__pin)):(1<<((__pin)+16)))
+
+// GPIO port configuration lock register.
+#define CYGHWR_HAL_STM32_GPIO_LCKR_LCKK               BIT_(16)
+#define CYGHWR_HAL_STM32_GPIO_LCKR_LCK(__pin)         BIT_((__pin))
+
+// GPIO alternate function low register.
+#define CYGHWR_HAL_STM32_GPIO_AFRL0                   MASK_(0,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL1                   MASK_(4,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL2                   MASK_(8,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL3                   MASK_(12,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL4                   MASK_(16,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL5                   MASK_(20,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL6                   MASK_(24,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRL7                   MASK_(28,4)
+// GPIO alternate function high register.
+#define CYGHWR_HAL_STM32_GPIO_AFRH8                   MASK_(0,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH9                   MASK_(4,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH10                  MASK_(8,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH11                  MASK_(12,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH12                  MASK_(16,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH13                  MASK_(20,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH14                  MASK_(24,4)
+#define CYGHWR_HAL_STM32_GPIO_AFRH15                  MASK_(28,4)
+
+// Set alternate function. We try to keep this as a macro as most times the
+// arguments will be constant so can easily be collapsed substantially by the
+// compiler.
+// Note, this is not interrupt-safe, unavoidably. Provide your own protection
+// if that's needed, although in general this will happen at startup time.
+#define CYGHWR_HAL_STM32_GPIO_AFR_SET(__portbaseaddr, __pin, __func)    \
+  CYG_MACRO_START                                                       \
+  cyg_uint32 __cur_afr, __mask;                                         \
+  volatile cyg_uint32 *__reg;                                           \
+  cyg_uint8 __reg_pin = (__pin);                                        \
+  if (__pin < 8) {                                                      \
+    __reg = CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_AFRL); \
+  } else {                                                              \
+    __reg = CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_AFRH); \
+    __reg_pin -= 8;                                                     \
+  }                                                                     \
+  HAL_READ_UINT32( __reg, __cur_afr );                                  \
+  __mask = 0xf << (__reg_pin<<2);                                       \
+  __cur_afr &= ~__mask;                                                 \
+  __mask = (__func) << (__reg_pin<<2);                                  \
+  __cur_afr |= __mask;                                                  \
+  HAL_WRITE_UINT32( __reg, __cur_afr );                                 \
+  CYG_MACRO_END
+
+
+// This macro packs the port number, bit number, mode and
+// configuration for a GPIO pin into a single word. The packing puts
+// the GPIO bank at bits 16:19, the pin at bits 12:15, the mode (i.e. function)
+// at bits 10:11, for ALTFN mode the specific mapping at bits 6:9, pushpull(0)
+// or open drain(1) at bit 5, pull-up(1) pull-down (2) or neither(0) at
+// bits 3:4, and speed at bits 0:2 (low, med, fast, high).
+// To keep definitions short, we simplify most of the arguments so they
+// can be passed in with only their last components.
+
+// FIXME: This should be renamed to something like CYGHWR_HAL_STM32_PIN(... when
+// bringing F1 into line with this way of declaring pins.
+
+#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __af, __ppod, __pupd, __speed) \
+  ( ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) << 6 ) |	\
+    (__bit << 12) |							\
+    (CYGHWR_HAL_STM32_GPIO_MODE_##__mode << 10) |			\
+    (__af << 6) |                                                       \
+    (CYGHWR_HAL_STM32_GPIO_OTYPE_##__ppod << 5) |			\
+    (CYGHWR_HAL_STM32_GPIO_PUPD_##__pupd << 3) |			\
+    (CYGHWR_HAL_STM32_GPIO_OSPEED_##__speed) )
+
+// Macros to extract encoded values
+#define CYGHWR_HAL_STM32_GPIO_PORT(__pin)       (CYGHWR_HAL_STM32_GPIOA+(((__pin)&0xF0000)>>6))
+#define CYGHWR_HAL_STM32_GPIO_BIT(__pin)        (((__pin)>>12)&0xF)
+#define CYGHWR_HAL_STM32_GPIO_MODE(__pin)       (((__pin)>>10)&0x3)
+#define CYGHWR_HAL_STM32_GPIO_AF(__pin)         (((__pin)>>6)&0xF)
+#define CYGHWR_HAL_STM32_GPIO_OPENDRAIN(__pin)  (((__pin)>>5)&0x1)
+#define CYGHWR_HAL_STM32_GPIO_PULLUPDOWN(__pin) (((__pin)>>3)&0x3)
+#define CYGHWR_HAL_STM32_GPIO_SPEED(__pin)       ((__pin)&0x7)
+
+#endif  //if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+//=============================================================================
+
+#define CYGHWR_HAL_STM32_GPIO_NONE      (0xFFFFFFFF)
+
+// Functions and macros to configure GPIO ports.
+
+__externC void hal_stm32_gpio_set( cyg_uint32 pin );
+__externC void hal_stm32_gpio_out( cyg_uint32 pin, int val );
+__externC void hal_stm32_gpio_in ( cyg_uint32 pin, int *val );
+
+#define CYGHWR_HAL_STM32_GPIO_SET(__pin ) hal_stm32_gpio_set( __pin )
+#define CYGHWR_HAL_STM32_GPIO_OUT(__pin, __val ) hal_stm32_gpio_out( __pin, __val )
+#define CYGHWR_HAL_STM32_GPIO_IN(__pin,  __val ) hal_stm32_gpio_in( __pin, __val )
+
+//-----------------------------------------------------------------------------
+
+// For the following pin definition macros where __speed is a parameter the
+// actual rates available depend on the target family. The generic LOW, MED,
+// FAST and HIGH manifests can be used instead of explicit values, or more
+// usefully the AT_LEAST(__mhz) and AT_MOST(__mhz) macros can be used to specify
+// an acceptable limit instead.
+
+// The CYGHWR_HAL_STM32_PIN_OUT() macro defines a GPIO output pin. The __ppod
+// parameter can be one of PUSHPULL or OPENDRAIN. The __pupd parameter can be
+// one of NONE, PULLUP or PULLDOWN. For F1 devices the __pupd parameter is
+// not-relevant and is ignored.
+// e.g.
+//   CYGHWR_HAL_STM32_PIN_OUT(B,8,OPENDRAIN,NONE,FAST);
+//   CYGHWR_HAL_STM32_PIN_OUT(B,9,OPENDRAIN,NONE.AT_LEAST(50));
+
+// The CYGHWR_HAL_STM32_PIN_ALTFN_OUT() macro defines an alternative function
+// output pin. For F1 family devices the __af field is not-relevant and is
+// ignored. The __ppod should be PUSHPULL or OPENDRAIN. The __pupd parameter can
+// be one of NONE, PULLUP or PULLDOWN. For F1 devices the __pupd parameter is
+// not-relevant and is ignored.
+// e.g.
+//   CYGHWR_HAL_STM32_PIN_ALTFN_OUT(B,6,4,OPENDRAIN,NONE,MED);
+//   CYGHWR_HAL_STM32_PIN_ALTFN_OUT(B,10,4,OPENDRAIN,NONE,AT_LEAST(10));
+
+// The CYGHWR_HAL_STM32_PIN_IN() macro is used to define GPIO input pins. The
+// __pupd should be one of NONE. FLOATING, PULLUP or PULLDOWN.
+// e.g.
+//   CYGHWR_HAL_STM32_PIN_IN(B,4,PULLUP);
+
+// The CYGHWR_HAL_STM32_PIN_ALTFN_IN() macro is used to define alternate
+// function input pins. The __ppod parameter can be one of PUSHPULL,
+// OPENDRAIN or NA. The __pupd should be one of NONE. FLOATING, PULLUP or
+// PULLDOWN. For F1 family devices the __af and _ppod fields are not relevant
+// and are ignored, and in reality this macro peforms the same function as
+// CYGHWR_HAL_STM32_PIN_IN() for F1 family devices since extra AFIO
+// configuration is needed.
+// e.g.
+//   CYGHWR_HAL_STM32_PIN_ALTFN_IN(B,4,6,OPENDRAIN,PULLUP);
+
+// The CYGHWR_HAL_STM32_PIN_ANALOG() macro defines an analog mode pin. For F1
+// family devices this is for input only, e.g. ADC.
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#define CYGHWR_HAL_STM32_GPIO_CNF_NONE (CYGHWR_HAL_STM32_GPIO_CNF_FLOATING) // Should not be needed for F1 family but ensure HIPERFORMANCE compatible name NONE exists
+
+#define CYGHWR_HAL_STM32_PIN_OUT(__port,__pin,__ppod,__pupd,__speed) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,OUT_##__speed,OUT_##__ppod)
+
+#define CYGHWR_HAL_STM32_PIN_ALTFN_OUT(__port,__pin,__af,__ppod,__pupd,__speed) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,OUT_##__speed,ALT_##__ppod)
+
+#define CYGHWR_HAL_STM32_PIN_IN(__port,__pin,__pupd)     \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,__pupd)
+
+#define CYGHWR_HAL_STM32_PIN_ALTFN_IN(__port,__pin,__af,__ppod,__pupd)  \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,__pupd) // NOTE: Identical to CYGHWR_HAL_STM32_PIN_IN() at the moment
+
+#define CYGHWR_HAL_STM32_PIN_ANALOG(__port,__pin) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,ANALOG)
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_GPIO_PUPD_FLOATING (CYGHWR_HAL_STM32_GPIO_PUPD_NONE) // Should not be needed for HIPERFORMANCE family but ensure F1 compatible name FLOATING exists
+
+#define CYGHWR_HAL_STM32_PIN_OUT(__port,__pin,__ppod,__pupd,__speed) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,GPIO_OUT,0,__ppod,__pupd,__speed)
+
+#define CYGHWR_HAL_STM32_PIN_ALTFN_OUT(__port,__pin,__af,__ppod,__pupd,__speed) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,ALTFN,__af,__ppod,__pupd,__speed)
+
+#define CYGHWR_HAL_STM32_PIN_IN(__port,__pin,__pupd) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,GPIO_IN,0,NA,__pupd,NA)
+
+#define CYGHWR_HAL_STM32_PIN_ALTFN_IN(__port,__pin,__af,__ppod,__pupd)  \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,ALTFN,__af,__ppod,__pupd,NA)
+
+#define CYGHWR_HAL_STM32_PIN_ANALOG(__port,__pin) \
+  CYGHWR_HAL_STM32_GPIO(__port,__pin,ANALOG,0,NA,NONE,NA)
+
+#else
+#error "Unknown STM32 family for GPIO PIN macros"
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_io_pins.h
+#endif // CYGONCE_HAL_VAR_IO_PINS_H
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h
new file mode 100644
index 0000000..2f00053
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h
@@ -0,0 +1,264 @@
+#ifndef CYGONCE_HAL_VAR_IO_USART_H
+#define CYGONCE_HAL_VAR_IO_USART_H
+//=============================================================================
+//
+//      var_io_usart.h
+//
+//      USART-specific variant definitions
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, jlarmour
+// Date:        2008-07-30
+// Purpose:     STM32 variant USART specific registers
+// Description: 
+// Usage:       Do not include this header file directly. Instead:
+//              #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#ifndef CYGONCE_HAL_VAR_IO_H
+# error Do not include var_io_usart.h directly, use var_io.h
+#endif
+
+//=============================================================================
+// UARTs
+
+#define CYGHWR_HAL_STM32_UART_SR                0x00
+#define CYGHWR_HAL_STM32_UART_DR                0x04
+#define CYGHWR_HAL_STM32_UART_BRR               0x08
+#define CYGHWR_HAL_STM32_UART_CR1               0x0C
+#define CYGHWR_HAL_STM32_UART_CR2               0x10
+#define CYGHWR_HAL_STM32_UART_CR3               0x14
+#define CYGHWR_HAL_STM32_UART_GTPR              0x18
+
+// SR Bits
+
+#define CYGHWR_HAL_STM32_UART_SR_PE             BIT_(0)
+#define CYGHWR_HAL_STM32_UART_SR_FE             BIT_(1)
+#define CYGHWR_HAL_STM32_UART_SR_NE             BIT_(2)
+#define CYGHWR_HAL_STM32_UART_SR_NF             BIT_(2)
+#define CYGHWR_HAL_STM32_UART_SR_ORE            BIT_(3)
+#define CYGHWR_HAL_STM32_UART_SR_IDLE           BIT_(4)
+#define CYGHWR_HAL_STM32_UART_SR_RXNE           BIT_(5)
+#define CYGHWR_HAL_STM32_UART_SR_TC             BIT_(6)
+#define CYGHWR_HAL_STM32_UART_SR_TXE            BIT_(7)
+#define CYGHWR_HAL_STM32_UART_SR_LBD            BIT_(8)
+#define CYGHWR_HAL_STM32_UART_SR_CTS            BIT_(9)
+
+// BRR bits
+
+#define CYGHWR_HAL_STM32_UART_BRR_DIVF(__f)      VALUE_(0,__f)
+#define CYGHWR_HAL_STM32_UART_BRR_DIVM(__m)      VALUE_(4,__m)
+
+// CR1 bits
+
+#define CYGHWR_HAL_STM32_UART_CR1_SBK           BIT_(0)
+#define CYGHWR_HAL_STM32_UART_CR1_RWU           BIT_(1)
+#define CYGHWR_HAL_STM32_UART_CR1_RE            BIT_(2)
+#define CYGHWR_HAL_STM32_UART_CR1_TE            BIT_(3)
+#define CYGHWR_HAL_STM32_UART_CR1_IDLEIE        BIT_(4)
+#define CYGHWR_HAL_STM32_UART_CR1_RXNEIE        BIT_(5)
+#define CYGHWR_HAL_STM32_UART_CR1_TCIE          BIT_(6)
+#define CYGHWR_HAL_STM32_UART_CR1_TXEIE         BIT_(7)
+#define CYGHWR_HAL_STM32_UART_CR1_PEIE          BIT_(8)
+#define CYGHWR_HAL_STM32_UART_CR1_PS_EVEN       0
+#define CYGHWR_HAL_STM32_UART_CR1_PS_ODD        BIT_(9)
+#define CYGHWR_HAL_STM32_UART_CR1_PCE           BIT_(10)
+#define CYGHWR_HAL_STM32_UART_CR1_WAKE          BIT_(11)
+#define CYGHWR_HAL_STM32_UART_CR1_M_8           0
+#define CYGHWR_HAL_STM32_UART_CR1_M_9           BIT_(12)
+#define CYGHWR_HAL_STM32_UART_CR1_UE            BIT_(13)
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+#define CYGHWR_HAL_STM32_UART_CR1_OVER8         BIT_(15)
+#endif
+
+// CR2 bits
+
+#define CYGHWR_HAL_STM32_UART_CR2_ADD(__a)      VALUE_(0,__a)
+#define CYGHWR_HAL_STM32_UART_CR2_LBDL          BIT_(5)
+#define CYGHWR_HAL_STM32_UART_CR2_LBDIE         BIT_(6)
+#define CYGHWR_HAL_STM32_UART_CR2_LBCL          BIT_(8)
+#define CYGHWR_HAL_STM32_UART_CR2_CPHA          BIT_(9)
+#define CYGHWR_HAL_STM32_UART_CR2_CPOL          BIT_(10)
+#define CYGHWR_HAL_STM32_UART_CR2_CLKEN         BIT_(11)
+#define CYGHWR_HAL_STM32_UART_CR2_STOP_1        VALUE_(12,0)
+#define CYGHWR_HAL_STM32_UART_CR2_STOP_0_5      VALUE_(12,1)
+#define CYGHWR_HAL_STM32_UART_CR2_STOP_2        VALUE_(12,2)
+#define CYGHWR_HAL_STM32_UART_CR2_STOP_1_5      VALUE_(12,3)
+#define CYGHWR_HAL_STM32_UART_CR2_LINEN         BIT_(14)
+
+// CR3 bits
+
+#define CYGHWR_HAL_STM32_UART_CR3_EIE           BIT_(0)
+#define CYGHWR_HAL_STM32_UART_CR3_IREN          BIT_(1)
+#define CYGHWR_HAL_STM32_UART_CR3_IRLP          BIT_(2)
+#define CYGHWR_HAL_STM32_UART_CR3_HDSEL         BIT_(3)
+#define CYGHWR_HAL_STM32_UART_CR3_NACK          BIT_(4)
+#define CYGHWR_HAL_STM32_UART_CR3_SCEN          BIT_(5)
+#define CYGHWR_HAL_STM32_UART_CR3_DMAR          BIT_(6)
+#define CYGHWR_HAL_STM32_UART_CR3_DMAT          BIT_(7)
+#define CYGHWR_HAL_STM32_UART_CR3_RTSE          BIT_(8)
+#define CYGHWR_HAL_STM32_UART_CR3_CTSE          BIT_(9)
+#define CYGHWR_HAL_STM32_UART_CR3_CTSIE         BIT_(10)
+
+// GTPR fields
+
+#define CYGHWR_HAL_STM32_UART_GTPR_PSC(__p)     VALUE_(0,__p)
+#define CYGHWR_HAL_STM32_UART_GTPR_GT(__g)      VALUE_(8,__g)
+
+// UART GPIO pins
+
+// NOTE: For those UARTS providing a RTS pin the driver uses HW CTS control but
+// manually controls the RTS as a GPIO.
+
+#ifndef CYGHWR_HAL_STM32_UART0_REMAP
+#define CYGHWR_HAL_STM32_UART1_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A, 10,  7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART1_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  9,  7, PUSHPULL, NONE,    50MHZ )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG     0
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#else // CYGHWR_HAL_STM32_UART0_REMAP
+#define CYGHWR_HAL_STM32_UART1_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B,  7,  7, NA  ,     FLOATING )
+#define CYGHWR_HAL_STM32_UART1_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B,  6,  7, PUSHPULL, NONE,    50MHZ )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#endif // else CYGHWR_HAL_STM32_UART0_REMAP
+
+#define CYGHWR_HAL_STM32_UART1_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A, 11,  7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART1_RTS              CYGHWR_HAL_STM32_PIN_OUT( A, 12, PUSHPULL, NONE, 50MHZ )
+
+#define CYGHWR_HAL_STM32_UART1_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, UART1 )
+
+#ifndef CYGHWR_HAL_STM32_UART1_REMAP
+#define CYGHWR_HAL_STM32_UART2_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  3, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART2_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A,  2, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART2_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  A,  0, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART2_RTS              CYGHWR_HAL_STM32_PIN_OUT( A, 1, PUSHPULL, NONE, 50MHZ )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG     0
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#else
+#define CYGHWR_HAL_STM32_UART2_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D,  6, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART2_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( D,  5, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART2_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D,  3, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART2_RTS              CYGHWR_HAL_STM32_PIN_OUT( D,  4, PUSHPULL, NONE, 50MHZ )
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+#endif
+
+#define CYGHWR_HAL_STM32_UART2_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, UART2 )
+
+#if defined(CYGHWR_HAL_STM32_UART2_REMAP_PARTIAL)
+
+#define CYGHWR_HAL_STM32_UART3_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C, 11, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART3_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B, 13, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_RTS              CYGHWR_HAL_STM32_PIN_OUT( B, 14, PUSHPULL, NONE, 50MHZ )
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#elif defined(CYGHWR_HAL_STM32_UART2_REMAP_FULL)
+
+#define CYGHWR_HAL_STM32_UART3_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D,  9, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( D,  8, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART3_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D, 11, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_RTS              CYGHWR_HAL_STM32_PIN_OUT( D, 12, PUSHPULL, NONE, 50MHZ )
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#else
+
+#define CYGHWR_HAL_STM32_UART3_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B, 11, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, 7, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART3_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  B, 13, 7, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART3_RTS              CYGHWR_HAL_STM32_PIN_OUT( B, 14, PUSHPULL, NONE, 50MHZ )
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG     CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#endif
+
+#define CYGHWR_HAL_STM32_UART3_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, UART3 )
+
+#define CYGHWR_HAL_STM32_UART4_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C, 11, 8, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART4_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 8, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART4_CTS              CYGHWR_HAL_STM32_GPIO_NONE
+#define CYGHWR_HAL_STM32_UART4_RTS              CYGHWR_HAL_STM32_GPIO_NONE
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART4_REMAP_CONFIG     0
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#define CYGHWR_HAL_STM32_UART4_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, UART4 )
+
+#define CYGHWR_HAL_STM32_UART5_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  D,  2, 8, NA,       FLOATING )
+#define CYGHWR_HAL_STM32_UART5_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, 8, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART5_CTS              CYGHWR_HAL_STM32_GPIO_NONE
+#define CYGHWR_HAL_STM32_UART5_RTS              CYGHWR_HAL_STM32_GPIO_NONE
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+#define CYGHWR_HAL_STM32_UART5_REMAP_CONFIG     0
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1
+
+#define CYGHWR_HAL_STM32_UART5_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB1, UART5 )
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#define CYGHWR_HAL_STM32_UART6_RX               CYGHWR_HAL_STM32_PIN_ALTFN_IN(  C,  7, 8, NA,       NONE )
+#define CYGHWR_HAL_STM32_UART6_TX               CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C,  6, 8, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART6_CTS              CYGHWR_HAL_STM32_PIN_ALTFN_IN(  G, 15, 8, NA,       NONE )
+#define CYGHWR_HAL_STM32_UART6_RTS              CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G,  8, 8, PUSHPULL, NONE, 50MHZ )
+#define CYGHWR_HAL_STM32_UART6_CLOCK            CYGHWR_HAL_STM32_CLOCK( APB2, UART6 )
+
+#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_stm32_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+#endif
+
+#endif // CYGONCE_HAL_VAR_IO_USART_H
+//-----------------------------------------------------------------------------
+// end of var_io_usart.h
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc b/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc
new file mode 100644
index 0000000..4c72d2e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc
@@ -0,0 +1,54 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_stm32.h>
+
+//==========================================================================
+// EOF variant.inc
+
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/stm32/var/current/src/hal_diag.c
new file mode 100644
index 0000000..1049de1
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/src/hal_diag.c
@@ -0,0 +1,434 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2008-07-30
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing
+
+#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+
+#include <cyg/hal/var_io.h>             // USART registers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32          uart;
+    CYG_ADDRESS         base;
+    cyg_int32           msec_timeout;
+    int                 isr_vector;
+    cyg_uint32          rxpin;
+    cyg_uint32          txpin;
+    cyg_uint32          clkena;
+#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    cyg_uint32          remap;
+#endif
+    cyg_uint32          baud_rate;
+    int                 irq_state;
+    
+} channel_data_t;
+
+// If remap isn't supported (e.g. F2/F4 parts) just #define to nothing. The struct initialiser will still work.
+#ifndef CYGHWR_HAL_STM32_UART1_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG
+#endif
+#ifndef CYGHWR_HAL_STM32_UART2_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG
+#endif
+#ifndef CYGHWR_HAL_STM32_UART3_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG
+#endif
+#ifndef CYGHWR_HAL_STM32_UART4_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART4_REMAP_CONFIG
+#endif
+#ifndef CYGHWR_HAL_STM32_UART5_REMAP_CONFIG
+#define CYGHWR_HAL_STM32_UART5_REMAP_CONFIG
+#endif
+
+static channel_data_t stm32_ser_channels[] = {
+#if CYGINT_HAL_STM32_UART0>0
+    { 0, CYGHWR_HAL_STM32_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1, CYGHWR_HAL_STM32_UART1_RX, CYGHWR_HAL_STM32_UART1_TX,
+      CYGHWR_HAL_STM32_UART1_CLOCK, CYGHWR_HAL_STM32_UART1_REMAP_CONFIG },
+#endif
+#if CYGINT_HAL_STM32_UART1>0
+    { 1, CYGHWR_HAL_STM32_UART2, 1000, CYGNUM_HAL_INTERRUPT_UART2, CYGHWR_HAL_STM32_UART2_RX, CYGHWR_HAL_STM32_UART2_TX,
+      CYGHWR_HAL_STM32_UART2_CLOCK, CYGHWR_HAL_STM32_UART2_REMAP_CONFIG },
+#endif
+#if CYGINT_HAL_STM32_UART2>0
+    { 2, CYGHWR_HAL_STM32_UART3, 1000, CYGNUM_HAL_INTERRUPT_UART3, CYGHWR_HAL_STM32_UART3_RX, CYGHWR_HAL_STM32_UART3_TX,
+      CYGHWR_HAL_STM32_UART3_CLOCK, CYGHWR_HAL_STM32_UART3_REMAP_CONFIG },
+#endif
+#if CYGINT_HAL_STM32_UART3>0
+    { 3, CYGHWR_HAL_STM32_UART4, 1000, CYGNUM_HAL_INTERRUPT_UART4, CYGHWR_HAL_STM32_UART4_RX, CYGHWR_HAL_STM32_UART4_TX,
+      CYGHWR_HAL_STM32_UART4_CLOCK, CYGHWR_HAL_STM32_UART4_REMAP_CONFIG },
+#endif
+#if CYGINT_HAL_STM32_UART4>0
+    { 4, CYGHWR_HAL_STM32_UART5, 1000, CYGNUM_HAL_INTERRUPT_UART5, CYGHWR_HAL_STM32_UART5_RX, CYGHWR_HAL_STM32_UART5_TX,
+      CYGHWR_HAL_STM32_UART5_CLOCK, CYGHWR_HAL_STM32_UART5_REMAP_CONFIG },
+#endif
+#if CYGINT_HAL_STM32_UART5>0
+    { 5, CYGHWR_HAL_STM32_UART6, 1000, CYGNUM_HAL_INTERRUPT_UART6, CYGHWR_HAL_STM32_UART6_RX, CYGHWR_HAL_STM32_UART6_TX,
+      CYGHWR_HAL_STM32_UART6_CLOCK },  // UART6 only supported on F2/F4 so no remap config needed.
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void
+hal_stm32_serial_init_channel(void* __ch_data)
+{
+    channel_data_t *chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS base = chan->base;
+    cyg_uint32 cr1, cr2;
+
+    // Enable the PIO lines for the serial channel
+
+    CYGHWR_HAL_STM32_GPIO_SET( chan->rxpin );
+    CYGHWR_HAL_STM32_GPIO_SET( chan->txpin );
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( chan->clkena );
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    if( chan->remap != 0 )
+    {
+        CYG_ADDRESS afio = CYGHWR_HAL_STM32_AFIO;
+        cyg_uint32 mapr;
+        CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_AFIO_CLOCK );
+        HAL_READ_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr );
+        mapr |= chan->remap;
+        HAL_WRITE_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr );
+    }
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+    cr2 = CYGHWR_HAL_STM32_UART_CR2_STOP_1;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR2, cr2 );
+
+    cr1 = CYGHWR_HAL_STM32_UART_CR1_M_8;
+    cr1 |= CYGHWR_HAL_STM32_UART_CR1_TE | CYGHWR_HAL_STM32_UART_CR1_RE;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 );
+
+    // Set up Baud rate
+    chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
+    hal_stm32_uart_setbaud( base, chan->baud_rate );
+
+    // Enable the uart
+    cr1 |= CYGHWR_HAL_STM32_UART_CR1_UE;
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 );    
+
+}
+
+void
+hal_stm32_serial_putc(void *__ch_data, char c)
+{
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint32 sr;
+    CYGARC_HAL_SAVE_GP();
+
+     do
+     {
+         HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, sr );
+     } while ((sr & CYGHWR_HAL_STM32_UART_SR_TXE) == 0);
+
+     HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c );     
+    
+    CYGARC_HAL_RESTORE_GP();    
+}
+
+static cyg_bool
+hal_stm32_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint32 sr;
+    cyg_uint32 c;
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, sr );
+
+    if( (sr & CYGHWR_HAL_STM32_UART_SR_RXNE) == 0 )
+        return false;
+
+    HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c );     
+
+    *ch = (cyg_uint8)c;
+
+    CYGARC_HAL_RESTORE_GP();    
+
+    return true;
+}
+
+cyg_uint8
+hal_stm32_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!hal_stm32_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+hal_stm32_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        hal_stm32_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+hal_stm32_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = hal_stm32_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+hal_stm32_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 100; // delay in 10 us steps
+
+    for(;;) {
+        res = hal_stm32_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+        
+        CYGACC_CALL_IF_DELAY_US(10);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+hal_stm32_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base;
+    int ret = 0;
+    cyg_uint32 cr1;
+
+    va_list ap;
+
+    CYGARC_HAL_SAVE_GP();
+
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE( chan->isr_vector );
+        HAL_INTERRUPT_UNMASK( chan->isr_vector );
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 );
+        cr1 |= CYGHWR_HAL_STM32_UART_CR1_RXNEIE;
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 );        
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK( chan->isr_vector );
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 );
+        cr1 &= ~CYGHWR_HAL_STM32_UART_CR1_RXNEIE;
+        HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 );        
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+
+        va_start(ap, __func);
+
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }        
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        hal_stm32_uart_setbaud( base, chan->baud_rate );
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+hal_stm32_serial_isr(void *__ch_data, int* __ctrlc, 
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8 ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+     *__ctrlc = 0;
+
+     if( hal_stm32_serial_getc_nonblock(__ch_data, &ch) )
+     {
+         if( cyg_hal_is_break( (char *)&ch , 1 ) )
+             *__ctrlc = 1; 
+     }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+    return 1;
+}
+
+static void
+hal_stm32_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur;
+    int i;
+
+    cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    for( i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS ; i++ )
+    {
+        hal_stm32_serial_init_channel(&stm32_ser_channels[i]);
+
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &stm32_ser_channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, hal_stm32_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, hal_stm32_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, hal_stm32_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, hal_stm32_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, hal_stm32_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_stm32_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_stm32_serial_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+
+    // set debug channel baud rate if different
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate = 
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate( &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] );
+#endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    hal_stm32_serial_init();
+}
+
+#endif
+
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void hal_stm32_diag_init(void)
+{
+    hal_stm32_serial_init( &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+void hal_stm32_diag_putc(char c)
+{
+    hal_stm32_serial_putc( &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8 hal_stm32_diag_getc(void)
+{
+    return hal_stm32_serial_getc( &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+
+#endif
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c b/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c
new file mode 100644
index 0000000..78a869d
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c
@@ -0,0 +1,308 @@
+/*=============================================================================
+//
+//      stm32_dma.c
+//
+//      STM32 DMA support
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Contributors: 
+// Date:         2009-10-11
+// Purpose:      STM32 DMA support
+// Description:  This file provides the implementation for the STM32's
+//               on-chip DMA controllers.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/var_dma.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_ass.h>
+
+//=============================================================================
+
+#if 0
+#define dma_diag( __fmt, ... ) diag_printf("DMA: %20s[%3d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
+#define dma_dump_buf(__addr, __size ) diag_dump_buf( __addr, __size )
+#else
+#define dma_diag( __fmt, ... )
+#define dma_dump_buf(__addr, __size )
+#endif
+
+//=============================================================================
+
+static const struct
+{
+    CYG_ADDRWORD        base;
+    cyg_uint32          clock;
+} hal_stm32_dma_controller[] =
+{
+    { 0, 0 },
+    { CYGHWR_HAL_STM32_DMA1, CYGHWR_HAL_STM32_DMA1_CLOCK },
+    { CYGHWR_HAL_STM32_DMA2, CYGHWR_HAL_STM32_DMA2_CLOCK },
+};
+
+//-----------------------------------------------------------------------------
+
+static cyg_uint32 hal_stm32_dma_isr( cyg_vector_t vector, CYG_ADDRWORD data )
+{
+    hal_stm32_dma_stream *stream = (hal_stm32_dma_stream *)data;
+    cyg_uint32 ret = CYG_ISR_HANDLED;    
+    cyg_uint32 isr;
+
+    HAL_READ_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_ISR_REG(stream->stream), isr );
+
+    dma_diag("ctlr %08x stream %d chan %d isr %08x\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), isr );
+
+    if( isr & CYGHWR_HAL_STM32_DMA_ISR_TCIF(stream->stream) )
+    {
+        // Clear all stream interrupt bits
+        HAL_WRITE_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_IFCR_REG(stream->stream),
+                          CYGHWR_HAL_STM32_DMA_IFCR_MASK(stream->stream) );
+        
+        if( (stream->ccr & CYGHWR_HAL_STM32_DMA_CCR_CIRC) == 0)
+        {
+            // Disable the stream
+            HAL_WRITE_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 );
+        }
+
+        // Update the count
+        HAL_READ_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_CNDTR(stream->stream), stream->count );
+
+        ret = CYG_ISR_CALL_DSR;
+    }
+
+    return ret;
+}
+
+//-----------------------------------------------------------------------------
+
+static void hal_stm32_dma_dsr( cyg_vector_t vector, cyg_ucount32 count, CYG_ADDRWORD data )
+{
+    hal_stm32_dma_stream *stream = (hal_stm32_dma_stream *)data;
+
+    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+    
+    stream->callback( stream, stream->count, stream->data );
+
+    stream->active = false;    
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_init( hal_stm32_dma_stream *stream, int pri )
+{
+    stream->ctlr = hal_stm32_dma_controller[CYGHWR_HAL_STM32_DMA_CONTROLLER(stream->desc)].base;
+    stream->stream = CYGHWR_HAL_STM32_DMA_STREAM(stream->desc);
+
+    dma_diag("ctlr %08x stream %d chan %d pri %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), pri );
+             
+    cyg_drv_interrupt_create( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc),
+                              pri,
+                              (CYG_ADDRWORD)stream,
+                              hal_stm32_dma_isr,
+                              hal_stm32_dma_dsr,
+                              &stream->handle,
+                              &stream->interrupt );
+    cyg_drv_interrupt_attach( stream->handle );
+    cyg_drv_interrupt_unmask( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc) );
+
+    // Enable DMA controller clock
+    CYGHWR_HAL_STM32_CLOCK_ENABLE( hal_stm32_dma_controller[CYGHWR_HAL_STM32_DMA_CONTROLLER(stream->desc)].clock );
+
+
+    // Clear CCR, disable channel and put into known state
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 );
+
+    
+    // Initialize a private copy of the CCR, we don't write this to
+    // the hardware until we are ready to start the transfer.
+
+    stream->ccr = CYGHWR_HAL_STM32_DMA_CCR_EN;
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    // Select channel number in F2/F4 variants. The F1 variants simply
+    // have the various device DMA request lines wire-ORed together.
+    stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_CHSEL(CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc));
+#endif
+    
+    // Set stream direction
+    if( CYGHWR_HAL_STM32_DMA_MODE(stream->desc) == CYGHWR_HAL_STM32_DMA_MODE_M2P )
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MEM2P;
+
+    // Set memory increment mode
+    stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MINC;
+           
+    // Transfer end interrupt enable
+    stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_TCIE;
+
+    // Use top 2 bits of priority to define DMA stream priority
+    stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PL((pri>>6)&3);
+    
+    dma_diag("ccr %08x\n", stream->ccr);
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_delete( hal_stm32_dma_stream *stream )
+{
+    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+
+    // Clear CCR, disables stream
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 );
+
+    // Mask, detach and delete interrupt object
+    cyg_drv_interrupt_mask( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc) );
+    cyg_drv_interrupt_detach( stream->handle );
+    cyg_drv_interrupt_delete( stream->handle );
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_disable( hal_stm32_dma_stream *stream )
+{
+    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+
+    // Clear CCR, disables stream
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 );
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_poll( hal_stm32_dma_stream *stream )
+{
+//    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+//             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+    
+    if( stream->active )
+        if( hal_stm32_dma_isr( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), (CYG_ADDRWORD)stream ) & CYG_ISR_CALL_DSR )
+            hal_stm32_dma_dsr( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), 1, (CYG_ADDRWORD)stream );
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_configure( hal_stm32_dma_stream *stream, int tfr_size, cyg_bool no_minc, cyg_bool polled  )
+{
+    dma_diag("ctlr %08x stream %d chan %d tfr_size %d no_minc %d polled %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), tfr_size, no_minc, polled );
+    
+    if( tfr_size == 8 )
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE8;
+    else if( tfr_size == 16 )
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE16;
+    else 
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE32 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE32;
+
+    // Clear MINC bit if not wanted
+    if( no_minc )
+        stream->ccr &= ~CYGHWR_HAL_STM32_DMA_CCR_MINC;
+    else
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MINC;
+
+    // Clear interrupt enables if polled mode, otherwise enable them
+    if( polled )
+        stream->ccr &= ~(CYGHWR_HAL_STM32_DMA_CCR_TCIE | CYGHWR_HAL_STM32_DMA_CCR_TEIE);
+    else
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_TCIE | CYGHWR_HAL_STM32_DMA_CCR_TEIE;
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_configure_circular( hal_stm32_dma_stream *stream, cyg_bool enable)
+{
+    if (enable) {
+        stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_CIRC;
+    } else {
+        stream->ccr &= ~CYGHWR_HAL_STM32_DMA_CCR_CIRC;
+    }
+}
+
+//-----------------------------------------------------------------------------
+
+void hal_stm32_dma_start( hal_stm32_dma_stream *stream, void *memory, CYG_ADDRESS peripheral, cyg_uint32 size )
+{
+    dma_diag("ctlr %08x stream %d chan %d mem %08x peri %08x size %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), memory, peripheral, size );
+
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CMAR(stream->stream), (cyg_uint32)memory );
+
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CPAR(stream->stream), peripheral );
+
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CNDTR(stream->stream), size );
+
+    HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), stream->ccr );
+
+    stream->active = true;
+}
+
+//=============================================================================
+
+void hal_stm32_dma_show( hal_stm32_dma_stream *stream )
+{
+    cyg_uint32 dma = stream->ctlr;
+    cyg_uint32 chan = stream->stream;
+    cyg_uint32 reg;
+    
+    dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream,
+             CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) );
+    dma_diag("vector %d stream->ccr %08x\n", CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), stream->ccr );
+
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_ISR_REG(chan), reg );
+    dma_diag("DMA   ISR:   %08x\n", reg );
+    
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CCR(chan), reg );   dma_diag("DMA %d CCR:   %08x\n", chan, reg );
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CNDTR(chan), reg ); dma_diag("DMA %d CNDTR: %08x\n", chan, reg );
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CPAR(chan), reg );  dma_diag("DMA %d CPAR:  %08x\n", chan, reg );
+    HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CMAR(chan), reg );  dma_diag("DMA %d CMAR:  %08x\n", chan, reg );
+    
+}
+
+
+//=============================================================================
+/* EOF stm32_dma.c */
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c b/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c
new file mode 100644
index 0000000..df624a3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c
@@ -0,0 +1,574 @@
+/*==========================================================================
+//
+//      stm32_misc.c
+//
+//      Cortex-M STM32 HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009, 2011, 2014 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Contributors: jld
+// Date:         2008-07-30
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+#ifdef CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/profile/profile.h>        // __profile_hit()
+#endif
+
+//==========================================================================
+// Clock Initialization values
+
+#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_1
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 2
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_2
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 4
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_4
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 8
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_8
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 16
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_16
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 64
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_64
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 128
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_128
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 256
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_256
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 512
+# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_512
+#endif
+
+#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 1
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 2
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 8
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 16
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16
+#endif
+
+#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 1
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 4
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 8
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8
+#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 16
+# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16
+#endif
+
+
+//==========================================================================
+// Clock frequencies
+//
+// These are set to the frequencies of the various system clocks.
+
+cyg_uint32 hal_stm32_sysclk;
+cyg_uint32 hal_stm32_hclk;
+cyg_uint32 hal_stm32_pclk1;
+cyg_uint32 hal_stm32_pclk2;
+cyg_uint32 hal_cortexm_systick_clock;
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+cyg_uint32 hal_stm32_qclk;
+#endif
+
+void hal_start_clocks( void );
+cyg_uint32 hal_exti_isr( cyg_uint32 vector, CYG_ADDRWORD data );
+
+//==========================================================================
+
+void hal_variant_init( void )
+{
+
+#if 1 //!defined(CYG_HAL_STARTUP_RAM)
+    hal_start_clocks();
+#endif
+
+    // Attach EXTI springboard to interrupt vectors
+    HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_EXTI9_5,   hal_exti_isr, 0, 0 );
+    HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_EXTI15_10, hal_exti_isr, 0, 0 );
+    
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//==========================================================================
+// Setup up system clocks
+//
+// Set up clocks from configuration. In the future this should be extended so
+// that clock rates can be changed at runtime.
+
+void hal_start_clocks( void )
+{
+    CYG_ADDRESS rcc = CYGHWR_HAL_STM32_RCC;
+    cyg_uint32 cr, cfgr;
+    
+    // Reset RCC
+
+    cr = CYGHWR_HAL_STM32_RCC_CR_HSION;
+    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
+    
+    // Start up HSE clock
+    
+    cr |= CYGHWR_HAL_STM32_RCC_CR_HSEON;
+    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
+    
+    // Wait for HSE clock to startup
+    
+    do
+    {
+        HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
+    } while( !(cr & CYGHWR_HAL_STM32_RCC_CR_HSERDY) );
+
+    // Configure clocks
+    
+    // Temporarily divide by 4 until we've dealt with potential large
+    // multiplications overflow.
+    hal_stm32_sysclk = CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK >> 2;
+    
+    cfgr = 0;
+
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE)
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE;
+#endif
+
+    // Just a little sanity check.
+#if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSI) && (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV != 2)
+# error PLL PREDIV must be 2
+#endif
+
+    // Ordering could be important if divisions below cause truncation, so multiply first.
+    hal_stm32_sysclk *= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL;
+
+#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY
+    HAL_WRITE_UINT32( rcc + CYGHWR_HAL_STM32_RCC_CFGR2,
+                      CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV-1) );
+    hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV;
+#else
+    // Non-connectivity parts can only use PLLXTPRE
+    if ( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 2 )
+    {
+        cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE; // irrelevant if HSI used, so just set anyway.
+    hal_stm32_sysclk /= 2;
+    }
+#endif
+    hal_stm32_sysclk <<= 2; // return to correct range now we've dealt with risk of overflow.
+    
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLMUL(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL);
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_HPRE;
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE1;
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE2;
+
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+#if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE)
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSE;
+#endif
+
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV);
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL);
+    // Ordering could be important if divisions below cause truncation, so multiply first.
+    hal_stm32_sysclk *= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL;
+    hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV;
+
+    hal_stm32_sysclk <<= 2; // return to correct range now we've dealt with risk of overflow.
+
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP(CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV);
+    cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV);
+
+    // qclk divides down VCO output, so calc it first before updating sysclk for PLLP
+    hal_stm32_qclk = hal_stm32_sysclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV;
+
+    hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV;
+
+    HAL_WRITE_UINT32( rcc + CYGHWR_HAL_STM32_RCC_PLLCFGR, cfgr );
+
+    cfgr  = CYGHWR_HAL_STM32_RCC_CFGR_HPRE;
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE1;
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE2;
+
+    // RTCPRE divides down HSE, which is the input clock. Must be 1MHz.
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE( CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK/1000000 );
+
+#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+
+    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CFGR, cfgr );
+
+    // Enable the PLL and wait for it to lock
+    
+    cr |= CYGHWR_HAL_STM32_RCC_CR_PLLON;
+
+    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
+    do
+    {
+        HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr );
+    } while( !(cr & CYGHWR_HAL_STM32_RCC_CR_PLLRDY) );
+
+    // Now switch to use PLL as SYSCLK
+    // TODO: make this configurable between HSI, HSE and PLL
+    
+    cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_SW_PLL;
+
+    HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CFGR, cfgr );
+    do
+    {
+        HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CFGR, cfgr );
+    } while( (cfgr & CYGHWR_HAL_STM32_RCC_CFGR_SWS_XXX) != 
+             CYGHWR_HAL_STM32_RCC_CFGR_SWS_PLL );
+
+    // Calculate clocks from configuration
+
+    hal_stm32_hclk = hal_stm32_sysclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV;
+    hal_stm32_pclk1 = hal_stm32_hclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV;
+    hal_stm32_pclk2 = hal_stm32_hclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV;
+#ifdef CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_INTERNAL
+    hal_cortexm_systick_clock = hal_stm32_hclk;
+#else
+    hal_cortexm_systick_clock = hal_stm32_hclk / 8;
+#endif
+}
+
+//==========================================================================
+// ISR springboard
+//
+// This is attached to the ISR table entries for EXTI9_5 and EXTI15_10
+// to decode the contents of the EXTI registers and deliver the
+// interrupt to the correct ISR.
+
+cyg_uint32 hal_exti_isr( cyg_uint32 vector, CYG_ADDRWORD data )
+{
+    CYG_ADDRESS base = CYGHWR_HAL_STM32_EXTI;
+    cyg_uint32 imr, pr;
+
+    // Get EXTI pending and interrupt mask registers
+    HAL_READ_UINT32( base+CYGHWR_HAL_STM32_EXTI_IMR, imr );
+    HAL_READ_UINT32( base+CYGHWR_HAL_STM32_EXTI_PR, pr );
+
+    // Mask PR by IMR and lose ls 5 bits
+    pr &= imr;
+    pr &= 0xFFFFFFE0;
+
+    // Isolate LS pending bit and translate into interrupt vector
+    // number.
+    HAL_LSBIT_INDEX( vector, pr );
+    vector += CYGNUM_HAL_INTERRUPT_EXTI5 - 5;
+
+    // Deliver it
+    hal_deliver_interrupt( vector );
+
+    return 0;
+}
+
+//==========================================================================
+// GPIO support
+//
+// These functions provide configuration and IO for GPIO pins.
+
+__externC void hal_stm32_gpio_set( cyg_uint32 pin )
+{
+  // FIXME: Power on GPIO ports selectively here, rather than
+  // platform having to power them all on for boot.
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+    cyg_uint32 cm = CYGHWR_HAL_STM32_GPIO_CFG(pin);
+    cyg_uint32 cr;
+
+    if( pin == CYGHWR_HAL_STM32_GPIO_NONE )
+        return;
+    
+    if( bit > 7 ) port += 4, bit -= 8;
+    HAL_READ_UINT32( port, cr );
+    CYGHWR_HAL_STM32_GPIO_CNFMODE_SET(bit,cm,cr);
+    HAL_WRITE_UINT32( port, cr );
+
+    // If this is a pullup/down input, set the ODR bit to switch on
+    // the appropriate pullup/down resistor.
+    if( cm == (CYGHWR_HAL_STM32_GPIO_MODE_IN|CYGHWR_HAL_STM32_GPIO_CNF_PULL) )
+    {
+        cyg_uint32 odr;
+        port = CYGHWR_HAL_STM32_GPIO_PORT( pin );
+        bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+        HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_ODR, odr );
+        if( pin & CYGHWR_HAL_STM32_GPIO_PULLUP )
+            odr |= (1<<bit);
+        else
+            odr &= ~(1<<bit);
+        HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_ODR, odr );
+    }
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+    cyg_uint32 mode = CYGHWR_HAL_STM32_GPIO_MODE(pin);
+    cyg_uint32 af = CYGHWR_HAL_STM32_GPIO_AF(pin);
+    cyg_uint32 od = CYGHWR_HAL_STM32_GPIO_OPENDRAIN(pin);
+    cyg_uint32 pupd = CYGHWR_HAL_STM32_GPIO_PULLUPDOWN(pin);
+    cyg_uint32 speed = CYGHWR_HAL_STM32_GPIO_SPEED(pin);
+    cyg_uint32 reg;
+
+    if( pin == CYGHWR_HAL_STM32_GPIO_NONE )
+        return;
+
+    
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_OTYPER, reg );
+    CYGHWR_HAL_STM32_GPIO_OTYPE_SET( bit, od, reg );
+    HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_OTYPER, reg );
+
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_OSPEEDR, reg );
+    CYGHWR_HAL_STM32_GPIO_OSPEED_SET( bit, speed, reg );
+    HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_OSPEEDR, reg );
+
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_PUPDR, reg );
+    CYGHWR_HAL_STM32_GPIO_PUPD_SET( bit, pupd, reg );
+    HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_PUPDR, reg );
+
+    if ( CYGHWR_HAL_STM32_GPIO_MODE_ALTFN == mode )
+    {
+        CYGHWR_HAL_STM32_GPIO_AFR_SET( port, bit, af );
+    }
+
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_MODER, reg );
+    CYGHWR_HAL_STM32_GPIO_MODE_SET( bit, mode, reg );
+    HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_MODER, reg );
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+}
+    
+__externC void hal_stm32_gpio_out( cyg_uint32 pin, int val )
+{
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+    
+    port += CYGHWR_HAL_STM32_GPIO_BSRR;
+    if( (val&1) == 0 ) port += 4;
+    HAL_WRITE_UINT32( port, 1<<bit );
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+
+    CYGHWR_HAL_STM32_GPIO_BSRR_SET( port, bit, val );
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+}
+    
+__externC void hal_stm32_gpio_in ( cyg_uint32 pin, int *val )
+{
+#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1)
+    cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+    cyg_uint32 pd;
+    
+    HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_IDR, pd );
+    *val = (pd>>bit)&1;
+#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+    CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin);
+    int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin);
+
+    CYGHWR_HAL_STM32_GPIO_IDR_GET( port, bit, *val );
+#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
+}
+
+//==========================================================================
+// Clock support.
+//
+// These functions provide support for enabling and disabling clock
+// control bits.
+
+__externC void hal_stm32_clock_enable( cyg_uint32 desc )
+{
+    cyg_uint32 r;
+    cyg_uint32 reg = CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_CLOCK_REG(desc);
+    HAL_READ_UINT32( reg, r );
+    r |= BIT_(CYGHWR_HAL_STM32_CLOCK_PIN(desc));
+    HAL_WRITE_UINT32( reg, r );
+}
+
+__externC void hal_stm32_clock_disable( cyg_uint32 desc )
+{
+    cyg_uint32 r;
+    cyg_uint32 reg = CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_CLOCK_REG(desc);
+    HAL_READ_UINT32( reg, r );
+    r &= ~BIT_(CYGHWR_HAL_STM32_CLOCK_PIN(desc));
+    HAL_WRITE_UINT32( reg, r );
+}
+
+//==========================================================================
+// Backup domain
+
+void hal_stm32_bd_protect( int protect )
+{
+    CYG_ADDRESS pwr = CYGHWR_HAL_STM32_PWR;
+    cyg_uint32 cr;
+    
+    HAL_READ_UINT32( pwr+CYGHWR_HAL_STM32_PWR_CR, cr );
+    if( protect )
+        cr &= ~CYGHWR_HAL_STM32_PWR_CR_DBP;
+    else
+        cr |= CYGHWR_HAL_STM32_PWR_CR_DBP;        
+    HAL_WRITE_UINT32( pwr+CYGHWR_HAL_STM32_PWR_CR, cr );
+}
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current APB clock settings.
+
+void hal_stm32_uart_setbaud( cyg_uint32 base, cyg_uint32 baud )
+{
+    cyg_uint32 apbclk = hal_stm32_pclk1;
+    cyg_uint32 int_div, frac_div;
+    cyg_uint32 brr;
+    
+    if( base == CYGHWR_HAL_STM32_UART1 ||
+#ifdef CYGHWR_HAL_STM32_UART6
+        base == CYGHWR_HAL_STM32_UART6 ||
+#endif
+        0)
+    {
+        apbclk = hal_stm32_pclk2;
+    }
+
+    int_div = (25 * apbclk ) / (4 * baud );
+    brr = ( int_div / 100 ) << 4;
+    frac_div = int_div - (( brr >> 4 ) * 100 );
+
+    brr |= (((frac_div * 16 ) + 50 ) / 100) & 0xF;
+
+    HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_BRR, brr );
+}
+
+//==========================================================================
+// Timer clock rate
+//
+// Returns the current timer clock rate of a timer.
+
+cyg_uint32 hal_stm32_timer_clock( CYG_ADDRESS base )
+{
+    if( base == CYGHWR_HAL_STM32_TIM1 ||
+        base == CYGHWR_HAL_STM32_TIM8 )
+    {
+#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 1
+        return hal_stm32_pclk2;
+#else
+        return hal_stm32_pclk2 << 1;
+#endif
+    } else {
+#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 1
+        return hal_stm32_pclk1;
+#else
+        return hal_stm32_pclk1 << 1;
+#endif
+    }
+}
+
+//==========================================================================
+// Profiling timer
+//
+// Implementation of profiling support using general-purpose timer TIM2.
+
+#ifdef CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER
+// Use TIM2 for profiling
+#define STM32_TIMER_PROFILE CYGHWR_HAL_STM32_TIM2
+#define STM32_CLOCK_PROFILE CYGHWR_HAL_STM32_TIM2_CLOCK
+#define HAL_INTERRUPT_PROFILE CYGNUM_HAL_INTERRUPT_TIM2
+
+// Profiling timer ISR
+static cyg_uint32 profile_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
+{
+    extern HAL_SavedRegisters *hal_saved_interrupt_state;
+
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_SR, 0); // clear interrupt pending flag
+    HAL_INTERRUPT_ACKNOWLEDGE(HAL_INTERRUPT_PROFILE);
+    __profile_hit(hal_saved_interrupt_state->u.interrupt.pc);
+    return CYG_ISR_HANDLED;
+}
+
+// Profiling timer setup
+int hal_enable_profile_timer(int resolution)
+{
+    CYG_ASSERT(resolution < 0x10000, "Invalid profile timer resolution"); // 16 bits only
+
+    // Enable clock
+    CYGHWR_HAL_STM32_CLOCK_ENABLE(STM32_CLOCK_PROFILE);
+
+    // Attach ISR
+    HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_PROFILE, &profile_isr, 0x1111, 0);
+    HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_PROFILE);
+
+    // Setup timer
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_PSC,
+        (hal_stm32_timer_clock(STM32_TIMER_PROFILE) / 1000000) - 1); // prescale to microseconds
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_CR2, 0);
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_DIER, CYGHWR_HAL_STM32_TIM_DIER_UIE);
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_ARR, resolution);
+    HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_CR1, CYGHWR_HAL_STM32_TIM_CR1_CEN);
+
+    return resolution;
+}
+
+#endif // CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER
+
+//==========================================================================
+// EOF stm32_misc.c
diff --git a/ecos/packages/hal/cortexm/stm32/var/current/tests/timers.c b/ecos/packages/hal/cortexm/stm32/var/current/tests/timers.c
new file mode 100644
index 0000000..7d5b823
--- /dev/null
+++ b/ecos/packages/hal/cortexm/stm32/var/current/tests/timers.c
@@ -0,0 +1,364 @@
+/*=============================================================================
+//
+//      timers.c
+//
+//      Test for STM32 Timers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-09-11
+//              
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+
+#if defined(CYGPKG_KERNEL)
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/testcase.h>
+
+//=============================================================================
+// Check all required packages and components are present
+
+#if !defined(CYGPKG_KERNEL) || !defined(CYGPKG_KERNEL_API)
+
+#define NA_MSG  "Configuration insufficient"
+
+#endif
+
+//=============================================================================
+// If everything is present, compile the full test.
+
+#ifndef NA_MSG
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_if.h>
+
+#include <cyg/kernel/kapi.h>
+#include <cyg/infra/diag.h>
+#include <string.h>
+
+//=============================================================================
+
+#define LOOPS      24           // == 2 minutes
+
+#define STACK_SIZE 8000
+
+static int test_stack[(STACK_SIZE/sizeof(int))];
+static cyg_thread test_thread;
+static cyg_handle_t main_thread;
+
+//=============================================================================
+
+struct timer
+{
+    cyg_uint32          timer;
+    cyg_uint32          base;
+    cyg_uint32          vector;
+    cyg_uint32          priority;
+    cyg_uint32          interval;
+    
+    cyg_uint32          ticks;
+
+    cyg_uint32          preempt[10];
+
+    cyg_uint32          preempt_dsr[10];
+    cyg_uint32          dsr_count[10];
+    
+    cyg_interrupt       interrupt_object;
+    cyg_handle_t        interrupt_handle;
+};
+
+struct timer timers[] =
+{
+#if 0
+    { 1, CYGHWR_HAL_STM32_TIM1, CYGNUM_HAL_INTERRUPT_TIM1_UP, 0x20,    1000 },    
+#elif 1
+    { 1, CYGHWR_HAL_STM32_TIM1, CYGNUM_HAL_INTERRUPT_TIM1_UP, 0x20,     127 },
+    { 2, CYGHWR_HAL_STM32_TIM2, CYGNUM_HAL_INTERRUPT_TIM2,    0x30,     355 },
+    { 3, CYGHWR_HAL_STM32_TIM3, CYGNUM_HAL_INTERRUPT_TIM3,    0x40,     731 },
+    { 4, CYGHWR_HAL_STM32_TIM4, CYGNUM_HAL_INTERRUPT_TIM4,    0x50,     999 },
+    { 5, CYGHWR_HAL_STM32_TIM5, CYGNUM_HAL_INTERRUPT_TIM5,    0x60,    1453 },
+    { 6, CYGHWR_HAL_STM32_TIM6, CYGNUM_HAL_INTERRUPT_TIM6,    0x70,    1931 },
+    { 7, CYGHWR_HAL_STM32_TIM7, CYGNUM_HAL_INTERRUPT_TIM7,    0x80,    2011 },
+#ifdef CYGNUM_HAL_INTERRUPT_TIM8_UP
+    { 8, CYGHWR_HAL_STM32_TIM8, CYGNUM_HAL_INTERRUPT_TIM8_UP, 0x90,    2345 },    
+#elif defined(CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13)
+    { 8, CYGHWR_HAL_STM32_TIM8, CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13, 0x90,    2345 },
+#endif
+#endif
+    { 0, 0, 0, 0 }
+};
+
+//=============================================================================
+
+volatile cyg_uint32 ticks = 0;
+volatile cyg_uint32 nesting = 0;
+volatile cyg_uint32 max_nesting = 0;
+volatile cyg_uint32 max_nesting_seen = 0;
+volatile cyg_uint32 current = 0;
+volatile cyg_uint32 in_dsr = 0;
+
+//=============================================================================
+
+__externC cyg_uint32 hal_stm32_pclk1;
+__externC cyg_uint32 hal_stm32_pclk2;
+
+void init_timer( cyg_uint32 base, cyg_uint32 interval )
+{
+    cyg_uint32 period = hal_stm32_pclk1;
+
+    if( base == CYGHWR_HAL_STM32_TIM1 || base == CYGHWR_HAL_STM32_TIM8 )
+    {
+        period = hal_stm32_pclk2;
+        if( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV != 1 )
+            period *= 2;
+    }
+    else
+    {
+        if( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV != 1 )
+            period *= 2;
+    }
+
+    period = period / 1000000;
+    
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_PSC, period-1 );
+
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_CR2, 0 );
+
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_DIER, CYGHWR_HAL_STM32_TIM_DIER_UIE );
+
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_ARR, interval );
+    
+    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_CR1, CYGHWR_HAL_STM32_TIM_CR1_CEN);
+}
+
+//=============================================================================
+
+cyg_uint32 timer_isr( cyg_uint32 vector, CYG_ADDRWORD data )
+{
+    struct timer *t = (struct timer *)data;
+    cyg_uint32 preempt = current;
+    CYG_ADDRWORD base = t->base;
+    cyg_uint32 cnt;
+    
+    current = t->timer;
+    t->ticks++;
+    ticks++;
+    t->preempt[preempt]++;
+    nesting++;
+
+    // Count only first ISR to preempt a DSR
+    if( preempt == 0 )
+        t->preempt_dsr[in_dsr]++;
+    
+    HAL_WRITE_UINT32(t->base+CYGHWR_HAL_STM32_TIM_SR, 0 );
+    
+    if( nesting > max_nesting )
+        max_nesting = nesting;
+    
+    // Loiter here for a proportion of the timer interval to give
+    // other timers the chance to preempt us.
+    do
+    {
+        HAL_READ_UINT32( base+CYGHWR_HAL_STM32_TIM_CNT, cnt );
+    } while( cnt < t->interval/10 );
+    
+    nesting--;
+    current = preempt;
+
+    if( (t->ticks % 10) == 0 )
+        return 3;
+    else
+        return 1;
+}
+
+//=============================================================================
+
+void timer_dsr( cyg_uint32 vector, cyg_uint32 count, CYG_ADDRWORD data )
+{
+    struct timer *t = (struct timer *)data;
+    int i;
+    
+    in_dsr = t->timer;
+
+    if( count >= 8 )
+        count = 8;
+
+    t->dsr_count[count]++;
+
+    // Loiter for a while
+    for( i = 0; i < t->interval/10; i++)
+        continue;
+
+    in_dsr = 0;
+}
+
+//=============================================================================
+
+void
+timers_test(cyg_addrword_t data)
+{
+    int loops = LOOPS;
+    int i;
+    CYG_INTERRUPT_STATE istate;
+    
+    CYG_TEST_INIT();
+    
+    CYG_TEST_INFO("Start Timers test");
+    
+    for( i = 0; timers[i].timer != 0; i++ )
+    {
+        struct timer *t = &timers[i];
+
+        init_timer( t->base, t->interval );
+
+        cyg_interrupt_create( t->vector,
+                              t->priority,
+                              (cyg_addrword_t)t,
+                              timer_isr,
+                              timer_dsr,
+                              &t->interrupt_handle,
+                              &t->interrupt_object
+            );
+
+        cyg_interrupt_attach( t->interrupt_handle );
+        cyg_interrupt_unmask( t->vector );
+                              
+    }
+
+    while( loops-- )
+    {
+        int j;
+
+        // 5 second delay
+        cyg_thread_delay( 5*100 );
+
+        // Disable interrupts while we print details, otherwise it
+        // comes out very slowly.
+        HAL_DISABLE_INTERRUPTS( istate );
+        
+        if( max_nesting > max_nesting_seen )
+            max_nesting_seen = max_nesting;
+        
+        diag_printf("\nISRs max_nesting %d max_nesting_seen %d\n", max_nesting, max_nesting_seen );
+        max_nesting = 0;
+
+        diag_printf(" T      Ticks ");
+
+        for( j = 0; j < 9; j++ )
+            diag_printf("%9d ", j );
+        diag_printf("\n");
+            
+        for( i = 0; timers[i].timer != 0; i++ )
+        {
+            struct timer *t = &timers[i];
+
+            diag_printf("%2d: %9d ", t->timer, t->ticks );
+
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->preempt[j] );
+            diag_printf("\n");
+
+        }
+
+        diag_printf("DSRs\n");
+
+        diag_printf(" T:           ");
+
+        for( j = 0; j < 9; j++ )
+            diag_printf("%9d ", j );
+        diag_printf("\n");
+        
+        for( i = 0; timers[i].timer != 0; i++ )
+        {
+            struct timer *t = &timers[i];
+
+            diag_printf("%2d:  preempt: ", t->timer);
+            
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->preempt_dsr[j] );
+            diag_printf("\n");
+
+            diag_printf("       count: ");
+
+            for( j = 0; j < 9; j++ )
+                diag_printf("%9d ", t->dsr_count[j] );
+            diag_printf("\n");
+        }
+        
+        HAL_RESTORE_INTERRUPTS( istate );        
+    }
+
+    CYG_TEST_PASS_FINISH("Timers test");
+}
+
+//=============================================================================
+
+void cyg_user_start(void)
+{
+    cyg_thread_create(0,                // Priority
+                      timers_test,
+                      0,               
+                      "timers test",    // Name
+                      test_stack,       // Stack
+                      STACK_SIZE,       // Size
+                      &main_thread,     // Handle
+                      &test_thread // Thread data structure
+        );
+    cyg_thread_resume( main_thread);
+}
+
+//=============================================================================
+// Print a message if we cannot run
+
+#else // NA_MSG
+
+void cyg_user_start(void)
+{
+    CYG_TEST_NA(NA_MSG);
+}
+
+#endif // NA_MSG
+
+//=============================================================================
+/* EOF timers.c */
diff --git a/ecos/packages/hal/cortexm/vybrid/col_vf61/current/cdl/hal_cortexm_vybrid_col_vf61.cdl b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/cdl/hal_cortexm_vybrid_col_vf61.cdl
new file mode 100644
index 0000000..4aaff82
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/cdl/hal_cortexm_vybrid_col_vf61.cdl
@@ -0,0 +1,314 @@
+##==========================================================================
+##
+##      hal_cortexm_vybrid_col_vf61.cdl
+##
+##      Toradex Colibri VF61 platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2012 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Antmicro Ltd. <contact@antmicro.com>
+## Date:         2014-03-28
+## Based on respective definitions for Kinetis twr_k70f120m platform
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_VYBRID_COL_VF61 {
+    display       "Toradex Colibri VF61 Platform"
+    parent        CYGPKG_HAL_CORTEXM_VYBRID
+    define_header hal_cortexm_vybrid_col_vf61.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The Toradex Colibri VF61 Platform HAL package provides the support
+        needed to run eCos on the Colibri VF61 development system."
+
+    compile       col_vf61_misc.c
+
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+
+    implements		CYGINT_HAL_CACHE
+    implements		CYGINT_HAL_FPV4_SP_D16
+
+  
+    ##---VYBRID-UARTS-CDL---
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART0
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART1
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART2
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART3
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART4
+    implements    CYGINT_IO_SERIAL_FREESCALE_UART5
+    ##---VYBRID-DIAGNOSTIC-UARTS-CDL---
+ 	implements    CYGINT_HAL_FREESCALE_UART1
+ 	implements    CYGINT_HAL_FREESCALE_UART2
+ 	
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_vybrid_col_vf61.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M4\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Toradex Colibri VF61\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+        puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000"
+    }
+
+	cdl_component CYGHWR_HAL_COLIBRTIVF61_MEMORY_RESOURCES {
+        display "On platform memory resources"
+        flavor none
+        no_define
+        description "
+        View and manage memory resources.
+        Output is used for naming of 'mlt' files."
+
+
+        cdl_option CYGHWR_HAL_CORTEXM_VYBRID_DRAM_KIB {
+            display "Colibri DRAM size \[KiB\]"
+            flavor data
+            calculated { 16384 }
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_VYBRID_DRAM {
+            display "Colibri VF61 DRAM size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_VYBRID_DRAM_KIB * 0x400}
+        }
+        }
+
+    cdl_component CYG_HAL_STARTUP_ENV {
+        display "Startup type"
+        flavor data
+        no_define
+        calculated {
+            !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP :
+            ((CYG_HAL_STARTUP_PLF == "ByVariant") ?
+            (CYG_HAL_STARTUP . "(Variant)") :
+            (CYG_HAL_STARTUP . "(Platform)"))
+        }
+        description "
+            Startup type configuration defines the system memory layout.
+            Startup type  can be defined by the variant (CYG_HAL_STARTUP_VAR)
+            or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+
+    cdl_option CYG_HAL_STARTUP_PLF {
+        display       "By platform"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { "ByVariant" }
+        legal_values  { "ByVariant" "DRAM" }
+		no_define
+        description   "
+            Startup tupes provided by the platform, in addition to variant
+            startup types.
+            If 'ByVariant' is selected, then startup type shall be selected
+            from the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup
+            builds application similar to Variant's 'ROM' but using external
+            RAM (DDRAM)."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT_PLF {
+        display "Memory layout by platform"
+        flavor data
+        active_if { CYG_HAL_STARTUP_PLF != "ByVariant" }
+        implements CYGINT_HAL_CORTEXM_VYBRID_DDRAM
+        no_define
+        parent  CYGHWR_MEMORY_LAYOUT
+        calculated {
+            (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" :
+            (CYG_HAL_STARTUP == "DRAM") ? "vybrid_ext_dram" :
+            "Error!"
+        }
+        description "
+            Combination of 'Startup type' and 'Vybrid member in use'
+            produces the memory layout."
+    }
+
+	    cdl_component CYG_HAL_VTOR_ADRESS {
+        display       "NVIC VTOR memory"
+        flavor        data
+        calculated    { (CYG_HAL_STARTUP == "DRAM") ? 0x0f000000 :
+        				(CYG_HAL_STARTUP == "OCRAM") ? 0x1f000000 :
+        				(CYG_HAL_STARTUP == "TCML") ? 0x1f800000 :
+        				 0
+                       }
+        description   "      
+        Choose the memory type from which eCOS code will be executed. Possible options are: DDRAM 256MB in external chip on Colibri module
+        and OCRAM (Vybrid's OnChipRAM)"
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        legal_values 0 to 2
+        default_value   2
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    1
+        description      "
+			This option chooses which UART interface will be used for debugging purposes. GDB approach is assumed.  
+        	In general the Colibri VF61 module has 5 UART ports, however availability of certain ports depends on the pinout of carrier board holding the Colibri VF61 module.
+        	Please refer to carrier board's specification/schematic for further details regarding serial port connectivity.
+        	For example Iris Carrier board rev. 1.1 from Toradex has 3 serial interfaces and assumes the following channel mapping: UART0->UARTA, UART1->UARTC, UART2->UARTB.
+        	"
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    1
+        description      "
+        	This option chooses which UART port will be used for diagnostic output. 
+        	In general the Colibri VF61 module has 5 UART ports, however availability of certain ports depends on the pinout of carrier board holding the Colibri VF61 module.
+        	Please refer to carrier board's specification/schematic for further details regarding serial port connectivity.
+        	For example Iris Carrier board rev. 1.1 from Toradex has 3 serial interfaces and assumes the following channel mapping: UART0->UARTA, UART1->UARTC, UART2->UARTB.
+            "
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port if the
+            diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console port
+            if the console and GDB port are the same."
+    }
+
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME {
+        display "Interrupt priority scheme"
+        flavor none
+        description "Consolidated interrupt priority scheme setting."
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+            Global build options including control over
+            compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m4 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=cortex-m4 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the encoding
+            of diagnostic output, or the overriding of hardware interrupt
+            vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This is
+            the most basic support which is likely to be common to most
+            implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included in
+            the ROM monitor or boot ROM."
+    }
+}
diff --git a/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/pkgconf/mlt_vybrid_ext_dram.h b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/pkgconf/mlt_vybrid_ext_dram.h
new file mode 100644
index 0000000..0e15c03
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/pkgconf/mlt_vybrid_ext_dram.h
@@ -0,0 +1,21 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+#endif
+
+#define CYGMEM_REGION_sram (0x0f000000)
+#define CYGMEM_REGION_sram_SIZE (0x9FFFF0) //10MB
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (CYGMEM_REGION_sram)
+#define CYGMEM_REGION_ram_SIZE (CYGMEM_REGION_sram_SIZE)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_sram_ATTR)
+
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/pkgconf/mlt_vybrid_ext_dram.ldi b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/pkgconf/mlt_vybrid_ext_dram.ldi
new file mode 100644
index 0000000..bb5b199
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/pkgconf/mlt_vybrid_ext_dram.ldi
@@ -0,0 +1,36 @@
+// eCos memory layout
+// modified for VYBRID
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+	DRAM 	: ORIGIN = 0x0f000000, LENGTH = 0x9FFFF0 - (CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCMU  	: ORIGIN = 0x3f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCMU - (CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (DRAM, 0x0f000400, LMA_EQ_VMA)
+    SECTION_RELOCS (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (DRAM, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_bss (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (DRAM, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x0f000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x0f000000 + 0x9FFFF0); 
+
+
diff --git a/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_arch.h b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_arch.h
new file mode 100644
index 0000000..fe7d24e
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Antmicro Ltd <contact@antmicro.com>
+// Based on:	{...}/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h
+// Date:        2014-03-28
+// Purpose:     Colibri VF61 platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_vybrid_col_vf61.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_arch.h
+#endif // CYGONCE_HAL_PLF_ARCH_H
diff --git a/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_intr.h b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_intr.h
new file mode 100644
index 0000000..a0017e2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_intr.h
@@ -0,0 +1,64 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+
+// Author(s):   Antmicro Ltd <contact@antmicro.com>
+// Based on:	{...}/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h
+// Date:        2014-03-28
+// Purpose:     Colibri VF61 platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_vybrid_col_vf61.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_intr.h
+#endif // CYGONCE_HAL_PLF_INTR_H
diff --git a/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_io.h b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_io.h
new file mode 100644
index 0000000..09f4d30
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/plf_io.h
@@ -0,0 +1,141 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Antmicro Ltd <contact@antmicro.com>
+// Based on:	{...}/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h
+// Date:        2014-03-28
+// Purpose:     Colibri VF61 platform specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_vybrid_col_vf61.h>
+
+#ifndef CYGHWR_HAL_FREESCALE_UART0_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_RX 	CYGHWR_HAL_VYBRID_PIN(B, 11, 1, 0)
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_TX 	CYGHWR_HAL_VYBRID_PIN(B, 10, 1, 0)
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RX 	CYGHWR_HAL_FREESCALE_UART0_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_TX 	CYGHWR_HAL_FREESCALE_UART0_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS 	CYGHWR_HAL_FREESCALE_UART0_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS 	CYGHWR_HAL_FREESCALE_UART0_PIN_CTS
+#endif
+
+#ifndef CYGHWR_HAL_FREESCALE_UART1_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART1_PIN_RX 	CYGHWR_HAL_VYBRID_PIN(B, 5, 2, 0)
+# define CYGHWR_HAL_FREESCALE_UART1_PIN_TX	CYGHWR_HAL_VYBRID_PIN(B, 4, 2, 0)
+# define CYGHWR_HAL_FREESCALE_UART1_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART1_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_RX 	CYGHWR_HAL_FREESCALE_UART1_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART1_PIN_TX 	CYGHWR_HAL_FREESCALE_UART1_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART1_PIN_RTS	CYGHWR_HAL_FREESCALE_UART1_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART1_PIN_CTS	CYGHWR_HAL_FREESCALE_UART1_PIN_CTS
+#endif
+
+#ifndef CYGHWR_HAL_FREESCALE_UART2_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_RX  CYGHWR_HAL_VYBRID_PIN(D, 1, 2, 0)
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_TX  CYGHWR_HAL_VYBRID_PIN(D, 0, 2, 0)
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RX 	CYGHWR_HAL_FREESCALE_UART2_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_TX 	CYGHWR_HAL_FREESCALE_UART2_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS 	CYGHWR_HAL_FREESCALE_UART2_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS 	CYGHWR_HAL_FREESCALE_UART2_PIN_CTS
+#endif
+
+#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX  CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX  CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX 	CYGHWR_HAL_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX 	CYGHWR_HAL_FREESCALE_UART3_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS 	CYGHWR_HAL_FREESCALE_UART3_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS 	CYGHWR_HAL_FREESCALE_UART3_PIN_CTS
+#endif
+
+#ifndef CYGHWR_HAL_FREESCALE_UART4_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_RX  CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_TX  CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RX 	CYGHWR_HAL_FREESCALE_UART4_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_TX 	CYGHWR_HAL_FREESCALE_UART4_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS 	CYGHWR_HAL_FREESCALE_UART4_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS 	CYGHWR_HAL_FREESCALE_UART4_PIN_CTS
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART5_PIN_RX
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RX 	CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_TX 	CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_HAL_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RX 	CYGHWR_HAL_FREESCALE_UART5_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_TX 	CYGHWR_HAL_FREESCALE_UART5_PIN_TX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS 	CYGHWR_HAL_FREESCALE_UART5_PIN_RTS
+# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS 	CYGHWR_HAL_FREESCALE_UART5_PIN_CTS
+#endif
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count );
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
+
diff --git a/ecos/packages/hal/cortexm/vybrid/col_vf61/current/src/col_vf61_misc.c b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/src/col_vf61_misc.c
new file mode 100644
index 0000000..95bdc38
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/col_vf61/current/src/col_vf61_misc.c
@@ -0,0 +1,98 @@
+//==========================================================================
+//
+//      col_vf61_misc.c
+//
+//      Cortex-M4 Colibri VF61 Module HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Antmicro Ltd <contact@antmicro.com>
+// Date:        2014-03-28
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_vybrid.h>
+#include <pkgconf/hal_cortexm_vybrid_col_vf61.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void
+hal_system_init( void )
+{
+
+}
+
+//===========================================================================
+// hal_misc_init
+//===========================================================================
+static inline void
+hal_misc_init(void)
+{
+
+}
+//==========================================================================
+// hal_platform_init
+//==========================================================================
+__externC void
+hal_platform_init( void )
+{
+
+}
+
+//==========================================================================
+// EOF col_vf61_misc.c
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/cdl/hal_cortexm_vybrid.cdl b/ecos/packages/hal/cortexm/vybrid/var/current/cdl/hal_cortexm_vybrid.cdl
new file mode 100644
index 0000000..dc0b08a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/cdl/hal_cortexm_vybrid.cdl
@@ -0,0 +1,339 @@
+##==========================================================================
+##
+##      hal_cortexm_vybrid.cdl
+##
+##      Cortex-M Freescale Vybrid variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Antmicro Ltd <contact@antmicro.com>
+## Date:         2014-03-28
+## Based on respective definitions from /hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl
+## 
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+######MODIFICATION#####
+##
+## CYG_HAL_STARTUP_VAR legal_values added "RAM"
+## CYGHWR_MEMORY_LAYOUT addded new compute value (RAM)
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_VYBRID {
+    display       "Freescale Vybrid Cortex-M4 Variant"
+    parent        CYGPKG_HAL_CORTEXM
+    doc           ref/hal-cortexm-vybrid-var.html
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_vybrid.h
+    description   "
+        This package provides generic support for the Freescale Cortex-M4
+        based Vybrid microcontroller family.
+        It is also necessary to select a variant and platform HAL package."
+
+    compile       hal_diag.c vybrid_misc.c vybrid_clocking.c
+
+    #implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    #implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+	
+	
+    requires      { CYGHWR_HAL_CORTEXM == "M4" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_vybrid.h>"
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU exception priority level bits"
+        flavor        data
+        default_value 4
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M
+            CPU implements."
+    }
+
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP
+        description   "Set clock ISR priority. Default setting is lowest priority."
+    }
+
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 1000
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "
+                The period defined here is something of a fake, it is
+                expressed in terms of a notional 1MHz clock. The value
+                actually installed in the hardware is calculated from
+                the current settings of the clock generation hardware."
+        }
+    }
+
+    cdl_option CYG_HAL_STARTUP_VAR {
+        display      "By variant"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        default_value { "OCRAM" }
+        legal_values  { "TCML" "OCRAM" }
+        active_if     ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant"))
+        description   "
+            'OCRAM' startup builds a stand-alone application hich will be placed into OnChipRAM. 
+            This type of memory is intended to be written via bootloaders such like uBoot or 
+            from Linux system running on the Cortex A5 core of Vybrid processor.
+            Note: Variant Startup Type can be overriden/overloaded by
+            Platform Startup Type."
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type calculator"
+        flavor        data
+        parent        CYG_HAL_STARTUP_ENV
+        calculated    { (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ?
+                        CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR}
+        define        -file system.h CYG_HAL_STARTUP
+        description   "
+            Startup type defines what type of application shall be built.
+            Startup type  can be defined by variant (CYG_HAL_STARTUP_VAR)
+            or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
+            is defined and not equal to 'ByVariant' then it shall
+            override CYG_HAL_STARTUP_VAR."
+    }
+    
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        parent CYG_HAL_STARTUP_ENV
+        calculated {
+            (CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF :
+            (CYG_HAL_STARTUP == "TCML") ? "vybrid_tcml"  :
+            (CYG_HAL_STARTUP == "OCRAM") ? "vybrid_ocram"  :
+            "undefined" }
+        description "
+            Combination of 'Startup type' and 'Vybrid part'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+    }
+
+
+    cdl_component CYGHWR_HAL_VYBRID_MEMORY_RESOURCES {
+        display "On chip memory resources"
+        flavor none
+        no_define
+        description "
+        View and manage on-chip memory resources.
+        Output is used for naming of 'mlt' files."
+
+
+        cdl_option CYGHWR_HAL_CORTEXM_VYBRID_OCRAM_KIB {
+            display "Vybrid on chip SysRAM0 size \[KiB\]"
+            flavor data
+            calculated { 256 }
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_VYBRID_OCRAM {
+            display "Vybrid on chip SysRAM0 size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_VYBRID_OCRAM_KIB * 0x400}
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_VYBRID_TCMU_KIB {
+            display "Vybrid on chip TCMU (data) size \[KiB\]"
+            flavor data
+            calculated { 32 }
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_VYBRID_TCMU {
+            display "Vybrid on chip TCMU (data) size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_VYBRID_TCMU_KIB * 0x400 }
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_VYBRID_TCML_KIB {
+            display "Vybrid on chip TCML (data) size \[KiB\]"
+            flavor data
+            calculated { 32 }
+        }
+        
+        cdl_option CYGHWR_HAL_CORTEXM_VYBRID_TCML {
+            display "Vybrid on chip TCML (data) size"
+            flavor data
+            calculated { CYGHWR_HAL_CORTEXM_VYBRID_TCML_KIB * 0x400 }
+        }
+
+
+    }
+
+    cdl_interface CYGINT_HAL_CACHE {
+        display "Platform has cache"
+        flavor bool
+    }
+
+    cdl_interface CYGINT_HAL_HAS_NONCACHED {
+        display "Platform has non-cached regions"
+        flavor bool
+    }
+
+    cdl_component CYGPKG_HAL_VYBRID_CACHE {
+        display "Cache memory"
+        flavor bool
+
+        default_value false
+        active_if (CYGINT_HAL_CACHE)
+    }
+
+    cdl_interface CYGINT_HAL_CORTEXM_VYBRID_DDRAM {
+        display "Platform uses DDRAM"
+        flavor bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DDRAM and if DDRAM is
+            used on target hardware"
+    }
+
+
+    for { set ::channel 0 } { $::channel < 6 } { incr ::channel } {
+
+        cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] {
+            display     "Platform provides UART [set ::channel] HAL"
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                controller being used has on-chip UART [set ::channel],
+                and if that UART is accessible on the target hardware."
+        }
+
+        cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel]_RTSCTS {
+            display     "Platform provides HAL for UART[set ::channel] hardware flow control."
+            flavor      bool
+            description "
+                This interface will be implemented if the specific
+                on-chip UART [set ::channel] has RTS/CTS flow control
+                that is accessible on the target hardware."
+        }
+    }
+
+    cdl_interface CYGINT_HAL_DMA {
+        display     "Platform uses DMA"
+        flavor      bool
+        description "
+            This interface will be implemented if the specific
+            controller being used provides DMA and if DMA is
+            used on target hardware"
+    }
+
+    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+        display     "Variant IRQ priority defaults"
+        no_define
+        flavor      none
+        parent      CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+        description "
+            Interrupt priorities defined by Vybrid variant"
+        script vybrid_irq_scheme.cdl
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_VYBRID_OPTIONS {
+        display      "Build options"
+        flavor       none
+        no_define
+        description   "
+            Package specific build options including control over
+            compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_VYBRID_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Vybrid variant HAL package. These flags
+                are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_VYBRID_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the Vybrid variant HAL package. These flags
+                are removed from the set of global flags if present."
+        }
+    }
+}
+
+# EOF hal_cortexm_vybrid.cdl
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/cdl/vybrid_irq_scheme.cdl b/ecos/packages/hal/cortexm/vybrid/var/current/cdl/vybrid_irq_scheme.cdl
new file mode 100644
index 0000000..2e63a77
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/cdl/vybrid_irq_scheme.cdl
@@ -0,0 +1,138 @@
+##==========================================================================
+##
+##      vybrid_irq_scheme.cdl
+##
+##      Cortex-M Freescale Vybrid IRQ configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011 Free Software Foundation, Inc.                  
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Antmicro Ltd <contact@antmicro.com>
+## Date:         2014-03-28
+## Based on respective definitions from /hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+#    cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
+#        display "Variant IRQ priority defaults"
+#        no_define
+#        flavor none
+#        parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
+#        description "
+#            Interrupt priorities defined by Vybrid variant"
+
+        cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP {
+            display       "Clock IRQ priority"
+            flavor        data
+            no_define
+            default_value 0xE0
+            description   "Set clock ISR priority. Default setting is lowest priority."
+            legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+
+        }
+
+        cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_UART {
+            display "UART IRQ priorities"
+            flavor none
+            no_define
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY_SP {
+                display "UART0 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART0
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY_SP {
+                display "UART1 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART1
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY_SP {
+                display "UART2 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART2
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY_SP {
+                display "UART3 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART3
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY_SP {
+                display "UART4 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART4
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+
+            cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY_SP {
+                display "UART5 interrupt priority"
+                flavor data
+                no_define
+                active_if CYGPKG_IO_SERIAL_FREESCALE_UART5
+                legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80
+                    0x90 0xA0 0xB0 0xC0 0xD0 0xE0 }
+                default_value 0x80
+            }
+        }
+
+#    }
+
+
+# EOF vybrid_irq_scheme.cdl
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_cache.h
new file mode 100644
index 0000000..4b007f2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_cache.h
@@ -0,0 +1,211 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/hal_cache.h
+// Date:         2014-03-28
+// Purpose:      Cache control API
+// Description:  The macros defined here provide the HAL APIs for handling
+//               cache control operations.
+//
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+#ifdef CYGINT_HAL_CACHE
+
+// Data cache
+#define HAL_DCACHE_SIZE                 (1024 * 16)    // Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE            32      // Size of a data cache line
+#define HAL_DCACHE_WAYS                 2       // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE                 (1024 * 16)    // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE            32      // Size of a cache line
+#define HAL_ICACHE_WAYS                 2       // Associativity of the cache
+
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+#include <cyg/hal/var_io.h>
+#include <cyg/hal/var_io_lmem.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE() HAL_CORTEXM_VYBRID_CACHE_PS_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE() HAL_CORTEXM_VYBRID_CACHE_PS_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL() HAL_CORTEXM_VYBRID_CACHE_PS_INVALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC() HAL_CORTEXM_VYBRID_CACHE_PS_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL() HAL_CORTEXM_VYBRID_CACHE_PS_CLEAR()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)                         \
+    CYG_MACRO_START                                            \
+        (_state_) = HAL_CORTEXM_VYBRID_CACHE_PS_IS_ENABLED(); \
+    CYG_MACRO_END
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                  \
+            HAL_CORTEXM_VYBRID_CACHE_PS_INVALIDATE(_base_, _size_)
+
+// Write dirty cache lines to memory and invalidate the cache entries
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )                  \
+            HAL_CORTEXM_VYBRID_CACHE_PS_CLR(_base_, _size_)
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE() HAL_CORTEXM_VYBRID_CACHE_PC_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE() HAL_CORTEXM_VYBRID_CACHE_PC_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL() HAL_CORTEXM_VYBRID_CACHE_PC_INVALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC() HAL_CORTEXM_VYBRID_CACHE_PC_SYNC()
+
+// Purge contents of data cache
+#define HAL_ICACHE_PURGE_ALL() HAL_CORTEXM_VYBRID_CACHE_PC_CLEAR()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)                        \
+    CYG_MACRO_START                                           \
+        (_state_) = HAL_CORTEXM_VYBRID_CACHE_PC_IS_ENABLED(); \
+    CYG_MACRO_END
+
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )                  \
+            HAL_CORTEXM_VYBRID_CACHE_PC_INVALIDATE(_base_, _size_)
+
+#else // CYGINT_HAL_CACHE
+
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+    CYG_MACRO_START                    \
+    (_state_) = 0;                     \
+    CYG_MACRO_END
+
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+    CYG_MACRO_START                    \
+        (_state_) = 0;                 \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+#endif // CYGINT_HAL_CACHE
+
+// End of hal_cache.h
+#endif // CYGONCE_HAL_CACHE_H
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_diag.h
new file mode 100644
index 0000000..c1f10df
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_diag.h
@@ -0,0 +1,92 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/hal_diag.h
+// Date:         2014-03-28
+// Purpose:      HAL diagnostics
+// Description: 
+// Usage:        #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) //VYBRID defined as 1
+
+#define HAL_DIAG_INIT()          hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void hal_plf_diag_init(void);
+__externC void hal_plf_diag_putc(char);
+__externC cyg_uint8 hal_plf_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_plf_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc()
+# endif
+
+#endif
+
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h
new file mode 100644
index 0000000..d10ccc2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+#endif
+
+
+#define CYGMEM_REGION_sram_l (0x1f800000)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCML)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x1f000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_OCRAM)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x3f800000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCMU)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi
new file mode 100644
index 0000000..d634d52
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi
@@ -0,0 +1,37 @@
+// eCos memory layout
+// modified for VYBRID
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+//------------CM4 OCRAM code
+
+MEMORY
+{
+	OCRAM : ORIGIN = 0x1f000000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_OCRAM-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCML  : ORIGIN = 0x1f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCML-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCMU  : ORIGIN = 0x3f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCMU-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+}
+
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (OCRAM, 0x1f000400, LMA_EQ_VMA)
+    SECTION_RELOCS (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (OCRAM, ALIGN (0x8),LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x1f000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x1f000000 + CYGHWR_HAL_CORTEXM_VYBRID_OCRAM);
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h
new file mode 100644
index 0000000..d10ccc2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+#endif
+
+
+#define CYGMEM_REGION_sram_l (0x1f800000)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCML)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x1f000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_OCRAM)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x3f800000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCMU)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi
new file mode 100644
index 0000000..01086a8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi
@@ -0,0 +1,39 @@
+// eCos memory layout
+// modified for VYBRID
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+//------------CM4 TCML code
+
+MEMORY
+{
+	OCRAM : ORIGIN = 0x1f000000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_OCRAM-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCML  : ORIGIN = 0x1f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCML-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCMU  : ORIGIN = 0x3f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCMU-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (TCML, 0x1f800400, LMA_EQ_VMA)
+    SECTION_RELOCS (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (TCML, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_sram (TCMU, 0x3f800000, LMA_EQ_VMA)
+    SECTION_bss (TCMU, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x1f800000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x3f800000 + 0x00007ff0);
+
+
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/plf_stub.h
new file mode 100644
index 0000000..f42f1ab
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/plf_stub.h
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008,
+//               2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/plf_stub.h
+// Date:         2014-03-28
+// Purpose:     Platform HAL stub support for Vybrid variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+#include <cyg/hal/cortexm_stub.h>           // architecture stub support
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_arch.h
new file mode 100644
index 0000000..8a81c94
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_arch.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      Vybrid variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/var_arch.h
+// Date:         2014-03-28
+// Purpose:      Vybrid variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/plf_arch.h>
+
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_intr.h
new file mode 100644
index 0000000..35938e5
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_intr.h
@@ -0,0 +1,249 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for Vybrid variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/var_intr.h
+// Date:         2014-03-28
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for Freescale Vybrid variants are
+//               defined here.
+//
+// Usage:        #include <cyg/hal/var_intr.h>
+//               However applications should include using <cyg/hal/hal_intr.h>
+//               instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+typedef enum {
+    CYGNUM_HAL_INTERRUPT_CPU2CPU_0
+    	= CYGNUM_HAL_INTERRUPT_EXTERNAL,  // CPU to CPU int 0
+    CYGNUM_HAL_INTERRUPT_CPU2CPU_1,       // CPU to CPU int 1
+    CYGNUM_HAL_INTERRUPT_CPU2CPU_2,       // CPU to CPU int 2
+    CYGNUM_HAL_INTERRUPT_CPU2CPU_3,       // CPU to CPU int 3
+    CYGNUM_HAL_INTERRUPT_SEMA4,           // Directed Cortex-M4(= SEMA4)
+    CYGNUM_HAL_INTERRUPT_MCM,             // Directed Cortex-M4(= MCM)
+    CYGNUM_HAL_INTERRUPT_DIRECTED1,       // Directed Cortex-M4
+    CYGNUM_HAL_INTERRUPT_DIRECTED2,       // Directed Cortex-M4
+    CYGNUM_HAL_INTERRUPT_DMA0,            // DMA Channel 0 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA0_ERROR,      // DMA Channel 0 Error int
+    CYGNUM_HAL_INTERRUPT_DMA1,            // DMA Channel 1 Transfer Complete
+    CYGNUM_HAL_INTERRUPT_DMA1_ERROR,      // DMA Channel 1 Error int
+    CYGNUM_HAL_INTERRUPT_RESERVED_00,
+    CYGNUM_HAL_INTERRUPT_RESERVED_01,
+    CYGNUM_HAL_INTERRUPT_MSCM_ECC0,       // Error Correction and Control 0
+    CYGNUM_HAL_INTERRUPT_MSCM_ECC1,       // Error Correction and Control 1
+    CYGNUM_HAL_INTERRUPT_CSU_ALARM,       // CSU interrupt
+    CYGNUM_HAL_INTERRUPT_RESERVED_02,
+    CYGNUM_HAL_INTERRUPT_MSCM_ACTZS,      // Miscellaneous System Control Module - TrustZone Security
+    CYGNUM_HAL_INTERRUPT_RESERVED_03,
+    CYGNUM_HAL_INTERRUPT_WDOG_A5,         // WDOG A5 int
+    CYGNUM_HAL_INTERRUPT_WDOG_M4,         // WDOG M4 int
+    CYGNUM_HAL_INTERRUPT_WDOG_SNVS,       // TrustZone Watchdog
+    CYGNUM_HAL_INTERRUPT_CP1,             // CP1 Boot Fail
+    CYGNUM_HAL_INTERRUPT_QSPI0,           // QuadSPI0 int
+    CYGNUM_HAL_INTERRUPT_QSPI1,           // QuadSPI1 int
+    CYGNUM_HAL_INTERRUPT_DDRMC,           // SDRAM Memory Controller
+    CYGNUM_HAL_INTERRUPT_SDHC0,           // Secure Digital Host Controller 0
+    CYGNUM_HAL_INTERRUPT_SDHC1,           // Secure Digital Host Controller 1
+    CYGNUM_HAL_INTERRUPT_RESERVED_04,
+    CYGNUM_HAL_INTERRUPT_DCU0,            // Display Control Unit 0
+    CYGNUM_HAL_INTERRUPT_DCU1,            // Display Control Unit 1
+    CYGNUM_HAL_INTERRUPT_VIU,             // Video In Unit 
+    CYGNUM_HAL_INTERRUPT_RESERVED_05,
+    CYGNUM_HAL_INTERRUPT_RESERVED_06,
+    CYGNUM_HAL_INTERRUPT_RLE,             // Run Length Encoding (Decoder unit)
+    CYGNUM_HAL_INTERRUPT_SEG_LCD,         // LCD Controller
+    CYGNUM_HAL_INTERRUPT_RESERVED_07,
+    CYGNUM_HAL_INTERRUPT_RESERVED_08,
+    CYGNUM_HAL_INTERRUPT_PIT,             // Periodic interrupt timer
+    CYGNUM_HAL_INTERRUPT_LPT0,            // LPTimer0
+    CYGNUM_HAL_INTERRUPT_RESERVED_09,
+    CYGNUM_HAL_INTERRUPT_FLXT0,           // FlexTimer 0
+    CYGNUM_HAL_INTERRUPT_FLXT1,           // FlexTimer 1
+    CYGNUM_HAL_INTERRUPT_FLXT2,           // FlexTimer 2
+    CYGNUM_HAL_INTERRUPT_FLXT3,           // FlexTimer 3
+    CYGNUM_HAL_INTERRUPT_RESERVED_10,
+    CYGNUM_HAL_INTERRUPT_RESERVED_11,
+    CYGNUM_HAL_INTERRUPT_RESERVED_12,
+    CYGNUM_HAL_INTERRUPT_RESERVED_13,
+    CYGNUM_HAL_INTERRUPT_USBPHY0,         // USB PHY 0
+    CYGNUM_HAL_INTERRUPT_USBPHY1,         // USB PHY 1
+    CYGNUM_HAL_INTERRUPT_RESERVED_14,
+    CYGNUM_HAL_INTERRUPT_ADC0,            // AD Converter 0
+    CYGNUM_HAL_INTERRUPT_ADC1,            // AD Converter 1
+    CYGNUM_HAL_INTERRUPT_DAC0,            // DA Converter 0
+    CYGNUM_HAL_INTERRUPT_DAC1,            // DA Converter 1
+    CYGNUM_HAL_INTERRUPT_RESERVED_15,
+    CYGNUM_HAL_INTERRUPT_FLXCAN0,         // FlexCAN 0
+    CYGNUM_HAL_INTERRUPT_FLXCAN1,         // FlexCAN 1
+    CYGNUM_HAL_INTERRUPT_RESERVED_16,
+    CYGNUM_HAL_INTERRUPT_UART0_RX_TX,     // UART0 Controller
+    CYGNUM_HAL_INTERRUPT_UART1_RX_TX,     // UART1 Controller
+    CYGNUM_HAL_INTERRUPT_UART2_RX_TX,     // UART2 Controller
+    CYGNUM_HAL_INTERRUPT_UART3_RX_TX,     // UART3 Controller
+    CYGNUM_HAL_INTERRUPT_UART4_RX_TX,     // UART4 Controller
+    CYGNUM_HAL_INTERRUPT_UART5_RX_TX,     // UART5 Controller
+    CYGNUM_HAL_INTERRUPT_SPI0,            // SPI0
+    CYGNUM_HAL_INTERRUPT_SPI1,            // SPI1
+    CYGNUM_HAL_INTERRUPT_SPI2,            // SPI2
+    CYGNUM_HAL_INTERRUPT_SPI3,            // SPI3
+    CYGNUM_HAL_INTERRUPT_I2C0,            // I2C0
+    CYGNUM_HAL_INTERRUPT_I2C1,            // I2C1
+    CYGNUM_HAL_INTERRUPT_I2C2,            // I2C2
+    CYGNUM_HAL_INTERRUPT_I2C3,            // I2C3
+    CYGNUM_HAL_INTERRUPT_USBC0,           // USB 0 Controller
+    CYGNUM_HAL_INTERRUPT_USBC1,           // USB 1 Controller
+    CYGNUM_HAL_INTERRUPT_RESERVED_17,
+    CYGNUM_HAL_INTERRUPT_ENET0,           // Ethernet MAC 0
+    CYGNUM_HAL_INTERRUPT_ENET1,           // Ethernet MAC 1
+    CYGNUM_HAL_INTERRUPT_1588_0,          // IEEE 1588 T0
+    CYGNUM_HAL_INTERRUPT_1588_1,          // IEEE 1588 T1
+    CYGNUM_HAL_INTERRUPT_ENET_SWI,        // Ethernet L2 swich
+    CYGNUM_HAL_INTERRUPT_NFC,             // Nand Flash Controller
+    CYGNUM_HAL_INTERRUPT_SAI0,            // Synchronous Audio Interface 0
+    CYGNUM_HAL_INTERRUPT_SAI1,            // Synchronous Audio Interface 1
+    CYGNUM_HAL_INTERRUPT_SAI2,            // Synchronous Audio Interface 2
+    CYGNUM_HAL_INTERRUPT_SAI3,            // Synchronous Audio Interface 3
+    CYGNUM_HAL_INTERRUPT_ESAI_BIFIFO,     // Enhanced Serial Audio Interface Bus Interface and FIFO
+    CYGNUM_HAL_INTERRUPT_SPDIF,           // Sony/Philips Digital Interface
+    CYGNUM_HAL_INTERRUPT_ASRC,            // Audio Sample Rate Converter
+    CYGNUM_HAL_INTERRUPT_VREG,            // HVD Int
+    CYGNUM_HAL_INTERRUPT_WKPU0,           // Wake Up 0
+    CYGNUM_HAL_INTERRUPT_RESERVED_18,
+    CYGNUM_HAL_INTERRUPT_CCM,             // FXOSC ready int
+    CYGNUM_HAL_INTERRUPT_CCM_2,           // Logical OR of LRF of PLL1, PLL2, PLL3, PLL4
+    CYGNUM_HAL_INTERRUPT_SRC,             // System Reset Controller
+    CYGNUM_HAL_INTERRUPT_PDB,             // Programmable Delay Block
+    CYGNUM_HAL_INTERRUPT_EWM,             // External Watchdog Monitor
+    CYGNUM_HAL_INTERRUPT_RESERVED_19,
+    CYGNUM_HAL_INTERRUPT_RESERVED_20,
+    CYGNUM_HAL_INTERRUPT_RESERVED_21,
+    CYGNUM_HAL_INTERRUPT_RESERVED_22,
+    CYGNUM_HAL_INTERRUPT_RESERVED_23,
+    CYGNUM_HAL_INTERRUPT_RESERVED_24,
+    CYGNUM_HAL_INTERRUPT_RESERVED_25,
+    CYGNUM_HAL_INTERRUPT_RESERVED_26,
+    CYGNUM_HAL_INTERRUPT_GPIO0,           // GPIO PORT0 interrupts/ Wake-ups
+    CYGNUM_HAL_INTERRUPT_GPIO1,           // GPIO PORT1 interrupts/ Wake-ups
+    CYGNUM_HAL_INTERRUPT_GPIO2,           // GPIO PORT2 interrupts/ Wake-ups
+    CYGNUM_HAL_INTERRUPT_GPIO3,           // GPIO PORT3 interrupts/ Wake-ups
+    CYGNUM_HAL_INTERRUPT_GPIO4            // GPIO PORT4 interrupts/ Wake-ups
+} VybridExtInterrupt_e;
+
+
+// Ranges of usable interrupt sources
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX	CYGNUM_HAL_INTERRUPT_GPIO4
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX		 CYGNUM_HAL_INTERRUPT_GPIO4
+#define CYGNUM_HAL_ISR_COUNT          (CYGNUM_HAL_ISR_MAX + 1)
+
+#define CYGNUM_HAL_VSR_MIN            0
+#ifndef CYGNUM_HAL_VSR_MAX
+# define CYGNUM_HAL_VSR_MAX           (CYGNUM_HAL_VECTOR_SYS_TICK+ \
+                                       CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+
+#define CYGNUM_HAL_VSR_COUNT          (CYGNUM_HAL_VSR_MAX+1)
+
+//==========================================================================
+// Interrupt mask and config for variant-specific devices
+
+// PORT Pin interrupts
+
+#define CYGHWR_HAL_VYBRID_PIN_IRQ_VECTOR(__pin) \
+    (CYGNUM_HAL_INTERRUPT_PORTA + CYGHWR_HAL_VYBRID_PIN_PORT(__pin))
+
+//===========================================================================
+// Interrupt resources exported by HAL to device drivers
+
+// Export Interrupt vectors to serial driver.
+
+#define CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART0_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART1_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART2_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART3_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART4_RX_TX
+#define CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_UART5_RX_TX
+
+// Export Interrupt vectors to ENET driver.
+
+#define CYGNUM_FREESCALE_ENET0_1588_TIMER_INT_VECTOR \
+            CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER
+#define CYGNUM_FREESCALE_ENET0_TRANSMIT_INT_VECTOR   \
+            CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT
+#define CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR    \
+            CYGNUM_HAL_INTERRUPT_ENET_RECEIVE
+#define CYGNUM_FREESCALE_ENET0_ERROR_INT_VECTOR      \
+            CYGNUM_HAL_INTERRUPT_ENET_ERROR
+
+#define HAL_VAR_INTERRUPT_MASK( __vector ) CYG_EMPTY_STATEMENT
+#define HAL_VAR_INTERRUPT_UNMASK( __vector ) CYG_EMPTY_STATEMENT
+#define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up )  CYG_EMPTY_STATEMENT
+#define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) CYG_EMPTY_STATEMENT
+
+#define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) 				\
+{																		\
+    cyg_uint16 reg;                                                     \
+	if(__vector > 0 )													\
+	{																	\
+        HAL_READ_UINT16((CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_BASE + ((__vector - 1 )*2)), reg);\
+        reg |= (1 << CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_S);                                 \
+		HAL_WRITE_UINT16((CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_BASE + ((__vector - 1 )*2)), reg);\
+	}																	\
+}
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h
new file mode 100644
index 0000000..4e01990
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h
@@ -0,0 +1,753 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//===========================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/var_io.h
+// Date:         2014-03-28
+// Purpose:       Vybrid variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <pkgconf/hal_cortexm_vybrid.h>
+
+#include <cyg/hal/plf_io.h>
+
+//===========================================================================
+// Cortex-M architecture
+//---------------------------------------------------------------------------
+//---------------------------------------------------------------------------
+// Cortex-M architecture overrides
+//---------------------------------------------------------------------------
+// VTOR - Vector Table Offset Register
+
+#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
+#ifdef CYG_HAL_VTOR_ADRESS
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM CYG_HAL_VTOR_ADRESS
+#else
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM 0x1f800000
+#endif
+#endif
+
+//===========================================================================
+// Vybrid Memory layout
+//---------------------------------------------------------------------------
+#define CYGHWR_HAL_VYBRID_OCRAM1_BASE   0x3f040000
+#define CYGHWR_HAL_VYBRID_OCRAM1_SIZE   0x0003ffff
+
+//===========================================================================
+// Vybrid Peripherals
+//---------------------------------------------------------------------------
+//---------------------------------------------------------------------------
+// MSCM - Miscellaneous System Control Module
+#define CYGHWR_HAL_VYBRID_MSCM_BASE                     0x40001000
+#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE                  (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x000)
+#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE_PERSONALITY_M    0xFFFFFF00
+#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE_PERSONALITY_S    8
+#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE_RYPZ_M           0x000000FF
+#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE_RYPZ_S           0
+#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM                   (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x004)
+#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM_CPN_M             0x00000001
+#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM_CPN_S             0
+#define CYGHWR_HAL_VYBRID_MSCM_CPxMASTER                (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x008)
+#define CYGHWR_HAL_VYBRID_MSCM_CPxMASTER_PPN_M          0x0000001f
+#define CYGHWR_HAL_VYBRID_MSCM_CPxMASTER_PPN_S          0
+#define CYGHWR_HAL_VYBRID_MSCM_CPxCOUNT                 (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x00c)
+#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM_PCNT_M            0x00000001
+#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM_PCNT_S            0
+#define CYGHWR_HAL_VYBRID_MSCM_CPxCFG0                  (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x010)
+#define CYGHWR_HAL_VYBRID_MSCM_CPxCFG1                  (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x014)
+#define CYGHWR_HAL_VYBRID_MSCM_CPxCFG2                  (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x018)
+#define CYGHWR_HAL_VYBRID_MSCM_CPxCFG3                  (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x01c)
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR                  (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x800)
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT0_M           0x00000001
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT0_S           0
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT1_M           0x00000002
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT1_S           1
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT2_M           0x00000004
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT2_S           2
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT3_M           0x00000008
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT3_S           3
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR                  (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x804)
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT0_M           0x00000001
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT0_S           0
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT1_M           0x00000002
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT1_S           1
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT2_M           0x00000004
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT2_S           2
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT3_M           0x00000008
+#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT3_S           3
+#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR                  (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x820)
+#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_INTID_M          0x00000003
+#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_INTID_S          0
+#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_CPUTL_M          0x00030000
+#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_CPUTL_S          16
+#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_TLF_M            0x03000000
+#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_TLF_S            24
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_BASE             (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x880)
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_M          0x0002
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_S          0
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP0En_M          0x0001
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP0En_S          1
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_RO_M             0x8000
+#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_RO_S             15
+
+__externC int hal_get_core_num(void);
+
+//---------------------------------------------------------------------------
+// SEMA4 - IPS Semaphores
+// SEMA4 - Peripheral register structure
+typedef volatile struct cyghwr_hal_vybrid_sema4_s
+{
+    cyg_uint8   gate[16];
+    cyg_uint8   reserved0[50];
+    cyg_uint16  cp0ine;
+    cyg_uint8   reserved1[6];
+    cyg_uint16  cp1ine;
+    cyg_uint8   reserved2[54];
+    cyg_uint16  cp0ntf;
+    cyg_uint8   reserved3[6];
+    cyg_uint16  cp1ntf;
+    cyg_uint8   reserved4[118];
+    cyg_uint16  rstgt;
+    cyg_uint8   reserved5[2];
+    cyg_uint16  rstntf;
+} cyghwr_hal_vybrid_sema4_t;
+
+#define CYGHWR_HAL_VYBRID_SEMA4_GATE_GTFSM_M       0x03
+#define CYGHWR_HAL_VYBRID_SEMA4_P ((cyghwr_hal_vybrid_sema4_t *) 0x4001d000)
+
+//---------------------------------------------------------------------------
+// CCM - Clock Controller Module
+// CCM - Peripheral register structure
+typedef volatile struct cyghwr_hal_vybrid_ccm_s {
+    cyg_uint32 ccr;           // 
+    cyg_uint32 csr;           // 
+    cyg_uint32 ccsr;          // 
+    cyg_uint32 cacrr;         // 
+    cyg_uint32 cscmr1;        // 
+    cyg_uint32 cscdr1;        // 
+    cyg_uint32 cscdr2;        // 
+    cyg_uint32 cscdr3;        // 
+    cyg_uint32 cscmr2;        // 
+    cyg_uint32 reserved0;     //
+    cyg_uint32 ctor;          // 
+    cyg_uint32 clpcr;         // 
+    cyg_uint32 cisr;          // 
+    cyg_uint32 cimr;          // 
+    cyg_uint32 ccosr;         // 
+    cyg_uint32 cgpr;          // 
+    cyg_uint32 ccgr0;         // 
+    cyg_uint32 ccgr1;         // 
+    cyg_uint32 ccgr2;         // 
+    cyg_uint32 ccgr3;         // 
+    cyg_uint32 ccgr4;         // 
+    cyg_uint32 ccgr5;         // 
+    cyg_uint32 ccgr6;         // 
+    cyg_uint32 ccgr7;         // 
+    cyg_uint32 ccgr8;         // 
+    cyg_uint32 ccgr9;         // 
+    cyg_uint32 ccgr10;        // 
+    cyg_uint32 ccgr11;        // 
+    cyg_uint32 cmeor0;        // 
+    cyg_uint32 cmeor1;        // 
+    cyg_uint32 cmeor2;        // 
+    cyg_uint32 cmeor3;        // 
+    cyg_uint32 cmeor4;        // 
+    cyg_uint32 cmeor5;        // 
+    cyg_uint32 cppdsr;        // 
+    cyg_uint32 ccowr;         // 
+    cyg_uint32 ccpgr0;        // 
+    cyg_uint32 ccpgr1;        // 
+    cyg_uint32 ccpgr2;        // 
+    cyg_uint32 ccpgr3;        // 
+
+} cyghwr_hal_vybrid_ccm_t;
+
+
+#define CYGHWR_HAL_VYBRID_CCM_P ((cyghwr_hal_vybrid_ccm_t *) 0x4006B000)
+
+// CCR Fields
+#define CYGHWR_HAL_VYBRID_CCM_CCR_FIRC_M				0x00010000
+#define CYGHWR_HAL_VYBRID_CCM_CCR_FIRC_S				16
+#define CYGHWR_HAL_VYBRID_CCM_CCR_FXOSC_EN_M			0x00001000
+#define CYGHWR_HAL_VYBRID_CCM_CCR_FXOSC_EN_S			12
+#define CYGHWR_HAL_VYBRID_CCM_CCR_OSCNT_M				0x000000ff
+#define CYGHWR_HAL_VYBRID_CCM_CCR_OSCNT_S				0
+
+// CSR Fields
+#define CYGHWR_HAL_VYBRID_CCM_CSR_FXOSC_RDY_M			0x00000020
+#define CYGHWR_HAL_VYBRID_CCM_CSR_FXOSC_RDY_S			5
+
+
+// CACRR Bit Fields
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_FLEX_CLK_DIV_M      0x1C00000
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_FLEX_CLK_DIV_S      22
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL6_CLK_DIV_M      0x0200000
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL6_CLK_DIV_S      21
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL3_CLK_DIV_M      0x0100000
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL3_CLK_DIV_S      20
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL1_PFD_CLK_DIV_M  0x0030000
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL1_PFD_CLK_DIV_S  16
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_IPG_CLK_DIV_M       0x0001800
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_IPG_CLK_DIV_S       11
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL4_CLK_DIV_M      0x00001C0
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL4_CLK_DIV_S      6
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_BUS_CLK_DIV_M       0x0000038
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_BUS_CLK_DIV_S       3
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_ARM_CLK_DIV_M       0x0000007
+#define CYGHWR_HAL_VYBRID_CCM_CACRR_ARM_CLK_DIV_S       0
+
+// CCSR Bit Fields
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD4_EN_M       0x80000000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD4_EN_S       31
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD3_EN_M       0x40000000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD3_EN_S       30
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD2_EN_M       0x20000000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD2_EN_S       29
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD1_EN_M       0x10000000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD1_EN_S       28
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_DAP_EN_M     	  	0x01000000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_DAP_EN_S 	    	24
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD_CLK_SEL_M  	0x00380000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD_CLK_SEL_S  	19
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD_CLK_SEL_M	0x00070000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD_CLK_SEL_S	16
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD4_EN_M       0x00008000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD4_EN_S       15
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD3_EN_M       0x00004000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD3_EN_S       14
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD2_EN_M       0x00002000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD2_EN_S       13
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD1_EN_M       0x00001000
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD1_EN_S       12
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD4_EN_M       0x00000800
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD4_EN_S       11
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD3_EN_M       0x00000400
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD3_EN_S       10
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD2_EN_M       0x00000200
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD2_EN_S       9
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD1_EN_M       0x00000100
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD1_EN_S       8
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_DDRC_CLK_SEL_M       0x00000040
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_DDRC_CLK_SEL_S       6
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_FAST_CLK_SEL_M       0x00000020
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_FAST_CLK_SEL_S       5
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_SLOW_CLK_SEL_M       0x00000010
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_SLOW_CLK_SEL_S       4
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_SYS_CLK_SEL_M        0x00000007
+#define CYGHWR_HAL_VYBRID_CCM_CCSR_SYS_CLK_SEL_S        0
+
+
+// CSCMR1 Bit Fields
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_DCU1_CLK_SEL_M      0x20000000
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_DCU1_CLK_SEL_S      29
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_DCU0_CLK_SEL_M      0x10000000
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_DCU0_CLK_SEL_S      28
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_QSPI1_CLK_SEL_M     0x03000000
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_QSPI1_CLK_SEL_S     24
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_QSPIO_CLK_SEL_M     0x00C00000
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_QSPIO_CLK_SEL_S     22
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESAI_CLK_SEL_M      0x00300000
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESAI_CLK_SEL_S      20
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESDHC1_CLK_SEL_M    0x000C0000
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESDHC1_CLK_SEL_S    18
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESDHC0_CLK_SEL_M    0x00030000
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESDHC0_CLK_SEL_S    16
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_NFC_CLK_SEL_M       0x00003000
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_NFC_CLK_SEL_S       12
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_VADC_CLK_SEL_M      0x00000300
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_VADC_CLK_SEL_S      8
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI3_CLK_SEL_M      0x000000C0
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI3_CLK_SEL_S      6
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI2_CLK_SEL_M      0x00000030
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI2_CLK_SEL_S      4
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI1_CLK_SEL_M      0x0000000C
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI1_CLK_SEL_S      2
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI0_CLK_SEL_M      0x00000003
+#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI0_CLK_SEL_S      0
+
+//---------------------------------------------------------------------------
+// FTM - Flex Timer Module 
+typedef volatile struct cyghwr_hal_vybrid_ftm_chnl_s {
+	cyg_uint32 sc;
+	cyg_uint32 v;	
+}cyghwr_hal_vybrid_ftm_chnl_t;
+
+	
+typedef volatile struct cyghwr_hal_vybrid_ftm_s {
+	cyg_uint32 sc;
+	cyg_uint32 cnt;
+	cyg_uint32 mod;
+	cyghwr_hal_vybrid_ftm_chnl_t c[8];	
+	cyg_uint32 cntin;
+	cyg_uint32 status;
+	cyg_uint32 mode;
+	cyg_uint32 sync;
+	cyg_uint32 outinit;
+	cyg_uint32 outmask;
+	cyg_uint32 combine;
+	cyg_uint32 deadtime;
+	cyg_uint32 exttrig;
+	cyg_uint32 pol;
+	cyg_uint32 fms;
+	cyg_uint32 filter;
+	cyg_uint32 fltctrl;
+	cyg_uint32 qdctrl;
+	cyg_uint32 conf;
+	cyg_uint32 fltpol;
+	cyg_uint32 synconf;
+	cyg_uint32 invctrl;
+	cyg_uint32 swoctrl;
+	cyg_uint32 pwmload;	
+} cyghwr_hal_vybrid_ftm_t;
+
+
+#define CYGHWR_HAL_VYBRID_FTM0_P ((cyghwr_hal_vybrid_ftm_t *)0x40038000)
+#define CYGHWR_HAL_VYBRID_FTM1_P ((cyghwr_hal_vybrid_ftm_t *)0x40039000)
+#define CYGHWR_HAL_VYBRID_FTM2_P ((cyghwr_hal_vybrid_ftm_t *)0x400b8000)
+#define CYGHWR_HAL_VYBRID_FTM3_P ((cyghwr_hal_vybrid_ftm_t *)0x400b9000)
+
+
+//---------------------------------------------------------------------------
+// ANADIG - Analog components control digital interface
+// ANADIG - Peripheral register structure
+
+// The ANADIG module has a very wide memory layout.
+// Between each register is a 12 bytes free space. Therefore typical implementation
+// of this module as structure is wasteful.
+
+#define CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR              0x40050000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL              (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x270)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_SS                (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x280)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_NUM               (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x290)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_DENOM             (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x2a0)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD               (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x2b0)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL              (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x30)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_SS                (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x40)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_NUM               (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x50)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_DENOM             (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x60)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD               (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x100)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL              (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x10)
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD               (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x60)
+
+// PLL1_CTRL Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_LOCK_M           0x80000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_LOCK_S           31
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_PFD_OFFSET_EN_M  0x00040000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_PFD_OFFSET_EN_S  18
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DITHER_ENABLE_M  0x00020000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DITHER_ENABLE_S  17
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_BYPASS_M         0x00010000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_BYPASS_S         16
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_BYPASS_CLK_SRC_M 0x00004000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_BYPASS_CLK_SRC_S 14
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_ENABLE_M         0x00002000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_ENABLE_S         13
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_POWERDOWN_M      0x00001000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_POWERDOWN_S      12
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DIV_SELECT_M     0x00000002
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DIV_SELECT_S     1
+
+// PLL1_NUM Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_NUM_M                 0x7FFFFFFF
+
+// PLL1_DENOM Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_DENOM_M               0x7FFFFFFF
+
+// PLL2_PFD Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_CLKGATE_M    0x80000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_CLKGATE_S    31
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_STABLE_M     0x40000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_STABLE_S     30
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_FRAC_M       0x3F000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_FRAC_S       24
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_CLKGATE_M    0x00800000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_CLKGATE_S    23
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_STABLE_M     0x00400000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_STABLE_S     22
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_FRAC_M       0x003F0000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_FRAC_S       16
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_CLKGATE_M    0x00008000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_CLKGATE_S    15
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_STABLE_M     0x00004000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_STABLE_S     14
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_FRAC_M       0x00003F00
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_FRAC_S       8
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_CLKGATE_M    0x00000080
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_CLKGATE_S    7
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_STABLE_M     0x00000040
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_STABLE_S     6
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_FRAC_M       0x0000003F
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_FRAC_S       0
+
+// PLL2_CTRL Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_LOCK_M           0x80000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_LOCK_S           31
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_PFD_OFFSET_EN_M  0x00040000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_PFD_OFFSET_EN_S  18
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DITHER_ENABLE_M  0x00020000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DITHER_ENABLE_S  17
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_M         0x00010000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_S         16
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_CLK_SRC_M 0x00004000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_CLK_SRC_S 14
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_ENABLE_M         0x00002000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_ENABLE_S         13
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_POWERDOWN_M      0x00001000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_POWERDOWN_S      12
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M     0x00000002
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_S     1
+
+// PLL2_NUM Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_NUM_M                 0x7FFFFFFF
+
+// PLL2_DENOM Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_DENOM_M               0x7FFFFFFF
+
+// PLL2_PFD Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_CLKGATE_M    0x80000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_CLKGATE_S    31
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_STABLE_M     0x40000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_STABLE_S     30
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_FRAC_M       0x3F000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_FRAC_S       24
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_CLKGATE_M    0x00800000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_CLKGATE_S    23
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_STABLE_M     0x00400000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_STABLE_S     22
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_FRAC_M       0x003F0000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_FRAC_S       16
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_CLKGATE_M    0x00008000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_CLKGATE_S    15
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_STABLE_M     0x00004000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_STABLE_S     14
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_FRAC_M       0x00003F00
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_FRAC_S       8
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_CLKGATE_M    0x00000080
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_CLKGATE_S    7
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_STABLE_M     0x00000040
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_STABLE_S     6
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_FRAC_M       0x0000003F
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_FRAC_S       0
+
+// PLL3_CTRL Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_LOCK_M           0x80000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_LOCK_S           31
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_M         0x00010000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_S         16
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_CLK_SRC_M 0x00004000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_CLK_SRC_S 14
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_ENABLE_M         0x00002000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_ENABLE_S         13
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_POWER_M          0x00001000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_POWER_S          12
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_EN_USB_CLKS_M    0x00000040
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_EN_USB_CLKS_S    6
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_DIV_SELECT_M     0x00000002
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_DIV_SELECT_S     1
+
+// PLL3_PFD Bit Fields
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_CLKGATE_M    0x80000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_CLKGATE_S    31
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_STABLE_M     0x40000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_STABLE_S     30
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_FRAC_M       0x3F000000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_FRAC_S       24
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_CLKGATE_M    0x00800000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_CLKGATE_S    23
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_STABLE_M     0x00400000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_STABLE_S     22
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_FRAC_M       0x003F0000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_FRAC_S       16
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_CLKGATE_M    0x00008000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_CLKGATE_S    15
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_STABLE_M     0x00004000
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_STABLE_S     14
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_FRAC_M       0x00003F00
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_FRAC_S       8
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_CLKGATE_M    0x00000080
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_CLKGATE_S    7
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_STABLE_M     0x00000040
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_STABLE_S     6
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_FRAC_M       0x0000003F
+#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_FRAC_S       0
+
+//---------------------------------------------------------------------------
+// Clock distribution
+// The following encodes the control register and clock bit number
+// into clock configuration descriptor (CLKCD).
+#define CYGHWR_HAL_VYBRID_CCM_CCGR(__reg,__cg) (((__reg) & 0x0F) + ((((__cg - (__reg * 16)) * 2) << 8) & 0x1F00))
+
+// Macros to extract encoded values.
+#define CYGHWR_HAL_VYBRID_CCM_CCGR_REG(__val) (((__val) & 0x0F))
+#define CYGHWR_HAL_VYBRID_CCM_CCGR_BIT(__val) (((__val) >> 8) & 0x1F)
+
+// Functions and macros to enable/disable clocks.
+#define CYGHWR_HAL_CCGR_NONE (0xFFFFFFFF)
+__externC void hal_clock_enable(cyg_uint32 ccgr);
+__externC void hal_clock_disable(cyg_uint32 ccgr);
+
+#define CYGHWR_HAL_CLOCK_ENABLE(__ccgr) hal_clock_enable(__ccgr)
+#define CYGHWR_HAL_CLOCK_DISABLE(__ccgr) hal_clock_disable(__ccgr)
+#include <cyg/hal/var_io_clkgat.h>
+
+
+//---------------------------------------------------------------------------
+// PORT - Peripheral register structure
+
+typedef volatile struct cyghwr_hal_vybrid_port_s {
+    cyg_uint32 pcr[32];      // Pin Control Register n, array
+    cyg_uint8 reserved0[24];
+    cyg_uint32 isfr;         // Interrupt Status Flag Register
+    cyg_uint8 reserved1[28];
+    cyg_uint32 dfer;         // Digital Filter Enable Register
+    cyg_uint32 dfcr;         // Digital Filter Clock Register
+    cyg_uint32 dfwr;         // Digital Filter Width Register
+} cyghwr_hal_vybrid_port_t;
+
+
+// PORT - Peripheral instance base addresses
+#define CYGHWR_HAL_VYBRID_PORTA_P  ((cyghwr_hal_vybrid_port_t *)0x40049000)
+#define CYGHWR_HAL_VYBRID_PORTB_P  ((cyghwr_hal_vybrid_port_t *)0x4004A000)
+#define CYGHWR_HAL_VYBRID_PORTC_P  ((cyghwr_hal_vybrid_port_t *)0x4004B000)
+#define CYGHWR_HAL_VYBRID_PORTD_P  ((cyghwr_hal_vybrid_port_t *)0x4004C000)
+#define CYGHWR_HAL_VYBRID_PORTE_P  ((cyghwr_hal_vybrid_port_t *)0x4004D000)
+#define CYGHWR_HAL_VYBRID_PORTF_P  ((cyghwr_hal_vybrid_port_t *)0x4004E000)
+
+enum {
+    CYGHWR_HAL_VYBRID_PORTA, CYGHWR_HAL_VYBRID_PORTB,
+    CYGHWR_HAL_VYBRID_PORTC, CYGHWR_HAL_VYBRID_PORTD,
+    CYGHWR_HAL_VYBRID_PORTE, CYGHWR_HAL_VYBRID_PORTF
+};
+
+#define CYGHWR_HAL_VYBRID_PORT(__port, __reg) \
+        (CYGHWR_HAL_VYBRID_PORT##__port##_P)->__reg
+
+// PCR Bit Fields TODO To remove
+#define CYGHWR_HAL_VYBRID_PORT_PCR_PS_M          0x1
+#define CYGHWR_HAL_VYBRID_PORT_PCR_PS_S          0
+#define CYGHWR_HAL_VYBRID_PORT_PCR_PE_M          0x2
+#define CYGHWR_HAL_VYBRID_PORT_PCR_PE_S          1
+#define CYGHWR_HAL_VYBRID_PORT_PCR_SRE_M         0x4
+#define CYGHWR_HAL_VYBRID_PORT_PCR_SRE_S         2
+#define CYGHWR_HAL_VYBRID_PORT_PCR_PFE_M         0x10
+#define CYGHWR_HAL_VYBRID_PORT_PCR_PFE_S         4
+#define CYGHWR_HAL_VYBRID_PORT_PCR_ODE_M         0x20
+#define CYGHWR_HAL_VYBRID_PORT_PCR_ODE_S         5
+#define CYGHWR_HAL_VYBRID_PORT_PCR_DSE_M         0x40
+#define CYGHWR_HAL_VYBRID_PORT_PCR_DSE_S         6
+#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_M         0x700
+#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_S         8	// VYBRID
+#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX(__val)    \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_PCR_MUX_S, __val)
+#define CYGHWR_HAL_VYBRID_PORT_PCR_LK_M          0x8000
+#define CYGHWR_HAL_VYBRID_PORT_PCR_LK_S          15
+#define CYGHWR_HAL_VYBRID_PORT_PCR_IRQC_M        0xF0000
+#define CYGHWR_HAL_VYBRID_PORT_PCR_IRQC_S        16
+#define CYGHWR_HAL_VYBRID_PORT_PCR_IRQC(__val)   \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_PCR_IRQC_S, __val)
+#define CYGHWR_HAL_VYBRID_PORT_PCR_ISF_M         0x1000000
+#define CYGHWR_HAL_VYBRID_PORT_PCR_ISF_S         24
+
+#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_ANALOG    0
+#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_DIS       0
+#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_GPIO      1
+
+#define CYGHWR_HAL_VYBRID_PORT_PCR_ISFR_CLEAR(__port, __pin) \
+        CYGHWR_HAL_VYBRID_PORT(__port, pcr[__pin]) |= BIT_(24)
+
+#define CYGHWR_HAL_VYBRID_PORT_ISFR_CLEAR(__port, __pin)     \
+        CYGHWR_HAL_VYBRID_PORT(__port, isfr) |= BIT_(__pin)
+
+
+
+#define CYGHWR_HAL_VYBRID_PIN_CFG(__port, __bit, __mux, __irqc, __cnf) \
+        ((CYGHWR_HAL_VYBRID_PORT##__port << 20) | ((__bit) << 27)      \
+         | CYGHWR_HAL_VYBRID_PORT_PCR_IRQC(__irqc)                     \
+         | CYGHWR_HAL_VYBRID_PORT_PCR_MUX(__mux) | (__cnf))
+
+#define CYGHWR_HAL_VYBRID_PIN(__port, __bit, __mux, __cnf) \
+        CYGHWR_HAL_VYBRID_PIN_CFG(__port, __bit, __mux, 0, __cnf)
+
+#define CYGHWR_HAL_VYBRID_PIN_PORT(__pin) (((__pin) >> 20) & 0x7)
+#define CYGHWR_HAL_VYBRID_PIN_BIT(__pin)  (((__pin) >> 27 ) & 0x1f)
+#define CYGHWR_HAL_VYBRID_PIN_FUNC(__pin) ((__pin) & 0x010f8777)
+#define CYGHWR_HAL_VYBRID_PIN_NONE (0xffffffff)
+
+// GPCLR Bit Fields
+#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWD_M      0xFFFF
+#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWD_S      0
+#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWD(__val) \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWD_S, __val)
+#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWE_M      0xFFFF0000
+#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWE_S      16
+#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWE(__val) \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWE_S, __val)
+// GPCHR Bit Fields
+#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWD_M      0xFFFF
+#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWD_S      0
+#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWD(__val) \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWD_S, __val)
+#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWE_M      0xFFFF0000
+#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWE_S      16
+#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWE(__val) \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWE_S, __val)
+// ISFR Bit Fields
+#define CYGHWR_HAL_VYBRID_PORT_ISFR_ISF_M        0xFFFFFFFF
+#define CYGHWR_HAL_VYBRID_PORT_ISFR_ISF_S        0
+#define CYGHWR_HAL_VYBRID_PORT_ISFR_ISF(__val)   \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_ISFR_ISF_S, __val)
+// DFER Bit Fields
+#define CYGHWR_HAL_VYBRID_PORT_DFER_DFE_M        0xFFFFFFFF
+#define CYGHWR_HAL_VYBRID_PORT_DFER_DFE_S        0
+#define CYGHWR_HAL_VYBRID_PORT_DFER_DFE(__val)   \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_DFER_DFE_S, __val)
+// DFCR Bit Fields
+#define CYGHWR_HAL_VYBRID_PORT_DFCR_CS_M         0x1
+#define CYGHWR_HAL_VYBRID_PORT_DFCR_CS_S         0
+// DFWR Bit Fields
+#define CYGHWR_HAL_VYBRID_PORT_DFWR_FILT_M       0x1F
+#define CYGHWR_HAL_VYBRID_PORT_DFWR_FILT_S       0
+#define CYGHWR_HAL_VYBRID_PORT_DFWR_FILT(__val)  \
+        VALUE_(CYGHWR_HAL_VYBRID_PORT_DFWR_FILT_S, __val)
+
+#ifndef __ASSEMBLER__
+
+// Pin configuration related functions
+__externC void  hal_set_pin_function(cyg_uint32 pin);
+__externC void  hal_dump_pin_function(cyg_uint32 pin);
+__externC void  hal_dump_pin_setting(cyg_uint32 pin);
+
+#endif
+
+#define HAL_SET_PINS(_pin_array) \
+CYG_MACRO_START \
+    const cyg_uint32 *_pin_p; \
+    for(_pin_p = &_pin_array[0]; \
+        _pin_p < &_pin_array[0] + sizeof(_pin_array)/sizeof(_pin_array[0]); \
+        hal_set_pin_function(*_pin_p++)); \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+// PMC Power Management Controller
+
+typedef volatile struct cyghwr_hal_vybrid_pmc_s {
+    cyg_uint8 lvdsc1;   // Low Voltage Detect Status and Control 1 Register
+    cyg_uint8 lvdsc2;   // Low Voltage Detect Status and Control 2 Register
+    cyg_uint8 regsc;    // Regulator Status and Control Register
+} cyghwr_hal_vybrid_pmc_t;
+
+// PMC base address
+#define CYGHWR_HAL_VYBRID_PMC_P  ((cyghwr_hal_vybrid_pmc_t *)0x4007D000)
+
+// LVDSC1 Bit Fields
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDV_M      0x3
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDV(__val) \
+        ((__val) & CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDV_M)
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDRE_M     0x10
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDRE_S     4
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDIE_M     0x20
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDIE_S     5
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDACK_M    0x40
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDACK_S    6
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDF_M      0x80
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDF_S      7
+// LVDSC2 Bit Fields
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWV_M      0x3
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWV(__val) \
+        ((__val) & CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWV_M)
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWIE_M     0x20
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWIE_S     5
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWACK_M    0x40
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWACK_S    6
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWF_M      0x80
+#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWF_S      7
+// REGSC Bit Fields
+#define CYGHWR_HAL_VYBRID_PMC_REGSC_BGBE_M       0x1
+#define CYGHWR_HAL_VYBRID_PMC_REGSC_BGBE_S       0
+#define CYGHWR_HAL_VYBRID_PMC_REGSC_REGONS_M     0x4
+#define CYGHWR_HAL_VYBRID_PMC_REGSC_REGONS_S     2
+#define CYGHWR_HAL_VYBRID_PMC_REGSC_ACKISO_M     0x8
+#define CYGHWR_HAL_VYBRID_PMC_REGSC_ACKISO_S     3
+#define CYGHWR_HAL_VYBRID_PMC_REGSC_BGEN_M       0x10
+#define CYGHWR_HAL_VYBRID_PMC_REGSC_BGEN_S       4
+
+
+//---------------------------------------------------------------------------
+// FlexBus
+#ifdef CYGPKG_HAL_CORTEXM_VYBRID_FLEXBUS
+# include <cyg/hal/var_io_flexbus.h>
+#endif
+
+//----------------------------------------------------------------------------
+// DDRMC - SDRAM controller
+#ifdef CYGPKG_HAL_CORTEXM_VYBRID_DDRMC
+# include <cyg/hal/var_io_ddrmc.h>
+#endif
+
+//---------------------------------------------------------------------------
+// GPIO
+#include <cyg/hal/var_io_gpio.h>
+
+//=============================================================================
+// DEVS:
+// Following macros may also be, and usually are borrowed by some device drivers.
+//-----------------------------------------------------------------------------
+#include <cyg/hal/var_io_devs.h>
+
+// End Peripherals
+
+// Some miscelaneous function prototypes
+// Clock related functions are in vybrid_clocking.c
+__externC void hal_start_clocks(void);
+__externC void hal_update_clock_var(void);
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+
+#endif // CYGONCE_HAL_VAR_IO_H
+
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_clkgat.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_clkgat.h
new file mode 100644
index 0000000..bd6348a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_clkgat.h
@@ -0,0 +1,67 @@
+#ifndef CYGONCE_HAL_VAR_IOCLKGAT_H
+#define CYGONCE_HAL_VAR_IOCLKGAT_H
+//===========================================================================
+//
+//      var_io_clkgat.h
+//
+//      Vybrid clock gating
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_clkgat.h
+// Date:         2014-03-28
+// Purpose:      Vybrid clock distribution macros
+// Description:
+// Usage:         This file is included by <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+//---------------------------------------------------------------------------
+// Clock distribution
+
+// Clock gating definitions
+#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART0 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 7)
+#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART1 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 8)
+#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART2 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 9)
+#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART3 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 10)
+#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART4 CYGHWR_HAL_VYBRID_CCM_CCGR(6, 105)
+#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART5 CYGHWR_HAL_VYBRID_CCM_CCGR(6, 106)
+
+
+#endif // CYGONCE_HAL_VAR_IOCLKGAT_H
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_devs.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_devs.h
new file mode 100644
index 0000000..64aefcf
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_devs.h
@@ -0,0 +1,173 @@
+#ifndef CYGONCE_HAL_VAR_IO_DEVS_H
+#define CYGONCE_HAL_VAR_IO_DEVS_H
+//===========================================================================
+//
+//      var_io_devs.h
+//
+//      Variant specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_devs.h
+// Date:         2014-03-28
+// Purpose:       Vybrid variant IO provided to various device drivers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h> //var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+
+//=============================================================================
+// DEVS:
+// Following macros may be, and usually are borrowed by some device drivers.
+
+// Peripheral clock [Hz];
+__externC cyg_uint32 hal_get_peripheral_clock(void);
+
+//-----------------------------------------------------------------------------
+// Freescale UART
+// Borrow some HAL resources to Freescale UART driver
+// UART  macros are used by both:
+//      src/hal_diag.c
+//      devs/serial/<version>/src/ser_freescale_uart.c
+
+#define CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE  0x40027000 
+#define CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE  0x40028000 
+#define CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE  0x40029000 
+#define CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE  0x4002A000 
+#define CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE  0x400A9000 
+#define CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE  0x400AA000 
+
+// UART Clock gating
+#define CYGHWR_IO_FREESCALE_UART0_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART0
+#define CYGHWR_IO_FREESCALE_UART1_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART1
+#define CYGHWR_IO_FREESCALE_UART2_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART2
+#define CYGHWR_IO_FREESCALE_UART3_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART3
+#define CYGHWR_IO_FREESCALE_UART4_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART4
+#define CYGHWR_IO_FREESCALE_UART5_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART5
+
+
+// UART PIN configuration
+// Note: May be overriden by plf_io.h
+
+#define CYGHWR_HAL_VYBRID_PORT_PIN_NONE CYGHWR_HAL_VYBRID_PIN_NONE
+
+#ifndef CYGHWR_IO_FREESCALE_UART0_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART1_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART1_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART1_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART2_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART3_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART4_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+#endif
+
+#ifndef CYGHWR_IO_FREESCALE_UART5_PIN_RX
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE
+#endif
+
+// Lend some HAL dependent functions to the UART serial device driver
+
+#ifndef __ASSEMBLER__
+
+# define CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) \
+        hal_freescale_uart_setbaud(__uart_p, _baud_)
+
+# define CYGHWR_IO_FREESCALE_UART_PIN(__pin) \
+        hal_set_pin_function(__pin)
+
+
+// Set baud rate
+__externC void hal_freescale_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+#endif
+//----------------------------------------------------------------------------
+// eDMA
+// Lend some eDMA macros to device driver that use DMA
+
+// Base address
+#define CYGHWR_HAL_FREESCALE_EDMA0_P  ((cyghwr_hal_freescale_edma_t *)0x40008000)
+// DMAMUX base addresses
+#define CYGHWR_HAL_FREESCALE_DMAMUX0_P ((cyghwr_hal_freescale_dmamux_t *) 0x40021000)
+#define CYGHWR_HAL_FREESCALE_DMAMUX1_P ((cyghwr_hal_freescale_dmamux_t *) 0x40022000)
+
+
+#define CYGHWR_IO_FREESCALE_EDMA0_P CYGHWR_HAL_FREESCALE_EDMA0_P
+#define CYGHWR_IO_FREESCALE_DMAMUX0_P CYGHWR_HAL_FREESCALE_DMAMUX0_P
+#define CYGHWR_IO_FREESCALE_DMAMUX1_P CYGHWR_HAL_FREESCALE_DMAMUX1_P
+
+//Clock distribution
+#define CYGHWR_IO_CLOCK_ENABLE(__ccgr) hal_clock_enable(__ccgr)
+
+
+#define CYGHWR_IO_FREESCALE_EDMA0_CLK   CYGHWR_HAL_KINETIS_SIM_SCGC_DMA
+#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0
+#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0
+#define CYGHWR_IO_FREESCALE_DMAMUX1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1
+//-----------------------------------------------------------------------------
+// end of var_io_devs.h
+#endif // CYGONCE_HAL_VAR_IO_DEVS_H
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h
new file mode 100644
index 0000000..b5e26bd
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h
@@ -0,0 +1,125 @@
+#ifndef CYGONCE_HAL_VAR_IO_GPIO_H
+#define CYGONCE_HAL_VAR_IO_GPIO_H
+//===========================================================================
+//
+//      var_io_gpio.h
+//
+//      Vybrid GPIO
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_devs.h
+// Date:         2014-03-28
+// Purpose:       Vybrid variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+//-----------------------------------------------------------------------------
+// VYBRID section for GPIO handling per pin operations are covered
+// as in VF61GS10 control of subsequent pins from ports e.g A,B,C is distributed between multiple registers
+//-----------------------------------------------------------------------------
+
+// the complete maps of available pads arranged with ascending adresses of 
+// corresponding IOMUX registers
+typedef enum vf61_rgpio_t{
+PTA6, PTA8, PTA9, PTA10,PTA11,PTA12,PTA16,PTA17,PTA18,PTA19,PTA20,
+PTA21,PTA22,PTA23,PTA24,PTA25,PTA26,PTA27,PTA28,PTA29,PTA30,PTA31,
+PTB0, PTB1, PTB2, PTB3, PTB4, PTB5, PTB6, PTB7, PTB8, PTB9, PTB10,
+PTB11,PTB12,PTB13,PTB14,PTB15,PTB16,PTB17,PTB18,PTB19,PTB20,PTB21,
+PTB22,PTC0, PTC1, PTC2, PTC3, PTC4, PTC5, PTC6, PTC7, PTC8, PTC9,
+PTC10,PTC11,PTC12,PTC13,PTC14,PTC15,PTC16,PTC17,PTD31,PTD30,PTD29,
+PTD28,PTD27,PTD26,PTD25,PTD24,PTD23,PTD22,PTD21,PTD20,PTD19,PTD18,
+PTD17,PTD16,PTD0, PTD1, PTD2, PTD3, PTD4, PTD5, PTD6, PTD7, PTD8,
+PTD9, PTD10,PTD11,PTD12,PTD13,PTB23,PTB24,PTB25,PTB26,PTB27,PTB28,
+PTC26,PTC27,PTC28,PTC29,PTC30,PTC31,PTE0, PTE1, PTE2, PTE3, PTE4,
+PTE5, PTE6, PTE7, PTE8, PTE9, PTE10,PTE11,PTE12,PTE13,PTE14,PTE15,
+PTE16,PTE17,PTE18,PTE19,PTE20,PTE21,PTE22,PTE23,PTE24,PTE25,PTE26,
+PTE27,PTE28,PTA7,NONE
+} vf61_rgpio;
+
+
+#define CYGHWR_HAL_VYBRID_RGPIO_BASE 0x40048000 //base for IOMUXC
+#define CYGHWR_HAL_VYBRID_GPIO_BASE 0x400ff000 //base for GPIO ports
+
+// GPIO pin control registers offsets
+#define CYGHWR_HAL_VYBRID_GPIO_PDOR 0x00
+#define CYGHWR_HAL_VYBRID_GPIO_PSOR 0x04
+#define CYGHWR_HAL_VYBRID_GPIO_PCOR 0x08
+#define CYGHWR_HAL_VYBRID_GPIO_PTOR 0x0c
+#define CYGHWR_HAL_VYBRID_GPIO_PDIR 0x10
+
+
+// gets port numer (0,1,2,3) from pin name 
+#define CYGHWR_HAL_VYBRID_GET_PORT(__pin) (vf61_rgpio)__pin >> 5
+
+// gets GPIO address from pin name
+#define CYGHWR_HAL_VYBRID_GET_GPIO(__pin) (CYGHWR_HAL_VYBRID_GPIO_BASE + 0x40*((vf61_rgpio)__pin >> 5))
+
+// gets bit location from pin name 
+#define CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin) (__pin-32*(__pin>>5))
+
+// gets IOMUXC address from pin name 
+#define CYGHWR_HAL_VYBRID_GET_IOMUXC(__pin) CYGHWR_HAL_VYBRID_RGPIO_BASE+(__pin<<2)
+
+// get pin status based onto pin name (returns non zero if pin is '1')
+#define CYGHWR_HAL_VYBRID_GPIO_GET_PIN(__pin) \
+	(*((volatile cyg_uint32 *)(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PDIR)) & (1 << CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin)))
+
+// set pin defined by name	
+#define CYGHWR_HAL_VYBRID_GPIO_SET_PIN(__pin) \
+	HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PSOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin))))
+
+// clear pin defined by name	
+#define CYGHWR_HAL_VYBRID_GPIO_CLEAR_PIN(__pin) \
+	HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PCOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin))))
+
+// toggle pin defined by name	
+#define CYGHWR_HAL_VYBRID_GPIO_TOGGLE_PIN(__pin) \
+	HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PTOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin))))
+
+// setup pin definition (mux, direction and so on_
+#define CYGHWR_HAL_VYBRID_PIN_SET_FUNCTION(__pin,__settings)\
+	HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_IOMUXC(__pin), __settings)
+
+//
+//-----------------------------------------------------------------------------
+// end of var_io_gpio.h
+#endif // CYGONCE_HAL_VAR_IO_GPIO_H
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_lmem.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_lmem.h
new file mode 100644
index 0000000..0f8f2d4
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_lmem.h
@@ -0,0 +1,254 @@
+#ifndef CYGONCE_HAL_VAR_IO_LMEM_H
+#define CYGONCE_HAL_VAR_IO_LMEM_H
+//===========================================================================
+//
+//      var_io_lmem.h
+//
+//      Vybrid Local memory controller specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2012 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_lmem.h
+// Date:         2014-03-28
+// Purpose:       Vybrid variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io_lmem.h>  // var_io.h includes this file
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+//----------------------------------------------------------------------------
+// LMEM - Local memory controller
+
+typedef volatile struct cyghwr_hal_vybrid_lmem_s {
+    cyg_uint32 ccr;    // PC bus Cache control register
+    cyg_uint32 clcr;   // PC bus Cache line control register
+    void *csar;        // PC bus Cache search address register
+    cyg_uint32 cvr;    // PC bus Cache read/write value register
+} cyghwr_hal_vybrid_lmem_t;
+
+#define CYGHWR_HAL_VYBRID_LMEM_PC_P  ((cyghwr_hal_vybrid_lmem_t *) 0xE0082000)
+#define CYGHWR_HAL_VYBRID_LMEM_PS_P  ((cyghwr_hal_vybrid_lmem_t *) 0xE0082800)
+
+// CCR Bit Fields
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_ENCACHE_M          0x00000001
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_ENWRBUF_M          0x00000002
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_PCCR2        	  0x00000004
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_PCCR3         	  0x00000008
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_INVW0_M            0x01000000
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW0_M           0x02000000
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_INVW1_M            0x04000000
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW1_M           0x08000000
+#define CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M               0x80000000
+
+//CLCR Bit Fields
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LGO_M             0x00000001
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_CACHEADDR_M       0x00000FFC
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_CACHEADDR_S       2
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_CACHEADDR(_ca_)   ((_ca_) << CYGHWR_HAL_VYBRID_LMEM_CLCR_CACHEADDR_S)
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_WSEL_M            0x00004000
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_TDSEL_M           0x00010000
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCIVB_M           0x00100000
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCIMB_M           0x00200000
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCWAY_M           0x00400000
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_M            0x03000000
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_S            24
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD(_cmd_)       ((_cmd_) << CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_S)
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_SRCH         0
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_INVAL        1
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_PUSH         2
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_CLR          3
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LADSEL_M          0x04000000
+#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LACC_M            0x08000000
+
+// CSAR Bit Fields
+#define CYGHWR_HAL_VYBRID_LMEM_CSAR_LGO_M             0x00000001
+#define CYGHWR_HAL_VYBRID_LMEM_CSAR_PHYADDR_M         0xFFFFFFFC
+#define CYGHWR_HAL_VYBRID_LMEM_CSAR_PHYADDR_S         2
+#define CYGHWR_HAL_VYBRID_LMEM_CSAR_PHYADDR(_adr_)    ((_adr_) << CYGHWR_HAL_VYBRID_LMEM_CSAR_PHYADDR_S)
+
+// CCVR Bit Fields
+#define CYGHWR_HAL_VYBRID_LMEM_CCVR_DATA_M            0xFFFFFFFF
+
+#define HAL_CORTEXM_VYBRID_CACHE_PC_ENABLE() \
+            hal_cortexm_vybrid_cache_enable(CYGHWR_HAL_VYBRID_LMEM_PC_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_ENABLE() \
+            hal_cortexm_vybrid_cache_enable(CYGHWR_HAL_VYBRID_LMEM_PS_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PC_DISABLE() \
+            hal_cortexm_vybrid_cache_disable(CYGHWR_HAL_VYBRID_LMEM_PC_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_DISABLE() \
+            hal_cortexm_vybrid_cache_disable(CYGHWR_HAL_VYBRID_LMEM_PS_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PC_INVALL() \
+            hal_cortexm_vybrid_cache_inval(CYGHWR_HAL_VYBRID_LMEM_PC_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_INVALL() \
+            hal_cortexm_vybrid_cache_inval(CYGHWR_HAL_VYBRID_LMEM_PS_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PC_SYNC() \
+            hal_cortexm_vybrid_cache_sync(CYGHWR_HAL_VYBRID_LMEM_PC_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_SYNC() \
+            hal_cortexm_vybrid_cache_sync(CYGHWR_HAL_VYBRID_LMEM_PS_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PC_CLEAR() \
+            hal_cortexm_vybrid_cache_clear(CYGHWR_HAL_VYBRID_LMEM_PC_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_CLEAR() \
+            hal_cortexm_vybrid_cache_clear(CYGHWR_HAL_VYBRID_LMEM_PS_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PC_IS_ENABLED() \
+            hal_cortexm_vybrid_cache_is_enabled(CYGHWR_HAL_VYBRID_LMEM_PC_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_IS_ENABLED() \
+            hal_cortexm_vybrid_cache_is_enabled(CYGHWR_HAL_VYBRID_LMEM_PS_P)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_SRCH(_base, _size_) \
+        hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_SRCH)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_INVALIDATE(_base, _size_) \
+        hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_INVAL)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_PUSH(_base, _size_) \
+        hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_PUSH)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PS_CLR(_base, _size_) \
+        hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PS_P, _base, _size_, \
+                                       CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_CLR)
+
+#define HAL_CORTEXM_VYBRID_CACHE_PC_INVALIDATE(_base, _size_) \
+        hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PC_P, _base, _size_, \
+                                       CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_INVAL)
+
+#define CYGHWR_HAL_VYBRID_CACHE_WAIT(_lmem_p)          \
+            while((_lmem_p)->ccr & CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M)
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_vybrid_cache_enable(cyghwr_hal_vybrid_lmem_t* lmem_p)
+{
+    lmem_p->ccr = ( CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M |
+                    CYGHWR_HAL_VYBRID_LMEM_CCR_INVW0_M |
+                    CYGHWR_HAL_VYBRID_LMEM_CCR_INVW1_M |
+                    CYGHWR_HAL_VYBRID_LMEM_CCR_ENCACHE_M |
+                    CYGHWR_HAL_VYBRID_LMEM_CCR_ENWRBUF_M
+                   );
+    CYGHWR_HAL_VYBRID_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_vybrid_cache_disable(cyghwr_hal_vybrid_lmem_t* lmem_p)
+{
+    lmem_p->ccr = 0;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_vybrid_cache_inval(cyghwr_hal_vybrid_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M |
+              CYGHWR_HAL_VYBRID_LMEM_CCR_INVW0_M |
+              CYGHWR_HAL_VYBRID_LMEM_CCR_INVW1_M
+              );
+    CYGHWR_HAL_VYBRID_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_vybrid_cache_store(cyghwr_hal_vybrid_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M |
+                     CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW0_M |
+                     CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW1_M
+                    );
+    CYGHWR_HAL_VYBRID_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_vybrid_cache_clear(cyghwr_hal_vybrid_lmem_t* lmem_p)
+{
+    lmem_p->ccr |= ( CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M |
+                    CYGHWR_HAL_VYBRID_LMEM_CCR_INVW0_M |
+                    CYGHWR_HAL_VYBRID_LMEM_CCR_INVW1_M |
+                    CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW0_M |
+                    CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW1_M
+                   );
+    CYGHWR_HAL_VYBRID_CACHE_WAIT(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_vybrid_cache_sync(cyghwr_hal_vybrid_lmem_t* lmem_p)
+{
+    hal_cortexm_vybrid_cache_store(lmem_p);
+    hal_cortexm_vybrid_cache_clear(lmem_p);
+}
+
+CYGBLD_FORCE_INLINE bool
+hal_cortexm_vybrid_cache_is_enabled(cyghwr_hal_vybrid_lmem_t* lmem_p)
+{
+    return lmem_p->ccr & CYGHWR_HAL_VYBRID_LMEM_CCR_ENCACHE_M;
+}
+
+
+CYGBLD_FORCE_INLINE void
+hal_cortexm_vybrid_cache_lines(cyghwr_hal_vybrid_lmem_t* lmem_p,
+                               void* addr_p, cyg_uint32 size,
+                               const cyg_uint32 oper)
+{
+    cyg_uint32 line_k;
+    line_k = (((cyg_uint32)addr_p & (HAL_DCACHE_LINE_SIZE-1)) + size) / HAL_DCACHE_LINE_SIZE + 1;
+
+    lmem_p->clcr = CYGHWR_HAL_VYBRID_LMEM_CLCR_LADSEL_M |
+                   CYGHWR_HAL_VYBRID_LMEM_CLCR_TDSEL_M  |
+                   CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD(oper);
+
+    addr_p = (void*)((((cyg_uint32) addr_p) & 0xfffffff0) |
+                          CYGHWR_HAL_VYBRID_LMEM_CLCR_LGO_M);
+    do {
+        lmem_p->csar = addr_p;
+        while(lmem_p->clcr & CYGHWR_HAL_VYBRID_LMEM_CLCR_LGO_M);
+        addr_p = (void*)(((cyg_uint32)addr_p) + HAL_DCACHE_LINE_SIZE);
+    } while(--line_k);
+}
+
+//-----------------------------------------------------------------------------
+// end of var_io_lmem.h
+#endif // CYGONCE_HAL_VAR_IO_LMEM_H
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/variant.inc b/ecos/packages/hal/cortexm/vybrid/var/current/include/variant.inc
new file mode 100644
index 0000000..c88a975
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/variant.inc
@@ -0,0 +1,55 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/variant.inc
+// Date:         2014-03-28
+
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_vybrid.h>
+
+//==========================================================================
+// EOF variant.inc
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/hal_diag.c
new file mode 100644
index 0000000..b4a3fd1
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/hal_diag.c
@@ -0,0 +1,405 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/src/hal_diag.c
+// Date:         2014-03-28
+// Purpose:     HAL diagnostic input/output
+// Description: Implementations of HAL diagnostic input/output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+ */
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+
+#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/hal/var_io.h>             //
+#include <cyg/io/ser_freescale_uart.h>  // UART registers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32 uart;
+    CYG_ADDRESS base;
+    cyg_int32 msec_timeout;
+    cyg_int32 isr_vector;
+    cyg_uint32 rx_pin;
+    cyg_uint32 tx_pin;
+    cyg_uint32 clock_gate;
+    cyg_int32 baud_rate;
+    cyg_int32 irq_state;
+} channel_data_t;
+
+channel_data_t plf_ser_channels[] = {
+#ifdef CYGINT_HAL_FREESCALE_UART0
+    { 0, CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART0_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART0_PIN_RX, CYGHWR_HAL_FREESCALE_UART0_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART0_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART1
+    { 1, CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART1_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART1_PIN_RX, CYGHWR_HAL_FREESCALE_UART1_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART1_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART2
+    { 2, CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART2_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART2_PIN_RX, CYGHWR_HAL_FREESCALE_UART2_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART2_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART3
+    { 3, CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART3_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART3_PIN_RX, CYGHWR_HAL_FREESCALE_UART3_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART3_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART4
+    { 4, CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART4_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART4_PIN_RX, CYGHWR_HAL_FREESCALE_UART4_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART4_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
+#endif
+#ifdef CYGINT_HAL_FREESCALE_UART5
+    { 5, CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, 1000,
+      CYGNUM_HAL_INTERRUPT_UART5_RX_TX,
+      CYGHWR_HAL_FREESCALE_UART5_PIN_RX, CYGHWR_HAL_FREESCALE_UART5_PIN_TX,
+      CYGHWR_IO_FREESCALE_UART5_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+void 
+cyg_hal_plf_serial_putc(void *__ch_data, char c);
+
+static void 
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = chan->base;
+
+    // Bring clock to the device
+    CYGHWR_IO_CLOCK_ENABLE(chan->clock_gate);
+
+    // Configure PORT pins
+    hal_set_pin_function(chan->rx_pin);
+    hal_set_pin_function(chan->tx_pin);
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C1, 0);
+    
+    CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_p, chan->baud_rate);
+
+    // Enable RX and TX
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2,
+                    (CYGHWR_DEV_FREESCALE_UART_C2_TE |
+                     CYGHWR_DEV_FREESCALE_UART_C2_RE));
+}
+
+void 
+cyg_hal_plf_serial_putc(void* __ch_data, char ch_out)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint32 uart_s1;
+
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    } while (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_TDRE));
+
+    HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_out);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* p_ch_in)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint8 uart_s1;
+    cyg_uint8 ch_in;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    if (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF))
+        return false;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
+    *p_ch_in = ch_in;
+
+    return true;
+}
+
+cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* p_ch_in)
+{
+    int delay_count;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    // delay in .1 ms steps
+    delay_count = ((channel_data_t*)__ch_data)->msec_timeout * 10;
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, p_ch_in);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 ser_port_reg;
+    int ret = 0;
+    va_list ap;
+
+    CYGARC_HAL_SAVE_GP();
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        cyg_hal_plf_serial_init_channel(chan);
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
+    cyg_uint8 uart_s1;
+    int res = 0;
+    cyg_uint8 ch_in;
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+
+    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
+    if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
+        if( cyg_hal_is_break( (char *) &ch_in , 1 ) )
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur;
+    int chan_i;
+
+    cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Init channels
+    for(chan_i=0; chan_i<CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; chan_i++) {
+        cyg_hal_plf_serial_init_channel(&plf_ser_channels[chan_i]);
+        // Setup procs in the vector table
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(chan_i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[chan_i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+    }
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] );
+#endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+    initialized = 1;
+    cyg_hal_plf_serial_init();
+}
+
+#else // !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+// #if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void hal_plf_diag_init(void)
+{
+    cyg_hal_plf_serial_init( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+void hal_plf_diag_putc(char c)
+{
+    cyg_hal_plf_serial_putc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8 hal_plf_diag_getc(void)
+{
+    return cyg_hal_plf_serial_getc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] );
+}
+
+#endif // defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c
new file mode 100644
index 0000000..3aac8ed
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c
@@ -0,0 +1,236 @@
+//==========================================================================
+//
+//      vybrid_clocking.c
+//
+//      Cortex-M Vybrid HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/kinetis_clocking.h
+// Date:         2014-03-28
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_vybrid.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/cortexm_endian.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+#include <cyg/io/ser_freescale_uart.h>
+
+//===========================================================================
+// Forward declarations
+//===========================================================================
+
+cyg_uint32 hal_cortexm_systick_clock;
+cyg_uint32 hal_vybrid_sysclk;
+cyg_uint32 hal_vybrid_busclk;
+
+cyg_uint32 hal_get_cpu_clock(void);
+
+cyg_uint32
+hal_get_cpu_clock(void)
+{
+    cyghwr_hal_vybrid_ccm_t *ccm = CYGHWR_HAL_VYBRID_CCM_P;
+    cyg_uint32 sys_clk_sel;
+    cyg_uint32 pfd_sel, pfd;
+    cyg_uint32 mfi, mfn, mfd;
+    cyg_uint32 freq = 0, arm_clk_div, bus_clk_div;
+
+    sys_clk_sel = (ccm->ccsr & CYGHWR_HAL_VYBRID_CCM_CCSR_SYS_CLK_SEL_M);
+    switch(sys_clk_sel) {
+        case 0: // Fast clock o/p defined by CCM_CCSR[FAST_CLK_SEL]
+            /* 24MHz clock. It might be internal RC or external OSC*/
+            freq = 24000000;
+            break;
+        case 1: // Slow clock o/p defined by CCM_CCSR[SLOW_CLK_SEL]
+            freq = 32000;
+            break;
+        case 2: // PLL2 PFD o/p clock defined by CCM_CCSR[PLL2_PFD_CLK_SEL]
+            pfd_sel = (ccm->ccsr & CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD_CLK_SEL_M);
+            pfd_sel = (pfd_sel >> CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD_CLK_SEL_S);
+            if(pfd_sel) {
+                HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_NUM, mfn);
+                HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_DENOM, mfd);
+                HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL, mfi);
+                // check the value of frequency multiplier
+                mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M;
+                // if CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT is set, then mfi is 22
+                mfi = (mfi ? 22 : 20);
+                // calculate the PLL! frequency
+                freq = (24000000 * (mfi + (mfn / mfd)));
+                HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD, pfd);
+                pfd = pfd >> (8*(pfd_sel-1));
+                pfd &= 0x3f;
+                //PFDout = PLLput * (18 / PFD_FRAC)
+                freq /= pfd;
+                freq *= 18;
+            }
+            break;
+            // Fall down as the pfd_sel == 0 selects PLL2 main clock
+        case 3: // PLL2 main clock
+            // check if PLL2 is bypassed
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL, mfi);
+            mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_M;
+            if (mfi) {
+                freq = 24000000;
+                break;
+            }
+            // get pll2 coefficients
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_NUM, mfn);
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_DENOM, mfd);
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL, mfi);
+            // check the value of frequency multiplier
+            mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M;
+            // if CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT is set, then mfi is 22
+            mfi = (mfi ? 22 : 20);
+            // calculate the PLL! frequency
+            freq = (24000000 * (mfi + (mfn / mfd)));
+            break;
+        case 4: // PLL1 PFD o/p clock defined by CCM_CCSR[PLL1_PFD_CLK_SEL]
+            pfd_sel = (ccm->ccsr & CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD_CLK_SEL_M);
+            pfd_sel = (pfd_sel >> CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD_CLK_SEL_S);
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL1_NUM, mfn);
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL1_DENOM, mfd);
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL, mfi);
+            // check the value of frequency multiplier
+            mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DIV_SELECT_M;
+            // if CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DIV_SELECT is set, then mfi is 22
+            mfi = 22;//(mfi ? 22 : 20); -> uncertain in VRM p. 726 (11.21.26 ANADIG PLL1_PFD definition register (ANADIG_PLL1_PFD))
+            // calculate the PLL1 frequency PLLout = Fref*(MFI + MFN/MFD) where Fref=24MHz
+            freq = (24000000 * (mfi + (mfn / mfd)));
+            if(pfd_sel) {
+                HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD, pfd);
+                pfd = pfd >> (8*(pfd_sel-1));
+                pfd &= 0x3f;
+                freq /= pfd;
+                freq *= 18;
+            }
+            //TODO: handle the PLL1 main clk
+            break;
+        case 5: // PLL3 main clock
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL, mfi);
+            mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_M;
+            if (mfi) {
+                freq = 24000000;
+                break;
+            }
+            HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL, mfi);
+            // check the value of frequency multiplier
+            mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M;
+            // if CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT is set, then mfi is 22
+            // freq is fixed (MFN and MFD not available) and the only variable is MFI
+            freq = (mfi ? 480000000 : 440000000);
+            break;
+        default: // Other values are not allowed
+            freq = 0;
+    }
+
+    arm_clk_div = ccm->cacrr & CYGHWR_HAL_VYBRID_CCM_CACRR_ARM_CLK_DIV_M;
+    arm_clk_div = (arm_clk_div >> CYGHWR_HAL_VYBRID_CCM_CACRR_ARM_CLK_DIV_S) + 1;
+    bus_clk_div = ccm->cacrr & CYGHWR_HAL_VYBRID_CCM_CACRR_BUS_CLK_DIV_M;
+    bus_clk_div = (bus_clk_div >> CYGHWR_HAL_VYBRID_CCM_CACRR_BUS_CLK_DIV_S) + 1;
+
+    freq /= arm_clk_div; // now we have a CA5 clock
+    freq /= bus_clk_div; // and now we have a CM4 clock
+
+    return freq;
+}
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current clock settings.
+
+
+void 
+hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud)
+{
+    cyg_uint32 sbr, brfa;
+    cyg_uint32 regval;
+
+    sbr = hal_vybrid_busclk / (16 * baud); //VYBRID: only this is allowed as all uarts run on BUS Clock
+
+    if(sbr) {
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval);
+        regval &= 0xE0;
+        regval |= sbr >> 8;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval);
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDL, (sbr & 0xFF));
+        brfa = (((32*hal_vybrid_busclk)/(16*baud))-(32*sbr));
+        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval);
+        regval &= 0xE0;
+        regval |= brfa & 0x1f;
+        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval);
+    }
+}
+
+
+void
+hal_update_clock_var(void)
+{
+    hal_vybrid_sysclk = hal_get_cpu_clock();
+    hal_vybrid_busclk = hal_vybrid_sysclk /
+          2; //TODO: place option for selecting CCM_CACRR[IPG_CLK_DIV] from CDL
+    hal_cortexm_systick_clock = hal_vybrid_sysclk;
+}
+
+
+cyg_uint32
+hal_get_peripheral_clock(void)
+{
+    return hal_vybrid_busclk;
+}
+
+//==========================================================================
+// EOF vybrid_clocking.c
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c
new file mode 100644
index 0000000..751b8c0
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c
@@ -0,0 +1,238 @@
+//==========================================================================
+//
+//      vybrid_misc.c
+//
+//      Cortex-M Vybrid HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Antmicro Ltd <contact@antmicro.com>
+// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/kinetis_misc.h
+// Date:         2014-03-28
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+ 
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_vybrid.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/cortexm_endian.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+
+#include <cyg/hal/hal_cache.h>
+
+#include <cyg/hal/var_io_gpio.h>
+#include <assert.h>
+
+void sst25xx_freescale_dspi_reg(void);
+
+//==========================================================================
+// Setup variant specific hardware
+//=========================================================================
+
+
+const char vf61_pads[] ={
+// port A
+NONE, NONE, NONE, NONE, NONE, NONE, PTA6, PTA7,
+PTA8, PTA9, PTA10,PTA11,PTA12,NONE, NONE, NONE,
+PTA16,PTA17,PTA18,PTA19,PTA20,PTA21,PTA22,PTA23,
+PTA24,PTA25,PTA26,PTA27,PTA28,PTA29,PTA30,PTA31,
+// port B
+PTB0, PTB1, PTB2, PTB3, PTB4, PTB5, PTB6, PTB7,
+PTB8, PTB9, PTB10,PTB11,PTB12,PTB13,PTB14,PTB15,
+PTB16,PTB17,PTB18,PTB19,PTB20,PTB21,PTB22,PTB23,
+PTB24,PTB25,PTB26,PTB27,PTB28,NONE, NONE, NONE, 
+// port C
+PTC0, PTC1, PTC2, PTC3, PTC4, PTC5, PTC6, PTC7,
+PTC8, PTC9, PTC10,PTC11,PTC12,PTC13,PTC14,PTC15,
+PTC16,PTC17,NONE, NONE, NONE, NONE, NONE, NONE,
+NONE, NONE, PTC26,PTC27,PTC28,PTC29,PTC30,PTC31,
+// port D
+PTD0, PTD1, PTD2, PTD3, PTD4, PTD5, PTD6, PTD7,
+PTD8, PTD9, PTD10,PTD11,PTD12,PTD13,NONE, NONE,
+PTD16,PTD17,PTD18,PTD19,PTD20,PTD21,PTD22,PTD23,
+PTD24,PTD25,PTD26,PTD27,PTD28,PTD29,PTD30,PTD31,
+// port E
+PTE0, PTE1, PTE2, PTE3, PTE4, PTE5, PTE6, PTE7, 
+PTE8, PTE9, PTE10,PTE11,PTE12,PTE13,PTE14,PTE15, 
+PTE16,PTE17,PTE18,PTE19,PTE20,PTE21,PTE22,PTE23,
+PTE24,PTE25,PTE26,PTE27,PTE28,NONE, NONE, NONE
+};
+
+void hal_variant_init( void )
+{
+#if defined CYGPKG_HAL_VYBRID_CACHE
+# if defined CYG_HAL_STARTUP_RAM
+    register CYG_INTERRUPT_STATE oldints;
+# endif
+#endif
+
+    hal_update_clock_var(); //VYBRID
+
+#if defined CYGPKG_HAL_VYBRID_CACHE
+# if defined CYG_HAL_STARTUP_RAM
+    HAL_DISABLE_INTERRUPTS(oldints);
+    HAL_DCACHE_SYNC();
+    HAL_DCACHE_DISABLE();
+    HAL_DCACHE_PURGE_ALL();
+    HAL_ICACHE_DISABLE();
+    HAL_ICACHE_INVALIDATE_ALL();
+# endif // defined CYG_HAL_STARTUP_RAM
+# if defined CYG_HAL_STARTUP_RAM
+    HAL_RESTORE_INTERRUPTS(oldints);
+# endif
+# ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
+    HAL_ICACHE_ENABLE();
+# endif
+# ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+    HAL_DCACHE_ENABLE();
+# endif
+#endif // defined CYGPKG_HAL_VYBRID_CACHE
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//==========================================================================
+// Pin configuration functions
+//==========================================================================
+
+static cyghwr_hal_vybrid_port_t * const Ports[] = {
+    CYGHWR_HAL_VYBRID_PORTA_P, CYGHWR_HAL_VYBRID_PORTB_P,
+    CYGHWR_HAL_VYBRID_PORTC_P, CYGHWR_HAL_VYBRID_PORTD_P,
+    CYGHWR_HAL_VYBRID_PORTE_P, CYGHWR_HAL_VYBRID_PORTF_P
+};
+
+
+void
+hal_set_pin_function(cyg_uint32 pin)
+{	
+	if (pin==CYGHWR_HAL_VYBRID_PORT_PIN_NONE) return;
+    
+	cyg_uint32 func = CYGHWR_HAL_VYBRID_PIN_FUNC(pin);	
+	cyg_uint32 pad = vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)];
+	
+	// pad must exist in the device
+	assert(pad != NONE);
+	
+	cyg_uint32 mux_val, mux_cnf;
+	
+	HAL_READ_UINT32(CYGHWR_HAL_VYBRID_GET_IOMUXC(pad),mux_val);
+	
+	mux_val &= 0xff8fffff; // clear the MUX_MODE
+	
+	mux_val |= ((func & 0xf00) << 12); //assign new MUX_MODE
+
+	mux_cnf = pin & 0x0000003f; // extract cnf from pin definition
+	
+	if (mux_cnf) // non zero cnf assigned
+	{		
+		mux_val &= 0xffffffc0; 
+		mux_val |= mux_cnf; 
+	}
+	
+	HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_IOMUXC(pad),mux_val);    
+}
+
+void
+hal_dump_pin_function(cyg_uint32 pin)
+{
+	if(pin == CYGHWR_HAL_VYBRID_PIN_NONE) return;
+	
+	cyg_uint32 port = CYGHWR_HAL_VYBRID_PIN_PORT(pin);
+    cyg_uint32 bit =  CYGHWR_HAL_VYBRID_PIN_BIT(pin);
+
+	cyg_uint32 pad = vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)];	
+	cyg_uint32 mux_val;	
+	HAL_READ_UINT32(CYGHWR_HAL_VYBRID_GET_IOMUXC(pad),mux_val);	
+	diag_printf("Pin PT%c%d: IOMUX=0x08%x\n",0x41+port,bit,mux_val);
+}
+
+//==========================================================================
+// VYBRID Clock distribution
+//==========================================================================
+
+void
+hal_clock_enable(cyg_uint32 ccgr)
+{
+    volatile cyg_uint32 *ccm_p;
+
+    if(ccgr != CYGHWR_HAL_CCGR_NONE) {
+        ccm_p = &CYGHWR_HAL_VYBRID_CCM_P->ccgr0 +
+                 CYGHWR_HAL_VYBRID_CCM_CCGR_REG(ccgr);
+        *ccm_p |= 3 << CYGHWR_HAL_VYBRID_CCM_CCGR_BIT(ccgr);
+    }
+}
+
+void
+hal_clock_disable(cyg_uint32 ccgr)
+{
+    volatile cyg_uint32 *ccm_p;
+
+    if(ccgr != CYGHWR_HAL_CCGR_NONE) {
+        ccm_p = &CYGHWR_HAL_VYBRID_CCM_P->ccgr0 +
+                 CYGHWR_HAL_VYBRID_CCM_CCGR_REG(ccgr);
+        *ccm_p &= ~(3 << CYGHWR_HAL_VYBRID_CCM_CCGR_BIT(ccgr));
+    }
+}
+
+//==========================================================================
+// VYBRID Misc functions
+//==========================================================================
+
+int
+hal_get_core_num(void)
+{
+    return CYGHWR_HAL_VYBRID_MSCM_CPxNUM & CYGHWR_HAL_VYBRID_MSCM_CPxNUM_CPN_M;
+}
+
+//==========================================================================
+// EOF vybrid_misc.c
author	Michael Gielda <mgielda@antmicro.com>	2014-04-03 14:53:04 +0200
committer	Michael Gielda <mgielda@antmicro.com>	2014-04-03 14:53:04 +0200
commit	ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch)
tree	f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/cortexm
parent	f157da5337118d3c5cd464266796de4262ac9dbd (diff)