diff options
| author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
|---|---|---|
| committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
| commit | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch) | |
| tree | f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/m68k | |
| parent | f157da5337118d3c5cd464266796de4262ac9dbd (diff) | |
Added the OS files
Diffstat (limited to 'ecos/packages/hal/m68k')
56 files changed, 16183 insertions, 0 deletions
diff --git a/ecos/packages/hal/m68k/arch/current/ChangeLog b/ecos/packages/hal/m68k/arch/current/ChangeLog new file mode 100644 index 0000000..df2fd86 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/ChangeLog @@ -0,0 +1,341 @@ +2008-11-18 Bart Veer <bartv@ecoscentric.com> + + * whole package. Replace the original M68K port. + +2008-11-17 Bart Veer <bartv@ecoscentric.com> + + * doc/m68k.sgml, cdl/hal_m68k.cdl, include/arch.inc, + src/hal_arch.S, src/m68k.ld, src/m68k_stub.c: minor clean-ups. + +2008-09-11 Bart Veer <bartv@ecoscentric.com> + + * src/hal_arch.S: in the interrupt VSR only lock the scheduler in + kernel configurations. + + * include/hal_intr.h (hal_interrupt_handlers): add a define'd + alias for cyg_hal_interrupt_handlers, needed by objloader. + +2008-05-08 Bart Veer <bartv@ecoscentric.com> + + * include/hal_arch.h: add bset and bclr utility macros. + +2008-02-28 Bart Veer <bartv@ecoscentric.com> + + * src/hal_arch.S: call DSRs even in non-kernel configurations. + + * include/arch.inc: include some debug info in assembler functions + + * cdl/hal_m68k.cdl, tests/iram1.c: add test for on-chip memory and + the iram linker script section. + +2008-02-14 Bart Veer <bartv@ecoscentric.com> + + * include/hal_io.h: cope with being #include'd from inside a + linker script. + + * include/hal_intr.h: fix HAL_VSR_SET() macro for + autoincrement/decrement pointer argument. Fix HAL_DELAY_US() + support for cached vs. uncached execution. + +2007-02-04 Bart Veer <bartv@ecoscentric.com> + + * src/plf_stub.h (HAL_STUB_PLATFORM_INIT_SERIAL): do not both with + plf_comms_init() if the virtual vector init code has already taken + care of it. + +2006-12-21 Bart Veer <bartv@ecoscentric.com> + + * src/m68k.ld: ensure the ctors table is properly aligned. + +2006-12-13 Bart Veer <bartv@ecoscentric.com> + + * src/m68k.ld: default to placing _stext at the start of + .m68k_startup instead of .text, but allow platforms to override + this. + + * src/vectors.S: minor code size optimizations to the startup + code. + +2006-12-03 Bart Veer <bartv@ecoscentric.com> + + * src/vectors.S: allow platforms to suppress the exception vector + entries in .ram_vectors while preserving the virtual vectors and + any variant/processor/platform-specific data. + + * include/hal_cache.h: allow indirect inclusion from assembler + files. + +2006-10-12 Bart Veer <bartv@ecoscentric.com> + + * src/m68k.ld (SECTION_iram): fix alignment problems when the + on-chip code is not a multiple of 4 bytes + +2006-10-11 Nick Garnett <nickg@ecoscentric.com> + + * src/m68k.ld: Removed a stray '.' from _EH_FRAME1_. Added + _region_ argument to _EH_FRAME1_ and _GCC_EXCEPT_TABLE1_. + +2006-09-25 Bart Veer <bartv@ecoscentric.com> + + * doc/m68k.sgml: update to reflect recent changes in the M68K + HALs. + +2006-09-25 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_m68k.cdl: Restore CYGBLD_LINKER_SCRIPT - required by the + eCos Configuration Tool. + +2006-09-13 Jonathan Larmour <jifl@eCosCentric.com> + + * src/vectors.S: Place hal_m68k_exception_reset in its own + section, to avoid its section being at 0x0 which confuses + GDB. + +2006-09-10 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k.cdl: there is no need for the linker script to be + an option. + + * cdl/hal_m68k.cdl, src/plf_stub.h: allow the architectural HAL to + provide plf_stub.h at the platform HAL's request, to avoid lots of + duplication of the same header. + +2006-09-08 Bart Veer <bartv@ecoscentric.com> + + * src/m68k.ld: greatly simplify M68K linker script support. Add + support for on-chip RAM. + + * src/vectors.S: tidy up. Add support for on-chip RAM. + + * src/hal_m68k.c: move hal_if_init() up the hierarchy + + * include/hal_io.h: can now be safely #include'd by assembler + files. + + * include/hal_arch.h: change gdb stub target_register_t definition + to avoid compiler warning. + +2006-09-05 Bart Veer <bartv@ecoscentric.com> + + * src/vectors.S: fix fencepost bug in BSS initialization + + * src/m68k.ld: discard exception-related sections unless libstdcxx + is in the configuration. + + * src/hal_m68k.c: remove idle thread action function, now defaults + to just an empty macro. + + * src/hal_arch.S: tidy up comment. + + * include/hal_intr.h: HAL_VSR_SET() is now optional. + + * include/hal_cache.h: fix default cache definitions. + + * include/hal_arch.h: allow lower-level HAL to provide the LSBIT + and MSBIT macros. Do not initialize interrupts in a thread context + when building RedBoot, so loaded applications start with ints + disabled. + + * cdl/hal_m68k.cdl: fix custom build rules for proper dependency + handling. + + +2006-07-10 Bart Veer <bartv@ecoscentric.com> + + * src/m68k.ld, src/vectors.S: distinguish cleanly between the + exception vectors and the startup code. Add support for mcf52xx + cfm flash security settings. + + * src/hal_m68k.c: rationalize hal_arch_default_isr() & + hal_default_isr() functions + + * cdl/hal_m68k.cdl, src/hal_arch.S, include/arch.inc: default to + providing startup/interrupt stack in the architectural HAL + + * include/hal_intr.h: default to providing HAL_DELAY_US() in the + architectural HAL + +2006-06-26 Jonathan Larmour <jifl@ecoscentric.com> + + * cdl/hal_m68k.cdl: Use correct syntax for modern GNU tail. + +2006-03-10 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_m68k.cdl: Add reference to M68k architecture documentation. + +2006-02-21 Bart Veer <bartv@ecoscentric.com> + + * include/hal_intr.h (HAL_ENABLE_INTERRUPTS): fix + DEFAULT_IPL_LEVEL usage. + +2005-06-10 Jonathan Larmour <jifl@eCosCentric.com> + + * src/m68k.ld: gcc_except_table subsections don't need to be + kept. + +2005-06-03 Jonathan Larmour <jifl@eCosCentric.com> + + * src/m68k.ld: gcc_except_table needs to be marked KEEP. + +2005-05-23 Jonathan Larmour <jifl@eCosCentric.com> +2005-05-23 Bart Veer <bartv@eCosCentric.com> + + * src/hal_arch.S (hal_m68k_exception_handler): Zero frame pointer + to improve GDB backtraces. + (hal_interrupt_stack_call_pending_DSRs): Ditto. + * src/vectors.S (hal_m68k_exception_reset): Use shorter suba.l + instruction to zero frame pointer. + +2005-02-17 Jonathan Larmour <jifl@eCosCentric.com> + + * src/m68k.ld: Use CYGBLD_HAL_LINKER_GROUPED_LIBS from the common HAL + for GROUP() list now. + +2004-10-22 Bart Veer <bartv@ecoscentric.com> + + * src/hal_m68k.c (hal_m68k_startup): add more init macros if the + platform needs them. + * doc/m68k.sgml: document the various init macros + +2004-09-22 John Dallaway <jld@ecoscentric.com> + + * src/m68k.ld: Add got, frame and RELOCS sections. Accommodate .bss* + +2004-06-24 Bart Veer <bartv@ecoscentric.com> + + * src/vectors.S: extend fixed_vectors with sections for the + variant, processor and platform HALs. This makes it easier to + share data between RedBoot and the application. + + * src/hal_m68k.c (hal_m68k_startup): support init routines + provided by the variant and processor HALs. + +2004-02-11 Bart Veer <bartv@ecoscentric.com> + + * src/vectors.S: give .fixed_vectors the right section attributes, + and fix comment. + + * src/hal_arch.S (hal_m68k_interrupt_vsr): use new macro + hal_context_extract_isr_vector_shl2, saving an instruction in the + main interrupt handling path. + + * doc/m68k.sgml: document new macro + hal_context_extract_isr_vector_shl2 + +2004-01-09 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_m68k.cdl: + Correct capitalisation of "Variant details" string. + +2004-01-05 Bart Veer <bartv@ecoscentric.com> + + * src/hal_m68k.c (cyg_hal_invoke_constructors): + This function should not be static. In some configurations it may + get called from the libc startup code. + +2003-09-30 Bart Veer <bartv@ecoscentric.com> + + * src/hal_arch.S: __profile_mcount() was referenced even if the + profiling package was absent. This was only a problem when + building without linker garbage collection. + +2003-09-26 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k.cdl, src/hal_arch.S, doc/m68k.sgml: + The architectural HAL now provides mcount profiling support. + +2003-08-01 Bart Veer <bartv@ecoscentric.com> + + * src/hal_arch.S: rework VSR and + hal_interrupt_stack_call_pending_DSRs so that interrupts are only + re-enabled while running the DSR, not elsewhere in the interrupt + handling code. Currently this is the only way to guarantee that + stack usage remains bounded. + + * src/hal_m68k.c: define new variable hal_m68k_dsr_ipl_level, + the IPL level that should be used when running DSRs. + + * include/hal_intr.h: HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() is + now defined even when not running with an interrupt stack, so that + DSRs still run with interrupts enabled. + + * doc/m68k.sgml: Minor updates following changes to the interrupt + handling. + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): A thread would be + initialized with the wrong status register value if the default + IPL level was not zero + +2003-07-22 Bart Veer <bartv@ecoscentric.com> + + * doc/m68k.sgml: Fix various typos etc. + +2003-07-17 Bart Veer <bartv@ecoscentric.com> + + * doc/m68k.sgml: update documentation. + +2003-07-06 Bart Veer <bartv@ecoscentric.com> + + * src/hal_arch.S: Add support for kernel interrupt + instrumentation. + +2003-07-04 Bart Veer <bartv@ecoscentric.com> + + * src/hal_arch.S: + Rework interrupt and exception VSR's to make the use of an + interrupt stack optional, and to allow interrupt nesting to be + disabled. + + * src/hal_m68k.c: + * src/vectors.S: + hal_m68k_interrupt_nesting count is no longer required. Instead + the stack pointer itself is compared with the interrupt stack base + and top when deciding whether or not to switch to the interrupt + stack. + + * include/hal_intr.h: + HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() is only provided if there + is an interrupt stack + + * include/hal_arch.h: + Adjust stack sizes for different interrupt-related configurations + + * cdl/hal_m68k.cdl: + Interrupt stacks and nesting are now optional as on other + architectures. + +2003-06-25 Bart Veer <bartv@ecoscentric.com> + + * include/hal_arch.h: + Eliminate a build warning. + + * include/hal_intr.h: + Provide default implementation of HAL_TRANSLATE_VECTOR() + +2003-06-04 Bart Veer <bartv@ecoscentric.com> + + * New version of the M68K support + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/m68k/arch/current/cdl/hal_m68k.cdl b/ecos/packages/hal/m68k/arch/current/cdl/hal_m68k.cdl new file mode 100644 index 0000000..7c78e8f --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/cdl/hal_m68k.cdl @@ -0,0 +1,262 @@ +# ==================================================================== +# +# hal_m68k.cdl +# +# m68k architectural HAL package configuration data +# +# ==================================================================== +# ####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later +# version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with eCos; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered by +# the GNU General Public License. However the source code for this file +# must still be made available in accordance with section (3) of the GNU +# General Public License v2. +# +# This exception does not invalidate any other reasons why a work based +# on this file might be covered by the GNU General Public License. +# ------------------------------------------- +# ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Date: 2003-06-04 +# +#####DESCRIPTIONEND#### +#======================================================================== + +cdl_package CYGPKG_HAL_M68K { + display "m68k architecture" + parent CYGPKG_HAL + doc ref/hal-m68k-arch.html + hardware + description " + The m68k architecture HAL package provides generic + support for 68000 and ColdFire processors." + + include_dir cyg/hal + compile hal_m68k.c hal_arch.S m68k_stub.c + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_m68k.h>" + } + make { + <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S + $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -c -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 vectors.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm vectors.tmp + } + + # callgraph profiling, i.e. compiling with -pg, is supported. However + # -pg is incompatible with -fomit-frame-pointer + implements CYGINT_PROFILE_HAL_MCOUNT + requires { ! (is_substr(CYGBLD_GLOBAL_CFLAGS, " -pg") && is_substr(CYGBLD_GLOBAL_CFLAGS, "-fomit-frame-pointer")) } + + cdl_option CYGNUM_HAL_DEFAULT_INTERRUPT_STACK_SIZE { + display "Default size for the startup and interrupt stack" + description " + The M68K HAL uses a single stack for system startup and for handling + interrupts and exceptions. The size of this stack is configurable via + the common HAL's CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE option, but + this architectural HAL provides a default value." + flavor data + calculated { is_enabled(CYGNUM_HAL_M68K_PLATFORM_DEFAULT_INTERRUPT_STACK_SIZE) ? + CYGNUM_HAL_M68K_PLATFORM_DEFAULT_INTERRUPT_STACK_SIZE : + (CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING ? 4096 : 2048) } + } + + cdl_option CYGNUM_HAL_M68K_STARTUP_STACK_SIZE { + display "Stack size to use during startup" + active_if !CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + flavor data + default_value 2048 + description " + By default eCos runs with a separate interrupt stack, which also gets + used during system startup. This saves memory because it is not necessary + to allow for interrupt overheads on every thread stack, but adds a number + of instructions to the interrupt processing code. If the interrupt stack + is disabled then a separate startup stack is needed. That stack will be + used for running system initialization and for running some application + code including cyg_start() and C++ static constructions." + } + + cdl_component CYGPKG_HAL_M68K_VARIANT { + display "Variant details" + flavor none + description " + Various subsystems like the floating point and memory management + units are available on some but not all 68000 processors. Variant + HAL packages will list which of these subsystems are actually + present." + + cdl_interface CYGINT_HAL_M68K_VARIANT_TYPES { + display "Data types" + flavor bool + description " + This interface will be implemented if the specific processor + being used requires non-default data type definitions." + } + + cdl_interface CYGINT_HAL_M68K_VARIANT_FPU { + display "Floating point unit" + flavor bool + description " + This interface will be implemented if the specific processor + being used has floating point hardware." + } + + if { 0 } { + # No MMU support available yet + cdl_interface CYGINT_HAL_M68K_VARIANT_MMU { + display "Floating point unit" + flavor bool + description " + This interface will be implemented if the specific processor + being used has a memory management unit." + } + } + + cdl_interface CYGINT_HAL_M68K_VARIANT_CACHE { + display "Cache" + flavor bool + description " + This interface will be implemented if the specific processor + being used has an instruction cache, a data cache, or both." + } + + cdl_interface CYGINT_HAL_M68K_VARIANT_IRAM { + display "On-chip RAM" + flavor bool + description " + This interface will be implemented if the specific processor + being used has on-chip RAM." + } + + cdl_interface CYGINT_HAL_M68K_USE_STANDARD_PLATFORM_STUB_SUPPORT { + display "Use standard platform gdb stub support" + flavor bool + make -priority 1 { + <PREFIX>/include/cyg/hal/plf_stub.h : <PACKAGE>/src/plf_stub.h + @cp $< $@ + } + description " + For platforms where target-side gdb stub support may be used the + platform HAL is expected to provide a header file <cyg/hal/plf_stub.h>. + In practice the same header file is applicable to nearly all platforms + so the M68K architectural HAL will provide this header when the platform + HAL requests this interface." + } + } + + cdl_component CYGPKG_HAL_M68K_FPU { + display "Support for the floating point unit" + active_if CYGINT_HAL_M68K_VARIANT_FPU + flavor none + description " + If the target processor has a hardware floating point unit then + this component defines additional configuration options related + to that unit." + + cdl_option CYGIMP_HAL_M68K_FPU_SAVE { + display "Save FPU state during context switch" + default_value 1 + description " + By default the floating point context gets saved during a + context switch. This can be suppressed if the application + does not actually perform any floating point arithmetic, or + if it only does so from one thread." + } + + cdl_option CYGNUM_HAL_M68K_FPU_CR_DEFAULT { + display "Default value for the FPU control register" + flavor data + default_value 0 + legal_values 0 to 0x0FFFF + description " + The FPU control register controls rounding modes, precision, + and exceptions. The default value of 0 gives IEE754 standard + behaviour. It is assumed that the control register's value is + not changed while the system is running, and hence does not + have to be saved or restored during a thread switch or when + an interrupt happens." + } + } + + cdl_component CYGPKG_HAL_M68K_OPTIONS { + display "Architectural HAL build options" + flavor none + description " + Package-specific build options including control over compiler + flags used only when building this package, and details of which + tests are built." + + cdl_option CYGPKG_HAL_M68K_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for building + the architectural HAL package. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_M68K_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for building + the architectural HAL package. These flags are removed from + the set of global flags if present." + } + + cdl_option CYGPKG_HAL_M68K_TESTS { + display "Architectural HAL tests" + flavor data + no_define + calculated { (CYGINT_HAL_M68K_VARIANT_IRAM ? "tests/iram1" : "") . + "" + } + description " + This option specifies the set of tests for the M68K architectural HAL." + } + + cdl_option CYGBLD_LINKER_SCRIPT { + display "Linker script" + flavor data + no_define + calculated { "src/m68k.ld" } + make { + <PREFIX>/lib/target.ld: <PACKAGE>/src/m68k.ld + $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 target.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm target.tmp + } + } + } +} diff --git a/ecos/packages/hal/m68k/arch/current/doc/m68k.sgml b/ecos/packages/hal/m68k/arch/current/doc/m68k.sgml new file mode 100644 index 0000000..cee9ebb --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/doc/m68k.sgml @@ -0,0 +1,877 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- m68k.sgml --> +<!-- --> +<!-- m68k architectural documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): bartv --> +<!-- Contact(s): bartv --> +<!-- Date: 2003/06/04 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-m68k-arch"><title>M68000 Architectural Support</title> + +<!-- {{{ Overview --> + +<refentry id="m68k"> + <refmeta> + <refentrytitle>Overview</refentrytitle> + </refmeta> + <refnamediv> + <refname>Overview</refname> + <refpurpose>eCos Support for the M68K Family of Processors</refpurpose> + </refnamediv> + + <refsect1 id="m68k-description"><title>Description</title> + <para> +The original Motorola 68000 processor was released in 1979, and +featured the following: + </para> + <itemizedlist> + <listitem><para> +Eight general purpose 32-bit data registers, %D0 to %D7. Seven 32-bit +address registers %A0 to %A6, with %A7 dedicated as the stack pointer. +A 16-bit status register. + </para></listitem> + <listitem><para> +A linear address space, limited to 24-bits because the chip package +only had 24 address pins. Hence the processor could address 16 +megabytes of memory. + </para></listitem> + <listitem><para> +No separate address space for I/O operations. Instead devices are +accessed just like memory via the main address and data buses. + </para></listitem> + <listitem><para> +16-bit external data bus, even though the data registers were 32 bits +wide. + </para></listitem> + <listitem><para> +A CISC variable-length instruction set with no less than 14 different +addressing modes (although of course the terms RISC and CISC were not +yet in common use). + </para></listitem> + <listitem><para> +Separate supervisor and user modes. The processor actually has two +distinct stack pointer registers %A7, and the mode determines which one +gets used. + </para></listitem> + <listitem><para> +An interrupt subsystem with support for vectored and prioritized +interrupts. + </para></listitem> + </itemizedlist> + <para> +The 68000 processor was used in several microcomputers of its time, +including the original Apple Macintosh, the Commodore Amiga, and the +Atari ST. Over the years numerous variants have been developed. The +core instruction set has remained essentially unchanged. Some of the +variants have additional instructions. The development of MMUs led to +changes in exception handling. In more recent variants, notably the +Freescale ColdFire family, some infrequently used instructions and +addressing modes have been removed. + </para> + <itemizedlist> + <listitem><para> +The 68008 reduced the widths of the external data and address buses to +8 bits and 20 bits respectively, giving the processor slow access to +only one megabyte. + </para></listitem> + <listitem><para> +The 68010 (1982) added virtual memory support. + </para></listitem> + <listitem><para> +In the 68020 (1984) both the address and data buses were made 32-bits wide. A +256-byte instruction cache was added, as were some new instructions +and addressing modes. + </para></listitem> + <listitem><para> +The 68030 (1987) included an on-chip mmu and a 256-byte data cache. + </para></listitem> + <listitem><para> +The 68040 (1991) added hardware floating point (previous processors relied on +an external coprocessor or on software emulation). It also had larger +caches and an improved mmu. + </para></listitem> + <listitem><para> +The 68060 (1994) involved an internally very different superscalar +implementation of the architecture, but few changes at the interface +level. It also contained support for power management. + </para></listitem> + <listitem><para> +There have been numerous 683xx variants for embedded use, with +on-chip peripherals like UARTs and timers. The cpu core of these +variants is also known as cpu32. + </para></listitem> + <listitem><para> +The MCFxxxx ColdFire series (1995) resembles a stripped-down 68060, +with some instructions and addressing modes removed to allow for a +much smaller and more efficient implementation. Various hardware units +such as the and FPU and MMU have become optional. + </para></listitem> + </itemizedlist> + + <para> +eCos only provides support for some of these variants, although it +should be possible to add support for additional variants with few or +no changes to the architectural HAL package. + </para> + <para> +The architectural HAL provides support for those features which are +common to all members of the 68000 and ColdFire families, and for +certain features which are present on some but not all members. A +typical eCos configuration will also contain: a variant HAL package +with support code for a family of processors, for example MCFxxxx; +possibly a processor HAL package with support for one specific +processor, for example the MCF5272; and a platform HAL +which contains the code needed for a specific hardware platform such +as the m5272c3. + </para> + </refsect1> +</refentry> + +<!-- }}} --> +<!-- {{{ Configuration --> + +<refentry id="m68k-configuration"> + <refmeta> + <refentrytitle>Configuration</refentrytitle> + </refmeta> + <refnamediv> + <refname>Options</refname> + <refpurpose>Configuring the M68K Architectural Package</refpurpose> + </refnamediv> + + <refsect1 id="m68k-config-load"><title>Loading and Unloading the Package</title> + <para> +The M68K architectural HAL package <varname>CYGPKG_HAL_M68K</varname> +should be loaded automatically when eCos is configured for M68K-based +target hardware. It should never be necessary to load this package +explicitly. Unloading the package should only happen as a side effect +of switching target hardware. <varname>CYGPKG_HAL_M68K</varname> +serves primarily as a container for lower-level HALs and has only a +small number of configuration options. + </para> + </refsect1> + + <refsect1 id="m68k-config-stacks"><title>Stacks</title> + <para> +By default the architectural HAL provides a single block of memory to +act as both the startup stack and the interrupt stack. The variant, +processor or platform HAL may override this. For example if there are +several banks of RAM with different performance characteristics it may +be desirable to place the interrupt stack in fast RAM rather than in +ordinary RAM. + </para> + <para> +The assembler startup code sets the stack pointer to the startup stack +before switching to C code. This stack used for all HAL +initialization, running any C++ static constructors defined either by +eCos or by the application, and the <function>cyg_start</function> +entry point. In configurations containing the eCos kernel +<function>cyg_start</function> will enable interrupts, activate the +scheduler and threads will then run on their own stacks. In non-kernel +single-threaded applications the whole system continues to run on the +startup stack. + </para> + <para> +When an interrupt occurs the default behaviour is to switch to a +separate interrupt stack. This behaviour is controlled by the common +HAL configuration option +<varname>CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK</varname>. +It reduces the stack requirements of all threads in the system, at the +cost of some extra instructions during interrupt handling. In kernel +configurations the startup stack is no longer used once the scheduler +starts running so its memory can be reused for the interrupt stack. To +handle the possibility of nested interrupts the interrupt handling +code will detect if it is already on the interrupt stack, so in +non-kernel configurations it is also safe to use the same area of +memory for both startup and interrupt stacks. This leads to the +following scenarios: + </para> + <orderedlist> + <listitem><para> +If interrupt stacks are enabled via +<varname>CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK</varname> +and the interrupt stack is not provided by the variant, processor or +platform HAL then a single block of memory will be used for both +startup and interrupt stacks. The size of this block is determined by +the common HAL configuration option +<varname>CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE</varname>, with a +default value +<varname>CYGNUM_HAL_DEFAULT_INTERRUPT_STACK_SIZE</varname> provided by +the M68K architectural HAL. + </para></listitem> + <listitem><para> +If the use of an interrupt stack is disabled then the M68K +architectural HAL will provide just the startup stack, unless this is +done by the variant, processor or platform HAL. The size of the +startup stack is controlled by +<varname>CYGNUM_HAL_M68K_STARTUP_STACK_SIZE</varname>. + </para></listitem> + <listitem><para> +Otherwise the interrupt and/or startup stacks are provided by other +packages and it is up to those packages to provide configuration +options for setting the sizes. + </para></listitem> + </orderedlist> + </refsect1> + + <refsect1 id="m68k-config-fpu"><title>Floating Point Support</title> + <para> +There are many variants of the basic M68K architecture. Some of these +have hardware floating point support. Originally this came in the form +of a separate 68881 coprocessor, but with modern variants it will be +part of the main processor chip. If the processor does not have +hardware floating point then software emulation will be used instead. + </para> + <para> +If the processor on the target hardware has a floating point unit then +the variant or processor HAL will implement the CDL interface +<varname>CYGINT_HAL_M68K_VARIANT_FPU</varname>. This allows the +architectural HAL and other packages to do the right thing on +different hardware. + </para> + <para> +Saving and restoring hardware floating point context increases +interrupt and dispatch latency, code size, and data size. If the +application does not actually use floating point then these overheads +are unnecessary, and can be suppressed by disabling the configuration +option <varname>CYGIMP_HAL_M68K_FPU_SAVE</varname>. Some applications +do use floating point but only in one thread. In that scenario it is +also unnecessary to save the floating point context during interrupts +and context switches, so the configuration option can be disabled. + </para> + <para> +The exact behaviour of the hardware floating point unit is determined +by the floating point control register <varname>%fpcr</varname>. By +default this is initialized to 0, giving IEE754 standard behaviour, +but another initial value can be specified using the configuration +option <varname>CYGNUM_HAL_M68K_FPU_CR_DEFAULT</varname>. For details +of the various bits in this control register see appropriate hardware +documentation. eCos assumes that the control register does not change +on a per-thread basis and hence the register is not saved or restored +during interrupt handling or a context switch. + </para> + <warning> + <para> +At the time of writing eCos has not run on an M68K processor with +hardware floating point so the support for this is untested. + </para> + </warning> + </refsect1> + + <refsect1 id="m68k-config-other"><title>Other Options</title> + <para> +There are configuration options to change the compiler flags used for +building this packages. +The M68K architectural HAL package does not define any other +configuration options that can be manipulated by the user. It does +define a number of interfaces such as +<varname>CYGINT_HAL_M68K_USE_STANDARD_PLATFORM_STUB_SUPPORT</varname> +which can be used by lower levels of the M68K HAL hierarchy to enable +certain functionality within the architectural package. Usually these +are of no interest to application developers. + </para> + </refsect1> +</refentry> + +<!-- }}} --> +<!-- {{{ HAL Porting Details --> + +<refentry id="m68k-port"> + <refmeta> + <refentrytitle>The HAL Port</refentrytitle> + </refmeta> + <refnamediv> + <refname>HAL Port</refname> + <refpurpose>Implementation Details</refpurpose> + </refnamediv> + + <refsect1 id="m68k-port-description"><title>Description</title> + <para> +This documentation explains how the eCos HAL specification has been +mapped onto M68K hardware, and should be read in conjunction with +that specification. It also describes how variant, processor and +platform HALs can modify the default behaviour. + </para> + <para> +eCos support for any given target will involve either three or four +HAL packages: the architectural HAL, the platform HAL, the variant +HAL, and optionally a processor HAL. This package, the architectural +HAL, provides code and definitions that are applicable to all M68K +processors. The platform HAL provides support for one specific +board, for example an M5272C3 evaluation board, or possibly for a +number of almost-identical boards. The processor HAL, if present, +serves mainly to provide details of on-chip peripherals including the +interrupt controller. The variant HAL provides functionality that is +common to a group of processors, for example all MCFxxxx processors +have very similar UARTs and hence can share HAL diagnostic code. +There is no fixed specification of what should go into the variant HAL +versus the processor HAL. For simplicity the description below only +refers to variant HALs, but the work may actually happen in a +processor HAL instead. + </para> + <para> +As a design goal lower-level HALs can always override functionality +that is normally provided higher up. For example the architectural HAL +will provide the required eCos <function>HAL_LSBIT_INDEX</function> +and <function>HAL_MSBIT_INDEX</function> macros, but these can be +provided lower down instead. Many but not all ColdFire processors have +the <literal>ff1</literal> and <literal>bitrev</literal> instructions +which allow for a more efficient implementation than the default +architectural ones. In some areas such as handling context switching +the architectural HAL will usually provide the basic functionality but +it may be extended by lower HALs, for example to add support for the +multiply-accumulate units present in certain ColdFire processors. + </para> + <para> +The architectural HAL provides header files <filename +class="headerfile">cyg/hal/hal_arch.h</filename>, <filename +class="headerfile">cyg/hal/hal_intr.h</filename>, <filename +class="headerfile">cyg/hal/hal_cache.h</filename>, <filename +class="headerfile">cyg/hal/hal_io.h</filename> and <filename +class="headerfile">cyg/hal/arch.inc</filename>. These automatically +include an equivalent header file from the variant HAL, for example +<filename class="headerfile">cyg/hal/var_arch.h</filename>. The +variant HAL header will in turn include processor and +platform-specific headers. This means that application developers and +other packages can simply include the architectural HAL headers +without needing to know about variants or platforms. It also allows +the variant and platform HALs to override architectural settings. + </para> + <para> +The port assumes that eCos and application code always runs in +supervisor mode, with full access to all hardware and special +registers. + </para> + + <refsect2 id="m68k-port-types"><title>Data Types</title> + <para> +For eCos purposes all M68K processors are big-endian and 32-bit, so +the default data types in <filename +class="headerfile">cyg/infra/cyg_type.h</filename> are used. Some +variants have external bus widths less than 32-bit, but this does not +affect the architectural HAL. + </para> + <para> +When porting to another variant it is possible to override some or all +of the type definitions. The variant HAL needs to implement the CDL +interface <varname>CYGINT_HAL_M68K_VARIANT_TYPES</varname> and provide +a header file <filename +class="headerfile">cyg/hal/var_basetype.h</filename>. + </para> + </refsect2> + + <refsect2 id="m68k-port-startup"><title>Startup and Exception Vectors</title> + <para> +The conventional bootstrap mechanism involves a table of exception +vectors at the base of memory. The first two words of this table give +the initial program counter and stack pointer. In a typical embedded +system the hardware is arranged such that non-volatile flash memory is +found at location 0x0 so it is the start of flash that contains the +exception vectors and the boot code. The table of exception vectors is +used subsequently for interrupt handling and for hardware exceptions +such as attempts to execute an illegal instruction. There are a number +of common scenarios: + </para> + <orderedlist> + <listitem><para> +On systems with very limited memory flash may remain mapped at +location 0 and the table of exception vectors remains mapped there as +well. The M68K architecture defines the table to have 256 entries and +hence it occupies 1K of memory, but in reality many of the entries are +unused so part of the table may get used for code instead. Since the +whole exception vector table is in read-only memory parts of the eCos +interrupt and exception handling mechanisms have to be statically +initialized and macros like <function>HAL_VSR_SET</function> are not +available. + </para></listitem> + <listitem><para> +As a minor variation of the previous case, flash remains at location 0 +but the table of exception vectors gets remapped elsewhere in the +address space, usually RAM. This allows +<function>HAL_VSR_SET</function> to operate normally but at the cost +of increased memory usage. The exception vector table in flash only +contains two entries, for the initial program counter and stack +pointer. The exception vector table in RAM typically gets initialized +at run-time. + </para></listitem> + <listitem><para> +On systems with more memory it is conventional to rearrange the +address map during bootstrap. The flash gets relocated, typically to +near the end of the address space, and RAM gets placed at location 0 +instead. The exception vector table stays at location 0 but is now in +RAM and gets initialized at run-time. The bootstrap exception vector +table in flash again only needs two entries. A variation places the +RAM elsewhere in the address space and moves the exception vector +table there, leaving location 0 unused. This provides some protection +against null pointer accesses in errant code. + </para> + <para> +As a further complication, larger systems typically support different +startup types. The application can be linked against a ROM startup +configuration and placed directly in flash, as before. Alternatively +there may be a ROM monitor such as RedBoot in the flash, taking care +of initial bootstrap. The user's application is linked against a RAM +startup configuration, loaded into RAM via the ROM monitor, and +debugged using functionality provided by the ROM monitor. Yet another +possibility involves a RAM startup application but it gets loaded and +run via a hardware debug technology such as BDM, and the ROM monitor +is either missing or not used. + </para></listitem> + </orderedlist> + <para> +The exact hardware details, the various startup types, the steps +needed for low-level hardware initialization, and so on are not known +to the architectural HAL. Hence although the architectural HAL does +provide the basic framework for startup, much of the work is done via +macros provided by lower-level HAL packages and those macros are +likely to depend on various configuration options. Rather than try to +enumerate all the various combinations here it is better to look at +the actual code in <filename>vectors.S</filename> and in appropriate +variant, processor or platform HALs. <filename>vectors.S</filename> is +responsible for any low-level initialization that needs to happen. +This includes setting up a standard C environment with the stack +pointer set to the startup stack in working RAM, making sure all +statically initialized global variables have the correct values, and +that all uninitialized global variables are zeroed. Once the C +environment has been set up the code jumps to +<function>hal_m68k_c_startup</function> in file +<filename>hal_m68k.c</filename> which completes the initialization and +jumps to the application entry point. + </para> + </refsect2> + + <refsect2 id="m68k-port-interrupts"><title>Interrupt Handling</title> + <para> +The M68K architecture reserves a 1K area of memory for 256 exception +vectors. These are used for internal and external interrupts, +exceptions, software traps, and special operations such as reset +handling. Some of the vectors have well-defined uses. However when it +comes to interrupt handling the details will depend on the processor +variant and on the platform, and the appropriate package documentation +should be consulted for full details. Most platforms will not use the +full set of 256 vectors, instead re-using some of this memory for +other purposes. + </para> + <para> +By default the exception vectors are located at location 0, but some +variants allow the vectors to be located elsewhere. This is managed by +an M68K-specific macro <varname>CYG_HAL_VSR_TABLE</varname>. The +default value is 0, but a variant HAL can provide an alternative value. + </para> + <para> +The standard eCos macros <function>HAL_VSR_GET</function> and +<function>HAL_VSR_SET</function> just manipulate one of the 256 +entries in the table of exception vectors. Hence it is usually +possible to replace the default handlers for exceptions and traps in +addition to interrupt handlers. +<filename class="headerfile">hal_intr.h</filename> +provides <literal>#define</literal>'s for the more common exception +vectors, and additional ones can be provided by the platform or +variant. It is the responsibility of the platform or variant HAL to +initialize the table, and to provide the +<function>HAL_VSR_SET_TO_ECOS_HANDLER</function> macro since that +requires knowledge of the default table entries. + </para> + <para> +It should be noted that in some configurations the table of exception +vectors may reside in read-only memory so entries cannot be changed. +If so then the <function>HAL_VSR_SET</function> and +<function>HAL_VSR_SET_TO_ECOS_HANDLER</function> macros will not be +defined. Portable code may need to consider this possibility and test +for the existence of these macros before using them. + </para> + <para> +The architectural HAL provides an entry point +<function>hal_m68k_interrupt_vsr</function> in the file +<filename>hal_arch.S</filename>. When an interrupt occurs the original +68000 pushed the program counter and the status register on to the +stack, and then called the VSR via the exception table. On newer +variants some additional information is pushed, including details of +the interrupt source. <function>hal_m68k_interrupt_vsr</function> +assumes the latter and can be used directly as the VSR on these newer +variants. On older variants a small trampoline is needed which pushes +the additional information and then jumps to the generic VSR. +Interpreting the additional information is handled via an assembler +macro <function>hal_context_extract_isr_vector_shl2</function> +which should be defined by the variant, matching the behaviour of the +hardware or the trampoline. + </para> + <para> +At the architecture level there is no fixed mapping between VSR and +ISR vectors. Instead that is left to the variant or platform HAL. The +architectural HAL does provide default implementations of +<function>HAL_INTERRUPT_ATTACH</function>, +<function>HAL_INTERRUPT_DETACH</function> and +<function>HAL_INTERRUPT_IN_USE</function> since these just involve +updating a static table. + </para> + <para> +By default the interrupt state control macros +<function>HAL_DISABLE_INTERRUPTS</function>, +<function>HAL_RESTORE_INTERRUPTS</function>, +<function>HAL_ENABLE_INTERRUPTS</function> and +<function>HAL_QUERY_INTERRUPTS</function> are implemented by the +architectural HAL, and simply involve updating the status register. +Disabling interrupts involves setting the three IPL bits to 0x07. +Enabling interrupts involves setting those bits to a smaller value, +<varname>CYGNUM_HAL_INTERRUPT_DEFAULT_IPL_LEVEL</varname>, which +defaults to 0. + </para> + <para> +<function>HAL_DISABLE_INTERRUPTS</function> has no effect on +non-maskable interrupts. This causes a problem because parts of the +system assume that all normal interrupt sources are affected by this +macro. If the target hardware can raise non-maskable interrupts then +it is the responsibility of application code to install a suitable VSR +and handle non-maskable interrupts entirely within the application, +bypassing the usual eCos ISR and DSR mechanisms. + </para> + <para> +The architectural HAL does not provide any support for the interrupt +controller management macros like +<function>HAL_INTERRUPT_MASK</function>. These can only be implemented +on a per-variant, per-processor or per-platform basis. + </para> + </refsect2> + + <refsect2 id="m68k-port-exceptions"><title>Exception Handling</title> + <para> +Synchronous exception handling is done in much the same way as +interrupt handling. The architectural HAL provides a generic entry +point <function>hal_m68k_exception_vsr</function>. On some variants +this can be used directly as the exception VSR, on others it will be +called via a small trampoline. + </para> + <para> +The details of exception handling vary widely from one variant to the +next. Some variants push a great deal of additional information on to +the stack for certain exceptions, but not all. The pushed program +counter may correspond to the specific instruction that caused the +exception, or the next instruction, or there may be only a loose +correlation because of buffered writes. The architectural HAL makes no +attempt to cope with all these differences, although some variants may +provide more advanced support. Otherwise if an exception needs to be +handled in a very specific way then it is up to the application to +install a suitable VSR and handle the exception directly. + </para> + </refsect2> + + <refsect2 id="m68k-port-stacks"><title>Stacks and Stack Sizes</title> + <para> +<filename class="headerfile">cyg/hal/hal_arch.h</filename> defines +values for minimal and recommended thread stack sizes, +<varname>CYGNUM_HAL_STACK_SIZE_MINIMUM</varname> and +<varname>CYGNUM_HAL_STACK_SIZE_TYPICAL</varname>. These values are +specific to the current configuration, and are affected mainly by +options related to interrupt handling. + </para> + <para> +By default eCos uses a separate interrupt stack, although this can be +disabled through the configuration option +<varname>CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK</varname>. +When an interrupt or exception occurs eCos will save the context on +the current stack and then switch to the interrupt stack before +calling the appropriate ISR interrupt handler. This means that thread +stacks can be significantly smaller because there is no need to worry +about interrupt handling overheads, just the thread context. However +switching the stack does require some extra work and hence increases +the interrupt latency. Disabling the interrupt stack removes this +processing overhead but requires larger stack sizes. It depends on +the application whether or not this is a sensible trade off. + </para> + <para> +By default eCos does not allow nested interrupts, but this can be +controlled via the configuration option +<varname>CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING</varname>. +Supporting nested interrupts requires larger thread stacks, especially +if the separate interrupt stack is also disabled. + </para> + <para> +Although the M68K has enough registers for typical operation, the +calling conventions are memory-oriented. In particular all arguments +are pushed on the stack rather than held in registers, and the return +address is also pushed rather than ending up in a link register. To +allow for this the recommended minimum stack sizes are a little bit +larger than for some other architectures. Variant HALs cannot directly +affect these stack sizes. However the sizes do depend in part on the +size of a thread context, so if for example the processor supports +hardware floating point and support for that is enabled then the stack +sizes will increase. + </para> + <para> +Usually the M68K architectural HAL will provide a single block of +memory which acts as both the startup and interrupt stack, and there +are <link linkend="m68k-config-stacks">configuration options</link> to +control the size of this block. Alternatively a variant, processor or +platform HAL may define either or both of +<varname>_HAL_M68K_STARTUP_STACK_</varname> and +<varname>_HAL_M68K_INTERRUPT_STACK_BASE_</varname> if for some reason +the stacks should not be placed in ordinary RAM. + </para> + </refsect2> + + <refsect2 id="m68k-port-context"><title>Thread Contexts and Setjmp/Longjmp</title> + <para> +A typical thread context consists of the following: + </para> + <orderedlist> + <listitem><para> +The integer context. This consists of the data registers +<varname>%d0</varname> to <varname>%d7</varname> and the address +registers <varname>%a0</varname> to <varname>%a6</varname>, The stack +pointer register <varname>%a7</varname> does not have to be saved +explicitly since it is implicit in the pointer to the saved context. + </para> + <para> +The caller-save registers are <varname>%d0</varname>, +<varname>%d1</varname>, <varname>%a0</varname>, +<varname>%a1</varname>, <varname>%a7</varname> and the status +register. The remaining registers are callee-save. Function arguments +are always passed on the stack. The result is held in +<varname>%d0</varname>. + </para></listitem> + <listitem><para> +Floating point context, consisting of eight 64-bit floating point +registers <varname>%fp0</varname> to <varname>%fp7</varname> and two +support registers <varname>%fpsr</varname> and +<varname>%fpiar</varname>. Support for this is only relevant if the +processor variant has a hardware floating point unit, and even then +saving floating point context is optional and can be disabled using a +configuration option <varname>CYGIMP_HAL_M68K_FPU_SAVE</varname>. The +control register <varname>%fpcr</varname> is not saved as part of the +context. It is assumed that a single <varname>%fpcr</varname> value, +usually <literal>0</literal>, will be used throughout the application. + </para> + <para> +The architectural HAL provides support for the hardware floating point +unit. The variant or processor HAL should implement the CDL interface +<varname>CYGINT_HAL_M68K_VARIANT_FPU</varname> if this hardware unit +is actually present. + </para></listitem> + <listitem><para> +Some M68K variants have additional hardware units, for example the +multiply-accumulate units in certain ColdFire processors. The +architectural HAL allows the context to be extended through various +macros such as <varname>HAL_CONTEXT_OTHER</varname>. + </para></listitem> + <listitem><para> +The status register <varname>%sr</varname> and the program counter. +These are special because when an interrupt occurs the hardware +automatically pushes these onto the stack, but exactly what gets +pushed depends on the variant. + </para></listitem> + </orderedlist> + <para> +<function>setjmp</function> and <function>longjmp</function> only deal +with the integer and fpu contexts. It is assumed that any special +hardware units will only be used by application code, not by the +compiler. Hence it is the responsibility of application code to +define and implement appropriate setjmp semantics for these units. +The variant HAL package can override the default implementations if +necessary. + </para> + <para> +When porting to a new M68K variant, if this has a hardware floating +point unit then the variant HAL should implement the CDL interface +<varname>CYGINT_HAL_M68K_VARIANT_FPU</varname>, thus enabling support +provided by the architectural HAL. If the variant has additional +hardware units involving state that should be preserved during a +context switch or when an interrupt occurs, the variant HAL should +define a number of macros. The header file <filename +class="headerfile">cyg/hal/var_arch.h</filename> should define +<varname>HAL_CONTEXT_OTHER</varname>, +<varname>HAL_CONTEXT_OTHER_SIZE</varname>, and +<varname>HAL_CONTEXT_OTHER_INIT</varname>, either directly or via +<filename class="headerfile">cyg/hal/proc_arch.h</filename>. The +assembler header file <filename +class="headerfile">cyg/hal/var.inc</filename> should define a number +of macros such as <function>hal_context_other_save_caller</function>. +For details of these macros see the architectural +<filename>hal_arch.S</filename> file. + </para> + <para> +Variants also need to define exactly how the status register and +program counter are saved onto the stack when an interrupt or +exception occurs. This is handled through C macros +<varname>HAL_CONTEXT_PCSR_SIZE</varname>, +<varname>HAL_CONTEXT_PCSR_RTE_ADJUST</varname>, and +<function>HAL_CONTEXT_PCSR_INIT</function>, and a number of assembler +macros such as <function>hal_context_pcsr_save_sr</function>. Again +the architectural files <filename +class="headerfile">cyg/hal/hal_arch.h</filename> and +<filename>hal_arch.S</filename> provide more details of these. + </para> + </refsect2> + + <refsect2 id="m68k-port-bitindex"><title>Bit Indexing</title> + <para> +For performance reasons the <function>HAL_LSBIT_INDEX</function> and +<function>HAL_MSBIT_INDEX</function> macros are implemented using +assembler functions. A variant HAL can override the default +definitions if, for example, the variant has special instructions to +perform these operations. + </para> + </refsect2> + + <refsect2 id="m68k-port-idle"><title>Idle Thread Processing</title> + <para> +The default <function>HAL_IDLE_THREAD_ACTION</function> implementation +is a no-op. A variant HAL may override this, for example to put the +processor into sleep mode. Alternative implementations should consider +exactly how this macro gets used in eCos kernel code. + </para> + </refsect2> + + <refsect2 id="m68k-port-clock"><title>Clock Support</title> + <para> +The architectural HAL cannot provide the required clock support +because it does not know what timer hardware may be available on the +target hardware. Instead this is left to either the variant or +platform HAL, depending on whether the processor has a suitable +on-chip timer or whether an off-chip timer has to be used. + </para> + </refsect2> + + <refsect2 id="m68k-port-io"><title>HAL I/O</title> + <para> +The M68K architecture does not have a separate I/O bus. Instead all +hardware is assumed to be memory-mapped. Further it is assumed that +all peripherals on the memory bus are wired appropriately for a +big-endian processor and that there is no need for any byte swapping. +Hence the various HAL macros for performing I/O simply involve +pointers to volatile memory. + </para> + <para> +The variant, processor and platform equivalents of the <filename +class="headerfile">cyg/hal/hal_io.h</filename> header will typically +also provide details of some or all of the peripherals, for example +register offsets and the meaning of various bits in those registers. + </para> + </refsect2> + + <refsect2 id="m68k-port-cache"><title>Cache Handling</title> + <para> +If the processor has a cache then the variant HAL should implement the +CDL interface <varname>CYGINT_HAL_M68K_VARIANT_CACHE</varname>. This +causes the architectural header <filename +class="headerfile">cyg/hal/hal_cache.h</filename> to pick up +appropriate definitions from <filename +class="headerfile">cyg/hal/var_cache.h</filename>. The architectural +header will provide null defaults for anything not defined by the +variant. + </para> + </refsect2> + + <refsect2 id="m68k-port-ldscript"><title>Linker Scripts</title> + <para> +The architectural HAL will generate the linker script for eCos +applications. This involves the architectural file +<filename>m68k.ld</filename> and a <filename>.ldi</filename> memory +layout file provided lower down, typically by the platform HAL. It is +the LDI file which specifies the types and amount of memory available +and which places code and data in appropriate places, but most of the +hard work is done via macros provided by the architectural +<filename>m68k.ld</filename> file. + </para> + </refsect2> + + <refsect2 id="m68k-port-diag"><title>Diagnostic Support</title> + <para> +The architectural HAL does not implement diagnostic support. Instead +this is left to the variant or platform HAL, depending on whether +suitable peripherals are available on-chip or off-chip. + </para> + </refsect2> + + <refsect2 id="m68k-port-smp"><title>SMP Support</title> + <para> +The M68K port does not have SMP support. + </para> + </refsect2> + + <refsect2 id="m68k-port-gdb"><title>Debug Support</title> + <para> +The M68K architectural HAL package provides basic support only for gdb +stubs. There is no support for more advanced debug features like +hardware watchpoints. + </para> + <para> +The generic gdb support in the common HAL requires a platform header +<filename class="headerfile"><cyg/hal/plf_stub.h</filename>. In +practice there is rarely any need for the contents of this file to +change between platforms so the architectural HAL can provide a +suitable default. It will do so if the CDL interface +<varname>CYGINT_HAL_M68K_USE_STANDARD_PLATFORM_STUB_SUPPORT</varname> +is implemented. + </para> + </refsect2> + + <refsect2 id="m68k-port-delay"><title>HAL_DELAY_US Macro</title> + <para> +The architectural HAL provides a default implementation of the +standard <function>HAL_DELAY_US</function> macro using a simply busy +loop. To use this support a lower-level HAL should define +<varname>_HAL_M68K_DELAY_US_LOOPS_</varname>, typically a small number +of about 20 but it will need to be calibrated during the porting +process. If the processor has a cache then the lower-level HAL may +also define <varname>_HAL_M68K_DELAY_US_LOOPS_UNCACHED_</varname> for +the case when a delay loop is triggered while the cache is disabled. + </para> + </refsect2> + + <refsect2 id="m68k-port-profiling"><title>Profiling Support</title> + <para> +The M68K architectural HAL implements the <function>mcount</function> +function, allowing profiling tools like +<application>gprof</application> to determine the application's call +graph. It does not implement the profiling timer. Instead that +functionality needs to be provided by the variant or platform HAL. +The implementation of <function>mcount</function> requires a dedicated +frame pointer register so code should be compiled without the +<option>-fomit-frame-pointer</option> flag. + </para> + </refsect2> + + <refsect2 id="m68k-port-other"><title>Other Functionality</title> + <para> +The M68K architectural HAL only implements the functionality provided +by the eCos HAL specification and does not export any extra +functionality. + </para> + </refsect2> + + </refsect1> + +</refentry> + +<!-- }}} --> + +</part> diff --git a/ecos/packages/hal/m68k/arch/current/include/arch.inc b/ecos/packages/hal/m68k/arch/current/include/arch.inc new file mode 100644 index 0000000..dde50b9 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/include/arch.inc @@ -0,0 +1,88 @@ +##============================================================================= +## +## arch.inc +## +## M68K architecture assembler header file +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): bartv +## Date: 2003-06-04 +######DESCRIPTIONEND#### +##============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/var.inc> + +// ---------------------------------------------------------------------------- +// Utility macros for defining normal and weak functions. + +#define FUNC_START(name) \ + .section .text. ## name ; \ + .balign 4 ; \ + .globl name ; \ + .type name, @function ; \ +name: + +#define FUNC_START_WEAK(name) \ + .section .text._ ## name ; \ + .weak name ; \ + .set name, _ ## name ; \ + .balign 4 ; \ + .globl _ ## name ; \ + .type name, @function ; \ +_ ## name: + +// ---------------------------------------------------------------------------- +// Default system and interrupt stack. This is used only if the +// platform HAL has not already supplied suitable stacks. + +#ifndef _HAL_M68K_STARTUP_STACK_ + .extern _hal_m68k_startup_stack_base_ + .extern _hal_m68k_startup_stack_ +# define _HAL_M68K_STARTUP_STACK_ # _hal_m68k_startup_stack_ +# define _HAL_M68K_INSTANTIATE_STARTUP_STACK_ +#endif +#ifndef _HAL_M68K_INTERRUPT_STACK_BASE_ + .extern _hal_m68k_interrupt_stack_base_ + .extern _hal_m68k_interrupt_stack_ +# define _HAL_M68K_INTERRUPT_STACK_BASE_ # _hal_m68k_interrupt_stack_base_ +# define _HAL_M68K_INTERRUPT_STACK_ # _hal_m68k_interrupt_stack_ +# define _HAL_M68K_INSTANTIATE_INTERRUPT_STACK_ +#endif + +#------------------------------------------------------------------------------ +# end of arch.inc diff --git a/ecos/packages/hal/m68k/arch/current/include/basetype.h b/ecos/packages/hal/m68k/arch/current/include/basetype.h new file mode 100644 index 0000000..920816e --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/include/basetype.h @@ -0,0 +1,82 @@ +#ifndef CYGONCE_HAL_BASETYPE_H +#define CYGONCE_HAL_BASETYPE_H + +//============================================================================= +// +// basetype.h +// +// Standard types for this architecture. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal_m68k.h> +#ifdef CYGINT_HAL_M68K_VARIANT_TYPES +# include <cyg/hal/var_basetype.h> +#endif + +//----------------------------------------------------------------------------- +// Characterize the architecture: big-endian +#ifndef CYG_BYTEORDER +# define CYG_BYTEORDER CYG_MSBFIRST +#endif + +//----------------------------------------------------------------------------- +// 68k does not usually use labels with underscores. +#define CYG_LABEL_NAME(_name_) _name_ + +// ---------------------------------------------------------------------------- +// The 68k architecture uses the default definitions of the base types, +// so we do not need to define any here. + +//----------------------------------------------------------------------------- +// Override the alignment definitions from cyg_type.h. +// Most 68k variants use a 4 byte alignment. +// A few variants (68000) may override this setting to use a 2 byte alignment. +#ifndef CYGARC_ALIGNMENT +# define CYGARC_ALIGNMENT 4 +#endif +// the corresponding power of two alignment +#ifndef CYGARC_P2ALIGNMENT +# define CYGARC_P2ALIGNMENT 2 +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_BASETYPE_H diff --git a/ecos/packages/hal/m68k/arch/current/include/hal_arch.h b/ecos/packages/hal/m68k/arch/current/include/hal_arch.h new file mode 100644 index 0000000..baae8e2 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/include/hal_arch.h @@ -0,0 +1,474 @@ +#ifndef CYGONCE_HAL_ARCH_H +#define CYGONCE_HAL_ARCH_H + +//============================================================================= +// +// hal_arch.h +// +// Architecture specific abstractions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/var_arch.h> + +// ---------------------------------------------------------------------------- +// The default IPL level for when interrupts are enabled. Usually this will +// be set to 0, but on some platforms it may be appropriate to run with +// a higher IPL level and effectively leave some interrupts disabled. + +#ifndef CYGNUM_HAL_INTERRUPT_DEFAULT_IPL_LEVEL +# define CYGNUM_HAL_INTERRUPT_DEFAULT_IPL_LEVEL 0 +#endif + +// ---------------------------------------------------------------------------- +// setjmp/longjmp support. These only deal with the integer and fpu units. +// If there are other hardware units then they are unlikely to be used +// directly by the compiler, only by application code. Hence it is +// application code that should decide whether or not each unit's state +// should be preserved across setjmp/longjmp boundaries. +// +// Floating point registers have to be saved/restored here even if they +// are not saved during a context switch, because we are concerned +// about state within a single thread. The control and status registers +// are saved as well, but fpiar can be ignored - setjmp() is not going +// to happen while handling a floating point exception. +// +// The default implementation is in assembler and uses weak aliases. That +// code has to be kept in step with this structure definition. + +#ifndef HAL_SETJMP +#define HAL_SETJMP + +typedef struct { + CYG_ADDRESS pc; + CYG_ADDRESS sp; + cyg_uint32 d[6]; // d2 to d7, d0 and d1 are caller-save + CYG_ADDRESS a[5]; // a2 to a6, a0 and a1 are caller-save, a7 (sp) is separate +#ifdef CYGINT_HAL_M68K_VARIANT_FPU + long double f[6]; // f2 to f7, f0 and f1 are caller-save +#endif +} hal_jmp_buf_t; + +// This type is used by normal routines to pass the address of the +// structure into our routines without having to explicitly take the +// address of the structure. +typedef cyg_uint32 hal_jmp_buf[sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32)]; + +externC int hal_m68k_setjmp(hal_jmp_buf); +externC void hal_m68k_longjmp(hal_jmp_buf, int); +#define hal_setjmp(_env) hal_m68k_setjmp(_env) +#define hal_longjmp(_env, _val) hal_m68k_longjmp(_env, _val) + +#endif // HAL_SETJMP + +// ---------------------------------------------------------------------------- +// Thread context support. The implementation is in assembler functions +// rather than inline macros. That makes it easier to cope with +// hardware-specific units which have their own context. +// +// A thread context consists of an integer part, a floating point part +// (iff the hardware has a standard FPU and if the configuration makes +// FPU context part of the save state), and OTHER for extra hardware +// units. + +#define HAL_M68K_SR_C (0x01 << 0) +#define HAL_M68K_SR_V (0x01 << 1) +#define HAL_M68K_SR_Z (0x01 << 2) +#define HAL_M68K_SR_N (0x01 << 3) +#define HAL_M68K_SR_X (0x01 << 4) +#define HAL_M68K_SR_S (0x01 << 13) +#define HAL_M68K_SR_T (0x01 << 15) +#define HAL_M68K_SR_IPL_MASK (0x07 << 8) +#define HAL_M68K_SR_IPL_SHIFT 8 + +typedef struct { + // The integer context, d0-d7,a0-a6 + cyg_uint32 da[15]; + + // FPU context. This is only relevant if the hardware has an FPU, + // and then only if the configuration makes the FPU context part + // of the save state. +#ifdef CYGIMP_HAL_M68K_FPU_SAVE + cyg_uint32 fpsr; + CYG_ADDRESS fpiar; + long double f[8]; +#endif + + // Some m68k variants may have additional state that should be part + // of a thread context. +#ifdef HAL_CONTEXT_OTHER + HAL_CONTEXT_OTHER +#endif + + // Program counter, status register, etc. The exact layout is + // determined by the variant. The intention is that the structure + // matches the state pushed onto the stack by the hardware when an + // interrupt occurs, so the context can overlap this part of the + // stack. That avoids having to copy the saved PC and SR registers + // from the stack into the context structure. The final step of + // a context switch is an rte instruction. + HAL_CONTEXT_PCSR + +} HAL_SavedRegisters; + +#define HAL_CONTEXT_INTEGER_SIZE (15 * 4) +#ifdef CYGIMP_HAL_M68K_FPU_SAVE +# define HAL_CONTEXT_FPU_SIZE ((2 * 4) + (8 * 12)) +#else +# define HAL_CONTEXT_FPU_SIZE 0 +#endif +#ifndef HAL_CONTEXT_OTHER_SIZE +# define HAL_CONTEXT_OTHER_SIZE 0 +#endif +#ifndef HAL_CONTEXT_PCSR_SIZE +# define HAL_CONTEXT_PCSR_SIZE 8 +#endif + +#define HAL_CONTEXT_FULL_SIZE (HAL_CONTEXT_INTEGER_SIZE + HAL_CONTEXT_FPU_SIZE + HAL_CONTEXT_OTHER_SIZE + HAL_CONTEXT_PCSR_SIZE) + +// Load and switch are handled by functions in hal_arch.S. One level +// of indirection is removed here for the destination thread, so that +// the actual stack pointer gets passed to assembler. +externC void hal_thread_load_context(CYG_ADDRESS) CYGBLD_ATTRIB_NORET; +externC void hal_thread_switch_context(CYG_ADDRESS, CYG_ADDRESS); + +#define HAL_THREAD_LOAD_CONTEXT(_to_) \ + CYG_MACRO_START \ + hal_thread_load_context((CYG_ADDRESS) *(_to_)); \ + CYG_MACRO_END + +#define HAL_THREAD_SWITCH_CONTEXT(_from_, _to_) \ + CYG_MACRO_START \ + hal_thread_switch_context((CYG_ADDRESS)(_from_), (CYG_ADDRESS)*(_to_)); \ + CYG_MACRO_END + +// Init context can be done easily in C. +// +// LOAD_CONTEXT and SWITCH_CONTEXT will end up doing an rte, so at the top +// of the stack we want the SR, return PC, a dummy PC for the entry point's +// stack frame, and the argument to the function. +// +// +----------------+ +// | _thread_ arg | +// +----------------+ +// | return PC | +// +----------------+ +// | _entry_ PC | +// +- - - - - - - - + +// | SR | +// SP ----> +- - - - - - - - + +// | HAL | +// | SavedRegisters | +// | | +// +// FPU and OTHER contexts are handled by macros which may or may not expand. +// +// The PC/SR fields are handled by variant-specific code. + +#ifdef CYGIMP_HAL_M68K_FPU_SAVE +# define HAL_CONTEXT_FPU_INIT(_regs_) \ + CYG_MACRO_START \ + int _j_; \ + (_regs_)->fpsr = 0; \ + (_regs_)->fpiar = 0; \ + for (_j_ = 0; _j_ < 8; _j_++) { \ + (_regs_)->f[_j_] = 0.0; \ + } \ + CYG_MACRO_END +#else +# define HAL_CONTEXT_FPU_INIT(_regs_) +#endif +#ifndef HAL_CONTEXT_OTHER_INIT +# define HAL_CONTEXT_OTHER_INIT(_regs_) +#endif + +// Only initialize with ints enabled if CYGPKG_KERNEL. RedBoot does a +// LoadContext, causing interrupts to be enabled prematurely. +#ifdef CYGPKG_KERNEL +# define _HAL_M68K_INIT_CONTEXT_SR_ (0x2000 | (CYGNUM_HAL_INTERRUPT_DEFAULT_IPL_LEVEL<<8)) +#else +# define _HAL_M68K_INIT_CONTEXT_SR_ (0x2700) +#endif + +#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_) \ + CYG_MACRO_START \ + cyg_uint32* _sp_ = ((cyg_uint32*) ((cyg_uint32)(_sparg_) & ~(CYGARC_ALIGNMENT - 1))); \ + HAL_SavedRegisters* _regs_; \ + int _i_; \ + *(--_sp_) = (cyg_uint32)(_thread_); \ + *(--_sp_) = 0xDEADC0DE; \ + _regs_ = (HAL_SavedRegisters*) ((cyg_uint32)_sp_ - sizeof(HAL_SavedRegisters)); \ + for (_i_ = 0; _i_ < 14; _i_++) { \ + _regs_->da[_i_] = _id_; \ + } \ + _regs_->da[14] = 0; \ + HAL_CONTEXT_FPU_INIT(_regs_) \ + HAL_CONTEXT_OTHER_INIT(_regs_) \ + HAL_CONTEXT_PCSR_INIT(_regs_, _entry_, _HAL_M68K_INIT_CONTEXT_SR_); \ + (_sparg_) = (CYG_ADDRESS) (_regs_); \ + CYG_MACRO_END + +// ---------------------------------------------------------------------------- +// Minimal and sensible stack sizes: the intention is that applications +// will use these to provide a stack size in the first instance prior to +// proper analysis. Idle thread stack should be this big. +// +// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. +// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. +// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! +// +// This is not a config option because it should not be adjusted except +// under "enough rope" sort of disclaimers. + +// Stack frame overhead per call. 6 data registers, 5 address +// registers, frame pointer, and return address. We can't guess the +// local variables so just assume that using all of the registers +// averages out. +# define CYGNUM_HAL_STACK_FRAME_SIZE ((6 + 5 + 1 + 1) * 4) + +// Stack needed for a context switch. Allow for sr and vector as well. +#ifndef CYGNUM_HAL_STACK_CONTEXT_SIZE +# define CYGNUM_HAL_STACK_CONTEXT_SIZE HAL_CONTEXT_FULL_SIZE +#endif + +// Interrupt handling. These need to allow for nesting and a +// separate interrupt stack. +#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +# ifndef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING + +// No interrupt stack, no nesting. Worst case: a saved context, a +// frame for the interrupt_end() call, six frames for DSR processing, +// another saved context for an interrupt during the DSRs, and +// six frames for the ISR. +# define CYGNUM_HAL_STACK_INTERRUPT_SIZE ((2 * CYGNUM_HAL_STACK_CONTEXT_SIZE) + (13 * CYGNUM_HAL_STACK_FRAME_SIZE)) + +# else +// No interrupt stack but nesting. Worst case: a saved context, +// a frame for interrupt_end(), six frames for DSR processing, then +// up to five higher priority interrupts each requiring a context +// and six frames. +# define CYGNUM_HAL_STACK_INTERRUPT_SIZE ((6 * CYGNUM_HAL_STACK_CONTEXT_SIZE) + (37 * CYGNUM_HAL_STACK_FRAME_SIZE)) +# endif + +#else + +# ifndef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING +// An interrupt stack but no nesting. Worst case: a saved context, +// a frame for interrupt_end(), and another saved context. There +// is no need to worry about ISR or DSR frames since those will +// be on the interrupt stack. We also need to allow for nested +// interrupts before these are disabled, which will involve only +// 2 words rather than a full stack. +# define CYGNUM_HAL_STACK_INTERRUPT_SIZE ((2 * CYGNUM_HAL_STACK_CONTEXT_SIZE) + (1 * CYGNUM_HAL_STACK_FRAME_SIZE) + (5 * 2 * 4)) + +# else +// An interrupt stack and nesting. We need to allow for another five +// nested contexts because nested interrupts may happen after pushing +// the current context but before switching to the interrupt stack. +# define CYGNUM_HAL_STACK_INTERRUPT_SIZE ((7 * CYGNUM_HAL_STACK_CONTEXT_SIZE) + (1 * CYGNUM_HAL_STACK_FRAME_SIZE)) + +# endif +#endif + +// We define a minimum stack size as the minimum any thread could ever +// legitimately get away with. We can throw asserts if users ask for +// less than this. This allows for a saved context for context switching +// plus eight stack frames for cals, in addition to the interrupt overhead. +#define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_INTERRUPT_SIZE + CYGNUM_HAL_STACK_CONTEXT_SIZE + (8 * CYGNUM_HAL_STACK_FRAME_SIZE)) + +// Now make a reasonable choice for a typical thread size. Allow for +// another 8 call frames and a K for on-stack buffers, printf(), +// and debugging overheads. +#define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM + (8 * CYGNUM_HAL_STACK_FRAME_SIZE) + 1024) + +// ----------------------------------------------------------------------------- +// Bit manipulation routines. The vanilla 68000 has no special +// instructions for this so assembler implementations are used +// instead. Newer ColdFires do have suitable instructions so will +// define their own versions of these macro. + +#ifndef HAL_LSBIT_INDEX +externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); +#define HAL_LSBIT_INDEX(index, mask) (index) = hal_lsbit_index(mask); +#endif +#ifndef HAL_MSBIT_INDEX +externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); +#define HAL_MSBIT_INDEX(index, mask) (index) = hal_msbit_index(mask); +#endif + +// There are some useful bit-set and bit-clear instructions which allow +// for atomic updates of a single byte of memory. +#define HAL_M68K_BSET(_address_, _bit_) \ + CYG_MACRO_START \ + asm volatile("bset %0,(%1)\n" : : "i" (_bit_), "a" (_address_) : "cc", "memory"); \ + CYG_MACRO_END + +#define HAL_M68K_BCLR(_address_, _bit_) \ + CYG_MACRO_START \ + asm volatile("bclr %0,(%1)\n" : : "i" (_bit_), "a" (_address_) : "cc", "memory"); \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// Idle thread code. A plain 68000 has no special support, so a no-op +// function is used. Variants may use this to go into sleep mode. + +#ifndef HAL_IDLE_THREAD_ACTION +# define HAL_IDLE_THREAD_ACTION(_count_) CYG_EMPTY_STATEMENT +#endif + +//----------------------------------------------------------------------------- +// Execution reorder barrier. +// When optimizing the compiler can reorder code. In multithreaded systems +// where the order of actions is vital, this can sometimes cause problems. +// This macro may be inserted into places where reordering should not happen. + +#define HAL_REORDER_BARRIER() __asm__ volatile ( "" : : : "memory" ) + +//-------------------------------------------------------------------------- +// Macros for switching context between two eCos instances (jump from +// code in ROM to code in RAM or vice versa). The 68000 does not have any +// relevant global state so these macros are no-ops. + +#define CYGARC_HAL_SAVE_GP() +#define CYGARC_HAL_RESTORE_GP() + +//----------------------------------------------------------------------------- +// gdb support + +// Translate a stack pointer as saved by the thread context macros +// into a pointer to a HAL_SavedRegisters structure. On the 68K +// these are equivalent. +#define HAL_THREAD_GET_SAVED_REGISTERS(_stack_, _regs_) \ + CYG_MACRO_START \ + (_regs_) = (HAL_SavedRegisters*)(_stack_); \ + CYG_MACRO_END + +// Translate between an eCos context and a gdb register set. +externC void hal_get_gdb_registers(CYG_ADDRWORD*, HAL_SavedRegisters*); +externC void hal_set_gdb_registers(HAL_SavedRegisters*, CYG_ADDRWORD*); + +#define HAL_GET_GDB_REGISTERS(_regval_, _regs_) \ + CYG_MACRO_START \ + hal_get_gdb_registers((CYG_ADDRWORD*)(_regval_), (HAL_SavedRegisters*)(_regs_)); \ + CYG_MACRO_END + +#define HAL_SET_GDB_REGISTERS(_regs_,_regval_) \ + CYG_MACRO_START \ + hal_set_gdb_registers((HAL_SavedRegisters*)(_regs_), (CYG_ADDRWORD*)(_regval_)); \ + CYG_MACRO_END + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen +// if executed. +// HAL_BREAKINST is the value of the breakpoint instruction and +// HAL_BREAKINST_SIZE is its size in bytes. + +#define HAL_BREAKPOINT(_label_) \ +__asm__ volatile (" .globl " #_label_ ";" \ + #_label_":" \ + " trap #15" \ + ); + +#define HAL_BREAKINST 0x4E4F + +#define HAL_BREAKINST_SIZE 2 + +// The GDB register definitions. as per gdb/m68k-stub.c +// FIXME: more work is needed for floating point support. +enum regnames { + D0, D1, D2, D3, D4, D5, D6, D7, + A0, A1, A2, A3, A4, A5, FP, SP, + PS, PC, +#ifdef CYGINT_HAL_M68K_VARIANT_FPU + FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, + FPCONTROL, FPSTATUS, FPIADDR +#endif +}; + +#ifdef CYGINT_HAL_M68K_VARIANT_FPU +# define NUMREGS 29 +#else +# define NUMREGS 18 +#endif + +#define REGSIZE(_x_) (4) + +typedef enum regnames regnames_t; +typedef CYG_ADDRWORD target_register_t; + +externC int __computeSignal(unsigned int trap_number); +externC int __get_trap_number(void); +externC void __install_breakpoints(void); +externC void __clear_breakpoints(void); +externC void __single_step(void); +externC void __clear_single_step(void); +externC void __skipinst(void); +externC int __is_breakpoint_function(void); +externC void set_pc(target_register_t); + +#define HAL_STUB_PLATFORM_STUBS_FIXUP() \ + CYG_MACRO_START \ + if (CYGNUM_HAL_VECTOR_TRAP15 == __get_trap_number()) \ + put_register(PC, get_register(PC) - 2); \ + CYG_MACRO_END + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +// Exception handling function. +// This function is defined by the kernel according to this prototype. It is +// invoked from the HAL to deal with any CPU exceptions that the HAL does +// not want to deal with itself. It usually invokes the kernel's exception +// delivery mechanism. +#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && defined(CYGPKG_HAL_EXCEPTIONS) +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_ARCH_H +// End of hal_arch.h + diff --git a/ecos/packages/hal/m68k/arch/current/include/hal_cache.h b/ecos/packages/hal/m68k/arch/current/include/hal_cache.h new file mode 100644 index 0000000..1004b1e --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/include/hal_cache.h @@ -0,0 +1,103 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k.h> +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#endif + +#ifdef CYGINT_HAL_M68K_VARIANT_CACHE +# include <cyg/hal/var_cache.h> +#endif + +// Default anything not defined by the variant HAL. Some of these +// macros get used unconditionally by other code so must be +// defined, to no-op. +#ifndef HAL_ICACHE_ENABLE +# define HAL_ICACHE_ENABLE() +#endif +#ifndef HAL_ICACHE_DISABLE +# define HAL_ICACHE_DISABLE() +#endif +#ifndef HAL_ICACHE_SYNC +# define HAL_ICACHE_SYNC() +#endif +#ifndef HAL_ICACHE_INVALIDATE_ALL +# define HAL_ICACHE_INVALIDATE_ALL() +#endif +#ifndef HAL_ICACHE_IS_ENABLED +# define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END +#endif + +#ifndef HAL_DCACHE_ENABLE +# define HAL_DCACHE_ENABLE() +#endif +#ifndef HAL_DCACHE_DISABLE +# define HAL_DCACHE_DISABLE() +#endif +#ifndef HAL_DCACHE_SYNC +# define HAL_DCACHE_SYNC() +#endif +#ifndef HAL_DCACHE_INVALIDATE_ALL +# define HAL_DCACHE_INVALIDATE_ALL() +#endif +#ifndef HAL_DCACHE_IS_ENABLED +# define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END +#endif + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h diff --git a/ecos/packages/hal/m68k/arch/current/include/hal_intr.h b/ecos/packages/hal/m68k/arch/current/include/hal_intr.h new file mode 100644 index 0000000..4faf2c9 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/include/hal_intr.h @@ -0,0 +1,349 @@ +#ifndef CYGONCE_HAL_HAL_INTR_H +#define CYGONCE_HAL_HAL_INTR_H + +//========================================================================== +// +// hal_intr.h +// +// m68k Interrupt and clock support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/hal/hal_arch.h> + +// Allow variants to override some of these settings. +#include <cyg/hal/var_intr.h> + +//-------------------------------------------------------------------------- +// m68k exception vectors. These correspond to VSRs and are the values +// to use for HAL_VSR_GET/SET + +extern CYG_ADDRESS hal_m68k_vsr_table[]; + +#ifndef HAL_VSR_GET +# define HAL_VSR_GET( _vector_, _pvsr_ ) \ + CYG_MACRO_START \ + *((CYG_ADDRESS *)(_pvsr_)) = hal_m68k_vsr_table[(_vector_)]; \ + CYG_MACRO_END +#endif + +#if !defined(HAL_VSR_SET) && !defined(_HAL_M68K_NO_VSR_SET_) +# define HAL_VSR_SET( _vector_arg_, _vsr_, _poldvsr_arg_ ) \ + CYG_MACRO_START \ + cyg_uint32 _vector_ = (cyg_uint32) (_vector_arg_); \ + CYG_ADDRESS* _poldvsr_ = (CYG_ADDRESS*)(_poldvsr_arg_); \ + if(_poldvsr_ != (CYG_ADDRESS*)0 ) \ + *_poldvsr_ = hal_m68k_vsr_table[(_vector_)]; \ + hal_m68k_vsr_table[(_vector_)] = (CYG_ADDRESS)(_vsr_); \ + CYG_MACRO_END +#endif + +#define CYGNUM_HAL_VECTOR_SSP 0 +#define CYGNUM_HAL_VECTOR_RESET 1 +#define CYGNUM_HAL_VECTOR_BUSERR 2 +#define CYGNUM_HAL_VECTOR_ADDERR 3 +#define CYGNUM_HAL_VECTOR_ILLINST 4 +#define CYGNUM_HAL_VECTOR_ZERODIV 5 +#define CYGNUM_HAL_VECTOR_CHKINST 6 +#define CYGNUM_HAL_VECTOR_TRAPVINST 7 +#define CYGNUM_HAL_VECTOR_PRIVVIOLATION 8 +#define CYGNUM_HAL_VECTOR_TRACE 9 +#define CYGNUM_HAL_VECTOR_L1010 10 +// 12-14 are reserved +#define CYGNUM_HAL_VECTOR_L1111 11 +#define CYGNUM_HAL_VECTOR_UNINITINT 15 +// 16-23 are reserved +#define CYGNUM_HAL_VECTOR_SPURINT 24 +#define CYGNUM_HAL_VECTOR_AUTOVEC1 25 +#define CYGNUM_HAL_VECTOR_AUTOVEC2 26 +#define CYGNUM_HAL_VECTOR_AUTOVEC3 27 +#define CYGNUM_HAL_VECTOR_AUTOVEC4 28 +#define CYGNUM_HAL_VECTOR_AUTOVEC5 29 +#define CYGNUM_HAL_VECTOR_AUTOVEC6 30 +#define CYGNUM_HAL_VECTOR_AUTOVEC7 31 +#define CYGNUM_HAL_VECTOR_NMI CYGNUM_HAL_VECTOR_AUTOVEC7 +#define CYGNUM_HAL_VECTOR_TRAP0 32 +#define CYGNUM_HAL_VECTOR_TRAPFIRST 32 +#define CYGNUM_HAL_VECTOR_TRAP1 33 +#define CYGNUM_HAL_VECTOR_TRAP2 34 +#define CYGNUM_HAL_VECTOR_TRAP3 35 +#define CYGNUM_HAL_VECTOR_TRAP4 36 +#define CYGNUM_HAL_VECTOR_TRAP5 37 +#define CYGNUM_HAL_VECTOR_TRAP6 38 +#define CYGNUM_HAL_VECTOR_TRAP7 39 +#define CYGNUM_HAL_VECTOR_TRAP8 40 +#define CYGNUM_HAL_VECTOR_TRAP9 41 +#define CYGNUM_HAL_VECTOR_TRAP10 42 +#define CYGNUM_HAL_VECTOR_TRAP11 43 +#define CYGNUM_HAL_VECTOR_TRAP12 44 +#define CYGNUM_HAL_VECTOR_TRAP13 45 +#define CYGNUM_HAL_VECTOR_TRAP14 46 +/* TRAP15 is used by gdb stubs */ +#define CYGNUM_HAL_VECTOR_TRAP15 47 +#define CYGNUM_HAL_VECTOR_TRAPLAST CYGNUM_HAL_VECTOR_TRAP15 +#define CYGNUM_HAL_VECTOR_NUMTRAPS 16 +// 48-63 are reserved +#define CYGNUM_HAL_VECTOR_INTRFIRST 64 +#define CYGNUM_HAL_VECTOR_NUMINTRS 192 +#define CYGNUM_HAL_VECTOR_INTRLAST (CYGNUM_HAL_VECTOR_INTRFIRST+CYGNUM_HAL_VECTOR_NUMINTRS-1) + +#define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_SSP +#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTRLAST +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + +// ---------------------------------------------------------------------------- +// Also give details of the defined exceptions. Only some of the exceptions +// are named explicitly here. +// NOTE: FPU exceptions should be added + +#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_BUSERR +#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS CYGNUM_HAL_VECTOR_ADDERR +#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION CYGNUM_HAL_VECTOR_ILLINST +#define CYGNUM_HAL_EXCEPTION_DIV_BY_ZERO CYGNUM_HAL_VECTOR_ZERODIV +#define CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR CYGNUM_HAL_VECTOR_CHKINST +#define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE +#define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_TRAP15 + +#ifndef CYGNUM_HAL_EXCEPTION_COUNT +# define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VECTOR_BUSERR +# define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VECTOR_TRAPLAST +# define CYGNUM_HAL_EXCEPTION_COUNT ((CYGNUM_HAL_EXCEPTION_MAX-CYGNUM_HAL_EXCEPTION_MIN)+1) +#endif + +//-------------------------------------------------------------------------- +// ISR vectors. + +#ifndef CYGNUM_HAL_ISR_COUNT +# error The variant or platform HAL should provide details of ISR vectors. +#endif + +// Default definition of HAL_TRANSLATE_VECTOR() +#ifndef HAL_TRANSLATE_VECTOR +# define HAL_TRANSLATE_VECTOR(_vector_, _index_) \ + ((_index_) = ((_vector_) - CYGNUM_HAL_ISR_MIN)) +#endif + +externC volatile CYG_ADDRESS cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRESS cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); +// For consistency with other architectures. +#define hal_interrupt_handlers cyg_hal_interrupt_handlers + +#ifndef HAL_INTERRUPT_IN_USE +# define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ + CYG_MACRO_START \ + if (cyg_hal_interrupt_handlers[(_vector_)] ==(CYG_ADDRESS)&hal_default_isr) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ + CYG_MACRO_END +#endif + +#ifndef HAL_INTERRUPT_ATTACH +# define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ + CYG_MACRO_START \ + cyg_hal_interrupt_handlers[(_vector_)] = (CYG_ADDRESS)(_isr_); \ + cyg_hal_interrupt_data[(_vector_)] = (CYG_ADDRWORD)(_data_); \ + cyg_hal_interrupt_objects[(_vector_)] = (CYG_ADDRESS)(_object_); \ + CYG_MACRO_END +#endif + +#ifndef HAL_INTERRUPT_DETACH +# define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ + CYG_MACRO_START \ + if (cyg_hal_interrupt_handlers[(_vector_)] == (CYG_ADDRESS)(_isr_)) { \ + cyg_hal_interrupt_handlers[(_vector_)] = (CYG_ADDRESS)&hal_default_isr; \ + cyg_hal_interrupt_data[(_vector_)] = 0; \ + cyg_hal_interrupt_objects[(_vector_)] = 0; \ + } \ + CYG_MACRO_END +#endif + +//-------------------------------------------------------------------------- +// Interrupt control macros. These just operate on the entire status +// register. + +typedef cyg_uint16 CYG_INTERRUPT_STATE; + +#ifndef HAL_ENABLE_INTERRUPTS +# define HAL_ENABLE_INTERRUPTS() \ + CYG_MACRO_START \ + asm volatile ("move.w %0,%%sr\n" \ + : \ + : "J" (0x2000 | (CYGNUM_HAL_INTERRUPT_DEFAULT_IPL_LEVEL << 8)) \ + : "cc"); \ + CYG_MACRO_END +#endif // HAL_ENABLE_INTERRUPTS + +#ifndef HAL_DISABLE_INTERRUPTS +# define HAL_DISABLE_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + asm volatile ("move.w %%sr,%0\n" \ + "move.w #0x2700,%%sr\n" : "=d" (_old_) : : "cc"); \ + CYG_MACRO_END +#endif // HAL_DISABLE_INTERRUPTS + +#ifndef HAL_RESTORE_INTERRUPTS +# define HAL_RESTORE_INTERRUPTS(_prev_) \ + CYG_MACRO_START \ + asm volatile ("move.w %0,%%sr\n" : : "d" (_prev_) : "cc"); \ + CYG_MACRO_END +#endif + +#ifndef HAL_QUERY_INTERRUPTS +# define HAL_QUERY_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + asm volatile ("move.w %%sr,%0\n" : "=d" (_old_) : ); \ + CYG_MACRO_END +#endif + +// ---------------------------------------------------------------------------- +// DSR's should always run on the interrupt stack if available. +// Even if no interrupt stack is in use we still want to go +// via call_pending_DSRs() so that it can manipulate the IPL +// level. +externC void hal_interrupt_stack_call_pending_DSRs(void); +# define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() hal_interrupt_stack_call_pending_DSRs() + +// ---------------------------------------------------------------------------- +// HAL_DELAY_US(). This implementation should work fine on all M68K +// processors. The variant/processor/platform HAL may already have +// supplied an implementation if for some reason this version is +// inappropriate. +// +// Lower-level HALs should define a count _HAL_M68K_DELAY_US_LOOPS_, +// and optionally _HAL_M68K_DELAY_US_LOOPS_UNCACHED_. These give the +// number of iterations needed for a single microsecond delay. In +// theory it can be worked out from the cpu and board specs, but in +// practice it is easier to do a bit of experimenting and fine-tune +// the numbers. Good initial values are 20 and 1 respectively. Note +// that the symbols need not be compile-time constants if e.g. the +// processor frequency may change at run-time for power management, +// but it is assumed that the values will not change as a side +// effect of interrupts or anything like that. +// +// An inline assembler version is used for two reasons. First it +// prevents the compiler from optimizing the code. Second it avoids +// problems when different versions of the compiler generate slightly +// better or worse code. +#ifndef HAL_DELAY_US +# ifndef _HAL_M68K_DELAY_US_LOOPS_ +# error Variant, processor or platform HAL should supply loop count parameters +# else +# ifdef _HAL_M68K_DELAY_US_LOOPS_UNCACHED_ +// A cache-aware version of the macro +# include <cyg/hal/hal_cache.h> +# define HAL_DELAY_US(_delay_) \ + CYG_MACRO_START \ + int _icache_enabled_; \ + int _loops_; \ + HAL_ICACHE_IS_ENABLED(_icache_enabled_); \ + _loops_ = (_icache_enabled_) ? _HAL_M68K_DELAY_US_LOOPS_ : \ + _HAL_M68K_DELAY_US_LOOPS_UNCACHED_; \ + asm volatile ( "move.l %0, %%d0\n" \ + "1:\n" \ + "subq.l #1, %%d0\n" \ + "beq 3f\n" \ + "move.l %1, %%d1\n" \ + "2:\n" \ + "subq.l #1,%%d1\n" \ + "bne 2b\n" \ + "bra 1b\n" \ + "3:\n" \ + : \ + : "d" ((_delay_) + 1), "d" ((_loops_)) \ + : "cc", "d0", "d1"); \ + CYG_MACRO_END +# else +# define HAL_DELAY_US(_delay_) \ + CYG_MACRO_START \ + int _loops_ = _HAL_M68K_DELAY_US_LOOPS_; \ + asm volatile ( "move.l %0, %%d0\n" \ + "1:\n" \ + "subq.l #1, %%d0\n" \ + "beq 3f\n" \ + "move.l %1, %%d1\n" \ + "2:\n" \ + "subq.l #1,%%d1\n" \ + "bne 2b\n" \ + "bra 1b\n" \ + "3:\n" \ + : \ + : "d" ((_delay_) + 1), "d" ((_loops_)) \ + : "cc", "d0", "d1"); \ + CYG_MACRO_END +# endif +# endif +#endif + +// ---------------------------------------------------------------------------- +// Reset support. This is done by disabling all interrupts and indirecting +// through the exception vector. Where possible variant or processor HALs +// should instead activate an on-chip reset controller. + +#ifndef HAL_PLATFORM_RESET +# define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + asm volatile ("move.w #0x2700,%%sr\n" \ + "move.l %0,%%a0\n" \ + "move.l 0(%%a0),%%a7\n" \ + "move.l 4(%%a0),%%a1\n" \ + "jmp (%%a1)\n" \ + : : "a" (hal_m68k_vsr_table) : "a0", "a1", "memory"); \ + CYG_MACRO_END +#endif +#ifndef HAL_PLATFORM_RESET_ENTRY +# define HAL_PLATFORM_RESET_ENTRY (*(cyg_uint32*)0x04) +#endif + +// ---------------------------------------------------------------------------- +// Functions/symbols exported to the variant and platform HAL's +externC void hal_m68k_exception_reset(void); +externC void hal_m68k_rte(void); +externC void hal_m68k_exception_vsr(void); +externC void hal_m68k_interrupt_vsr(void); + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_HAL_INTR_H diff --git a/ecos/packages/hal/m68k/arch/current/include/hal_io.h b/ecos/packages/hal/m68k/arch/current/include/hal_io.h new file mode 100644 index 0000000..3f44db8 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/include/hal_io.h @@ -0,0 +1,156 @@ +#ifndef CYGONCE_HAL_HAL_IO_H +#define CYGONCE_HAL_HAL_IO_H + +//============================================================================= +// +// hal_io.h +// +// HAL device IO register support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +//####DESCRIPTIONEND#### +//============================================================================= + +#if !defined(__ASSEMBLER__) && !defined(__LDI__) +#include <cyg/infra/cyg_type.h> +#endif +#include <cyg/hal/var_io.h> + +#if !defined(__ASSEMBLER__) && !defined(__LDI__) +//----------------------------------------------------------------------------- +// IO Register address. +// This type is for recording the address of an IO register. +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; + +//----------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + +#define HAL_READ_UINT8( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_BYTE *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + + +//----------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + +#define HAL_READ_UINT16( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_WORD16 *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_WORD32 *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + +#endif + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_HAL_IO_H +// End of hal_io.h diff --git a/ecos/packages/hal/m68k/arch/current/src/hal_arch.S b/ecos/packages/hal/m68k/arch/current/src/hal_arch.S new file mode 100644 index 0000000..6578b12 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/src/hal_arch.S @@ -0,0 +1,763 @@ +// #======================================================================== +// # +// # hal_arch.S +// # +// # M68K support for contexts, exceptions and interrupts +// # +// #======================================================================== +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================ +//###DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//###DESCRIPTIONEND#### +//======================================================================== + + .file "hal_arch.S" + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k.h> +#ifdef CYGPKG_KERNEL + // For instrumentation options +# include <pkgconf/kernel.h> +#endif +#include <cyg/hal/arch.inc> + +// ---------------------------------------------------------------------------- +// The system startup and/or interrupt stack, unless the platform HAL +// provides its own. +// +// The default behaviour is a separate interrupt stack via common HAL +// configuration options, with the interrupt stack reused as the +// startup stack. If the use of an interrupt stack is disabled then +// a separate startup stack is needed. Either the startup stack, the +// interrupt stack, or both can be provided by the platform HAL, for +// example to place the stack in an area of memory that is not otherwise +// readily usable. + +#if defined(_HAL_M68K_INSTANTIATE_STARTUP_STACK_) || defined(_HAL_M68K_INSTANTIATE_INTERRUPT_STACK_) + .section .bss + .balign 4 +# ifdef _HAL_M68K_INSTANTIATE_STARTUP_STACK_ + .global _hal_m68k_startup_stack_base_ +_hal_m68k_startup_stack_base_: +# endif +# ifdef _HAL_M68K_INSTANTIATE_INTERRUPT_STACK_ + .global _hal_m68k_interrupt_stack_base_ +_hal_m68k_interrupt_stack_base_: +# endif +# ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + .byte 0 + .endr + .balign 4 +# else + .rept CYGNUM_HAL_M68K_STARTUP_STACK_SIZE + .byte 0 + .endr + .balign 4 +# endif +# ifdef _HAL_M68K_INSTANTIATE_STARTUP_STACK_ + .global _hal_m68k_startup_stack_ +_hal_m68k_startup_stack_: +# endif +# ifdef _HAL_M68K_INSTANTIATE_INTERRUPT_STACK_ + .global _hal_m68k_interrupt_stack_ +_hal_m68k_interrupt_stack_: +# endif + +#endif + +// ---------------------------------------------------------------------------- +// M68K calling conventions. +// +// The stack pointer always points at the first word of the stack that +// is currently in use. Pushing additional data requires a predecrement. +// +// Frame pointers are not required but the compiler usually defaults to +// using them, to make debugging easier. This assembler code typically +// does not use a frame pointer. +// +// All arguments are pushed onto the stack, never in registers. D0 is +// used for return values. +// +// According to CALL_USED_REGISTERS in gcc/config/m68k/m68k.h, +// d0/d1/a0/a1/fp0/fp1 are caller-save, i.e. must be saved in an interrupt +// handler but can be ignored in a function called from C. The fp status +// registers are also caller-save. +// +// d2-d7/a2-a6/fp2-fp7 are callee-save registers, i.e. must be saved by +// a C function. fpsr is not callee-save, a C function can perform floating +// point operations and hence clobber the status. Similarly fpiar is not +// callee-save. fpcr is +// +// Floating point support is only available on some variants. There can also +// be other hardware units such as multiply-accumulators which may have state +// that should be saved. + +// ---------------------------------------------------------------------------- +// Context switch support. +// +// The context consists of generic integer registers, possibly floating +// point registers, possibly another hardware unit, and space for pc/sr +// at the end in a variant-specific format. + + .equ hal_context_integer_offset, 0 + .equ hal_context_integer_d0_offset, 0 + .equ hal_context_integer_d2_offset, (2 * 4) + .equ hal_context_integer_a0_offset, (8 * 4) + .equ hal_context_integer_a2_offset, ((8+2) * 4) + .equ hal_context_integer_size, (15 * 4) + + .equ hal_context_fpu_offset, (hal_context_integer_offset + hal_context_integer_size) +#ifdef CYGIMP_HAL_M68K_FPU_SAVE + .equ hal_context_fpu_fpsr_offset, (hal_context_fpu_offset + 0) + .equ hal_context_fpu_fpiar_offset, (hal_context_fpu_offset + 4) + .equ hal_context_fpu_fp0_offset, (hal_context_fpu_offset + 8) + .equ hal_context_fpu_fp2_offset, (hal_context_fpu_fp0_offset + (2 * 12)) + .equ hal_context_fpu_size, ((2 * 4) + (8 * 12)) +#else + .equ hal_context_fpu_size, 0 +#endif + + .equ hal_context_other_offset, (hal_context_fpu_offset + hal_context_fpu_size) +#ifdef HAL_CONTEXT_OTHER_SIZE + .equ hal_context_other_size, HAL_CONTEXT_OTHER_SIZE +#else + .equ hal_context_other_size, 0 +#endif + + .equ hal_context_pcsr_offset, (hal_context_other_offset + hal_context_other_size) +#ifdef HAL_CONTEXT_PCSR_SIZE + .equ hal_context_pcsr_size, HAL_CONTEXT_PCSR_SIZE +#else + .equ hal_context_pcsr_size, 8 +#endif + .equ hal_context_size, (hal_context_pcsr_offset + hal_context_pcsr_size) + +// The offset to be used when switching to a new thread. For some variants +// this is 0 because the rte instruction will pop the entire pcsr part of +// the structure. For other variants some additional data may have to be popped. +#ifdef HAL_CONTEXT_PCSR_RTE_ADJUST + .equ hal_context_rte_adjust, (hal_context_pcsr_offset + HAL_CONTEXT_PCSR_RTE_ADJUST) +#else + .equ hal_context_rte_adjust, hal_context_pcsr_offset +#endif + + +// Definitions for saving/restoring FPU context, if the FPU is part of the +// saved context. It can be assumed that %sp points at the thread context. +// FIXME: this code should probably use fsave/frestore to ensure that +// floating point operations have completed. +#ifdef CYGIMP_HAL_M68K_FPU_SAVE + + .macro hal_context_fpu_save_caller areg=%sp + fmove.l %fpsr, hal_context_fpu_fpsr_offset(\areg) + fmove.l %fpiar, hal_context_fpu_fpiar_offset(\areg) + fmovem.x %fp0-%fp1, hal_context_fpu_fp0_offset(\areg) + .endm + + .macro hal_context_fpu_load_caller areg=%sp + fmove.l hal_context_fpu_fpsr_offset(\areg), %fpisr + fmove.l hal_context_fpu_fpiar_offset(\areg), %fpiar + fmovem.x hal_context_fpu_fp0_offset(\areg),%fp0-%fp1 + .endm + + .macro hal_context_fpu_save_callee areg=%sp + fmovem.x %fp2-%fp7, hal_context_fpu_fp2_offset(\areg) + .endm + + .macro hal_context_fpu_load_callee areg=%sp + fmovem.x hal_context_fpu_fp2_offset(\areg), %fp2-%fp7 + .endm + + .macro hal_context_fpu_save_all areg=%sp + fmove.l %fpsr, hal_context_fpu_fpsr_offset(\areg) + fmove.l %fpiar, hal_context_fpu_fpiar_offset(\areg) + fmovem.x %fp0-%fp7, hal_context_fpu_fp0_offset(\areg) + .endm + + .macro hal_context_fpu_load_all areg=%sp + fmove.l hal_context_fpu_fpsr_offset(\areg), %fpsr + fmove.l hal_context_fpu_fpiar_offset(\areg), %fpiar + fmovem.x hal_context_fpu_fp0_offset(\areg), %fp0-%fp7 + .endm +#else + .macro hal_context_fpu_save_caller areg=%sp + .endm + .macro hal_context_fpu_load_caller areg=%sp + .endm + .macro hal_context_fpu_save_callee areg=%sp + .endm + .macro hal_context_fpu_load_callee areg=%sp + .endm + .macro hal_context_fpu_save_all areg=%sp + .endm + .macro hal_context_fpu_load_all areg=%sp + .endm +#endif + +// No-op defaults for saving/restoring the OTHER context. If there is in fact +// something to be done then the variant HAL should have defined +// HAL_CONTEXT_OTHER_SIZE +#ifndef HAL_CONTEXT_OTHER_SIZE + .macro hal_context_other_save_caller areg=%sp + .endm + .macro hal_context_other_load_caller areg=%sp + .endm + .macro hal_context_other_save_callee areg=%sp + .endm + .macro hal_context_other_load_callee areg=%sp + .endm + .macro hal_context_other_save_all areg=%sp + .endm + .macro hal_context_other_load_all areg=%sp + .endm +#endif + +// ---------------------------------------------------------------------------- +// LOAD_CONTEXT is called to start a new thread, usually only during system +// startup. +// +// void hal_thread_load_context(void* sp) + + FUNC_START(hal_thread_load_context) + move.l 4(%sp),%sp + hal_context_other_load_all + hal_context_fpu_load_all + movem.l hal_context_integer_offset(%sp),%d0-%d7/%a0-%a6 + add.l #hal_context_rte_adjust, %sp + rte + +// ---------------------------------------------------------------------------- +// void hal_thread_switch_context(void** from, void* to) + + FUNC_START(hal_thread_switch_context) + + // Space for the saved thread context. The PC is already on the + // stack. "from" is on the stack immediately after the context, + // then "to". + mov.l 4(%sp),%a0 + sub.l # (hal_context_size - 4), %sp + mov.l %sp, 0(%a0) + +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + // Save all the callee-save integer registers, so that they become + // available to the other macros. + movem.l %d2-%d7, hal_context_integer_d2_offset(%sp) + movem.l %a2-%a6, hal_context_integer_a2_offset(%sp) + + // The status register must be saved here, since loading a thread + // context always involves an rte instruction. The details are + // variant-specific. + hal_context_pcsr_save_sr %sp,0,%d0 + + // Now the fpu and other contexts can be saved. All registers + // are available. + hal_context_fpu_save_callee + hal_context_other_save_callee +#else + movem.l %d0-%d7/%a0-%a6, hal_context_integer_offset(%sp) + hal_context_pcsr_save_sr %sp,0,%d0 + hal_context_fpu_save_all + hal_context_other_save_all +#endif + + // All thread state has now been saved, so switch to the new one. + mov.l (hal_context_size+4)(%sp),%sp + +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + hal_context_other_load_callee + hal_context_fpu_load_callee + movem.l hal_context_integer_d2_offset(%sp),%d2-%d7 + movem.l hal_context_integer_a2_offset(%sp),%a2-%a6 +#else + hal_context_other_load_all + hal_context_fpu_load_all + movem.l hal_context_integer_offset(%sp),%d0-%d7/%a0-%a6 +#endif + + add.l #hal_context_rte_adjust, %sp + rte + +// ---------------------------------------------------------------------------- +// setjmp()/longjmp(). See hal_arch.h for details. +// +// int hal_m68k_setjmp(hal_jmp_buf); +// void hal_m68k_longjmp(hal_jmp_buf, val) + + FUNC_START_WEAK(hal_m68k_setjmp) + lea.l 4(%sp),%a1 // return stack pointer. longjmp() does an indirect jmp, not an rts + move.l 0(%a1),%a0 // the jmp_buf structure + move.l 0(%sp),0(%a0) // return pc + move.l %a1,4(%a0) + movem.l %d2-%d7/%a2-%a6,8(%a0) // 11 longs, occupying offsets 8 to 51 +#ifdef CYGINT_HAL_M68K_VARIANT_FPU + fmovem.x %fp2-%fp7,52(%a0) +#endif + clr.l %d0 // setjmp() always returns 0 + rts + + FUNC_START_WEAK(hal_m68k_longjmp) + move.l 8(%sp),%d0 // val argument, and hence return value + move.l 4(%sp),%a0 // The jmp_buf structure + movem.l 8(%a0),%d2-%d7/%a2-%a6 +#ifdef CYGINT_HAL_M68K_VARIANT_FPU + fmovem.x 52(%a0),%fp2-%fp7 +#endif + move.l 0(%a0),%a1 // The return pc + move.l 4(%a0),%sp + jmp (%a1) + +// ---------------------------------------------------------------------------- +// Synchronous exceptions. Interrupts are disabled because that could confuse +// some code like gdb stubs (breakpoints also involve synchronous exceptions). +// Full state is saved on the current stack, then usually we switch to the +// interrupt stack and handle the rest of the exception there. That avoids +// having to worry about gdb stubs stack requirements in every thread context. +// +// It is assumed that on entry there is pc/sr context information already +// on the stack. Some or all of this will have been provided by the hardware. +// Other bits, e.g. the specific exception number, may have been pushed by +// software that then jumped here. The hardware may also have pushed some +// additional state which has already been removed or stashes elsewhere, +// to keep things simple. + + .extern hal_m68k_exception_handler + + FUNC_START(hal_m68k_exception_vsr) + mov.w #0x2700, %sr + sub.l #hal_context_pcsr_offset, %sp + + // If CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT is enabled + // then only caller-save registers need to be saved here, but + // exceptions should be rare and the additional info may prove + // useful to higher-level code. + movem.l %d0-%d7/%a0-%a6, hal_context_integer_offset(%sp) + hal_context_fpu_save_all + hal_context_other_save_all + + // Remember the current stack pointer in a callee-save register, + // which have all been saved anyway. That makes it easier to restore + // the stack later. + move.l %sp,%a2 + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + // Do we need to switch to the interrupt stack? + cmpa.l _HAL_M68K_INTERRUPT_STACK_, %sp + jbgt 1f + cmpa.l _HAL_M68K_INTERRUPT_STACK_BASE_, %sp + jbge 2f +1: + mova.l _HAL_M68K_INTERRUPT_STACK_, %sp +2: +#endif + // Zero out the frame pointer to encourage GDB to backtrace correctly + suba.l %a6, %a6 + + // Now call into C with a single argument, the HAL_SavedRegisters + mov.l %a2,-(%sp) + jbsr hal_m68k_exception_handler + + // We can switch back to the right stack by re-using a2, irrespective + // of whether or not we switched to the interrupt stack. + move.l %a2,%sp + + // Restore the entire state. In theory only the callee-save registers + // should have changed, but some others may have been manipulated by + // gdb. + hal_context_other_load_all + hal_context_fpu_load_all + movem.l hal_context_integer_offset(%sp), %d0-%d7/%a0-%a6 + add.l #hal_context_rte_adjust, %sp + rte + +// ---------------------------------------------------------------------------- +// Interrupt handling. +// +// The current stack may be a thread stack or the interrupt stack. +// On some variants this code will be called directly by the hardware. +// On others there will have been a trampoline doing some stack +// manipulation and then jumping here. We assume that the stack is +// properly aligned and that the pc/sr part has been correctly saved. + + FUNC_START(hal_m68k_interrupt_vsr) + +#ifndef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING + // If nesting is not of interest then just disable all interrupts. + // Otherwise interrupt nesting is controlled via the M68K IPL + move.w #0x2700, %sr +#endif + + sub.l # hal_context_pcsr_offset, %sp +#ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + // Even for a minimum context the callee-save a2 register + // is saved. This makes it easier to restore the stack + // to the right place after the ISR call, allowing for + // the optional interrupt stack. + movem.l %d0-%d1,hal_context_integer_d0_offset(%sp) + movem.l %a0-%a2,hal_context_integer_a0_offset(%sp) + hal_context_fpu_save_caller %sp + hal_context_other_save_caller %sp +#else + movem.l %d0-%d7/%a0-%a6, hal_context_integer_d0_offset(%sp) + hal_context_fpu_save_all %sp + hal_context_other_save_all %sp +#endif + +#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) + // Let gdb stubs know which thread was interrupted, in case this + // interrupt was a ctrl-C. + .extern hal_saved_interrupt_state + move.l %sp, hal_saved_interrupt_state +#endif + + // d0/d1/a0/a1/a2 are now available. + // We want to extract the ISR vector while it is readily accessible. + // The details depend the particular M68K variant. The result should + // be the vector << 2 to facilitate indexing. On some processors that + // actually requires less code than getting the vector itself. + hal_context_extract_isr_vector_shl2 %sp,0,%d0 + +#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) + // We need to call cyg_instrument(INTR.RAISE, vector, intr_number) + // The actual interrupt number is not readily available, it depends + // on the variant and possibly the platform, so just instrument 0 + // instead. The vector is preserved in callee-save a2 since it may + // take several instructions to refetch it. + movea.l %d0, %a2 + lsr.l #2, %d0 + move.l #0, -(%sp) + move.l %d0, -(%sp) + move.l #0x0301, -(%sp) + jbsr cyg_instrument + add.l #12, %sp + move.l %a2, %d0 +#endif + + // %d0 holds the ISR vector << 2. d1/a0/a1/a2 are available. + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + // Increment the scheduler lock. In theory the ISR should not look + // at this so it could be deferred till just before the interrupt_end() + // call, but this provides protection against badly written ISR's. + // + // This is not sufficient on SMP systems. The test of the scheduler lock + // below also needs attention. + .extern cyg_scheduler_sched_lock + addq.l #1, cyg_scheduler_sched_lock +#endif + + // At the end of the VSR we need to call interrupt_end(). + // The last two arguments are cyg_hal_interrupt_objects[vec] + // and the saved registers. These are pushed now, while + // vec is readily available, at the cost of a slight increase + // in interrupt latency but saving some instructions later. + move.l %sp,-(%sp) + lea cyg_hal_interrupt_objects,%a0 + move.l 0(%a0,%d0), -(%sp) + + // We want to be able to restore the stack pointer to this location, + // irrespective of whether or not an interrupt stack is being used. + // Store it in a callee-save register. + movea.l %sp, %a2 + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + // Switch to the interrupt stack if we are not already running there. + cmpa.l _HAL_M68K_INTERRUPT_STACK_, %sp + jbgt 1f + cmpa.l _HAL_M68K_INTERRUPT_STACK_BASE_, %sp + jbge 2f +1: + movea.l _HAL_M68K_INTERRUPT_STACK_, %sp +2: +#endif + // FIXME: Some variation of the following should be considered to ensure that + // GDB can't get permanently lost when doing a backtrace from within an ISR. +#if 0 && defined(CYGPKG_INFRA_DEBUG) && !defined(CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT) + // Zero out the frame pointer to encourage GDB to backtrace correctly + // But only if explicitly debugging so that we don't adversely affect + // critical ISR latency + move.w #0,%a6 +#endif + + // d0 is the isr vector << 2. a2 holds a saved stack pointer. d1/a0/a1 are available. + // We need to call (*cyg_hal_interrupt_handlers[vec])(vec, cyg_hal_interrupt_data[vec]) + lea cyg_hal_interrupt_data,%a0 + move.l 0(%a0,%d0),-(%sp) + lea cyg_hal_interrupt_handlers,%a0 + move.l 0(%a0,%d0),%a1 + lsr.l #2,%d0 + move.l %d0,-(%sp) + jbsr (%a1) + + // We now want to return to the right position on the current + // stack, or to the thread stack if we switched to the interrupt + // stack. + movea.l %a2, %sp + + // Next we need to call interrupt_end(). If the scheduler was unlocked + // at the time of the interrupt then that will run the DSRs, possibly + // cause a context switch, and eventually return to this VSR. If the + // scheduler was already locked then interrupt_end() will return to + // the VSR almost immediately. The IPL level will be restored when + // the VSR executes the final rte. + // + // DSRs should run with interrupts re-enabled. Ideally we want to + // run them with the IPL level of the interrupted thread, and at + // the end reset the IPL level to what it is now. That way this + // VSR gets to return, without risk of unconstrained stack usage. + // However this is very hard: currently the desired IPL levels + // cannot be passed on the stack; they cannot be passed via globals + // either because of the possibility of a context switch. + // + // Instead there is a defined IPL level for running all DSRs. + // HAL_INTERRUPT_STACK_CALL_PENDING_DSRs() sets the IPL level to + // that value, and restores the IPL level when done. For most + // applications that will be fine, but it does make it more + // difficult to manipulate IPL levels on a per-thread level + // or anything similarly fancy. + + // We need to call interrupt_end(isr_return, cyg_hal_interrupt_objects[vec], saved_state_pointer) + // The last two have already been pushed onto the stack. d0 holds the return value. + move.l %d0,-(%sp) + jbsr interrupt_end + add.l #12,%sp + +#ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + hal_context_other_load_caller %sp + hal_context_fpu_load_caller %sp + movem.l hal_context_integer_a0_offset(%sp),%a0-%a2 + movem.l hal_context_integer_d0_offset(%sp),%d0-%d1 +#else + hal_context_other_load_all %sp + hal_context_fpu_load_all %sp + movem.l hal_context_integer_d0_offset(%sp),%d0-%d7/%a0-%a6 +#endif + add.l #hal_context_rte_adjust,%sp + rte + +// ---------------------------------------------------------------------------- +// On configurations with an interrupt stack HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() +// is used to run the DSRs on the interrupt stack rather than the thread stack, +// reducing stack size requirements for the latter. It is called only on a thread +// stack. In addition to the stack switch the IPL level is manipulated here, +// ensuring that DSRs run with interrupts enabled. +// +// On other architectures HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() is only called +// when a separate interrupt stack is used. If the interrupt stack is disabled +// then DSRs run with interrupts disabled, which is a bad idea. On the M68K +// HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() is always defined, thus sorting out +// the interrupt level, but only does the stack switch if an interrupt stack +// is actually being used. + + .extern hal_m68k_dsr_ipl_level + .extern cyg_interrupt_call_pending_DSRs + + FUNC_START(hal_interrupt_stack_call_pending_DSRs) +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + // Use callee-save registers to store the current stack and status register + // Also store the frame pointer so we can zero it to improve GDB debugging backtraces + move.l %a2,-(%sp) + move.l %d2,-(%sp) + move.l %a6,-(%sp) + movea.l %sp,%a2 + move.w %sr,%d2 + suba.l %a6,%a6 + + // There is a problem if the configuration contains the kernel but interrupts + // are enabled while still running the startup code. The kernel's interrupt_end() + // rather than the driver API's will be used, so this code gets to run. We now + // get to switch to the interrupt stack while still on the startup stack, which + // is a shame since the two are the same. This could be easily fixed by checking + // the current stack as happens in the interrupt_vsr, but at the cost of an + // extra four instructions in the DSR path. The scenario should probably not + // arise so those four instructions are left out for now. + movea.l _HAL_M68K_INTERRUPT_STACK_, %sp + move.l hal_m68k_dsr_ipl_level, %d0 + move.w %d0, %sr + + jbsr cyg_interrupt_call_pending_DSRs + + move.w %d2, %sr + movea.l %a2, %sp + movea.l (%sp)+,%a6 + move.l (%sp)+,%d2 + movea.l (%sp)+,%a2 + rts +#else + move.l %d2, -(%sp) + move.w %sr, %d2 + move.l hal_m68k_dsr_ipl_level, %d0 + move.w %d0, %sr + jbsr cyg_interrupt_call_pending_DSRs + move.w %d2, %sr + move.l (%sp)+, %d2 + rts +#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + + +// ---------------------------------------------------------------------------- +// A dummy entry point for unused entries in the system exception vector. + + FUNC_START(hal_m68k_rte) + rte + +// ---------------------------------------------------------------------------- +// Fast implementations of lsbit_index() and msbit_index() + + FUNC_START(hal_lsbit_index) + clr.l %d0 // result + mov.l 4(%sp),%d1 // mask + bne 1f // special case for 0 + subq.l #1,%d0 // lsbit_index(0) -> -1 + rts +1: + tst.w %d1 // anything set in the bottom 16 bits? + bne 2f + swap %d1 // the top 16 bits only are of interest + moveq.l #16, %d0 +2: + tst.b %d1 // anything set in the bottom 8 bits? + bne 3f + addq.l #8, %d0 // bottom byte is 0, switch to next byte + lsr.l #8, %d1 +3: + move.l %d1, %a0 // backup current data, so that we can manipulate it + and.l #0x0F, %d1 // anything in the bottom nibble? + bne 4f + move.l %a0, %d1 // nope, restore and use the next nibble + lsr.l #4, %d1 + and.l #0x0F, %d1 + addq.l #4, %d0 +4: + // The bottom nibble contains a number between 1 and 15 + // (not 0, that would have been caught by the test at the top). + lea 5f, %a0 + mov.b 0(%a0,%d1),%d1 // only zap bottom byte, the other bytes are already 0 + add.l %d1,%d0 + rts +5: + // Every odd number has an index of 0. The first entry is irrelevent. + .byte 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 + + FUNC_START(hal_msbit_index) + clr.l %d0 // result + mov.l 4(%sp), %d1 // mask + bne 1f // special case for 0 + subq.l #1, %d0 // msbit_index(0) -> -1 + rts +1: + cmpi.l #0x0000FFFF,%d1 + bls 2f + moveq.l #16,%d0 + clr.w %d1 + swap %d1 +2: + cmpi.l #0x00FF, %d1 + bls 3f + addq.l #8, %d0 + lsr.l #8, %d1 +3: + cmpi.l #0x000F, %d1 + bls 4f + addq.l #4, %d0 + lsr.l #4, %d1 + +4: + lea 5f, %a0 + mov.b 0(%a0,%d1), %d1 + add.l %d1,%d0 + rts + +5: + .byte 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 + +// ---------------------------------------------------------------------------- +// Profiling support. When code is compiled with -pg the compiler inserts +// calls to mcount() at the start of each function. This can be used to +// build a callgraph of the application. mcount() is tied to the compiler +// internals and does not always use standard calling conventions. +// +// mcount() should call __profile_mcount() with two arguments, caller_pc +// and callee_pc, where callee_pc refers to the function that calls +// mcount() and caller_pc refers to the place where that function is +// called from. callee_pc is readily accessed relative to sp, caller_pc +// can be accessed using the frame pointer. This assumes the code has +// not been built with -fomit-frame-pointer, a safe assumption since +// the compiler disallows combining -pg and -fomit-frame-pointer. +// +// The m68k compiler appears to implement mcount() a bit differently +// from other targets. It reserves a word for every function entry +// point which presumably is intended to act as the start of a linked +// list chain. On other targets the PC is used to index a hash table +// which contains the start of that linked list. That extra word is +// not used for eCos profiling since it would require customizing the +// profiling package on a per-target basis, so unfortunately the +// memory is wasted. +// +// It is assumed that d0/d1/a0/a1 (the callee-save registers) are +// available. a0 is certainly available because that is used to hold +// the above per-function word. If the assumption is false then this +// would have to save d0/d1/a1 because the C __profile_mcount() could +// zap them. +// +// This code is conditional on CYGPKG_PROFILE_GPROF since that provides +// the implementation of __profile_mcount. +#ifdef CYGPKG_PROFILE_GPROF + FUNC_START(mcount) + // __profile_mcount() should be called with interrupts disabled. + move.w %sr,%d0 + move.l %d0,-(%sp) + // The callee-pc corresponds to the return address on the stack + move.l 4(%sp),%a0 + move.l %a0,-(%sp) + // The caller-pc is accessible relative to the frame pointer a6 + move.l 4(%a6),%a0 + move.l %a0,-(%sp) + + move.w #0x2700, %sr + jbsr __profile_mcount + + move.l 8(%sp),%d0 + add.l #12, %sp + move.w %d0,%sr + + rts +#endif + + .end diff --git a/ecos/packages/hal/m68k/arch/current/src/hal_m68k.c b/ecos/packages/hal/m68k/arch/current/src/hal_m68k.c new file mode 100644 index 0000000..f88bab2 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/src/hal_m68k.c @@ -0,0 +1,227 @@ +//========================================================================== +// +// hal_m68k.c +// +// M68K HAL miscellaneous C functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//###DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//###DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_stub.h> + +// ---------------------------------------------------------------------------- +// Interrupt support. +// +// Space for the interrupt data. These are updated by macros in hal_intr.h +volatile CYG_ADDRESS cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +volatile CYG_ADDRESS cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +// A status register value that should be used while running DSRs. +cyg_uint32 hal_m68k_dsr_ipl_level = 0x2000 | (CYGNUM_HAL_INTERRUPT_DEFAULT_IPL_LEVEL << 8); + +// In virtual vector configurations we can get apparently spurious +// interrupts in application space when the interrupt will be serviced +// by RedBoot instead. Hence the virtual vector code in the common HAL +// provides hal_default_isr() which gets installed as the default +// handler for all interrupts. If it turns out that RedBoot does not +// recognize the interrupt either, i.e. it really is spurious, then +// the virtual vector code will call hal_arch_default_isr(). +// +// In non-virtual vector configurations hal_default_isr() needs to +// be provided by the architecture/variant/processor/platform HAL +// on the off-chance that the interrupt is not entirely spurious +// and some useful processing can take place. + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT +# ifndef _HAL_M68K_HAL_ARCH_DEFAULT_ISR_DEFINED_ +cyg_uint32 +hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + CYG_FAIL("Spurious interrupt!"); + return 0; +} +# endif +#else +# ifndef _HAL_M68K_HAL_DEFAULT_ISR_DEFINED_ +cyg_uint32 +hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + CYG_FAIL("Spurious interrupt!"); + return 0; +} +# endif +#endif + +// ---------------------------------------------------------------------------- +// Exception handling. The assembler routine calls this C function as +// soon as possible. Usually exceptions are passed to gdb stubs - if +// this application does not have gdb stubs included then the relevant +// entries in the exception vector table will still belong to the stubs. + + +void +hal_m68k_exception_handler(HAL_SavedRegisters* regs) +{ +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + + // If we caught an exception inside the stubs, see if we were expecting it + // and if so jump to the saved address + extern void* volatile __mem_fault_handler; + if (__mem_fault_handler) { + regs->pc = (CYG_ADDRWORD)__mem_fault_handler; + return; // Caught an exception inside stubs + } + + _hal_registers = regs; + __handle_exception(); + +#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && defined(CYGPKG_HAL_EXCEPTIONS) + + CYG_WORD code; + HAL_CONTEXT_PCSR_GET_EXCEPTION(regs, code); + cyg_hal_deliver_exception(code, (CYG_ADDRWORD) regs); + +#else + + CYG_FAIL("Exception!!!"); + +#endif +} + +// ---------------------------------------------------------------------------- +// C++ constructor support. The constructors are run in a separate function +// so that a breakpoint can be set, at the cost of a couple of extra bytes +// of code. +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG +cyg_bool cyg_hal_stop_constructors = 0; +#endif + +typedef void (*pfunc)(void); +extern pfunc __CTOR_LIST__[]; +extern pfunc __CTOR_END__[]; + +void +cyg_hal_invoke_constructors(void) +{ +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + static pfunc* p = &__CTOR_END__[-1]; + cyg_hal_stop_constructors = 0; + for ( ; p >= __CTOR_LIST__; p--) { + (*p)(); + if (cyg_hal_stop_constructors) { + p--; + break; + } + } +#else + pfunc* p; + for ( p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) { + (*p)(); + } +#endif +} + +// ---------------------------------------------------------------------------- +// This entry point is called from vectors.S as soon as the C environment +// has been set up. We are running on the startup stack, interrupts are +// disabled, and the hardware is only minimally initialized. Most of +// the initialization will usually be done by the platform HAL. + +externC void cyg_start(void); + +void +hal_m68k_c_startup(void) +{ + int i; + + for (i = 0; i < CYGNUM_HAL_ISR_COUNT; i++) { + cyg_hal_interrupt_handlers[i] = (CYG_ADDRESS) &hal_default_isr; + } + +#ifdef HAL_M68K_VAR_INIT + HAL_M68K_VAR_INIT(); +#endif +#ifdef HAL_M68K_PROC_INIT + HAL_M68K_PROC_INIT(); +#endif +#ifdef HAL_M68K_PLATFORM_INIT + HAL_M68K_PLATFORM_INIT(); +#endif + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_if_init(); +#endif +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + initialize_stub(); +#endif +#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) + { + extern void hal_ctrlc_isr_init(void); + hal_ctrlc_isr_init(); + } +#endif + + cyg_hal_invoke_constructors(); + +#ifdef HAL_M68K_VAR_INIT2 + HAL_M68K_VAR_INIT2(); +#endif +#ifdef HAL_M68K_PROC_INIT2 + HAL_M68K_PROC_INIT2(); +#endif +#ifdef HAL_M68K_PLATFORM_INIT2 + HAL_M68K_PLATFORM_INIT2(); +#endif + + // And call into application-level code + cyg_start(); + for ( ; ; ); +} diff --git a/ecos/packages/hal/m68k/arch/current/src/m68k.ld b/ecos/packages/hal/m68k/arch/current/src/m68k.ld new file mode 100644 index 0000000..d398513 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/src/m68k.ld @@ -0,0 +1,302 @@ +/*========================================================================== +// +// m68k.ld +// +// Linker script +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//###DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//###DESCRIPTIONEND#### +//======================================================================== +*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#define __LDI__ 1 +#include CYGHWR_MEMORY_LAYOUT_H + +STARTUP(vectors.o) +ENTRY(hal_m68k_exception_reset) +#ifdef EXTRAS +INPUT(extras.o) +#endif +GROUP(libtarget.a libgcc.a libsupc++.a) + +#define ALIGN_LMA 4 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#ifndef CYG_LABEL_DEFN +# define CYG_LABEL_DEFN(_label) _label +#endif + +// Depending on the startup type and issues such as the memory map +// before and after any remapping, _stext should usually be defined +// either at the beginning of the .m68k_startup section or at the +// beginning of the .text section. Or conceivably somewhere else, in +// which case it is up to the platform-specific linker script or +// code to define _stext. The platform HAL can specify the desired +// behaviour via the LAYOUT_H file. +#if defined(_HAL_M68K_STEXT_AT_M68K_TEXT_) +# define _HAL_M68K_STARTUP_SECTION_STEXT_ +# define _HAL_TEXT_SECTION_STEXT_ _stext = . ; +#elif defined(_HAL_M68K_STEXT_ELSEWHERE_) +# define _HAL_M68K_STARTUP_SECTION_STEXT_ +# define _HAL_TEXT_SECTION_STEXT_ +#else +# define _HAL_M68K_STARTUP_SECTION_STEXT_ _stext = . ; +# define _HAL_TEXT_SECTION_STEXT_ +#endif + +#define SECTIONS_BEGIN + +// RAM vectors, i.e. the M68K exception table, the virtual vector table, +// and possibly some data that needs to be shared between eCos and +// RedBoot. Usually this will be located at 0 but may be at another +// address via e.g. %vbr. Some platforms in some configurations may +// have an empty ram vectors section with all the work done in +// .vectors instead. The section may or may not be loadable. + +#define SECTION_ram_vectors(_region_, _vma_) \ + . = ALIGN( _vma_ , ALIGN_LMA ) ; \ + _hal_ram_vectors_section_start = . ; \ + .ram_vectors . : { KEEP (*(.ram_vectors)) } > _region_ \ + . = ALIGN(ALIGN_LMA) ; \ + _hal_ram_vectors_section_end = . ; \ + _hal_ram_vectors_section_size = _hal_ram_vectors_section_end - \ + _hal_ram_vectors_section_start ; + +// .m68k_startup usually contains only the M68K startup code. It may also +// contain the exception vectors if booting from flash and the exception +// vectors are held in flash as well. .vectors.0 is for backwards +// compatibility with older HALs. +#define SECTION_m68k_start(_region_, _vma_) \ + . = ALIGN( _vma_ , ALIGN_LMA ) ; \ + _hal_m68k_start_section_start = . ; \ + _HAL_M68K_STARTUP_SECTION_STEXT_ \ + .m68k_start . : { KEEP (*(.m68k_start)) KEEP (*(.m68k_start.*)) KEEP (*(.vectors.0)) } > _region_ \ + . = ALIGN(ALIGN_LMA) ; \ + _hal_m68k_start_section_end = . ; \ + _hal_m68k_start_section_size = _hal_m68k_start_section_end - _hal_m68k_start_section_start ; + +// Some coldfires booting from internal flash need a signature block at +// a magic location +#define SECTION_mcfxxxx_cfm_security_settings(_region_, _vma_) \ + . = ALIGN( _vma_ , ALIGN_LMA ) ; \ + _hal_mcfxxxx_cfm_security_settings_section_start = . ; \ + .mcfxxxx_cfm_security_settings . : \ + { \ + FORCE_OUTPUT; \ + KEEP (*(.mcfxxxx_cfm_security_settings)); \ + } > _region_ \ + . = ALIGN(ALIGN_LMA) ; \ + _hal_mcfxxxx_cfm_security_settings_section_end = . ; \ + _hal_mcfxxxx_cfm_security_settings_section_size = _hal_mcfxxxx_cfm_security_settings_section_end - \ + _hal_mcfxxxx_cfm_security_settings_section_start ; + +// ---------------------------------------------------------------------------- +// C++ support. It should always be possible to discard the global destructors +// since eCos applications are not expected to exit. The exception handling +// support is normally needed only if linking with libstdc++, otherwise +// there is no code in the system to use the exception frame info. +#if defined(CYGINT_HAL_LINKER_SCRIPT_KEEP_DTORS) +# define _DTORS1_ \ + __DTOR_LIST__ = ABSOLUTE(.); \ + KEEP(*(SORT(.dtors*))) \ + __DTOR_END__ = ABSOLUTE(.); \ +# define _DTORS2_ +#else +# define _DTORS1_ +# define _DTORS2_ /DISCARD/ : { *(.dtors*) } +#endif + +#if defined(CYGPKG_LIBSTDCXX) || defined(CYGINT_HAL_LINKER_SCRIPT_KEEP_EH_FRAME) +# define _EH_FRAME1_(_region_) \ + .eh_frame . : { \ + FORCE_OUTPUT; __EH_FRAME_BEGIN__ = ABSOLUTE(.); \ + KEEP(*(.eh_frame)) \ + . = ALIGN(ALIGN_LMA); \ + __FRAME_END__ = ABSOLUTE(.); \ + LONG(0) \ + LONG(0) \ + } > _region_ = 0 +# define _EH_FRAME2_ +#else +# define _EH_FRAME1_(_region_) +# define _EH_FRAME2_ /DISCARD/ : { *(.eh_frame) } +#endif + +#if defined(CYGPKG_LIBSTDCXX) || defined(CYGINT_HAL_LINKER_SCRIPT_KEEP_GCC_EXCEPT_TABLE) +# define _GCC_EXCEPT_TABLE1_(_region_) \ + .gcc_except_table . : { \ + __EXCEPT_START__ = ABSOLUTE(.); \ + KEEP(*(.gcc_except_table)) *(.gcc_except_table.*) \ + __EXCEPT_END__ = ABSOLUTE(.); \ + } > _region_ +# define _GCC_EXCEPT_TABLE2_ +#else +# define _GCC_EXCEPT_TABLE1_(_region_) +# define _GCC_EXCEPT_TABLE2_ /DISCARD/ : { *(.gcc_except_table) *(.gcc_except_table.*) } +#endif + +#define SECTION_code(_region_, _vma_) \ + . = ALIGN( _vma_ , ALIGN_LMA ) ; \ + _hal_code_section_start = . ; \ + _hal_text_section_start = . ; \ + _HAL_TEXT_SECTION_STEXT_ \ + .text . : { \ + *(.text*) *(.gnu.warning) *(.gnu.linkonce.t*) *(.init) \ + . = ALIGN (4); \ + __CTOR_LIST__ = ABSOLUTE(.); \ + KEEP(*(SORT(.ctors*))); \ + __CTOR_END__ = ABSOLUTE(.); \ + . = ALIGN (4); \ + _DTORS1_ \ + } > _region_ \ + . = ALIGN(ALIGN_LMA) ; \ + _etext = . ; PROVIDE (etext = .) ; \ + _hal_text_section_end = . ; \ + _hal_text_section_size = _hal_text_section_end - _hal_text_section_start ; \ + .rodata . : { *(.rodata1) *(.rodata*) *(.gnu.linkonce.r.*) } > _region_ \ + . = ALIGN(ALIGN_LMA) ; \ + _EH_FRAME1_(_region_) \ + . = ALIGN(ALIGN_LMA) ; \ + _GCC_EXCEPT_TABLE1_(_region_) \ + . = ALIGN(ALIGN_LMA) ; \ + .rel.text : { *(.rel.text) *(.rel.text.*) *(.rel.gnu.linkonce.t*) } > _region_ \ + .rela.text : { *(.rela.text) *(.rela.text.*) *(.rela.gnu.linkonce.t*) } > _region_ \ + .rel.data : { *(.rel.data) *(.rel.data.*) *(.rel.gnu.linkonce.d*) } > _region_ \ + .rela.data : { *(.rela.data) *(.rela.data.*) *(.rela.gnu.linkonce.d*) } > _region_ \ + .rel.rodata : { *(.rel.rodata) *(.rel.rodata.*) *(.rel.gnu.linkonce.r*) } > _region_ \ + .rela.rodata : { *(.rela.rodata) *(.rela.rodata.*) *(.rela.gnu.linkonce.r*) } > _region_ \ + .rel.got : { *(.rel.got) } > _region_ \ + .fixup . : { \ + __FIXUP_START__ = ABSOLUTE(.); \ + *(.fixup) \ + __FIXUP_END__ = ABSOLUTE(.); \ + } > _region_ \ + .got . : { \ + FORCE_OUTPUT; *(.got.plt) *(.got) \ + _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ + _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ + } > _region_ \ + . = ALIGN(ALIGN_LMA) ; \ + _hal_code_section_end = . ; \ + _hal_code_section_size = _hal_code_section_end - _hal_code_section_start ; \ + _DTORS2_ \ + _EH_FRAME2_ \ + _GCC_EXCEPT_TABLE2_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + . = ALIGN( _vma_ , ALIGN_LMA ) ; \ + _hal_data_section_start_vma = . ; \ + .data . : _lma_ { \ + *(.shdata*) *(.data*) *(.gnu.linkonce.d.*) *(.sdata) *(.gnu.linkonce.s.*) \ + . = ALIGN (4); \ + *(.2ram.*) \ + . = ALIGN (4); \ + KEEP(*( SORT (.ecos.table.*))); \ + . = ALIGN (4); \ + } > _region_ \ + . = ALIGN(ALIGN_LMA); \ + _hal_data_section_start_lma = LOADADDR(.data) ; \ + _hal_data_section_end_vma = . ; \ + _hal_data_section_size = _hal_data_section_end_vma - _hal_data_section_start_vma ; \ + _hal_data_section_end_lma = _hal_data_section_start_lma + _hal_data_section_size ; \ + _hal_bss_start = . ; \ + .sbss . : { *(.sbss) *(.gnu.linkonce.sb.*) *(.scommon) } > _region_ \ + . = ALIGN(ALIGN_LMA) ; \ + .bss . : { *(.dynbss) *(.shbss) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON) } > _region_ \ + . = ALIGN(ALIGN_LMA) ; \ + _hal_bss_end = . ; \ + _hal_bss_size = _hal_bss_end - _hal_bss_start ; + +// Some ColdFire processors have on-chip RAM. Allocate .iram_text, .iram_data +// .iram_bss in the expected fashion. +#define SECTION_iram(_region_, _vma_, _lma_) \ + . = ALIGN( _vma_ , ALIGN_LMA ) ; \ + _hal_iram_section_start_vma = . ; \ + _hal_iram_text_section_start_vma = . ; \ + .iram_text . : _lma_ { *(.iram_text) *(.iram_text.*) } > _region_ =0 \ + _hal_iram_text_section_start_lma = LOADADDR(.iram_text) ; \ + . = ALIGN(ALIGN_LMA) ; \ + _hal_iram_text_section_end_vma = . ; \ + _hal_iram_text_section_size = _hal_iram_text_section_end_vma - _hal_iram_text_section_start_vma ; \ + _hal_iram_text_section_end_lma = _hal_iram_text_section_start_lma + _hal_iram_text_section_size ; \ + _hal_iram_data_section_start_vma = . ; \ + .iram_data . : AT(_hal_iram_text_section_end_lma) { *(.iram_data) *(.iram_data.*) } > _region_ =0 \ + . = ALIGN(ALIGN_LMA) ; \ + _hal_iram_data_section_start_lma = LOADADDR(.iram_data) ; \ + _hal_iram_data_section_end_vma = . ; \ + _hal_iram_data_section_size = _hal_iram_data_section_end_vma - _hal_iram_data_section_start_vma ; \ + _hal_iram_data_section_end_lma = _hal_iram_data_section_start_lma + _hal_iram_data_section_size ; \ + _hal_iram_bss_section_start = . ; \ + _iram_bss . (NOLOAD) : { *(.iram_bss) *(.iram_bss.*) } > _region_ =0 \ + . = ALIGN(ALIGN_LMA) ; \ + _hal_iram_bss_section_end = . ; \ + _hal_iram_section_end_vma = . ; \ + _hal_iram_section_size = _hal_iram_section_end_vma - _hal_iram_section_start_vma ; \ + _hal_iram_section_start_lma = LOADADDR(.iram_text) ; \ + _hal_iram_section_end_lma = _hal_iram_section_start_lma + _hal_iram_text_section_size + \ + _hal_iram_data_section_size ; + +#define SECTIONS_END \ + .stab 0 (NOLOAD) : { *(.stab) } \ + .stabstr 0 (NOLOAD) : { *(.stabstr) } \ + .comment 0 (NOLOAD) : { *(.comment) } \ + . = ALIGN(4); _end = .; PROVIDE (end = .); + +// These macros are for backwards compatibility. Some are redundant. +#define SECTION_fixed_vectors(_region_, _vma_, _lma_) SECTION_ram_vectors(_region_, _vma_) +#define SECTION_vectors(_region_, _vma_, _lma_) SECTION_m68k_start(_region_, _vma_) +#define SECTION_text(_region_, _vma_, _lma_) SECTION_code(_region_, _vma_) +#define SECTION_rodata(_region_, _vma_, _lma_) SECTION_constants(_region_, _vma_) +#define SECTION_rodata1(_region_, _vma_, _lma_) +#define SECTION_fini(_region_, _vma_, _lma_) +#define SECTION_fixup(_region_, _vma_, _lma_) +#define SECTION_RELOCS(_region_, _vma_, _lma_) +#define SECTION_eh_frame(_region_, _vma_, _lma_) +#define SECTION_gcc_except_table(_region_, _vma_, _lma) +#define SECTION_got(_region_, _vma_, _lma_) +#define SECTION_sbss(_region_, _vma_, _lma_) +#define SECTION_bss(_region_, _vma_, _lma_) + +#include <pkgconf/system.h> +#include CYGHWR_MEMORY_LAYOUT_LDI diff --git a/ecos/packages/hal/m68k/arch/current/src/m68k_stub.c b/ecos/packages/hal/m68k/arch/current/src/m68k_stub.c new file mode 100644 index 0000000..67d0192 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/src/m68k_stub.c @@ -0,0 +1,171 @@ +//========================================================================== +// +// m68k_stub.c +// +// M68K gdb support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//###DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//###DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_if.h> +#include <cyg/hal/hal_stub.h> + +// Translate between the eCos save state and what is expected by the gdb +// stubs. d0-d7/a0-a6 are in the right place already. SR/PS and the program +// counter need to come from variant-specific macros. The stack pointer +// can be determined from the saved context. +externC void +hal_get_gdb_registers(CYG_ADDRWORD* gdb_regs, HAL_SavedRegisters* ecos_regs) +{ + int sr; + int pc; + int i; + for (i = 0; i < 15; i++) { + gdb_regs[i] = ecos_regs->da[i]; + } + gdb_regs[15] = (CYG_ADDRWORD) &(ecos_regs[1]); + HAL_CONTEXT_PCSR_GET_SR(ecos_regs, sr); + HAL_CONTEXT_PCSR_GET_PC(ecos_regs, pc); + gdb_regs[16] = sr; + gdb_regs[17] = pc; +} + +externC void +hal_set_gdb_registers(HAL_SavedRegisters* ecos_regs, CYG_ADDRWORD* gdb_regs) +{ + int i; + for (i = 0; i < 15; i++) { + ecos_regs->da[i] = gdb_regs[i]; + } + if (gdb_regs[15] != (CYG_ADDRWORD) &(ecos_regs[1])) { + CYG_FAIL("gdb has requested a thread context switch - not supported,"); + } + HAL_CONTEXT_PCSR_SET_SR(ecos_regs, gdb_regs[16]); + HAL_CONTEXT_PCSR_SET_PC(ecos_regs, gdb_regs[17]); +} + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +externC int +__computeSignal(unsigned int trap_number) +{ + switch(trap_number) { + case CYGNUM_HAL_EXCEPTION_DATA_ACCESS: + return SIGBUS; + case CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS: + case CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR: + return SIGSEGV; + case CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION: + return SIGILL; + case CYGNUM_HAL_EXCEPTION_DIV_BY_ZERO: + return SIGFPE; + case CYGNUM_HAL_EXCEPTION_TRACE: + case CYGNUM_HAL_VECTOR_TRAP0 ... CYGNUM_HAL_VECTOR_TRAP15: + default: + return SIGTRAP; + } +} + +externC int +__get_trap_number(void) +{ + int result = CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR; + if ((HAL_SavedRegisters*)0 != _hal_registers) { + HAL_CONTEXT_PCSR_GET_EXCEPTION(_hal_registers, result); + } + return result; +} + +externC void +set_pc(target_register_t pc) +{ + _registers[PC] = pc; +} + +// Single-stepping just involves setting the trace bit in the status register +externC void +__single_step(void) +{ + _registers[PS] |= HAL_M68K_SR_T; +} + +externC void +__clear_single_step(void) +{ + _registers[PS] &= ~HAL_M68K_SR_T; +} + +// This breakpoint support is (probably) not needed because +// single-stepping is supported instead. +externC void +__install_breakpoints(void) +{ +} + +externC void +__clear_breakpoints(void) +{ +} + +externC int +__is_breakpoint_function(void) +{ + return _registers[PC] == (target_register_t)&_breakinst; +} + +// The 68K has variable length instructions so skipping an instruction +// is messy. However __skipinst() is only used for a breakpoint +// instruction or for a trap, and these are always 2 bytes. +externC void +__skipinst(void) +{ + _registers[PC] += 2; +} + +#endif diff --git a/ecos/packages/hal/m68k/arch/current/src/plf_stub.h b/ecos/packages/hal/m68k/arch/current/src/plf_stub.h new file mode 100644 index 0000000..a91eb15 --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/src/plf_stub.h @@ -0,0 +1,75 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Generic platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2007, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM +#include <cyg/hal/hal_arch.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS +# define HAL_STUB_PLATFORM_INIT_SERIAL() CYG_EMPTY_STATEMENT +#else +externC void cyg_hal_plf_comms_init(void); +# define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() +#endif + +# define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +# define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +# define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h diff --git a/ecos/packages/hal/m68k/arch/current/src/vectors.S b/ecos/packages/hal/m68k/arch/current/src/vectors.S new file mode 100644 index 0000000..257edca --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/src/vectors.S @@ -0,0 +1,254 @@ +// #======================================================================== +// # +// # vectors.S +// # +// # M68K startup and exception handling. +// # +// #======================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//======================================================================== +//###DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//###DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k.h> +#include CYGBLD_HAL_TARGET_H +#include <cyg/hal/hal_io.h> +#include <cyg/hal/arch.inc> + +// ---------------------------------------------------------------------------- +// These are for compatibility with older HALs +#ifdef HAL_M68K_EXCEPTION_VECTORS +# define _HAL_M68K_START_ HAL_M68K_EXCEPTION_VECTORS +# undef HAL_M68K_EXCEPTION_VECTORS +#endif +#ifdef HAL_M68K_COPY_ROM_DATA_TO_RAM +# define _HAL_M68K_COPY_ROM_DATA_TO_RAM_ 1 +# undef HAL_M68K_COPY_ROM_DATA_TO_RAM +#endif + +// ---------------------------------------------------------------------------- +// Exception vectors. Typically there are two exception vectors. There is +// one in flash which contains the h/w entry point. This is the section +// .m68k_start. Then there is the run-time set of exception vectors, typically +// held in RAM, which is the section .ram_vectors. In addition to the pointers +// to the exception and interrupt VSRs that section contains the virtual vector +// table and any data that needs to be shared between RedBoot and the application, +// for example shadow copies of read-only registers. +// +// Typical scenarios include the following: +// +// 1) _HAL_M68K_START_ code relocates the flash from its boot location of 0x0 +// to somewhere else. _HAL_M68K_PLATFORM_SETUP1_ initializes SDRAM and +// places it at 0x0. _HAL_M68K_START_ only contains the two initial exception +// vector slots for the start address and stack, the RAM vectors are fully +// populated at run-time by the architectural HAL. This is the typical +// scenario for "large" systems. +// +// 2) for "small" systems where usually there is no RedBoot and the application +// runs directly from flash, all the exception vectors also reside in flash +// and are statically initialized. _HAL_M68K_START_ contains the full set +// of vectors. +// +// 3) as a variant of (2) the run-time exception vectors may live in RAM, +// typically relocated via the VBR register. The vectors will usually be +// dynamically initialized, but if the application is loaded via gdb then +// some code may be saved by static initialization. + + + .section ".m68k_start", "ax" + // This will typically be defined by the platform HAL to get the world + // in a sane state. It should do one-off initializations like getting + // the system into a state matching the memory map. If booting from + // flash it should also contain the initial PC and stack exception + // vectors. +#ifdef _HAL_M68K_START_ + _HAL_M68K_START_ +#endif + + .section ".m68k_start.hal_m68k_exception_reset", "ax" + // The actual entry point, as defined in the linker script. The exact + // state of the system at this point depends on the configuration and + // the processor. + .global hal_m68k_exception_reset + .type hal_m68k_exception_reset, function +hal_m68k_exception_reset: + + // Make absolutely sure that the status register is in a + // sensible state with interrupts disabled, irrespective of + // the platform. + mov.w #0x2700,%sr + + // Platform-specific initialization. This will do things like starting + // up the SDRAM controller. It may also run variant and processor + // initialization code, but the platform HAL gets to decide the order. +#ifdef _HAL_M68K_PLATFORM_SETUP1_ + _HAL_M68K_PLATFORM_SETUP1_ +#endif + + // All memory should now be running so we can get the C environment + // set up. Clear BSS before switching to C mode + .extern _hal_bss_start + .extern _hal_bss_end + move.l # _hal_bss_start,%a0 + move.l # _hal_bss_end,%a1 +1: + cmp.l %a0,%a1 + ble 2f + clr.l (%a0)+ + jra 1b +2: + + // If booting from ROM, move .data from ROM to RAM +#ifdef _HAL_M68K_COPY_ROM_DATA_TO_RAM_ + .extern _hal_data_section_start_lma + .extern _hal_data_section_end_lma + .extern _hal_data_section_start_vma + move.l # _hal_data_section_start_lma, %a0 + move.l # _hal_data_section_end_lma, %a1 + move.l # _hal_data_section_start_vma, %a2 +1: + cmp.l %a0,%a1 + ble 2f + mov.l (%a0)+,(%a2)+ + jra 1b +2: +#endif + + // If there is an FPU, set the default mode +#ifdef CYGINT_HAL_M68K_VARIANT_FPU + mov.w # CYGNUM_HAL_M68K_FPU_CR_DEFAULT, %fpcr +#endif + + // If there is on-chip RAM, copy code and data there and clear + // its BSS. +#ifdef _HAL_M68K_INITIALIZE_IRAM_ + .extern _hal_iram_text_section_start_lma + .extern _hal_iram_data_section_end_lma + .extern _hal_iram_text_section_start_vma + .extern _hal_iram_bss_section_start + .extern _hal_iram_bss_section_end + + move.l # _hal_iram_text_section_start_lma, %a0 + move.l # _hal_iram_data_section_end_lma, %a1 + move.l # _hal_iram_text_section_start_vma, %a2 +1: + cmp.l %a0, %a1 + ble 2f + mov.l (%a0)+, (%a2)+ + jra 1b +2: + move.l # _hal_iram_bss_section_start, %a0 + move.l # _hal_iram_bss_section_end, %a1 +3: + cmp.l %a0, %a1 + ble 4f + clr.l (%a0)+ + jra 3b +4: +#endif + + // Now we just need a valid stack and we can switch to C + // for the remaining initialization. Clearing the frame + // pointer may make life easier for gdb. + mov.l _HAL_M68K_STARTUP_STACK_,%sp + suba.l %a6, %a6 + + .extern hal_m68k_c_startup + jmp hal_m68k_c_startup + +// The exception vector table. Usually this will be held in RAM +// at location 0x0, although it may get moved around via e.g. +// the %vbr register. In addition to the exception vectors the +// virtual vector table is held here, as is any data that needs +// to be shared between RedBoot and eCos. +// +// Some targets in some configurations may define their own version +// of this, if for example the exception vector is held in ROM. +#if defined(_HAL_M68K_RAM_VECTORS_) + + _HAL_M68K_RAM_VECTORS_ + +#elif !defined(_HAL_M68K_RAM_VECTORS_DEFINED_) + .section ".ram_vectors", "aw", @nobits + +# ifndef _HAL_M68K_SUPPRESS_RAM_VECTORS_VSR_TABLE_ + // Start with the interrupt/exception vectors. + .global hal_m68k_vsr_table +hal_m68k_vsr_table: + .rept HAL_M68K_VSR_COUNT + .long 0 + .endr +# endif + + // Next the virtual vector table. Space for this is usually allocated, + // even if virtual vectors are not supported. That avoids confusion + // if RedBoot and the application are configured differently. If a + // platform will never support RedBoot, e.g. because of lack of memory, + // then it can suppress the virtual vectors. + // + // The size of the table comes from <cyg/hal/hal_if.h>, + // CYGNUM_CALL_IF_TABLE_SIZE, but that header cannot easily be included + // in assembler. +# ifndef _HAL_M68K_SUPPRESS_VIRTUAL_VECTOR_ + .global hal_virtual_vector_table +hal_virtual_vector_table: + .rept 64 + .long 0 + .endr +# endif + + // Allow the variant, processor and platform HALs to store additional + // information in the global vectors section. Typically this is used for + // data which needs to be shared between RedBoot and the application, + // e.g. shadow copies of write-only hardware registers. +# ifdef _HAL_M68K_VARIANT_RAM_VECTORS_ + _HAL_M68K_VARIANT_RAM_VECTORS_ +# endif +# ifdef _HAL_M68K_PROCESSOR_RAM_VECTORS_ + _HAL_M68K_PROCESSOR_RAM_VECTORS_ +# endif +# ifdef _HAL_M68K_PLATFORM_RAM_VECTORS_ + _HAL_M68K_PLATFORM_RAM_VECTORS_ +# endif +#endif // _HAL_M68K_RAM_VECTORS_DEFINED_ + + +// ---------------------------------------------------------------------------- +// end of vectors.S diff --git a/ecos/packages/hal/m68k/arch/current/tests/iram1.c b/ecos/packages/hal/m68k/arch/current/tests/iram1.c new file mode 100644 index 0000000..281aeda --- /dev/null +++ b/ecos/packages/hal/m68k/arch/current/tests/iram1.c @@ -0,0 +1,204 @@ +//================================================================= +// +// iram.c +// +// Test support for on-chip memory +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2008-01-14 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/system.h> +#include CYGHWR_MEMORY_LAYOUT_H +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/testcase.h> +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_ass.h> + +#if !defined(CYGMEM_REGION_iram) +# define NA_MSG "No IRAM memory region defined" +#elif defined(CYGMEM_REGION_ram) && (CYGMEM_REGION_iram == CYGMEM_REGION_ram) +# define NA_MSG "IRAM is used as the main RAM memory bank" +#endif + +#ifdef NA_MSG + +externC void +cyg_start( void) +{ + CYG_TEST_INIT(); + CYG_TEST_NA(NA_MSG); +} + +#else // NA_MSG + +// These are provided by the linker script +externC cyg_uint8 _hal_iram_section_start_vma[]; +externC cyg_uint8 _hal_iram_bss_section_start[]; +externC cyg_uint8 _hal_iram_section_end_vma[]; + +// The external declarations which allow the attributes to be +// specified. +externC void onchip_fn1(void) CYGBLD_ATTRIB_SECTION(".iram_text.onchip_fn1"); +externC int onchip_fn2(int) CYGBLD_ATTRIB_SECTION(".iram_text.onchip_fn2"); +extern int onchip_data1[8] CYGBLD_ATTRIB_SECTION(".iram_data.onchip_data1"); +extern char onchip_data2 CYGBLD_ATTRIB_SECTION(".iram_data.onchip_data2"); +extern int onchip_data3[1024] CYGBLD_ATTRIB_SECTION(".iram_data.onchip_data3"); +extern int onchip_bss1 CYGBLD_ATTRIB_SECTION(".iram_bss.onchip_bss1"); +extern int onchip_bss2[42] CYGBLD_ATTRIB_SECTION(".iram_bss.onchip_bss2"); + +// Then the definitions. data3 should be garbage collected by the linker. +int onchip_data1[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; +char onchip_data2 = 42; +int onchip_data3[1024] = { 1 } ; +int onchip_bss1; +int onchip_bss2[42]; + +void +onchip_fn1(void) +{ + int i, data1_sum, fn2_result; + + diag_printf("PASS:<onchip_fn1 running>\n"); + + // Check again that the data has been correctly initialized, + // that there are no addressing funnies, and that the data can + // be overwritten. + for (i = 0, data1_sum = 0; i < 8; i++) { + data1_sum += onchip_data1[i]; + onchip_data1[i] -= i; + } + if (36 != data1_sum) { + diag_printf("FAIL:<onchip data1 array should add up to 36>\n"); + } + + for (i = 0, data1_sum = 0; i < 8; i++) { + data1_sum += onchip_data1[i]; + } + if (8 != data1_sum) { + diag_printf("FAIL:<onchip data1 array should now add up to 8>\n"); + } + // Call one on-chip function from another. + fn2_result = onchip_fn2(data1_sum); + if (861 != fn2_result) { + diag_printf("FAIL:<onchip_fn2 should return 903>\n"); + } +} + +int +onchip_fn2(int arg) +{ + int i; + int result; + diag_printf("PASS:<onchip_fn2 running>\n"); + + // Make sure that the on-chip bss is correctly zero-initialized + // and writable. + for (i = 0; i < 42; i++) { + if (0 != onchip_bss2[i]) { + diag_printf("FAIL:<onchip bss2 should be initialized to 0>\n"); + } + onchip_bss2[i] = i; + } + for (i = 0, result = 0; i < 42; i++) { + result += onchip_bss2[i]; + } + return result; +} + +void +check_addr(void* where) +{ + if ((where < (void*)_hal_iram_section_start_vma) || (where >= (void*)_hal_iram_section_end_vma)) { + diag_printf("FAIL:<ptr %p is not in IRAM region\n", where); + } +} + +externC void +cyg_start( void) +{ + int i; + int data1_sum; + + CYG_TEST_INIT(); + // For human inspection + diag_printf("INFO:<IRAM usage : %p -> %p\n", _hal_iram_section_start_vma, _hal_iram_section_end_vma); + diag_printf("INFO:<IRAM bss @ %p\n", _hal_iram_bss_section_start); + diag_printf("INFO:<RAM : %p -> %p\n", (void*)CYGMEM_REGION_ram, (void*)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE)); + diag_printf("INFO:<onchip_fn1 @ %p>\n", &onchip_fn1); + diag_printf("INFO:<onchip_fn2 @ %p>\n", &onchip_fn2); + diag_printf("INFO:<onchip_data1 @ %p>\n", &onchip_data1[0]); + + // Make sure that IRAM is really separate from main memory. + if ((_hal_iram_section_start_vma >= (cyg_uint8*)CYGMEM_REGION_ram) && + (_hal_iram_section_start_vma < (cyg_uint8*)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE))) { + CYG_TEST_FAIL("IRAM start overlaps SDRAM"); + } + if ((_hal_iram_section_end_vma >= (cyg_uint8*)CYGMEM_REGION_ram) && + (_hal_iram_section_end_vma < (cyg_uint8*)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE))) { + CYG_TEST_FAIL("IRAM end overlaps SDRAM"); + } + + // Make sure that various objects are correctly placed. + check_addr(&onchip_fn1); + check_addr(&onchip_fn2); + check_addr(&onchip_data1[0]); + check_addr(&onchip_data2); + // Not data3, we want that one to be garbage collected. + check_addr(&onchip_bss1); + check_addr(&onchip_bss2[0]); + + // Check that on-chip data is correctly initialized. + CYG_TEST_CHECK( 42 == onchip_data2, "onchip_data2 should be the answer"); + for (i = 0, data1_sum = 0; i < 8; i++) { + data1_sum += onchip_data1[i]; + } + CYG_TEST_CHECK( 36 == data1_sum, "onchip data1 array should add up to 36"); + + // Make sure we can call code located in iram. + { + void (*onchip_fn1_ptr)(void) = &onchip_fn1; + (*onchip_fn1_ptr)(); + } + + CYG_TEST_PASS_FINISH("IRAM test"); +} + +#endif // NA_MSG diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/ChangeLog b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/ChangeLog new file mode 100644 index 0000000..c413110 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/ChangeLog @@ -0,0 +1,194 @@ +2009-01-31 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: update compiler flags for gcc 4.x + +2008-11-18 Bart Veer <bartv@ecoscentric.com> + + * whole package. Replace the original M68K port. + +2008-11-17 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl, doc/m5272c3.sgml, include/plf.inc, + include/plf_io.h, src/platform.c: minor clean-ups. + +2007-09-14 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl, misc/redboot_DBUG.ecm, + misc/redboot_RAM.ecm, misc/redboot_ROM.ecm, + misc/redboot_ROMFFE.ecm : the V2 AMD driver requires an erase + burst duration of at least 400 to operate reliably. + +2007-07-27 John Dallaway <jld@ecoscentric.com> + + * misc/cfpe-stub.gdb: New GDB command file for debugging via + m68k-elf-cfpe-stub. + + * cdl/hal_m68k_m5272c3.cdl: Reference per-package documentation. + +2007-07-25 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: Define CYGHWR_MEMORY_LAYOUT as + required by the eCos Configuration Tool. + +2006-09-10 Bart Veer <bartv@ecoscentric.com> + + * include/plf.inc: processor HAL now uses more verbose names in + the init macros. + + * include/plf_io.h: no need to define MBAR, the processor HAL now + has a default. + + * cdl/hal_m68k_m5272c3.cdl, include/plf_stub.h (removed): allow + the architectural HAL to provide plf_stub.h + +2006-09-08 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: lots of changes for all the reasons + below. + + * src/platform.c: eliminate nearly all initialization. Some of + this now happens higher up in the processor, variant or + architectural HAL. The processor HAL now implements a proper reset + so we can assume the on-chip devices are in a default state. + + * include/plf_io.h: diagnostics definitions now use the variant + HAL defaults. + + * include/plf_arch.h: can now be #include'd by assembler. + + * src/flash.c (was source/m5272c3_flash.c): now uses V2 flash + driver. + + * src/platform/asm.S: no longer needed. + + * include/plf_intr, include/plf.inc: stacks are now provided by + the architectural HAL. + + * include/plf.inc: Initialization uses the processor HAL macros. + + * misc/redboot_DBUG.ecm, misc/redboot_RAM.ecm, + misc/redboot_ROM.ecm, misc/redboot_ROMFFE.ecm: regenerate + + * include/pkgconf/mlt_m5272c3.h, include/pkgconf/mlt_m5272c3.ldi: + Simplified linker scripts using the new architectural support + + * include/pkgconf/mlt_m68k_m5272c3_dbug.h, + include/pkgconf/mlt_m68k_m5272c3_dbug.ldi, + include/pkgconf/mlt_m68k_m5272c3_ram.h, + include/pkgconf/mlt_m68k_m5272c3_ram.ldi, + include/pkgconf/mlt_m68k_m5272c3_rom.h, + include/pkgconf/mlt_m68k_m5272c3_rom.ldi, + include/pkgconf/mlt_m68k_m5272c3_romffe.hi, + include/pkgconf/mlt_m68k_m5272c3_romffe.ldi: + All replaced by mlt_m5272c3.h and mlt_m5272c3.ldi + +2004-08-02 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: minor change following serial driver + change, specify that RTS and CTS are connected on both UARTs + +2004-06-25 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: CYGNUM_HAL_M68K_M5272C3_SCR, ethernet + should always have priority over the cpu, in case you are + debugging over ethernet. + +2004-06-24 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: HAL_M68K_VSR_COUNT has been moved to + the processor HAL + +2004-06-22 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: increase default startup stack size. + Doing a printf() in a static constructor while debugging over + ethernet could overflow. + +2004-05-17 Bart Veer <bartv@ecoscentric.com> + + * src/platform.c (hal_m68k_m5272c3_init): set up the GPIO + directions, then the control bits, to eliminate a small window + where a GPIO pin might be incorrectly set as an output + Fix the exception handling initialization. + + * cdl/hal_m68k_m5272c3.cdl: fix default SCR value for better + performance. + +2004-02-11 Bart Veer <bartv@ecoscentric.com> + + * doc/m5272c3.sgml: romffe startup has now been tested + + * src/platform.c (hal_m68k_m5272c3_init): minor fix to UART + initialization code + + * cdl/hal_m68k_m5272c3.cdl: fix typo in board name. + +2004-01-07 Bart Veer <bartv@ecoscentric.com> + + * doc/m5272c3.sgml, misc/redboot_ROMFFE.ecm: + Add .ecm file for building RedBoot to run from the first block of + flash. + +2003-11-13 Bart Veer <bartv@ecoscentric.com> + + * src/m5272c3_flash.c: remove spurious comment + +2003-09-14 John Dallaway <jld@ecoscentric.com> + + * misc/bdm.gdb: Add BDM macro file for use with GDB. + +2003-07-22 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: + Use a larger denominator. Small values cause problems for + time-related calculations elsewhere. + +2003-07-21 Bart Veer <bartv@ecoscentric.com> + + * doc/m5272c3.sgml: Add documentation + +2003-07-17 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: + Fix some mentions of mcf5272c3 to m5272c3 + +2003-07-11 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_m5272c3.cdl: + Make the default system clock configurable. + +2003-07-04 Bart Veer <bartv@ecoscentric.com> + + * src/platform_asm.S: + * include/plf_intr.h: + * include/plf.inc: + Interrupt stack is now optional and both the stack base and top + need to be exported. + +2003-06-04 Bart Veer <bartv@ecoscentric.com> + + * New version of the M68K support + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/cdl/hal_m68k_m5272c3.cdl b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/cdl/hal_m68k_m5272c3.cdl new file mode 100644 index 0000000..e0e9694 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/cdl/hal_m68k_m5272c3.cdl @@ -0,0 +1,384 @@ +# ==================================================================== +# +# hal_m68k_m5272c3.cdl +# +# Freescale m5272c3 evaluation board HAL package configuration data +# +# ==================================================================== +# ####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later +# version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with eCos; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered by +# the GNU General Public License. However the source code for this file +# must still be made available in accordance with section (3) of the GNU +# General Public License v2. +# +# This exception does not invalidate any other reasons why a work based +# on this file might be covered by the GNU General Public License. +# ------------------------------------------- +# ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Date: 2003-06-04 +# +#####DESCRIPTIONEND#### +#======================================================================== + +cdl_package CYGPKG_HAL_M68K_M5272C3 { + display "Freescale M5272C3 evaluation board" + doc ref/hal-m68k-m5272c3-part.html + parent CYGPKG_HAL_M68K_MCF5272 + include_dir cyg/hal + description "This package provides platform support for the Freescale + M5272C3 evaluation board." + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_m68k_m5272c3.h>" + puts $::cdl_system_header "#define HAL_PLATFORM_CPU \"Freescale MCF5272\"" + puts $::cdl_system_header "#define HAL_PLATFORM_BOARD \"M5272C3\"" + puts $::cdl_system_header "#define HAL_PLATFORM_EXTRA \"\"" + } + compile platform.c + implements CYGINT_HAL_M68K_USE_STANDARD_PLATFORM_STUB_SUPPORT + + implements CYGHWR_DEVS_FLASH_AMD_AM29XXXXX_V2_CACHED_ONLY + compile -library=libextras.a flash.c + define_proc { + puts $cdl_system_header "#define CYGHWR_MEMORY_LAYOUT_LDI <pkgconf/mlt_m5272c3.ldi>" + puts $cdl_system_header "#define CYGHWR_MEMORY_LAYOUT_H <pkgconf/mlt_m5272c3.h>" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM" "ROMFFE" "DBUG"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + + description " + The eCos port to the M5272C3 evaluation board can be used in four + ways. ROM startup should be used when the application will be written + into flash at location 0xFFF00000, alongside the existing dBUG ROM + monitor, and the board is made to boot from that location via + jumper 13. Typically RedBoot will use a ROM startup, and some applications + may do so as well. RAM startup should be used for application development, + if RedBoot is used as the ROM monitor. DBUG startup can be used to develop + software with the existing dBUG ROM monitor. ROMFFE is for applications + that will be written to flash at location 0xFFE00000, overwriting the + existing dBUG ROM monitor." + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + parent CYGPKG_HAL_ROM_MONITOR + default_value { is_loaded(CYGPKG_REDBOOT) } + description " + This option configures the M5272C3 platform HAL to act as a + ROM monitor." + + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Coexist with a ROM monitor" + parent CYGPKG_HAL_ROM_MONITOR + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + requires { CYG_HAL_STARTUP == "RAM" } + + description " + In a typical setup the M5272C3 boots from flash into the + RedBoot ROM monitor, which then provides support for gdb + debugging and for diagnostics. The application will leave + certain exception vectors to RedBoot, and typically the + diagnostics port will also be controlled by RedBoot rather + than directly by the application." + + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + } + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + no_define + description "Set the default system clock." + + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 10000 + description " + In most eCos configurations this option is used to control the + system clock. It specifies the number of microseconds between + clock ticks, so the default value of 10000 corresponds to + 10 milliseconds or 100 timer interrupts per second. The value + is used to program the timer reference register of the mcf5272's + timer 3." + } + + cdl_option CYGHWR_HAL_SYSTEM_CLOCK_HZ { + display "System clock speed in Hz" + flavor data + legal_values { 48000000 66000000 } + default_value 66000000 + define_proc { + puts $cdl_header "#define CYGHWR_HAL_SYSTEM_CLOCK_MHZ (CYGHWR_HAL_SYSTEM_CLOCK_HZ / 1000000)" + } + description " + This option identifies the system clock that the processor uses. + The value is used to set the system timer and calculate baud rates." + } + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated CYGNUM_HAL_RTC_DENOMINATOR * 1000 * CYGNUM_HAL_RTC_PERIOD + description " + This option is used by eCos to convert clock ticks to conventional + time units. CYGNUM_HAL_RTC_NUMERATOR divided by CYGNUM_HAL_RTC_DENOMINATOR + should be the number of nanoseconds per clock tick." + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + calculated 100 + description " + This option is used by eCos to convert clock ticks to conventional + time units. CYGNUM_HAL_RTC_NUMERATOR divided by CYGNUM_HAL_RTC_DENOMINATOR + should be the number of nanoseconds per clock tick." + } + } + + # Provide the extra information needed by the variant and processor HALs + implements CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT + requires !CYGHWR_HAL_M68K_MCFxxxx_UART0_RS485_RTS + requires !CYGHWR_HAL_M68K_MCFxxxx_UART1_RS485_RTS + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_DEFAULT_BAUD { + display "Default diagnostics baud rate" + flavor data + parent CYGPKG_HAL_M68K_MCFxxxx_DIAGNOSTICS + calculated { (CYG_HAL_STARTUP == "DBUG") ? "19200" : "38400" } + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_BOARD_PINS { + display "Board pin connectivity" + flavor data + parent CYGPKG_HAL_M68K_MCF5272_HARDWARE + + calculated { + "a0_usb_tp a1_usb_rp a2_usb_rn a3_usb_tn a4_usb_susp a5_usb_txen a6_usb_rxd a7_in " . + "a8_in a9_in a10_in a11_in a12_in a13_in a14_in a15_in " . + "b0_txd0 b1_rxd0 b2_cts0 b3_rts0 b4_in b5_in b6_in b7_in " . + "b8_etxd3 b9_etxd2 b10_etxd1 b11_erxd3 b12_erxd2 b13_erxd1 b14_erxer b15_e_mdc " . + "c0_in c1_in c2_in c3_in c4_in c5_in c6_in c7_in " . + "c8_in c9_in c10_in c11_in c12_in c13_in c14_in c15_in " . + "d0_none d1_rxd1 d2_cts1 d3_rts1 d4_txd1 d5_none d6_none d7_none" + } + } + + # Memory registers. These are all reparented below the variant HAL, but + # defined here to provide suitable defaults. + cdl_option CYGNUM_HAL_M68K_MCF5272_CACR { + display "Cache control register" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x80000100 + description " + This option specifies the initial value used for the cache control + register. Subsequently the HAL cache macros will only manipulate + the CENB cache enable bit and the CINVA cache invalidate bit." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_ROMBAR { + display "ROM base address register value" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x21000034 + description " + This option is the value used to initialize the ROMBAR register + which controls the location of the on-chip ROM in the memory + map and what types of access are permitted. By default the + internal ROM is disabled since neither eCos nor RedBoot use it + and leaving it disabled reduces power consumption." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_RAMBAR { + display "RAM base address register value" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x20000001 + requires { 0x20000000 == (CYGNUM_HAL_M68K_MCF5272_RAMBAR & 0xFFFFF000) } + description " + This option is the value used to initialize the RAMBAR register + which controls the location of the on-chip SRAM in the memory + map and what types of access are permitted. By default the + internal SRAM is mapped to location 0x20000000, enabled, and + all types of access are permitted. Neither eCos nor RedBoot + use the internal SRAM, instead it is left entirely for the + application." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_ACR0 { + display "Access control register 0" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x0000E020 + description " + This option is the value used to initialize the ACR0 register. + The default value controls access to SDRAM at location 0, + enabling caching and buffered writes." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_ACR1 { + display "Access control register 1" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0xFF00E000 + description " + This option is the value used to initialize the ACR0 register. + The default value controls access to the external flash memory + at location 0xFFE00000, enabling caching." + } + + cdl_option CYGNUM_HAL_M68K_MCF5272_SCR { + display "System configuration register" + parent CYGPKG_HAL_M68K_MCFxxxx_REGISTERS + flavor data + default_value 0x0003 + description " + This option is the value used to the initialize the System + Configuration Register in the System Integration Module. + This register controls bus arbitration and the hardware + watchdog." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + parent CYGPKG_NONE + + description "Global build options including control over compiler + flags, linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "m68k-elf" } + + description "This option specifies the command prefix used when invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=5272 -malign-int -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fomit-frame-pointer" } + description "This option controls the global compiler flags + which are used to compile all packages by default. + Individual packages may define options which + override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=5272 -g -nostdlib -Wl,--gc-sections -Wl,-static" } + + description "This option controls the global linker flags. + Individual packages may define options which + override these global flags." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { "mlt_m5272c3" } + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "RedBoot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This component holds target-specific options for RedBoot, + mainly rules for generating images in the appropriate format." + + cdl_option CYGBLD_M5272C3_REDBOOT_DBUG { + display "Build an srecord file for use with the dBUG monitor" + flavor none + no_define + active_if { "DBUG" == CYG_HAL_STARTUP } + make -priority 325 { + <PREFIX>/bin/redboot.dbug.srec : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O srec $< $@ + } + } + + cdl_option CYGBLD_M5272C3_REDBOOT_RAM { + display "Build a binary RedBoot image to run in RAM" + flavor none + no_define + active_if { "RAM" == CYG_HAL_STARTUP } + make -priority 325 { + <PREFIX>/bin/redboot.ram.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O binary $< $@ + } + } + + cdl_option CYGBLD_M5272C3_REDBOOT_ROM { + display "Build a binary RedBoot image to run in flash at 0xFFF00000" + flavor none + no_define + active_if { "ROM" == CYG_HAL_STARTUP } + make -priority 325 { + <PREFIX>/bin/redboot.rom.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O binary $< $@ + } + } + + cdl_option CYGBLD_M5272C3_REDBOOT_ROMFFE { + display "Build a binary RedBoot image to run in flash at 0xFFE00000" + flavor none + no_define + active_if { "ROMFFE" == CYG_HAL_STARTUP } + make -priority 325 { + <PREFIX>/bin/redboot.romffe.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) -O binary $< $@ + } + } + } +} diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/doc/m5272c3.sgml b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/doc/m5272c3.sgml new file mode 100644 index 0000000..dfdd039 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/doc/m5272c3.sgml @@ -0,0 +1,807 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- m5272c3.sgml --> +<!-- --> +<!-- m5272c3 platform HAL documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2003, 2004, 2008 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): bartv --> +<!-- Contact(s): bartv --> +<!-- Date: 2003/07/15 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-m68k-m5272c3-part"><title>Freescale M5272C3 Board Support</title> + +<!-- {{{ Overview --> + +<refentry id="m68k-m5272c3"> + <refmeta> + <refentrytitle>Overview</refentrytitle> + </refmeta> + <refnamediv> + <refname>eCos Support for the Freescale M5272C3 Board</refname> + <refpurpose>Overview</refpurpose> + </refnamediv> + + <refsect1 id="m68k-m5272c3-description"><title>Description</title> + <para> +The Freescale M5272C3 board has an MCF5272 ColdFire processor, 4MB of +external SDRAM, 2MB of external flash memory, and connectors plus +required support chips for all the on-chip peripherals. By default the +board comes with its own dBUG ROM monitor, located in the bottom half +of the flash. + </para> + <para> +For typical eCos development a RedBoot image is programmed into the +top half of the flash memory, and the board is made to boot this image +rather than the existing dBUG monitor. RedBoot provides gdb stub +functionality so it is then possible to download and debug eCos +applications via the gdb debugger. This can happen over either a +serial line or over ethernet. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-hardware"><title>Supported Hardware</title> + <para> +In a typical setup the bottom half of the flash memory is reserved for +the dBUG ROM monitor and is not accessible to eCos. That leaves four +flash blocks of 256K each. Of these one is used for the RedBoot image +and another is used for managing the flash and holding RedBoot fconfig +values. The remaining two blocks at 0xFFF40000 and 0xFFF80000 can be +used by application code. + </para> + <para> +By default eCos will only support the four megabytes of external SDRAM +present on the initial versions of the board, accessible at location +0x00000000. Later versions come with 16MB. If all 16MB of memory are +required then the ACR0 register needs to be changed. The default value +is controlled by the configuration option +<varname>CYGNUM_HAL_M68K_M5272C3_ACR0</varname>, but this option is +only used during ROM startup so in a typical setup it would be +necessary to rebuild and update RedBoot. Alternatively the register +can be updated by application code, preferably using a high priority +static constructor to ensure that the extra memory is visible before +any code tries to use that memory. It will also be necessary to change +the memory layout so that the linker knows about the additional +memory. + </para> + <para> +By default the 4K of internal SRAM is mapped to location 0x20000000 +using the RAMBAR register. This is not used by eCos or by RedBoot so +can be used by application code. The M68K architectural HAL has an +<filename>iram1.c</filename> testcase to illustrate the linker script +support for this. The internal 16K of ROM is left +disabled by default because its contents are of no use to most +applications. The on-chip peripherals are mapped at 0x10000000 via the +MBAR register. + </para> + <para> +There is a serial driver <varname>CYGPKG_DEVS_SERIAL_MCFxxxx</varname> +which supports both on-chip UARTs. One of the UARTs, usually uart0, +can be used by RedBoot for communication with the host. If this UART +is needed by the application, either directly or via the serial +driver, then it cannot also be used for RedBoot communication. Another +communication channel such as ethernet should be used instead. The +serial driver package is loaded automatically when configuring for the +M5272C3 target. + </para> + <para> +There is an ethernet driver <varname>CYGPKG_DEVS_ETH_MCFxxxx</varname> +for the on-chip ethernet device. This driver is also loaded +automatically when configuring for the M5272C3 target. The M5272C3 +board does not have a unique MAC address, so a suitable address has to +be programmed into flash via RedBoot's <command>fconfig</command> +command. + </para> + <para> +eCos manages the on-chip interrupt controller. Timer 3 is used to +implement the eCos system clock, but timers 0, 1 and 2 are unused and +left for the application. The GPIO pins are manipulated only as needed +to get the UARTs and ethernet working. eCos will reset the remaining +on-chip peripherals (DMA, USB, PLCI, QSPI and PWM) during system +startup or soft reset but will not otherwise manipulate them. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-tools"><title>Tools</title> + <para> +The M5272C3 port is intended to work with GNU tools configured for an +m68k-elf target. The original port was done using m68k-elf-gcc version +3.2.1, m68k-elf-gdb version 5.3, and binutils version 2.13.1. + </para> + <para> +By default eCos is built using the compiler flag +<option>-fomit-frame-pointer</option>. Omitting the frame pointer +eliminates some work on every function call and makes another register +available, so the code should be smaller and faster. However without a +frame pointer m68k-elf-gdb is not always able to identify stack +frames, so it may be unable to provide accurate backtrace information. +Removing this compiler flag from the configuration option +<varname>CYGBLD_GLOBAL_CFLAGS</varname> avoids such debug problems. + </para> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Hardware setup --> + +<refentry id="m68k-m5272c3-setup"> + <refmeta> + <refentrytitle>Setup</refentrytitle> + </refmeta> + <refnamediv> + <refname>Setup</refname> + <refpurpose>Preparing the M5272C3 board for eCos Development</refpurpose> + </refnamediv> + + <refsect1 id="m68k-m5272c3-setup-overview"><title>Overview</title> + <para> +In a typical development environment the M5272C3 board boots from +flash into the RedBoot ROM monitor. eCos applications are configured +for a RAM startup, and then downloaded and run on the board via the +debugger m68k-elf-gdb. Preparing the board therefore involves +programming a suitable RedBoot image into flash memory. + </para> + <para> +The following RedBoot configurations are supported: + </para> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Description</entry> + <entry>Use</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>RedBoot running from the board's flash</entry> + <entry>redboot_ROM.ecm</entry> + <entry>redboot_rom.bin</entry> + </row> + <row> + <entry>dBUG</entry> + <entry>Used for initial setup</entry> + <entry>redboot_DBUG.ecm</entry> + <entry>redboot_dbug.srec</entry> + </row> + <row> + <entry>RAM</entry> + <entry>Used for upgrading ROM version</entry> + <entry>redboot_RAM.ecm</entry> + <entry>redboot_ram.bin</entry> + </row> + <row> + <entry>ROMFFE</entry> + <entry>RedBoot running from the board's flash at 0xFFE00000</entry> + <entry>redboot_ROMFFE.ecm</entry> + <entry>redboot_romffe.bin</entry> + </row> + </tbody> + </tgroup> + </informaltable> + <para> +For serial communications all versions run with 8 bits, no parity, and +1 stop bit. The dBUG version runs at 19200 baud. The ROM and RAM +versions run at 38400 baud. These baud rates can be changed via the +configuration option +<varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD</varname> and +rebuilding RedBoot. By default RedBoot will use the board's terminal +port, corresponding to uart0, but this can also be changed via the +configuration option +<varname>CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT</varname>. On an +M5272C3 platform RedBoot also supports ethernet communication and +flash management. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-setup-first"><title>Initial Installation</title> + <para> +This process assumes that the board still has its original dBUG ROM +monitor and does not require any special debug hardware. It leaves the +existing ROM monitor in place, allowing the setup process to be +repeated just in case that should ever prove necessary. + </para> + <para> +Programming the RedBoot rom monitor into flash memory requires an +application that can manage flash blocks. RedBoot itself has this +capability. Rather than have a separate application that is used only +for flash management during the initial installation, a special +RAM-resident version of RedBoot is loaded into memory and run. This +version can then be used to load the normal flash-resident version of +RedBoot and program it into the flash. + </para> + <para> +The first step is to connect an RS232 cable between the M5272C3 +terminal port and the host PC. A suitable cable is supplied with the +board. Next start a terminal emulation application such as +HyperTerminal or minicom on the host PC and set the serial +communication parameters to 19200 baud, 8 data bits, no parity, 1 stop +bit (8N1) and no flow control (handshaking). Make sure that the jumper +next to the flash chip is set for bootstrap from the bottom of flash, +location 0xFFE00000. The details of this jumper depend on the revision +of the board, so the supplied board documentation should be consulted +for more details. Apply power to the board and you should see a +<prompt>dBUG></prompt> prompt. + </para> + <para> +Once dBUG is up and running the RAM-resident version of RedBoot can be +downloaded: + </para> + <screen> +dBUG> dl +Escape to local host and send S-records now... + </screen> + <para> +The required S-records file is <filename>redboot_dbug.srec</filename>, +which is normally supplied with the eCos release in the <filename +class="directory">loaders</filename> directory. If it needs to be +rebuilt then instructions for this are supplied <link +linkend="m68k-m5272c3-setup-rebuild">below</link>. The file should be +sent to the target as raw text using the terminal emulator: + </para> + <screen> +S-record download successful! +dBUG> + </screen> + <para> +It is now possible to run the RAM-resident version of RedBoot: + </para> + <screen> +dBUG> go 0x20000 ++FLASH configuration checksum error or invalid key +Ethernet eth0: MAC address 00:00:00:00:00:03 +Can't get BOOTP info for device! + +RedBoot(tm) bootstrap and debug environment [DBUG] +Non-certified release, version v2_0_1 - built 09:55:34, Jun 24 2003 + +Platform: M5272C3 (Freescale MCF5272) +Copyright (C) 2000, 2001, 2002, Free Software Foundation, Inc. + +RAM: 0x00000000-0x00400000, 0x0003f478-0x003bd000 available +FLASH: 0xffe00000 - 0x00000000, 8 blocks of 0x00040000 bytes each. +RedBoot> + </screen> + <para> +At this stage the RedBoot flash management initialization has not yet +happened so the warning about the configuration checksum error is +expected. To perform this initialization use the +<command>fis init -f</command> command: + </para> + <screen> +RedBoot> fis init -f +About to initialize [format] FLASH image system - continue (y/n)? y +*** Initialize FLASH Image System +... Erase from 0xfff40000-0xfffc0000: .. +... Erase from 0x00000000-0x00000000: +... Erase from 0xfffc0000-0xffffffff: . +... Program from 0x003bf000-0x003ff000 at 0xfffc0000: . +RedBoot> + </screen> + <para> +The flash chip on the M5272C3 board is slow at erasing flash blocks so +this operation can take some time. At the end the block of flash at +location 0xFFFC0000 holds information about the various flash blocks, +allowing other flash management operations to be performed. The next +step is to set up RedBoot's non-volatile configuration values: + </para> + <screen> +RedBoot> fconfig -i +Initialize non-volatile configuration - continue (y/n)? y +Run script at boot: false +Use BOOTP for network configuration: true +DNS server IP address: +GDB connection port: 9000 +Force console for special debug messages: false +Network hardware address [MAC]: 0x00:0x00:0x00:0x00:0x00:0x03 +Network debug at boot time: false +Update RedBoot non-volatile configuration - continue (y/n)? y +... Erase from 0xfffc0000-0xffffffff: . +... Program from 0x003bf000-0x003ff000 at 0xfffc0000: . +RedBoot> + </screen> + <para> +For most of these configuration variables the default value is +correct. If there is no suitable BOOTP service running on the local +network then BOOTP should be disabled, and instead RedBoot will prompt +for a fixed IP address, netmask, and addresses for the local gateway +and DNS server. The other exception is the network hardware address, +also known as MAC address. All boards should be given a unique MAC +address, not the one in the above example. If there are two boards on +the same network trying to use the same MAC address then the resulting +behaviour is undefined. + </para> + <para> +It is now possible to load the flash-resident version of RedBoot. +Because of the way that flash chips work it is better to first load it +into RAM and then program it into flash. + </para> + <screen> +RedBoot> load -r -m ymodem -b %{freememlo} + </screen> + <para> +The file <filename>redboot_rom.bin</filename> should now be uploaded +using the terminal emulator. The file is a raw binary and should be +transferred using the Y-modem protocol. + </para> + <screen> +Raw file loaded 0x0003f800-0x000545a3, assumed entry at 0x0003f800 +xyzModem - CRC mode, 2(SOH)/84(STX)/0(CAN) packets, 5 retries +RedBoot> + </screen> + <para> +Once RedBoot has been loaded into RAM it can be programmed into flash: + </para> + <screen> +RedBoot> fis create RedBoot -b %{freememlo} +An image named 'RedBoot' exists - continue (y/n)? y +... Erase from 0xfff00000-0xfff40000: . +... Program from 0x0003f800-0x0007f800 at 0xfff00000: . +... Erase from 0xfffc0000-0xffffffff: . +... Program from 0x003bf000-0x003ff000 at 0xfffc0000: . +RedBoot> + </screen> + <para> +The flash-resident version of RedBoot has now programmed at location +0xFFF00000, and the flash info block at 0xFFFC0000 has been updated. +The initial setup is now complete. Power off the board and set the +flash jumper to boot from location 0xFFF00000 instead of 0xFFE00000. +Also set the terminal emulator to run at 38400 baud (the usual baud +rate for RedBoot), and power up the board again. + </para> + <screen> ++Ethernet eth0: MAC address 00:00:00:00:00:03 +Can't get BOOTP info for device! + +RedBoot(tm) bootstrap and debug environment [ROM] +Non-certified release, version v2_0_1 - built 09:57:50, Jun 24 2003 + +Platform: M5272C3 (Freescale MCF5272) +Copyright (C) 2000, 2001, 2002, Free Software Foundation, Inc. + +RAM: 0x00000000-0x00400000, 0x0000b400-0x003bd000 available +FLASH: 0xffe00000 - 0x00000000, 8 blocks of 0x00040000 bytes each. +RedBoot> + </screen> + <para> +When RedBoot issues its prompt it is also ready to accept connections +from m68k-elf-gdb, allowing eCos applications to be downloaded and +debugged. + </para> + <para> +Occasionally it may prove necessary to update the installed RedBoot +image. This can be done simply by repeating the above process, using +dBUG to load the dBUG version of RedBoot +<filename>redboot_dbug.srec</filename>. Alternatively the existing +RedBoot install can be used to load a RAM-resident version, +<filename>redboot_ram.bin</filename>. + </para> + <para> +The ROMFFE version of RedBoot can be installed at location 0xFFE00000, +replacing dBUG. This may be useful if the system needs more flash +blocks than are available with the usual ROM RedBoot. Installing this +RedBoot image will typically involve a BDM-based utility. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-setup-rebuild"><title>Rebuilding RedBoot</title> + <para> +Should it prove necessary to rebuild a RedBoot binary, this is done +most conveniently at the command line. The steps needed to rebuild the +dBUG version of RedBoot are: + </para> + <screen> +$ mkdir redboot_dbug +$ cd redboot_dbug +$ ecosconfig new m5272c3 redboot +$ ecosconfig import $ECOS_REPOSITORY/hal/m68k/mcf52xx/mcf5272/m5272c3/v2_0_1/misc/redboot_DBUG.ecm +$ ecosconfig resolve +$ ecosconfig tree +$ make + </screen> + <para> +At the end of the build the <filename +class="directory">install/bin</filename> subdirectory should contain +the required file <filename>redboot_dbug.srec</filename>. + </para> + <para> +Rebuilding the RAM and ROM versions involves basically the same +process. The RAM version uses the file +<filename>redboot_RAM.ecm</filename> and generates a file +<filename>redboot_ram.bin</filename>. The ROM version uses the file +<filename>redboot_ROM.ecm</filename> and generates a file +<filename>redboot_rom.bin</filename>. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-bdm"><title>BDM</title> + <para> +An alternative to debugging an application on top of Redboot is to use +a BDM hardware debug solution. On the eCos side this requires building +the configuration for RAM startup and +with <varname>CYGSEM_HAL_USE_ROM_MONITOR</varname> disabled. Note that +a RAM build of RedBoot automatically has the latter configuration +option disabled, so it is possible to run a RAM RedBoot via BDM and +bypass the dBUG stages of the installation process. + </para> + <para> +On the host-side the details depend on exactly which BDM solution is +in use. Typically it will be necessary to initialize the hardware +prior to downloading the eCos application, either via a configuration +file or by using gdb macros. The +file <filename>misc/bdm.gdb</filename> in the platform HAL defines +example gdb macros. + </para> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Config --> + +<refentry id="m68k-m5272c3-config"> + <refmeta> + <refentrytitle>Configuration</refentrytitle> + </refmeta> + <refnamediv> + <refname>Configuration</refname> + <refpurpose>Platform-specific Configuration Options</refpurpose> + </refnamediv> + + <refsect1 id="m68k-m5272c3-config-overview"><title>Overview</title> + <para> +The M5272C3 platform HAL package is loaded automatically when eCos is +configured for an M5272C3 target. It should never be necessary to load +this package explicitly. Unloading the package should only happen as a +side effect of switching target hardware. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-startup"><title>Startup</title> + <para> +The M5272C3 platform HAL package supports four separate startup types: + </para> + <variablelist> + <varlistentry> + <term>RAM</term> + <listitem><para> +This is the startup type which is normally used during application +development. The board has RedBoot programmed into flash at location +0xFFF00000 and boots from that location. +<application>m68k-elf-gdb</application> is then used to load a RAM +startup application into memory and debug it. It is assumed that the +hardware has already been initialized by RedBoot. By default the +application will use eCos' virtual vectors mechanism to obtain certain +services from RedBoot, including diagnostic output. + </para></listitem> + </varlistentry> + <varlistentry> + <term>ROM</term> + <listitem><para> +This startup type can be used for finished applications which will +be programmed into flash at location 0xFFF00000. The application will +be self-contained with no dependencies on services provided by other +software. eCos startup code will perform all necessary hardware +initialization. + </para></listitem> + </varlistentry> + <varlistentry> + <term>ROMFFE</term> + <listitem><para> +This is a variant of the ROM startup type which can be used if the +application will be programmed into flash at location 0xFFE00000, +overwriting the board's dBUG ROM monitor. + </para> + </listitem> + </varlistentry> + <varlistentry> + <term>DBUG</term> + <listitem><para> +This is a variant of the RAM startup which allows applications to be +loaded via the board's dBUG ROM monitor rather than via RedBoot. It +exists mainly to support the dBUG version of RedBoot which is needed +during hardware setup. Once the application has started it will take +over all the hardware, and it will not depend on any services provided +by dBUG. This startup type does not provide gdb debug facilities. + </para></listitem> + </varlistentry> + </variablelist> + + </refsect1> + + <refsect1 id="m68k-m5272c3-config-redboot"><title>RedBoot and Virtual Vectors</title> + <para> +If the application is intended to act as a ROM monitor, providing +services for other applications, then the configuration option +<varname>CYGSEM_HAL_ROM_MONITOR</varname> should be set. Typically +this option is set only when building RedBoot. + </para> + <para> +If the application is supposed to make use of services provided by a +ROM monitor, via the eCos virtual vector mechanism, then the +configuration option <varname>CYGSEM_HAL_USE_ROM_MONITOR</varname> +should be set. By default this option is enabled when building for a +RAM startup, disabled otherwise. It can be manually disabled for a RAM +startup, making the application self-contained, as a testing step +before switching to ROM startup. + </para> + <para> +If the application does not rely on a ROM monitor for diagnostic +services then one of the serial ports will be claimed for HAL +diagnostics. By default eCos will use the terminal port, corresponding +to uart0. The auxiliary port, uart1, can be selected instead via the +configuration option +<varname>CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT</varname>. The baud +rate for the selected port is controlled by +<varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD</varname>. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-flash"><title>Flash Driver</title> + <para> +The platform HAL package contains flash driver support. By default +this is inactive, and it can be made active by loading the generic +flash package <varname>CYGPKG_IO_FLASH</varname>. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-registers"><title>Special Registers</title> + <para> +The MCF5272 processor has a number of special registers controlling +the cache, on-chip RAM and ROM, and so on. The platform HAL provides a +number of configuration options for setting these, for example +<varname>CYGNUM_HAL_M68K_M5272C3_RAMBAR</varname> controls the initial +value of the RAMBAR register. These options are only used during a ROM +or ROMFFE startup. For a RAM startup it will be RedBoot that +initializes these registers, so if the default values are not +appropriate for the target application then it will be necessary to +rebuild RedBoot with new settings for these options. Alternatively it +should be possible to reprogram some or all of the registers early on +during startup, for example by using a high-priority static +constructor. + </para> + <para> +One of the special registers, MBAR, cannot be controlled via a +configuration option. Changing the value of this register could have +drastic effects on the system, for example moving the on-chip +peripherals to a different location in memory, and it would be very +easy to end up with inconsistencies between RedBoot and the eCos +application. Instead the on-chip peripherals are always mapped to +location 0x10000000. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-clock"><title>System Clock</title> + <para> +By default the system clock interrupts once every 10ms, corresponding +to a 100Hz clock. This can be changed by the configuration option +<varname>CYGNUM_HAL_RTC_PERIOD</varname>, the number of microseconds +between clock ticks. Other clock-related settings are recalculated +automatically if the period is changed. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-config-flags"><title>Compiler Flags</title> + <para> +The platform HAL defines the default compiler and linker flags for all +packages, although it is possible to override these on a per-package +basis. Most of the flags used are the same as for other architectures +supported by eCos. There are three flags specific to this port: + </para> + <variablelist> + <varlistentry> + <term><option>-mcpu=5272</option></term> + <listitem><para> +The <application>m68k-elf-gcc</application> compiler supports many +variants of the M68K architecture, from the original 68000 onwards. +For an MCF5272 processor <option>-mcpu=5272</option> should be used. + </para></listitem> + </varlistentry> + <varlistentry> + <term><option>-malign-int</option></term> + <listitem><para> +This option forces <application>m68k-elf-gcc</application> to align +integer and floating point data to a 32-bit boundary rather than a +16-bit boundary. It should improve performance. However the resulting +code is incompatible with most published application binary interface +specifications for M68K processors, so it is possible that this option +causes problems with existing third-party object code. + </para></listitem> + </varlistentry> + <varlistentry> + <term><option>-fomit-frame-pointer</option></term> + <listitem><para> +Traditionally the <varname>%A6</varname> register was used as a +dedicated frame pointer, and the compiler was expected to generate +link and unlink instructions on procedure entry and exit. These days +the compiler is perfectly capable of generating working code without a +frame pointer, so omitting the frame pointer often saves some work +during procedure entry and exit and makes another register available +for optimization. However without a frame pointer register the +<application>m68k-elf-gdb</application> debugger is not always able to +interpret a thread stack, so it cannot reliably give a backtrace. +Removing <option>-fomit-frame-pointer</option> from the default flags +will make debugging easier, but the generated code may be worse. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + +</refentry> + +<!-- }}} --> +<!-- {{{ Port --> + +<refentry id="m68k-m5272c3-port"> + <refmeta> + <refentrytitle>The HAL Port</refentrytitle> + </refmeta> + <refnamediv> + <refname>HAL Port</refname> + <refpurpose>Implementation Details</refpurpose> + </refnamediv> + + <refsect1 id="m68k-m5272c3-port-overview"><title>Overview</title> + <para> +This documentation explains how the eCos HAL specification has been +mapped onto the M5272C3 hardware, and shold be read in conjunction +with that specification. The M5272C3 platform HAL package complements +the M68K architectural HAL, the MCFxxxx variant HAL, and the MCF5272 +processor HAL. It provides functionality which is specific to the +target board. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-startup"><title>Startup</title> + <para> +Following a hard or soft reset the HAL will initialize or +reinitialize most of the on-chip peripherals. There is an exception +for RAM startup applications which depend on a ROM monitor for certain +services: the UARTs and the ethernet device will not be reinitialized +because they may be in use by RedBoot for communication with the host. + </para> + <para> +For a ROM or ROMFFE startup the HAL will perform additional +initialization, setting up the external DRAM and programming the +various internal registers. The values used for most of these +registers are <link +linkend="m68k-m5272c3-config-registers">configurable</link>. Full +details can be found in the exported headers <filename +class="headerfile">cyg/hal/plf.inc</filename> +and <filename class="headerfile">cyg/hal/proc.inc</filename>. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-linker"><title>Linker Scripts and Memory Maps</title> + <para> +The platform HAL package provides the memory layout information needed +to generate the linker script. The key memory locations are as follows: + </para> + <variablelist> + <varlistentry> + <term>external SDRAM</term> + <listitem><para> +This is mapped to location 0x00000000. The first 384 bytes are used +for hardware exception vectors. The next 256 bytes are normally used +for the eCos virtual vectors, allowing RAM-based applications to use +services provided by the ROM monitor. For ROM and ROMFFE startup all +remaining SDRAM is available. For RAM and DBUG startup available SDRAM +starts at location 0x00020000, with the bottom 128K reserved for use +by either the RedBoot or dBUG ROM monitors. + </para></listitem> + </varlistentry> + <varlistentry> + <term>on-chip peripherals</term> + <listitem><para> +These are accessible at location 0x10000000 onwards, as per the +defined symbol <varname>HAL_MCFxxxx_MBAR</varname>. This address +cannot easily be changed during development because both the ROM +monitor and the application must use the same address. The +<varname>%mbar</varname> system register is initialized appropriately +during a ROM or ROMFFE startup. + </para></listitem> + </varlistentry> + <varlistentry> + <term>on-chip SRAM</term> + <listitem><para> +The 4K of internal SRAM are normally mapped at location 0x20000000. +The <varname>%rambar</varname> register is initialized +during a ROM startup using the value of the configuration +option <varname>CYGNUM_HAL_M68K_M5272C3_RAMBAR</varname>. Neither eCos +nor RedBoot use the internal SRAM so all of it is available to +application code. + </para></listitem> + </varlistentry> + <varlistentry> + <term>on-chip ROM</term> + <listitem><para> +Usually this is left disabled since its contents are of no interest to +most applications. If it is enabled then it is usually mapped at +location 0x21000000. The <varname>%rombar</varname> register is +initialized during a ROM startup using the value of the configuration +option <varname>CYGNUM_HAL_M68K_M5272C3_ROMBAR</varname>. + </para></listitem> + </varlistentry> + <varlistentry> + <term>off-chip Flash</term> + <listitem><para> +This is located at the top of memory, location 0xFFE00000 onwards. For +ROM and RAM startups it is assumed that a jumper is used to disable +the bottom half of the flash, so location 0xFFE00000 is actually a +mirror of 0xFFF00000. For ROMFFE and DBUG startups all of the flash is +visible. By default the flash block at location 0xFFF00000 is used to +hold RedBoot or another ROM startup application, and the block at +location 0xFFFC00000 is used to hold flash management data and the +RedBoot <command>fconfig</command> variables. The blocks at +0xFFF400000 and 0xFFF80000 can be used by application code. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-clock"><title>Clock Support</title> + <para> +The platform HAL provides configuration options for the eCos system +clock. This always uses the hardware timer 3, which should not be used +directly by application code. The gprof-based profiling code uses +timer 2, so that is only available when not profiling. Timers 0 and 1 +are never used by eCos so application code is free to manipulate these +as required. The actual HAL macros for managing the clock are provided +by the MCF5272 processor HAL. The specific numbers used are a +characteristic of the platform because they depend on the processor +speed. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-other-hal"><title>Other Issues</title> + <para> +The M5272C3 platform HAL does not affect the implementation of other +parts of the eCos HAL specification. The MCF5272 processor HAL, the +MCFxxxx variant HAL, and the M68K architectural HAL documentation +should be consulted for further details. + </para> + </refsect1> + + <refsect1 id="m68k-m5272c3-port-other"><title>Other Functionality</title> + <para> +The platform HAL package also provides a flash driver for the off-chip +AMD AM29PL160C flash chip. This driver is inactive by default, and +only becomes active if the configuration includes the generic flash +support <varname>CYGPKG_IO_FLASH</varname>. + </para> + </refsect1> + +</refentry> + +<!-- }}} --> + +</part> diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/pkgconf/mlt_m5272c3.h b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/pkgconf/mlt_m5272c3.h new file mode 100644 index 0000000..4b132c7 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/pkgconf/mlt_m5272c3.h @@ -0,0 +1,20 @@ +#if !defined(__ASSEMBLER__) && !defined(__LDI__) +#include <cyg/infra/cyg_type.h> +#include <stddef.h> +#endif + +#define CYGMEM_REGION_ram (0x0) +#define CYGMEM_REGION_ram_SIZE (0x00400000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_flash (0xFFE00000) +#define CYGMEM_REGION_flash_SIZE (0x00200000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) +#define CYGMEM_REGION_iram (0x20000000) +#define CYGMEM_REGION_iram_SIZE (0x00001000) +#define CYGMEM_REGION_iram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#if !defined(__ASSEMBLER__) && !defined(__LDI__) +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/pkgconf/mlt_m5272c3.ldi b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/pkgconf/mlt_m5272c3.ldi new file mode 100644 index 0000000..a5eb681 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/pkgconf/mlt_m5272c3.ldi @@ -0,0 +1,40 @@ +#define __LDI__ 1 +#include <pkgconf/hal_m68k_m5272c3.h> +#include <pkgconf/mlt_m5272c3.h> + +MEMORY +{ + ram : ORIGIN = CYGMEM_REGION_ram, LENGTH = CYGMEM_REGION_ram_SIZE + flash : ORIGIN = CYGMEM_REGION_flash, LENGTH = CYGMEM_REGION_flash_SIZE + iram : ORIGIN = CYGMEM_REGION_iram, LENGTH = CYGMEM_REGION_iram_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_ram_vectors( ram, 0x00000000) + +#if defined(CYG_HAL_STARTUP_ROM) + + SECTION_m68k_start ( flash, 0xFFF00000) + SECTION_code ( flash, .) + SECTION_iram( iram, CYGMEM_REGION_iram, AT(_hal_code_section_end)) + SECTION_data( ram, _hal_ram_vectors_section_end, AT(_hal_iram_section_end_lma)) + +#elif defined(CYG_HAL_STARTUP_ROMFFE) + + SECTION_m68k_start ( flash, 0xFFE00000) + SECTION_code ( flash, .) + SECTION_iram( iram, CYGMEM_REGION_iram, AT(_hal_code_section_end)) + SECTION_data( ram, _hal_ram_vectors_section_end, AT(_hal_iram_section_end_lma)) + +#elif defined(CYG_HAL_STARTUP_RAM) || defined(CYG_HAL_STARTUP_DBUG) + /* The first 128K of RAM are reserved for RedBoot */ + SECTION_m68k_start ( ram, 0x00020000 ) + SECTION_code ( ram, . ) + SECTION_iram( iram, CYGMEM_REGION_iram, AT(_hal_code_section_end)) + SECTION_data( ram, _hal_iram_section_end_lma, LMA_EQ_VMA) +#endif + CYG_LABEL_DEFN(__heap1) = ALIGN (0x4); + SECTIONS_END +} diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf.inc b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf.inc new file mode 100644 index 0000000..c734e7f --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf.inc @@ -0,0 +1,91 @@ +##============================================================================= +## +## plf.inc +## +## m5272c3 assembler header file +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): bartv +## Date: 2003-06-04 +######DESCRIPTIONEND#### +##============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_m5272c3.h> +#include <cyg/hal/var_io.h> + +// ---------------------------------------------------------------------------- +// Various constants to poke into coprocessor or SIM registers +// +// MBAR controls the location of the System Integration Module, +// i.e. all the on-chip hardware. Conventionally this is at +// location 0x10000000. Obviously it cannot contain code. + .equ _HAL_MCF5272_MBAR_VALUE_, (HAL_MCFxxxx_MBAR + HAL_MCF5272_MBAR_SC + HAL_MCF5272_MBAR_UC + HAL_MCF5272_MBAR_V) + +// Chip select 0 is connected to 2MB of flash @ 0xFFE00000. +// This chip is 16 bits wide and requires 6 wait states according +// to the docs. (dBUG uses 8 wait states initially, 5 later on). +// 5 seems to work fine. + .equ _HAL_MCF5272_CSBR0_VALUE_, (0xFFE00000 + HAL_MCF5272_CSBR_EBI_16_32 + HAL_MCF5272_CSBR_BW_16 + HAL_MCF5272_CSBR_ENABLE) + .equ _HAL_MCF5272_CSOR0_VALUE_, (0xFFE00000 + (0x05 << HAL_MCF5272_CSOR_WS_SHIFT)) + +// The board can be populated with sram on cs2, but for now assume a bare board. + +// Chip select 7 is connected to 4MB of SDRAM, which should be @ 0x0 + .equ _HAL_MCF5272_CSBR7_VALUE_, (0x00000000 + HAL_MCF5272_CSBR_EBI_SDRAM + HAL_MCF5272_CSBR_BW_CACHELINE + HAL_MCF5272_CSBR_ENABLE) + .equ _HAL_MCF5272_CSOR7_VALUE_, (0xFFC00000 + (0x1F << HAL_MCF5272_CSOR_WS_SHIFT)) + +// SDRAM control registers + .equ _HAL_MCF5272_SDCR_VALUE_, (HAL_MCF5272_SDCR_MCAS_A9 + HAL_MCF5272_SDCR_BALOC_A22_A21 + HAL_MCF5272_SDCR_REG + HAL_MCF5272_SDCR_INIT) +#if defined(CYGHWR_HAL_SYSTEM_CLOCK_HZ_66000000) + .equ _HAL_MCF5272_SDTR_VALUE_, (HAL_MCF5272_SDTR_RTP_66+HAL_MCF5272_SDTR_RC_6+HAL_MCF5272_SDTR_RP_4+HAL_MCF5272_SDTR_RCD_3+HAL_MCF5272_SDTR_CLT_2) +#elif defined(CYGHWR_HAL_SYSTEM_CLOCK_HZ_48000000) + .equ _HAL_MCF5272_SDTR_VALUE_, (HAL_MCF5272_SDTR_RTP_48+HAL_MCF5272_SDTR_RC_6+HAL_MCF5272_SDTR_RP_4+HAL_MCF5272_SDTR_RCD_3+HAL_MCF5272_SDTR_CLT_2) +#else +# error Unsupported system clock speed. +#endif + +// ---------------------------------------------------------------------------- +// Startup code. Use the processor defaults. +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMFFE) +# define _HAL_MCF5272_STANDARD_INIT_ROM_ 1 +#else +# define _HAL_MCF5272_STANDARD_INIT_RAM_ 1 +#endif + +//------------------------------------------------------------------------------ +// end of plf.inc diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_arch.h b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_arch.h new file mode 100644 index 0000000..19a72f0 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_arch.h @@ -0,0 +1,60 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H + +//============================================================================= +// +// plf_arch.h +// +// m5272c3 specific definitions. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> + +// Platform initialization +externC void hal_m68k_m5272c3_init(void); +#define HAL_M68K_PLATFORM_INIT() hal_m68k_m5272c3_init() +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_intr.h b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_intr.h new file mode 100644 index 0000000..a350d06 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_intr.h @@ -0,0 +1,66 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Platform specific interrupt and clock support +// +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/plf_arch.h> + +// Three of the external interrupt lines are connected to other hardware. +#define CYGNUM_HAL_VECTOR_PLI_B33 CYGNUM_HAL_VECTOR_EXTINT1 +#define CYGNUM_HAL_VECTOR_PLI_A34 CYGNUM_HAL_VECTOR_EXTINT3 +#define CYGNUM_HAL_VECTOR_ABORT CYGNUM_HAL_VECTOR_EXTINT6 + +#define CYGNUM_HAL_ISR_PLI_B33 CYGNUM_HAL_ISR_EXTINT1 +#define CYGNUM_HAL_ISR_PLI_A34 CYGNUM_HAL_ISR_EXTINT3 +#define CYGNUM_HAL_ISR_ABORT CYGNUM_HAL_ISR_EXTINT6 + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H + diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_io.h b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_io.h new file mode 100644 index 0000000..5d7f8fe --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/include/plf_io.h @@ -0,0 +1,54 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +# define CYGONCE_HAL_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Details of the m5272c3 platform +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2007, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal_m68k_m5272c3.h> + +// ---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/bdm.gdb b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/bdm.gdb new file mode 100644 index 0000000..d6fa11a --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/bdm.gdb @@ -0,0 +1,48 @@ +define bdm_preload + set $mbar = 0x10000001 + set $SCR = $mbar - 1 + 0x0004 + set $SPR = $mbar - 1 + 0x0006 + set $CSBR0 = $mbar - 1 + 0x0040 + set $CSOR0 = $mbar - 1 + 0x0044 + set $CSBR1 = $mbar - 1 + 0x0048 + set $CSOR1 = $mbar - 1 + 0x004C + set $CSBR2 = $mbar - 1 + 0x0050 + set $CSOR2 = $mbar - 1 + 0x0054 + set $CSBR3 = $mbar - 1 + 0x0058 + set $CSOR3 = $mbar - 1 + 0x005C + set $CSBR4 = $mbar - 1 + 0x0060 + set $CSOR4 = $mbar - 1 + 0x0064 + set $CSBR5 = $mbar - 1 + 0x0068 + set $CSOR5 = $mbar - 1 + 0x006C + set $CSBR6 = $mbar - 1 + 0x0070 + set $CSOR6 = $mbar - 1 + 0x0074 + set $CSBR7 = $mbar - 1 + 0x0078 + set $CSOR7 = $mbar - 1 + 0x007C + set $SDCR = $mbar - 1 + 0x0180 + set $SDTR = $mbar - 1 + 0x0184 + set *((short*) $SCR) = 0x0083 + set *((short*) $SPR) = 0xFFFF + set *((int*) $CSBR0) = 0xFFE00201 + set *((int*) $CSOR0) = 0xFFE00014 + set *((int*) $CSBR1) = 0 + set *((int*) $CSOR1) = 0 + set *((int*) $CSBR2) = 0 + set *((int*) $CSOR2) = 0 + set *((int*) $CSBR3) = 0 + set *((int*) $CSOR3) = 0 + set *((int*) $CSBR4) = 0 + set *((int*) $CSOR4) = 0 + set *((int*) $CSBR5) = 0 + set *((int*) $CSOR5) = 0 + set *((int*) $CSBR6) = 0 + set *((int*) $CSOR6) = 0 + set *((int*) $CSBR7) = 0x00000701 + set *((int*) $CSOR7) = 0xFFC0007C + set *((int*) $SDTR) = 0x0000F539 + set *((int*) $SDCR) = 0x00004211 + set *((int*)0) = 0 +end + +define bdm_postload + set $pc=0x20000 +end diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_DBUG.ecm b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_DBUG.ecm new file mode 100644 index 0000000..31aa46d --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_DBUG.ecm @@ -0,0 +1,102 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware m5272c3 ; + template redboot ; + package -hardware CYGPKG_HAL_M68K current ; + package -hardware CYGPKG_HAL_M68K_MCFxxxx current ; + package -hardware CYGPKG_HAL_M68K_MCF5272 current ; + package -hardware CYGPKG_HAL_M68K_M5272C3 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 current ; + package -hardware CYGPKG_DEVS_SERIAL_MCFxxxx current ; + package -hardware CYGPKG_DEVS_ETH_MCFxxxx current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value DBUG +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 0x100000 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_RAM.ecm b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_RAM.ecm new file mode 100644 index 0000000..f12c615 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_RAM.ecm @@ -0,0 +1,102 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware m5272c3 ; + template redboot ; + package -hardware CYGPKG_HAL_M68K current ; + package -hardware CYGPKG_HAL_M68K_MCFxxxx current ; + package -hardware CYGPKG_HAL_M68K_MCF5272 current ; + package -hardware CYGPKG_HAL_M68K_M5272C3 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 current ; + package -hardware CYGPKG_DEVS_SERIAL_MCFxxxx current ; + package -hardware CYGPKG_DEVS_ETH_MCFxxxx current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 0x100000 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_ROM.ecm b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_ROM.ecm new file mode 100644 index 0000000..e4f4d64 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_ROM.ecm @@ -0,0 +1,102 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware m5272c3 ; + template redboot ; + package -hardware CYGPKG_HAL_M68K current ; + package -hardware CYGPKG_HAL_M68K_MCFxxxx current ; + package -hardware CYGPKG_HAL_M68K_MCF5272 current ; + package -hardware CYGPKG_HAL_M68K_M5272C3 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 current ; + package -hardware CYGPKG_DEVS_SERIAL_MCFxxxx current ; + package -hardware CYGPKG_DEVS_ETH_MCFxxxx current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { + user_value 0x100000 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_ROMFFE.ecm b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_ROMFFE.ecm new file mode 100644 index 0000000..7e05dd6 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/misc/redboot_ROMFFE.ecm @@ -0,0 +1,98 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware m5272c3 ; + template redboot ; + package -hardware CYGPKG_HAL_M68K current ; + package -hardware CYGPKG_HAL_M68K_MCFxxxx current ; + package -hardware CYGPKG_HAL_M68K_MCF5272 current ; + package -hardware CYGPKG_HAL_M68K_M5272C3 current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2 current ; + package -hardware CYGPKG_DEVS_SERIAL_MCFxxxx current ; + package -hardware CYGPKG_DEVS_ETH_MCFxxxx current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROMFFE +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 <cyg/ns/dns/dns.h> +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/src/flash.c b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/src/flash.c new file mode 100644 index 0000000..5af0bd0 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/src/flash.c @@ -0,0 +1,83 @@ +//========================================================================== +// +// m5272c3_flash.c +// +// Support for AMD Flash devices on M5272C3 evaluation board +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/system.h> +#ifdef CYGPKG_IO_FLASH +# include <cyg/io/flash.h> +# include <cyg/io/flash_dev.h> +# include <cyg/io/am29xxxxx_dev.h> + +// There is a single AM29PL160C device. +static const CYG_FLASH_FUNS(hal_m5272c3_flash_amd_funs, + &cyg_am29xxxxx_init_check_devid_16, + &cyg_flash_devfn_query_nop, + &cyg_am29xxxxx_erase_16, + &cyg_am29xxxxx_program_16, + (int (*)(struct cyg_flash_dev*, const cyg_flashaddr_t, void*, size_t))0, + &cyg_am29xxxxx_lock_nop, + &cyg_am29xxxxx_unlock_nop); + +static const cyg_am29xxxxx_dev hal_m5272c3_flash_priv = { + .devid = 0x2245, + .block_info = { + { 0x00004000, 1 }, + { 0x00002000, 2 }, + { 0x00038000, 1 }, + { 0x00040000, 7 } + } +}; + +CYG_FLASH_DRIVER(hal_m5272c3_flash, + &hal_m5272c3_flash_amd_funs, + 0, + 0xFFE00000, + 0xFFFFFFFF, + 4, + hal_m5272c3_flash_priv.block_info, + &hal_m5272c3_flash_priv +); +#endif diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/src/platform.c b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/src/platform.c new file mode 100644 index 0000000..924ebc9 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/m5272c3/current/src/platform.c @@ -0,0 +1,87 @@ +//============================================================================= +// +// platform.c +// +// M5272C3 platform code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_m5272c3.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_if.h> + +// ---------------------------------------------------------------------------- +// Platform initialization. This is called early on from +// hal_m68k_startup(), once the C environment has been set up. We are +// running on the startup stack and interrupts are disabled. It is +// assumed that the memory map is already sane - either the ROM +// monitor or the assembler startup code should have taken care of +// that. +// +// For ROM/ROMFFE startup the assumption is that we have just come +// out of reset, either because of a hard reset or because a soft +// reset activated the watchdog. Hence we can assume all peripherals +// are at their default settings. + +void +hal_m68k_m5272c3_init(void) +{ + // Start with the hardware. If this code is reached from a hard + // reset, RedBoot or dBUG then most of the hardware should be in a + // reasonable state. For a soft reset assume that the watchdog has + // been used so again everything should be in a reasonable state. + // Hence we only need to worry about registers where the default + // settings are inappropriate. + + // After a power-up the ethernet phy needs a bit of time to negotiate + // the link. Without this delay packets appear to go out but are + // just lost, which is a problem for bootp. +#if defined(CYGPKG_DEVS_ETH_MCFxxxx) && (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMFFE)) + HAL_DELAY_US(10000); +#endif +} diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/ChangeLog b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/ChangeLog new file mode 100644 index 0000000..e27aa1a --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/ChangeLog @@ -0,0 +1,201 @@ +2008-11-18 Bart Veer <bartv@ecoscentric.com> + + * whole package. Replace the original M68K port. + +2008-11-17 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_mcd5272.cdl, cdl/gpio.cdl, include/proc_arch.h, + include/proc_cache.h, include/proc.inc, include/proc_intr.h, + include/proc_io.h, src/mcf5272.c, src/mcf5272_profile.S: minor + clean-ups. + +2008-09-02 Bart Veer <bartv@ecoscentric.com> + + * include/proc_arch.h: allow platform HALs to override the + PROC_INIT() macro. + +2007-07-27 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl: Reference per-package documentation. + +2006-10-13 Bart Veer <bartv@ecoscentric.com> + + * include/proc_io.h (HAL_MCF52xx_ETHx_TXBD_DEF): fix naming of the + TXBD error conditions. + +2006-10-09 Bart Veer <bartv@ecoscentric.com> + + * include/proc.inc: add utility macros for low-level bootstrap + (flash remapping etc.) to simplify most platform HALs. + +2006-09-11 Bart Veer <bartv@ecoscentric.com> + + * cdl/gpio.cdl, cdl/hal_m68k_mcf52xx.cdl, src/gpio.c : + Rationalize pin naming. + +2006-09-10 Bart Veer <bartv@ecoscentric.com> + + * include/proc.inc: take care to OR in the CSBR0 BW bits as per + the pin sampling on reset. Use more verbose names to distinguish + between registers and their values. + + * include/proc_io.h (HAL_MCF52xx_MBAR): provide a default + definition if the platform HAL has not specified one. + +2006-09-08 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_mcf5272.cdl: GPIO is now largely handled by the + processor HAL instead of the platform HAL. Diagnostics are now + handled by the variant HAL. + + * src/mcf5272.c: add processor initialization code. The processor + HAL now largely takes care of GPIO pins, interrupts and + exceptions, so less has to be done by the platform HAL. + + * src/mcf5272_profile.S: fix typo. + + * include/proc_io.h: update to match variant HAL changes. The + processor HAL now picks up variant HAL definitions for the UARTs, + ethernet and QSPI which are largely compatible with the 5282. + + * include/proc_intr.h: use HAL_DELAY_US() from the architectural + HAL. Add a reset macro which activates the watchdog. + + * include/proc_cache.h: use updated register definitions. + + * include/proc_arch.h: add processor init function and idle thread + action. + + * include/proc.inc: add macros for handling the flash remapping, + system registers, and memory initialization. + + * src/spi.c: instantiate the on-chip SPI bus device here. + + * tests/iram1.c: new testcase for MCF5272 on-chip RAM + + * cdl/gpio.cdl, src/gpio.c: make it easier for platform HALs to + define the GPIO pin connectivity. + +2006-09-06 Nick Garnett <nickg@ecoscentric.com> + + * include/proc_io.h (HAL_MCF5272_QSPI_QCRn_QSPI_CS_CSn): Added + this macro to permit easier definition of demultiplexed SPI chip + selects. + +2005-04-15 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_m68k_mcf5272.cdl: Define a HAL processor variant header in + <pkgconf/system.h> + +2005-02-21 Bart Veer <bartv@ecoscentric.com> + + * include/proc_intr.h (HAL_CLOCK_INITIALIZE): fix initialization + values. Both the prescaler and the period were off by one. + Reported by Matthew Miller. + + * src/mcf5272.c (hal_enable_profile_timer): similar adjustment for + the profile timer. + +2005-02-20 Bart Veer <bartv@ecoscentric.com> + + * include/proc_intr.h: implement HAL_CLOCK_LATENCY() + +2004-10-04 Bart Veer <bartv@ecoscentric.com> + + * include/proc_io.h (HAL_MCF5272_PBCNT_PBCNT5_TA): add missing + GPIO pin definition + +2004-06-24 Bart Veer <bartv@ecoscentric.com> + + * include/proc.inc, src/mcf5272.c: move cacr and icr_pri shadow + copies from .data to .fixed_vectors, so that they can be shared + between RedBoot and the application. + +2004-06-22 Bart Veer <bartv@ecoscentric.com> + + * include/proc_intr.h (HAL_DELAY_US): try to give accurate timings + irrespective of whether or not the icache is enabled + +2004-05-17 Bart Veer <bartv@ecoscentric.com> + + * include/proc_io.h: add more SPI-related definitions + +2004-03-08 Bart Veer <bartv@ecoscentric.com> + + * include/proc_io.h (HAL_MCF52xx_ETH0_PROC_INIT): only connect the + phy pins if the ethernet driver expects a phy. + + * cdl/hal_m68k_mcf5272.cdl: add calculated options for the legal + ISR priority range. + +2004-02-11 Bart Veer <bartv@ecoscentric.com> + + * include/proc_io.h: move cacr/acr/rambar/rombar definitions from + variant to processor HAL. Add processor-specific ethernet + initialization macro to allow the ethernet driver to be shared + between different coldfire processors. Add new HAL_MCF52xx() macro + to facilitate device driver sharing. + + * include/proc_cache.h: cacr defines are now processor-specific, + rather than defined by the 52xx variant HAL. + + * include/proc.inc: rework ISR vector extraction macros, to save + an instruction in the main VSR + +2003-11-13 Bart Veer <bartv@ecoscentric.com> + + * src/mcf5272.c: fix typo in header + +2003-09-26 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf5272.sgml, cdl/hal_m68k_mcf5272.sgml, + include/proc_intr.h, src/mcf5272.c, src/mcf5272_profile.S: + Implement a profiling timer. + +2003-07-22 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf5272.sgml: fix various typos etc. + +2003-07-17 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf5272.sgml: Add documentation + +2003-07-08 Bart Veer <bartv@ecoscentric.com> + + * include/proc_io.h: + Make some UART definitions MCF52xx rather than MCF5272, so that + the generic driver can test for these and adapt to what the + current MCF52xx processor actually supports + +2003-07-05 Bart Veer <bartv@ecoscentric.com> + + * include/proc_intr.h (HAL_MCF5272_EXTERNAL_INTERRUPTS): + Fix handling of external interrupts + +2003-06-04 Bart Veer <bartv@ecoscentric.com> + + * New version of the M68K support + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/cdl/gpio.cdl b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/cdl/gpio.cdl new file mode 100644 index 0000000..dad5fa9 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/cdl/gpio.cdl @@ -0,0 +1,717 @@ +# ==================================================================== +# +# gpio.cdl +# +# GPIO settings for a Freescale mcf5272 +# +# ==================================================================== +# ####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 2006, 2008 Free Software Foundation, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later +# version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with eCos; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered by +# the GNU General Public License. However the source code for this file +# must still be made available in accordance with section (3) of the GNU +# General Public License v2. +# +# This exception does not invalidate any other reasons why a work based +# on this file might be covered by the GNU General Public License. +# ------------------------------------------- +# ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +#######DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Date: 2006-07-10 +# +#####DESCRIPTIONEND#### +#======================================================================== + +cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA { + display "Configure port A pins" + flavor none + no_define + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0 { + display "Configure pin PA0" + flavor data + legal_values { "usb_tp" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a0_usb_tp") ? "usb_tp" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a0_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a0_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a0_out1") ? "out1" : + "invalid" + } + description " + Pin PA0 can be configured as the USB TP signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1 { + display "Configure pin PA1" + flavor data + legal_values { "usb_rp" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a1_usb_rp") ? "usb_rp" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a1_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a1_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a1_out1") ? "out1" : + "invalid" + } + description " + Pin PA1 can be configured as the USB RP signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2 { + display "Configure pin PA2" + flavor data + legal_values { "usb_rn" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a2_usb_rn") ? "usb_rn" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a2_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a2_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a2_out1") ? "out1" : + "invalid" + } + description " + Pin PA2 can be configured as the USB RN signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3 { + display "Configure pin PA3" + flavor data + legal_values { "usb_tn" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a3_usb_tn") ? "usb_tn" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a3_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a3_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a3_out1") ? "out1" : + "invalid" + } + description " + Pin PA3 can be configured as the USB TN signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4 { + display "Configure pin PA4" + flavor data + legal_values { "usb_susp" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a4_usb_susp") ? "usb_susp" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a4_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a4_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a4_out1") ? "out1" : + "invalid" + } + description " + Pin PA4 can be configured as the USB suspend signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5 { + display "Configure pin PA5" + flavor data + legal_values { "usb_txen" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a5_usb_txen") ? "usb_txen" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a5_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a5_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a5_out1") ? "out1" : + "invalid" + } + description " + Pin PA5 can be configured as the USB TxEn signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6 { + display "Configure pin PA6" + flavor data + legal_values { "usb_rxd" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a6_usb_rxd") ? "usb_rxd" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a6_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a6_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a6_out1") ? "out1" : + "invalid" + } + description " + Pin PA6 can be configured as the USB RxD signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7 { + display "Configure pin PA7" + flavor data + legal_values { "qspi_cs3" "dout3" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_qspi_cs3") ? "qspi_cs3" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_dout3") ? "dout3" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_out1") ? "out1" : + "invalid" + } + description " + Pin PA7 can be configured as the QSPI chip select 3 signal, the + PLIC DOUT3 signal, a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8 { + display "Configure pin PA8" + flavor data + legal_values { "fsc0_fsr0" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a8_fsc0_fsr0") ? "fsc0_fsr0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a8_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a8_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a8_out1") ? "out1" : + "invalid" + } + description " + Pin PA8 can be configured as the PLIC frame sync FSR0/FSC0 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9 { + display "Configure pin PA9" + flavor data + legal_values { "dgnt0" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a9_dgnt0") ? "dgnt0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a9_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a9_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a9_out1") ? "out1" : + "invalid" + } + description " + Pin PA9 can be configured as the PLIC D-Channel grant signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10 { + display "Configure pin PA10" + flavor data + legal_values { "dreq0_tp" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a10_dreq0") ? "dreq0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a10_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a10_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a10_out1") ? "out1" : + "invalid" + } + description " + Pin PA10 can be configured as the PLIC D-Channel request signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11 { + display "Configure pin PA11" + flavor data + legal_values { "qspi_cs1" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a11_qspi_cs1") ? "qspi_cs1" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a11_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a11_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a11_out1") ? "out1" : + "invalid" + } + description " + Pin PA11 can be configured as the QSPI CS1 chip select signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12 { + display "Configure pin PA12" + flavor data + legal_values { "dfsc2" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a12_dfsc2") ? "dfsc2" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a12_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a12_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a12_out1") ? "out1" : + "invalid" + } + description " + Pin PA12 can be configured as the PLIC delayed frame sync 2 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13 { + display "Configure pin PA13" + flavor data + legal_values { "dfsc3" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a13_dfsc3") ? "dfsc3" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a13_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a13_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a13_out1") ? "out1" : + "invalid" + } + description " + Pin PA13 can be configured as the PLIC delayed frame sync 3 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14 { + display "Configure pin PA14" + flavor data + legal_values { "dreq1" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a14_dreq1") ? "dreq1" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a14_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a14_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a14_out1") ? "out1" : + "invalid" + } + description " + Pin PA14 can be configured as the PLIC D-channel request 1 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15 { + display "Configure pin PA15" + flavor data + legal_values { "dgnt1" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a15_dgnt1") ? "dgnt1" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a15_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a15_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a15_out1") ? "out1" : + "invalid" + } + description " + Pin PA15 can be configured as the PLIC D-channel grant 1 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } +} + +cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB { + display "Configure port B pins" + flavor none + no_define + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0 { + display "Configure pin PB0" + flavor data + legal_values { "txd0" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b0_txd0") ? "txd0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b0_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b0_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b0_out1") ? "out1" : + "invalid" + } + description " + Pin PB0 can be configured as the UART0 tx signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1 { + display "Configure pin PB1" + flavor data + legal_values { "rxd0" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b1_rxd0") ? "rxd0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b1_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b1_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b1_out1") ? "out1" : + "invalid" + } + description " + Pin PB1 can be configured as the UART0 rx signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2 { + display "Configure pin PB2" + flavor data + legal_values { "cts0" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b2_cts0") ? "cts0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b2_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b2_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b2_out1") ? "out1" : + "invalid" + } + description " + Pin PB2 can be configured as the UART0 CTS signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3 { + display "Configure pin PB3" + flavor data + legal_values { "rts0" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b3_rts0") ? "rts0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b3_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b3_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b3_out1") ? "out1" : + "invalid" + } + description " + Pin PB3 can be configured as the UART0 RTS signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4 { + display "Configure pin PB4" + flavor data + legal_values { "clk0" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b4_clk0") ? "clk0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b4_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b4_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b4_out1") ? "out1" : + "invalid" + } + description " + Pin PB4 can be configured as the UART0 clock signal, a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5 { + display "Configure pin PB5" + flavor data + legal_values { "ta" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b5_ta") ? "ta" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b5_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b5_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b5_out1") ? "out1" : + "invalid" + } + description " + Pin PB5 can be configured as the bus control transfer acknowledge + signal, a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB6 { + display "Configure pin PB6" + flavor data + legal_values { "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b6_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b6_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b6_out1") ? "out1" : + "invalid" + } + description " + Pin PB6 can be configured as a GPIO input, or + a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7 { + display "Configure pin PB7" + flavor data + legal_values { "tout0" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b7_tout0") ? "tout0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b7_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b7_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b7_out1") ? "out1" : + "invalid" + } + description " + Pin PB7 can be configured as the timer output 0 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8 { + display "Configure pin PB8" + flavor data + legal_values { "etxd3" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b8_etxd3") ? "etxd3" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b8_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b8_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b8_out1") ? "out1" : + "invalid" + } + description " + Pin PB8 can be configured as the ethernet TxD3 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9 { + display "Configure pin PB9" + flavor data + legal_values { "etxd2" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b9_etxd2") ? "etxd2" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b9_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b9_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b9_out1") ? "out1" : + "invalid" + } + description " + Pin PB9 can be configured as the ethernet TxD2 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10 { + display "Configure pin PB10" + flavor data + legal_values { "etxd1" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b10_etxd1") ? "etxd1" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b10_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b10_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b10_out1") ? "out1" : + "invalid" + } + description " + Pin PB10 can be configured as the ethernet TxD1signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11 { + display "Configure pin PB11" + flavor data + legal_values { "erxd3" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b11_erxd3") ? "erxd3" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b11_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b11_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b11_out1") ? "out1" : + "invalid" + } + description " + Pin PB11 can be configured as the ethernet RxD3 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12 { + display "Configure pin PB12" + flavor data + legal_values { "erxd2" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b12_erxd2") ? "erxd2" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b12_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b12_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b12_out1") ? "out1" : + "invalid" + } + description " + Pin PB12 can be configured as the ethernet RxD2 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13 { + display "Configure pin PB13" + flavor data + legal_values { "erxd1" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b13_erxd1") ? "erxd1" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b13_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b13_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b13_out1") ? "out1" : + "invalid" + } + description " + Pin PB13 can be configured as the ethernet RxD1 signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14 { + display "Configure pin PB14" + flavor data + legal_values { "erxer" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b14_erxer") ? "erxer" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b14_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b14_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b14_out1") ? "out1" : + "invalid" + } + description " + Pin PB14 can be configured as the ethernet RxER signal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15 { + display "Configure pin PB15" + flavor data + legal_values { "e_mdc" "in" "out0" "out1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b15_e_mdc") ? "e_mdc" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b15_in") ? "in" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b15_out0") ? "out0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b15_out1") ? "out1" : + "invalid" + } + description " + Pin PB15 can be configured as the ethernet E_MDCsignal, + a GPIO input, or a GPIO output (initial value 0 or 1)." + } +} + +cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC { + display "Configure port C pins" + flavor none + no_define + + for { set pin 0 } { $pin < 16 } { incr pin } { + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC[set pin] { + display "Configure pin PC[set pin]" + flavor data + legal_values { "in" "out0" "out1" } + default_value \ + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, \"c[set pin]_in\") ? \"in\" : \ + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, \"c[set pin]_out0\") ? \"out0\" : \ + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, \"c[set pin]_out1\") ? \"out1\" : \ + \"invalid\" + description " + Pin PC[set pin] can be configured as a GPIO input, or a GPIO output (initial value 0 or 1)." + } + } +} + +cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD { + display "Configure port D pins" + flavor none + no_define + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD0 { + display "Configure pin PD0" + flavor data + legal_values { "none" "dcl0" "clk1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d0_none") ? "none" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d0_dcl0") ? "dcl0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d0_clk1") ? "clk1" : + "invalid" + } + description " + Pin PD0 can be configured as the IDL clock 0 signal, the UART1 + clock signal, or left at high impedance." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1 { + display "Configure pin PD1" + flavor data + legal_values { "none" "din0" "rxd1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d1_none") ? "none" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d1_din0") ? "din0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d1_rxd1") ? "rxd1" : + "invalid" + } + description " + Pin PD1 can be configured as the IDL input 0 signal, the UART1 + rx signal, or left at high impedance." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2 { + display "Configure pin PD2" + flavor data + legal_values { "none" "cts1" "qspi_cs2" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d2_none") ? "none" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d2_cts1") ? "cts1" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d2_qspi_cs2") ? "qspi_cs2" : + "invalid" + } + description " + Pin PD2 can be configured as the UART1 CTS signal, the QSPI chip + select 2 signal, or left at high impedance." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3 { + display "Configure pin PD3" + flavor data + legal_values { "none" "rts1" "int5" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d3_none") ? "none" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d3_rts1") ? "rts1" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d3_int5") ? "int5" : + "invalid" + } + description " + Pin PD3 can be configured as the UART1 RTS signal, an external + interrupt input, or left at high impedance." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4 { + display "Configure pin PD4" + flavor data + legal_values { "none" "dout0" "txd1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d4_none") ? "none" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d4_dout0") ? "dout0" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d4_txd1") ? "txd1" : + "invalid" + } + description " + Pin PD4 can be configured as the IDL serial data output 0 signal, + the UART1 TX signal, or left at high impedance." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD5 { + display "Configure pin PD5" + flavor data + legal_values { "none" "din3" "int4" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d5_none") ? "none" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d5_din3") ? "din3" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d5_int4") ? "int4" : + "invalid" + } + description " + Pin PD5 can be configured as the IDL input 3 signal, an + external interrupt input, or left at high impedance." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD6 { + display "Configure pin PD6" + flavor data + legal_values { "none" "pwm_out1" "tout1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d6_none") ? "none" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d6_pwm_out1") ? "pwm_out1" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d6_tout1") ? "tout1" : + "invalid" + } + description " + Pin PD6 can be configured as the PWM output 1 signal, the + timer 1 output signal, or left at high impedance." + } + + cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD7 { + display "Configure pin PD7" + flavor data + legal_values { "none" "pwm_out2" "tin1" } + default_value { + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d7_none") ? "none" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d7_pwm_out2") ? "pwm_out2" : + is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d7_tin1") ? "tin1" : + "invalid" + } + description " + Pin PD7 can be configured as the PWM output 2 signal, + the timer 1 input signal, or left at high impedance." + } +} diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/cdl/hal_m68k_mcf5272.cdl b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/cdl/hal_m68k_mcf5272.cdl new file mode 100644 index 0000000..e05442a --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/cdl/hal_m68k_mcf5272.cdl @@ -0,0 +1,230 @@ +# ==================================================================== +# +# hal_m68k_mcf5272.cdl +# +# Processor settings for a Freescale mcf5272 +# +# ==================================================================== +# ####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later +# version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with eCos; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered by +# the GNU General Public License. However the source code for this file +# must still be made available in accordance with section (3) of the GNU +# General Public License v2. +# +# This exception does not invalidate any other reasons why a work based +# on this file might be covered by the GNU General Public License. +# ------------------------------------------- +# ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +#######DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Date: 2003-06-04 +# +#####DESCRIPTIONEND#### +#======================================================================== + +cdl_package CYGPKG_HAL_M68K_MCF5272 { + display "MCF5272 ColdFire variant HAL" + doc ref/hal-m68k-mcf5272.html + parent CYGPKG_HAL_M68K_MCFxxxx + requires CYGPKG_HAL_M68K_MCFxxxx + implements CYGINT_HAL_M68K_VARIANT_CACHE + implements CYGINT_HAL_M68K_VARIANT_IRAM + hardware + include_dir cyg/hal + + description "The mcf5272 M68k/ColdFire processor HAL package provides + generic support for this processor." + + compile mcf5272.c + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PROC_H <pkgconf/hal_m68k_mcf5272.h>" + } + + cdl_component CYGPKG_HAL_M68K_MCF5272_HARDWARE { + display "Board-specific details" + flavor none + + cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO { + display "Configure GPIO pins" + flavor none + active_if CYGHWR_HAL_M68K_MCF5272_BOARD_PINS + script gpio.cdl + + description " + MCF5272 processors have 48 multi-purpose pins which can + be used for on-chip peripherals or for general purpose I/O. + Provided the platform HAL provides the appropriate information + the processor HAL will automatically set up each pin early on + during system initialization." + } + + cdl_component CYGHWR_HAL_M68K_MCFxxxx_UART0 { + display "UART0 details" + flavor bool + default_value { (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0 == "txd0") || (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1 == "rxd0") } + description " + MCF5272 processors have three built-in UARTs which can be + used for HAL diagnostics or through the serial driver + CYGPKG_DEVS_SERIAL_MCFxxxx. By default support for each + UART is enabled if the relevant GPIO configuration options + are appropriate, disabled otherwise. Users can override this if + necessary, for example if the pins should come up in GPIO mode + but may be switched to UART mode later on." + + cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_RTS { + display "UART0 RTS connected" + flavor bool + default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3 == "rts0" } + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + description " + This option enables support elsewhere in the system + when the UART0 RTS signal is connected to a processor pin." + } + + cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_CTS { + display "UART0 CTS connected" + flavor bool + default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2 == "cts0" } + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + description " + This option enables support elsewhere in the system + when the UART0 CTS signal is connected to a processor pin." + } + + cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_RS485_RTS { + display "UART0 RS485 support" + flavor bool + default_value 0 + active_if CYGHWR_HAL_M68K_MCFxxxx_UART0_RTS + requires { CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT != "uart0" } + description " + If the UART0 signals are connected to an RS485 transceiver instead of + an RS232 transceiver and the UART0 RTS line activates that transceiver + then this option can be enabled. It primarily affects h/w flow control + and transmit code within the generic mcfxxxx serial driver." + } + } + + cdl_component CYGHWR_HAL_M68K_MCFxxxx_UART1 { + display "UART1 details" + flavor bool + default_value { (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4 == "txd1") || (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1 == "rxd1") } + description " + MCF5272 processors have two built-in UARTs which can be + used for HAL diagnostics or through the serial driver + CYGPKG_DEVS_SERIAL_MCFxxxx. By default support for each + UART is enabled if the relevant GPIO configuration options + are appropriate, disabled otherwise. Users can override this if + necessary, for example if the pins should come up in GPIO mode + but may be switched to UART mode later on." + + cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_RTS { + display "UART1 RTS connected" + flavor bool + default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3 == "rts1" } + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + description " + This option enables support elsewhere in the system + when the UART1 RTS signal is connected to a processor pin." + } + + cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_CTS { + display "UART1 CTS connected" + flavor bool + default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2 == "cts1" } + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + description " + This option enables support elsewhere in the system + when the UART1 CTS signal is connected to a processor pin." + } + + cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_RS485_RTS { + display "UART1 RS485 support" + flavor bool + default_value 0 + active_if CYGHWR_HAL_M68K_MCFxxxx_UART1_RTS + requires { CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT != "uart1" } + description " + If the UART1 signals are connected to an RS485 transceiver instead of + an RS232 transceiver and the UART1 RTS line activates that transceiver + then this option can be enabled. This primarily affects h/w flow control + and transmit code within the generic mcfxxxx serial driver." + } + } + } + + cdl_option CYGIMP_HAL_M68K_MCF5272_IDLE { + display "Idle thread behaviour" + flavor data + legal_values { "run" "sleep" "stop" } + default_value { is_loaded(CYGPKG_CPULOAD) ? "run" : "sleep" } + description " + The processor can automatically enter a low power mode whenever + the system is idle. In run mode the cpu just spins. In sleep mode + the cpu clock is disabled but peripherals continue running, and any + interrupt will wake up the cpu. In stop mode the on-chip peripherals + are shut down as well and an external interrupt is required. The + MCF5272 provides finer-grained control over power management via + the PMR power management register but the processor HAL leaves + this to the application." + } + + cdl_option CYGFUN_HAL_M68K_MCF5272_PROFILE_TIMER { + display "Support profiling" + active_if CYGPKG_PROFILE_GPROF + default_value 1 + implements CYGINT_PROFILE_HAL_TIMER + compile mcf5272_profile.S + + description " + The MCF5272 processor HAL can provide support for gprof-based + profiling. This uses timer TMR2 to generate regular interrupts, + and the interrupt handler records the PC at the time of the + interrupt." + } + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN { + display "Lowest permitted interrupt priority" + flavor data + calculated 1 + description " + In the MCF5272 processor HAL interrupt priorities are mapped + directly onto M68K IPL levels, so valid priorities are in the + range 1 to 7. However IPL level 7 is non-maskable so should not + be used by typical eCos code." + } + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX { + display "Lowest permitted interrupt priority" + flavor data + calculated 6 + description " + In the MCF5272 processor HAL interrupt priorities are mapped + directly onto M68K IPL levels, so valid priorities are in the + range 1 to 7. However IPL level 7 is non-maskable so should not + be used by typical eCos code." + } +} diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/doc/mcf5272.sgml b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/doc/mcf5272.sgml new file mode 100644 index 0000000..51c711b --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/doc/mcf5272.sgml @@ -0,0 +1,226 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- mcf5272.sgml --> +<!-- --> +<!-- mcf5272 processor HAL documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2003, 2008 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): bartv --> +<!-- Contact(s): bartv --> +<!-- Date: 2003/07/15 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-m68k-mcf5272"><title>Freescale MCF5272 Processor Support</title> + +<refentry id="m68k-mcf5272"> + <refmeta> + <refentrytitle>The MCF5272 ColdFire Processor</refentrytitle> + </refmeta> + <refnamediv> + <refname><varname>CYGPKG_HAL_M68K_MCF5272</varname></refname> + <refpurpose>eCos Support for the Freescale MCF5272 Processor</refpurpose> + </refnamediv> + + <refsect1 id="m68k-mcf5272-description"><title>Description</title> + <para> +The MCF5272 is one member of the Freescale MCFxxxx ColdFire range of +processors. It comes with a number of on-chip peripherals including 2 +UARTs, ethernet, and USB slave. The processor HAL package +<varname>CYGPKG_HAL_M68K_MCF5272</varname> provides support for +features that are specific to the MCF5272. It complements the M68K +architectural HAL package <varname>CYGPKG_HAL_M68K</varname> and the +variant HAL package <varname>CYGPKG_HAL_M68K_MCFxxxx</varname>. An +eCos configuration should also include a platform HAL package, for +example <varname>CYGPKG_HAL_M68K_M5272C3</varname> to support +board-level details like the external memory chips. + </para> + </refsect1> + + <refsect1 id="m68k-mcf5272-config"><title>Configuration</title> + <para> +The MCF5272 processor HAL package should be loaded automatically when +eCos is configured for appropriate target hardware. It should never be +necessary to load this package explicitly. Unloading the package +should only happen as a side effect of switching target hardware. + </para> + <para> +The component <varname>CYGPKG_HAL_M68K_MCF5272_HARDWARE</varname> +contains configuration options for the available hardware. This +includes all GPIO pin settings, with defaults provided by the +platform HAL. In turn the pin settings are used to determine defaults +for other hardware settings, for example which of the two on-chip +uarts are usable. Users can override these settings if necessary, +subject to any constraints imposed by the platform HAL, but care has +to be taken that the resulting configuration still matches the actual +hardware. + </para> + <para> +The option <varname>CYGIMP_HAL_M68K_MCF5272_IDLE</varname> controls +what happens in configurations containing the eCos kernel when the +idle thread runs, i.e. when there is nothing for the processor to do +until the next interrupt comes in. Usually the processor made to +sleep, halting the cpu but leaving all peripherals active. + </para> + <para> +The package contains a single configuration option +<varname>CYGFUN_HAL_M68K_MCF5272_PROFILE_TIMER</varname>. This +controls the support for gprof-based profiling. By default it is +active and enabled if the configuration contains the gprof profiling +package, otherwise inactive. The relevant code uses hardware timer 2, +so that timer is no longer available for application code. If the +timer is required but a platform HAL provides an alternative +implementation of the profiling support then this option can be +disabled. + </para> + </refsect1> + + <refsect1 id="m68k-mcf5272-port"><title>The HAL Port</title> + <para> +This section describes how the MCF5272 processor HAL package +implements parts of the eCos HAL specification. It should be read in +conjunction with similar sections from the architectural and variant +HAL documentation. + </para> + + <refsect2 id="m68k-mcf5272-port-io"><title>HAL I/O</title> + <para> +The header +file <filename class="headerfile">cyg/hal/proc_io.h</filename> +specifies which generic MCFxxxx devices are present, and provides +details of MCF5272-specific devices. This header file is automatically +included by the architectural +header <filename class="headerfile">cyg/hal/hal_io.h</filename>, so +typically application code and other packages will just include the +latter. + </para> + <para> +It should be noted that the Freescale documentation is occasionally +confusing when it comes to numbering devices. For example the four +on-chip timers are numbered TMR0 to TMR3, but in the interrupt +controller the corresponding interrupts are numbered TMR1 to TMR4. The +eCos port consistently starts numbering at 0, so these interrupts have +been renamed TMR0 to TMR3. + </para> + </refsect2> + + <refsect2 id="m68k-mcf5272-port-interrupts"><title>Interrupt Handling</title> + <para> +The header file <filename +class="headerfile">cyg/hal/proc_intr.h</filename> provides VSR and ISR +vector numbers for all interrupt sources. The VSR vector number, for +example <varname>CYGNUM_HAL_VECTOR_TMR0</varname>, should be used +for calls like <function>cyg_interrupt_get_vsr</function>. It +corresponds directly to the M68K exception number. The ISR vector +number, for example <varname>CYGNUM_HAL_ISR_TMR0</varname>, should be +used for calls like <function>cyg_interrupt_create</function>. This +header file is automatically included by the architectural header +<filename class="headerfile">cyg/hal/hal_intr.h</filename>, and other +packages and application code will normally just include the latter. + </para> + <para> +The eCos HAL macros <function>HAL_INTERRUPT_MASK</function>, +<function>HAL_INTERRUPT_UNMASK</function>, +<function>HAL_INTERRUPT_SET_LEVEL</function>, +<function>HAL_INTERRUPT_ACKNOWLEDGE</function>, and +<function>HAL_INTERRUPT_CONFIGURE</function> are implemented by the +processor HAL. The mask and unmask operations are straightforward, +simply manipulating the on-chip interrupt controller. The acknowledge +and configure macros are only relevant for external interrupts: +internal interrupts generated by on-chip devices do not need to be +acknowledged. The set-level operation, used implicitly by higher level +code such as <function>cyg_interrupt_create</function>, is mapped on +to M68K IPL levels so interrupts can be given a priority between 1 +and 7. Priority 7 corresponds to non-maskable interrupts and must be +used with care: such interrupts cannot be managed safely by the usual +eCos ISR and DSR mechanisms; instead application code will have to +install a custom VSR and manage the entire interrupt. + </para> + </refsect2> + + <refsect2 id="m68k-mcf5272-port-clock"><title>Clock Support</title> + <para> +The processor HAL provides support for the eCos system clock. This +always uses hardware timer 3, which should not be used directly by +application code. If gprof-based profiling is in use then that will +use hardware timer 2. Timers 0 and 1 are never used by eCos so +application code is free to manipulate these as required. + </para> + <para> +Some of the configuration options related to the system clock, for +example <varname>CYGNUM_HAL_RTC_PERIOD</varname>, are actually +contained in the platform HAL rather than the processor HAL. These +options need to take into account the processor clock speed, a +characteristic of the platform rather than the processor. + </para> + </refsect2> + + <refsect2 id="m68k-mcf5272-port-cache"><title>Cache Handling</title> + <para> +The MCF5272 has a small instruction cache of 1024 bytes. This is fully +supported by the processor HAL. There is no data cache. + </para> + </refsect2> + + <refsect2 id="m68k-mcf5272-port-idle"><title>Idle Thread Support</title> + <para> +The configuration +option <varname>CYGIMP_HAL_M68K_MCF5272_IDLE</varname> controls what +happens when the kernel idle thread runs. The default behaviour is to +put the processor to sleep until the next interrupt. + </para> + </refsect2> + + <refsect2 id="m68k-mcf5272-port-profiling"><title>Profiling Support</title> + <para> +The MCF5272 processor HAL provides a profiling timer for use with the +gprof profiling package. This uses hardware timer 2, so application +code should not manipulate this timer if profiling is enabled. The +M68K architectural HAL implements the <function>mcount</function> +function so profiling is fully supported on all MCF5272-based platforms. + </para> + </refsect2> + + <refsect2 id="m68k-mcf5272-port-other-hal"><title>Other Issues</title> + <para> +The MCF5272 processor HAL does not affect the implementation of data +types, stack size definitions, linker scripts, SMP support, system +startup, or debug support. The architectural HAL's bit index +instructions are used rather than the MCFxxxx variant HAL's versions +since the MCF5272 does not implement the ff1 and bitrev instructions. + </para> + </refsect2> + + <refsect2 id="m68k-mcf5272-port-other"><title>Other Functionality</title> + <para> +The MCF5272 processor HAL only implements functionality defined in the +eCos HAL specification and does not export any additional functions. + </para> + </refsect2> + </refsect1> +</refentry> + +</part> diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc.inc b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc.inc new file mode 100644 index 0000000..f056bfe --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc.inc @@ -0,0 +1,252 @@ +##============================================================================= +## +## proc.inc +## +## mcf5272 processor +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): bartv +## Date: 2003-06-04 +######DESCRIPTIONEND#### +##============================================================================= + +#include <pkgconf/hal_m68k_mcf5272.h> + +// Vectors support. +// The 5272's interrupt vectors go up to slot 96: the standard 64 plus another +// 32 for the on-chip peripherals. +#define HAL_M68K_VSR_COUNT 96 + +// The chip has 4K on-chip RAM so enable the relevant init code in vectors.S +#define _HAL_M68K_INITIALIZE_IRAM_ 1 + +// Fixed vectors data. The cacr cache control register is write-only so +// a shadow copy is needed. This has to be shared between RedBoot and the +// application, otherwise confusing things can happen when both manipulate +// the cache e.g. during debugging. Shadow copies are also needed to +// implement interrupt priorities. Some space is allocated for future +// expansion. + .macro _hal_mcf5272_ram_vectors_ + .global hal_mcf5272_cacr +hal_mcf5272_cacr: + .long 0 + .global hal_mcf5272_icr_pri_mirror +hal_mcf5272_icr_pri_mirror: + .long 0, 0, 0, 0 + .rept 11 + .long 0 + .endr + .endm + +#define _HAL_M68K_PROCESSOR_RAM_VECTORS_ _hal_mcf5272_ram_vectors_ + +// ---------------------------------------------------------------------------- +// Utility macros for initialization. It is assumed that the platform HAL +// has provided the magic numbers. + +// Remap. Typically on an MCF5272 board flash memory starts of at location +// 0, everything else is still disabled. The flash needs to be moved to +// its final location, usually in high memory, while we are still running +// out of flash. The way to do this is to set the mask in the cs option +// register to 0, causing the flash to be mirrored throughout the address +// space, then branch to the actual flash location, and then the rest of +// the memory map can be sorted out. To access CSOR0, first we need to map +// the MBAR into memory. MBAR has priority over chip selects so it will +// remain visible even if the flash is mirrored. + + .macro _hal_mcf5272_remap_flash_ + move.l # _HAL_MCF5272_MBAR_VALUE_, %d0 + movec.l %d0, %mbar + move.l # HAL_MCFxxxx_MBAR, %a5 + move.l # (_HAL_MCF5272_CSOR0_VALUE_ & ~HAL_MCF5272_CSOR_BA_MASK), %d0 + move.l %d0, HAL_MCF5272_CSOR0 (%a5) + + // dBUG inserts a nop here and another in the branch location. + // Presumably this avoids pipeline problems if the memory map + // changes under the pipeline's feet. + nop + + // Now we can branch to the real location in the flash. The linker + // script is set up so that this code is mapped to the right place. + jmp _hal_mcf5272_flash_ + + // Put the next code in a separate section to stop the assembler turning + // the above jump into a PC-relative one + .section ".m68k_start.0", "ax" + +_hal_mcf5272_flash_: + // Another nop as per dBUG + nop + // We are now running out of flash. CSOR0 and MBAR have been changed, + // everything else is still at reset values. + .endm + +// Initialize all the system registers. Typically this is done unconditionally +// on the off-chance that RedBoot and the application need different values. + .macro _hal_mcf5272_init_sysregs_ + move.l # (HAL_MCFxxxx_CACR_CINV), %d0 + movec.l %d0, %cacr + move.l # (CYGNUM_HAL_M68K_MCF5272_ACR0), %d0 + movec.l %d0, %acr0 + move.l # (CYGNUM_HAL_M68K_MCF5272_ACR1), %d0 + movec.l %d0, %acr1 + move.l # (CYGNUM_HAL_M68K_MCF5272_ROMBAR), %d0 + movec.l %d0, %rombar + move.l # (CYGNUM_HAL_M68K_MCF5272_RAMBAR), %d0 + movec.l %d0, %rambar0 + move.l # (CYGNUM_HAL_M68K_MCF5272_CACR), %d0 + movec.l %d0, %cacr + .endm + +// Initialize memory, including starting the SDRAM controller + .macro _hal_mcf5272_init_memory_ + move.w # CYGNUM_HAL_M68K_MCF5272_SCR, %d0 + move.w %d0, HAL_MCF5272_SCR (%a5) + move.w # 0xFFFF, %d0 + move.w %d0, HAL_MCF5272_SPR (%a5) + + // chip selects and SDRAM. CS0 should always be connected to + // a boot flash. The BW bits are set from external pins + // QSPI_CS0/CSPI_CLK and are preserved here. Arguably that + // should not be necessary but it allows for platforms where + // the hardware has gone through several revisions and it + // is undesirable to build different images for different + // revisions. The overhead is small, just two instructions. + move.l HAL_MCF5272_CSBR0 (%a5), %d0 + andi.l # HAL_MCF5272_CSBR_BW_MASK, %d0 + ori.l # (_HAL_MCF5272_CSBR0_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSBR0 (%a5) + move.l # (_HAL_MCF5272_CSOR0_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSOR0 (%a5) + + // Chip selects 1-6 may or may not be connected. If not just leave + // them to their default disabled state. + .ifdef _HAL_MCF5272_CSBR1_VALUE_ + move.l # (_HAL_MCF5272_CSBR1_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSBR1 (%a5) + move.l # (_HAL_MCF5272_CSOR1_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSOR1 (%a5) + .endif + .ifdef _HAL_MCF5272_CSBR2_VALUE_ + move.l # (_HAL_MCF5272_CSBR2_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSBR2 (%a5) + move.l # (_HAL_MCF5272_CSOR2_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSOR2 (%a5) + .endif + .ifdef _HAL_MCF5272_CSBR3_VALUE_ + move.l # (_HAL_MCF5272_CSBR3_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSBR3 (%a5) + move.l # (_HAL_MCF5272_CSOR3_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSOR3 (%a5) + .endif + .ifdef _HAL_MCF5272_CSBR4_VALUE_ + move.l # (_HAL_MCF5272_CSBR4_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSBR4 (%a5) + move.l # (_HAL_MCF5272_CSOR4_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSOR4 (%a5) + .endif + .ifdef _HAL_MCF5272_CSBR5_VALUE_ + move.l # (_HAL_MCF5272_CSBR5_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSBR5 (%a5) + move.l # (_HAL_MCF5272_CSOR5_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSOR5 (%a5) + .endif + .ifdef _HAL_MCF5272_CSBR6_VALUE_ + move.l # (_HAL_MCF5272_CSBR6_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSBR6 (%a5) + move.l # (_HAL_MCF5272_CSOR6_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSOR6 (%a5) + .endif + + // CS7 will go the SDRAM. + move.l # (_HAL_MCF5272_CSBR7_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSBR7 (%a5) + move.l # (_HAL_MCF5272_CSOR7_VALUE_), %d0 + move.l %d0, HAL_MCF5272_CSOR7 (%a5) + + // The SDRAM should now be ready for its first commands. + // The timer register needs to be done first, then the + // control register, and finally a dummy write to memory. + // That dummy write causes the SDRAM controller to take + // the necessary actions, and the memory should be usable + // a few cycles later. + move.l # (_HAL_MCF5272_SDTR_VALUE_), %d0 + move.l %d0, HAL_MCF5272_SDTR (%a5) + move.l # (_HAL_MCF5272_SDCR_VALUE_), %d0 + move.l %d0, HAL_MCF5272_SDCR (%a5) + clr.l 0 + .endm + +// ---------------------------------------------------------------------------- +// Now that the utility macros are defined include the platform HAL. +#include <cyg/hal/plf.inc> + +// And if the platform HAL requests it, provide the standard initialization +// code. +#if defined(_HAL_MCF5272_STANDARD_INIT_ROM_) + .macro _hal_m68k_mcf5272_start_ + // Initial stack and program counter + .long 0 + .long 8 + _hal_mcf5272_remap_flash_ + .endm + + .macro _hal_m68k_mcf5272_setup1_ + _hal_mcf5272_init_sysregs_ + _hal_mcf5272_init_memory_ + .endm + +# define _HAL_M68K_START_ _hal_m68k_mcf5272_start_ +# define _HAL_M68K_PLATFORM_SETUP1_ _hal_m68k_mcf5272_setup1_ +# define _HAL_M68K_COPY_ROM_DATA_TO_RAM_ 1 + +#elif defined(_HAL_MCF5272_STANDARD_INIT_RAM_) + .macro _hal_m68k_mcf5272_start_ + .endm + + .macro _hal_m68k_mcf5272_setup1_ + // Always initialize the remaining system registers, in case the + // application needs different values from RedBoot for some reason. + _hal_mcf5272_init_sysregs_ + .endm + +# define _HAL_M68K_START_ _hal_m68k_mcf5272_start_ +# define _HAL_M68K_PLATFORM_SETUP1_ _hal_m68k_mcf5272_setup1_ +#endif + +// ---------------------------------------------------------------------------- +// end of proc.inc diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_arch.h b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_arch.h new file mode 100644 index 0000000..a29f687 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_arch.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_PROC_ARCH_H +#define CYGONCE_HAL_PROC_ARCH_H +//============================================================================= +// +// proc_arch.h +// +// Processor variant specific abstractions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal_m68k_mcf5272.h> +#include <cyg/hal/plf_arch.h> +#include <cyg/infra/cyg_type.h> + +// A processor-specific initialization routine is needed +#if !defined(__ASSEMBLER__) && !defined(HAL_M68K_PROC_INIT) +externC void hal_m68k_mcf5272_init(void); +#define HAL_M68K_PROC_INIT() hal_m68k_mcf5272_init() +#endif + +// The MCF5272 does not support the bitrev or ff1 instructions so the +// architectural default versions of HAL_LSBIT_INDEX() and +// HAL_MSBIT_INDEX() have to be used instead of the mcfxxxx ones. +#define _HAL_M68K_MCFxxxx_NO_FF1_ 1 + +// Idle action support. +#if !defined(HAL_IDLE_THREAD_ACTION) +# if defined(CYGIMP_HAL_M68K_MCF5272_IDLE_run) + // Do nothing, just use the architectural empty default +# else + +# define HAL_IDLE_THREAD_ACTION(_count_) \ + CYG_MACRO_START \ + asm volatile ( \ + "mov.w %%sr, %%d0 ; \n" \ + "mov.w %%d0, 0(%[alpr]); \n" \ + "stop #0x2000 ; \n" \ + "mov.w %%d0, %%sr ; \n" \ + : \ + : [alpr] "a" (HAL_MCFxxxx_MBAR + HAL_MCF5272_ALPR) \ + : "d0" ); \ + CYG_MACRO_END + +# endif +#endif + +// ---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PROC_ARCH_H + diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_cache.h b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_cache.h new file mode 100644 index 0000000..694777c --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_cache.h @@ -0,0 +1,102 @@ +#ifndef CYGONCE_PROC_CACHE_H +#define CYGONCE_PROC_CACHE_H +//============================================================================= +// +// proc_cache.h +// +// Cache details for an mcf5272 +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/var_io.h> + +// An mcf5272 has a 1k direct-mapped instruction cache, 64 lines * 16 bytes. +// There is no data cache. The cache control register is write-only so it +// is necessary to keep a soft copy. + +externC cyg_uint32 hal_mcf5272_cacr; + +#define HAL_ICACHE_SIZE 1024 +#define HAL_ICACHE_LINE_SIZE 16 +#define HAL_ICACHE_WAYS 64 +#define HAL_ICACHE_SETS 1 + +#define HAL_ICACHE_ENABLE() \ + CYG_MACRO_START \ + hal_mcf5272_cacr = (hal_mcf5272_cacr & ~HAL_MCFxxxx_CACR_CINV) | HAL_MCFxxxx_CACR_CENB; \ + asm volatile ( "movec.l %0,%%cacr\n" : : "d" (hal_mcf5272_cacr) : "memory") ; \ + CYG_MACRO_END + +#define HAL_ICACHE_DISABLE() \ + CYG_MACRO_START \ + hal_mcf5272_cacr &= ~(HAL_MCFxxxx_CACR_CENB | HAL_MCFxxxx_CACR_CINV); \ + asm volatile ( "movec.l %0,%%cacr\n" : : "d" (hal_mcf5272_cacr) : "memory") ; \ + CYG_MACRO_END + +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + _state_ = (0 != (hal_mcf5272_cacr & HAL_MCFxxxx_CACR_CENB)); \ + CYG_MACRO_END + +// A full cache invalidate takes 64 cycles. This is expensive if only one +// or two lines need to be invalidated, but doing the arithmetic and tests +// needed to affect just the necessary lines would also take quite a few +// cycles. Hence it is simpler to just invalidate the lot. +#define HAL_ICACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + asm volatile ( "movec.l %0,%%cacr\n" : : "d" (hal_mcf5272_cacr | HAL_MCFxxxx_CACR_CINV) : "memory" ); \ + CYG_MACRO_END + +#define HAL_ICACHE_INVALIDATE(_base_, _size_) \ + CYG_MACRO_START \ + HAL_ICACHE_INVALIDATE_ALL(); \ + CYG_MACRO_END + +#define HAL_ICACHE_SYNC() \ + CYG_MACRO_START \ + HAL_ICACHE_INVALIDATE_ALL(); \ + CYG_MACRO_END + +#endif // ifndef CYGONCE_PROC_CACHE_H +// End of proc_cache.h + diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_intr.h b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_intr.h new file mode 100644 index 0000000..58b821d --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_intr.h @@ -0,0 +1,307 @@ +#ifndef CYGONCE_HAL_PROC_INTR_H +#define CYGONCE_HAL_PROC_INTR_H + +//========================================================================== +// +// proc_intr.h +// +// mcf5272 Processor variant interrupt and clock support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/plf_intr.h> + +//--------------------------------------------------------------------------- +// Interrupt controller management +// +// There are 32 interrupt sources, all vectored using VSR's 64 onwards. +// The ISR vector numbers are 0 to 31. + +#define HAL_MCF5272_INT_VEC_BASE 64 + +// Vector numbers defined by the interrupt controller. +#define CYGNUM_HAL_VECTOR_USR_SPUR_INT ( 0 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT1 ( 1 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT2 ( 2 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT3 ( 3 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT4 ( 4 + HAL_MCF5272_INT_VEC_BASE) +// The User's Manual uses TMR1 to TMR4 for the interrupt numbers, which +// is inconsistent with the chapter on the timers themselves. TMR0-TMR3 +// are used here instead. +#define CYGNUM_HAL_VECTOR_TMR0 ( 5 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_TMR1 ( 6 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_TMR2 ( 7 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_TMR3 ( 8 + HAL_MCF5272_INT_VEC_BASE) +// The User's Manual uses UART1 and UART2 when describing the interrupt +// controller. UART0 and UART1 are used instead here, for consistency +// with other parts of the code and documentation. +#define CYGNUM_HAL_VECTOR_UART0 ( 9 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_UART1 (10 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_PLIP (11 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_PLIA (12 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB0 (13 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB1 (14 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB2 (15 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB3 (16 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB4 (17 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB5 (18 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB6 (19 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB7 (20 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_DMA (21 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_ERX (22 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_ETX (23 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_ENTC (24 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_QSPI (25 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT5 (26 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT6 (27 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_SWTO (28 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_RES1 (29 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_RES2 (30 + HAL_MCF5272_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_RES3 (31 + HAL_MCF5272_INT_VEC_BASE) + +// ISR numbering starts with 0 corresponding to VSR 64, even though +// that interrupt won't actually be raised. This costs some memory and +// adds a bit of complexity to the mask/unmask macros, but saves an +// instruction during ISR decoding. +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_USR_SPUR_INT 0 +#define CYGNUM_HAL_ISR_EXTINT1 1 +#define CYGNUM_HAL_ISR_EXTINT2 2 +#define CYGNUM_HAL_ISR_EXTINT3 3 +#define CYGNUM_HAL_ISR_EXTINT4 4 +#define CYGNUM_HAL_ISR_TMR0 5 +#define CYGNUM_HAL_ISR_TMR1 6 +#define CYGNUM_HAL_ISR_TMR2 7 +#define CYGNUM_HAL_ISR_TMR3 8 +#define CYGNUM_HAL_ISR_UART0 9 +#define CYGNUM_HAL_ISR_UART1 10 +#define CYGNUM_HAL_ISR_PLIP 11 +#define CYGNUM_HAL_ISR_PLIA 12 +#define CYGNUM_HAL_ISR_USB0 13 +#define CYGNUM_HAL_ISR_USB1 14 +#define CYGNUM_HAL_ISR_USB2 15 +#define CYGNUM_HAL_ISR_USB3 16 +#define CYGNUM_HAL_ISR_USB4 17 +#define CYGNUM_HAL_ISR_USB5 18 +#define CYGNUM_HAL_ISR_USB6 19 +#define CYGNUM_HAL_ISR_USB7 20 +#define CYGNUM_HAL_ISR_DMA 21 +#define CYGNUM_HAL_ISR_ERX 22 +#define CYGNUM_HAL_ISR_ETX 23 +#define CYGNUM_HAL_ISR_ENTC 24 +#define CYGNUM_HAL_ISR_QSPI 25 +#define CYGNUM_HAL_ISR_EXTINT5 26 +#define CYGNUM_HAL_ISR_EXTINT6 27 +#define CYGNUM_HAL_ISR_SWTO 28 +#define CYGNUM_HAL_ISR_RES1 29 +#define CYGNUM_HAL_ISR_RES2 30 +#define CYGNUM_HAL_ISR_RES3 31 + +#define CYGNUM_HAL_ISR_MAX 28 +#define CYGNUM_HAL_ISR_COUNT 29 + +//--------------------------------------------------------------------------- +// Interrupt controller macros. + +// Declare a mirror copy of the interrupt control registers used to +// set interrupt priorities. In order to mask and unmask a specific +// interrupt, we must be able to set its priority to zero and then +// restore it to ist original priority. We use these locations to +// determine the level to restore the interrupt to in the unmask +// macro. + +externC cyg_uint32 hal_mcf5272_icr_pri_mirror[4]; + +// Some of the operations should only be applied to external interrupts. +#define HAL_MCF5272_EXTERNAL_INTERRUPTS \ + ((0x01 << CYGNUM_HAL_ISR_EXTINT1) | (0x01 << CYGNUM_HAL_ISR_EXTINT2) | \ + (0x01 << CYGNUM_HAL_ISR_EXTINT3) | (0x01 << CYGNUM_HAL_ISR_EXTINT4) | \ + (0x01 << CYGNUM_HAL_ISR_EXTINT5) | (0x01 << CYGNUM_HAL_ISR_EXTINT6)) + +// Block an interrupt source. This involves setting the ISR vector's +// interrupt priority level to 0. The PI bit should be set to 1 for +// just the interrupt of interest, and the rest of the word written +// to the ICR register should be 0. + +#define HAL_INTERRUPT_MASK( _vector_ ) \ + CYG_MACRO_START \ + cyg_uint32 offset = ((_vector_) - 1) / 8; \ + cyg_uint32 shift = (((_vector_) - 1) % 8) * 4; \ + cyg_uint32 mask = 0x80000000; \ + mask >>= shift; \ + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_ICR1 + (offset << 2), mask); \ + CYG_MACRO_END + +// Unblock an interrupt source. This involves restoring the ISR vector's +// interrupt priority level using the saved mirrors. The PI bit should be +// set to 1 for just the interrupt of interest, so the rest of the write +// will be ignored. + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ + CYG_MACRO_START \ + cyg_uint32 offset = ((_vector_) - 1) / 8; \ + cyg_uint32 shift = (((_vector_) - 1) % 8) * 4; \ + cyg_uint32 mask = 0x80000000; \ + mask >>= shift; \ + mask |= hal_mcf5272_icr_pri_mirror[offset]; \ + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_ICR1 + (offset << 2), mask); \ + CYG_MACRO_END + +// Set the priority in the interrupt control register and the icr +// mirror. +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _prilevel_) \ + CYG_MACRO_START \ + CYG_INTERRUPT_STATE ints_enabled; \ + cyg_uint32 offset = ((_vector_) - 1) / 8; \ + cyg_uint32 shift = (((_vector_) - 1) % 8) * 4; \ + cyg_uint32 mask = 0xF0000000; \ + cyg_uint32 new_level = (_prilevel_) & 0x07; \ + mask >>= shift; \ + new_level <<= (28 - shift); \ + HAL_DISABLE_INTERRUPTS(ints_enabled); \ + hal_mcf5272_icr_pri_mirror[offset] &= ~mask; \ + hal_mcf5272_icr_pri_mirror[offset] |= new_level; \ + mask &= 0x88888888; \ + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_ICR1 + (offset << 2), mask | new_level); \ + HAL_RESTORE_INTERRUPTS(ints_enabled); \ + CYG_MACRO_END + +// Acknowledge is only relevant for external interrupts. It is necessary to +// write a 1 to the PI bit, which will unfortunately also reset this +// interrupt vector's priority level. +#define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \ + CYG_MACRO_START \ + if (0 != (HAL_MCF5272_EXTERNAL_INTERRUPTS & (0x01 << (_vector_)))) { \ + cyg_uint32 offset = ((_vector_) - 1) / 8; \ + cyg_uint32 shift = (((_vector_ - 1)) % 8) * 4; \ + cyg_uint32 mask = 0x80000000; \ + mask >>= shift; \ + mask |= hal_mcf5272_icr_pri_mirror[offset]; \ + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_ICR1 + (offset << 2), mask); \ + } \ + CYG_MACRO_END + +// Select between level and edge triggered. This is only relevant for the external +// interrupt sources. The interrupts remain level-triggered, but it is possible +// to choose between rising and falling interrupts. +// +// NOTE: the manual states 0 for low->high, 1 for high->low. The original code +// inverted this, claiming the manual is wrong. I have stuck with the original +// code's usage, but have not tested this. + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _leveltriggered_, _up_) \ + CYG_MACRO_START \ + if (0 != (HAL_MCF5272_EXTERNAL_INTERRUPTS & (0x01 << (_vector_)))) { \ + cyg_uint32 mask = 0x80000000 >> ((_vector_) - 1); \ + cyg_uint32 pitr; \ + HAL_READ_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PITR, pitr); \ + if (_up_) { \ + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PITR, pitr | mask); \ + } else { \ + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PITR, pitr & ~mask); \ + } \ + } \ + CYG_MACRO_END + +// ---------------------------------------------------------------------------- +// The clock. Timer 3 is used for the eCos system clock. Timers 0 and +// 1 offer additional functionality which is not required by eCos, so +// those are best left to application code. Timer 2 is used as the +// profiling timer, if desired. The prescaler is set to the clock's +// MHz rating provided by the platform HAL, so each tick is one +// microsecond. + +#define CYGNUM_HAL_INTERRUPT_RTC (CYGNUM_HAL_ISR_TMR3) + +#define HAL_CLOCK_INITIALIZE(_period_) \ + CYG_MACRO_START \ + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TMR, 0); \ + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TRR, \ + (_period_) - 1); \ + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TCN, 0); \ + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TER, \ + HAL_MCF5272_TIMER_TER_REF | HAL_MCF5272_TIMER_TER_CAP); \ + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TMR, \ + ((CYGHWR_HAL_SYSTEM_CLOCK_MHZ - 1) << HAL_MCF5272_TIMER_TMR_PS_SHIFT) | \ + HAL_MCF5272_TIMER_TMR_ORI | HAL_MCF5272_TIMER_TMR_FRR | \ + HAL_MCF5272_TIMER_TMR_CLK_MASTER | HAL_MCF5272_TIMER_TMR_RST); \ + CYG_MACRO_END + +// The timer itself runs in restart mode, but it is still necessary to +// reset the bits affecting the interrupt controller. +#define HAL_CLOCK_RESET(_vector_, _period_) \ + CYG_MACRO_START \ + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TER, HAL_MCF5272_TIMER_TER_REF); \ + CYG_MACRO_END + +#define HAL_CLOCK_READ(_pvalue_) \ + CYG_MACRO_START \ + cyg_uint16 _tmp_; \ + HAL_READ_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TCN, _tmp_); \ + *(_pvalue_) = _tmp_; \ + CYG_MACRO_END + +#define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_) + +// ---------------------------------------------------------------------------- +// HAL_DELAY_US(). Just use the default implementation from hal_intr.h +#ifndef _HAL_M68K_DELAY_US_LOOPS_ +# define _HAL_M68K_DELAY_US_LOOPS_ 20 +# define _HAL_M68K_DELAY_US_UNCACHED_ 2 +#endif + +// ---------------------------------------------------------------------------- +// For reset, use the watchdog device. +#ifndef HAL_PLATFORM_RESET +# define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + int _ints_state_; \ + HAL_DISABLE_INTERRUPTS(_ints_state_); \ + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_WRRR, 0x03); \ + for ( ; ; ) ; \ + CYG_MACRO_END +#endif + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PROC_INTR_H diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_io.h b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_io.h new file mode 100644 index 0000000..3ac7b75 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_io.h @@ -0,0 +1,1276 @@ +//============================================================================= +// +// proc_io.h +// +// Details of mcf5272 memory-mapped hardware +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +// This header gets #include'd twice by var_io.h. The first time is to +// define the peripherals which are shared with the 5282. The second +// time is for overriding, in case of small differences between this +// processor's on-chip peripherals and the 5282's. +#if !defined(CYGONCE_HAL_PROC_IO_H_FIRST) +# define CYGONCE_HAL_PROC_IO_H_FIRST + +# include <pkgconf/system.h> +# include <pkgconf/hal_m68k_mcf5272.h> +# include CYGBLD_HAL_PLATFORM_H + +# define HAL_MCFxxxx_HAS_MCF5282_RAMBAR 1 +# define HAL_MCFxxxx_HAS_MCF5282_VBR 1 +# define HAL_MCFxxxx_HAS_MCF5282_CACR_ACR 1 + +# define HAL_MCFxxxx_HAS_MCF5282_UART 2 +# define HAL_MCFxxxx_UART0_BASE (HAL_MCFxxxx_MBAR + 0x00000100) +# define HAL_MCFxxxx_UART1_BASE (HAL_MCFxxxx_MBAR + 0x00000140) +# define HAL_MCFxxxx_UART0_RXFIFO_SIZE 24 +# define HAL_MCFxxxx_UART1_RXFIFO_SIZE 24 +# define HAL_MCFxxxx_HAS_MCF5282_QSPI 1 +# define HAL_MCFxxxx_QSPI0_BASE (HAL_MCFxxxx_MBAR + 0x000000A0) +# define HAL_MCFxxxx_QSPI_SINGLETON_BASE HAL_MCFxxxx_QSPI0_BASE +# define HAL_MCFxxxx_QSPI_SINGLETON_ISRVEC CYGNUM_HAL_ISR_QSPI +# define HAL_MCFxxxx_QSPI_SINGLETON_ISRPRI CYGNUM_HAL_M68K_MCF5272_QSPI_ISRPRI +# define HAL_MCFxxxx_HAS_MCF5282_ETH 1 +# define HAL_MCFxxxx_ETH0_BASE (HAL_MCFxxxx_MBAR + 0x0840) + +// ---------------------------------------------------------------------------- +#elif !defined(CYGONCE_HAL_PROC_IO_H_SECOND) +# define CYGONCE_HAL_PROC_IO_H_SECOND + +// Now to handle the differences between the MCF5272 and the MCF5282 +// MBAR - controls access to the system integration module + +#define HAL_MCF5272_MBAR_BA_MASK 0xFFFF0000 +#define HAL_MCF5272_MBAR_BA_SHIFT 16 +#define HAL_MCF5272_MBAR_SC (0x01 << 4) +#define HAL_MCF5272_MBAR_SD (0x01 << 3) +#define HAL_MCF5272_MBAR_UC (0x01 << 2) +#define HAL_MCF5272_MBAR_UD (0x01 << 1) +#define HAL_MCF5272_MBAR_V (0x01 << 0) + +# undef HAL_MCFxxxx_RAMBAR +# define HAL_MCFxxxx_RAMBAR 0x0C04 +# undef HAL_MCFxxxx_RAMBAR_PRI_MASK +# undef HAL_MCFxxxx_RAMBAR_PRI_SHIFT +# undef HAL_MCFxxxx_RAMBAR_PRI_CPU_CPU +# undef HAL_MCFxxxx_RAMBAR_PRI_CPU_DMA +# undef HAL_MCFxxxx_RAMBAR_PRI_DMA_CPU +# undef HAL_MCFxxxx_RAMBAR_PRI_DMA_DMA +# undef HAL_MCFxxxx_RAMBAR_SPV + +# undef HAL_MCFxxxx_CACR_DISI +# undef HAL_MCFxxxx_CACR_DISD +# undef HAL_MCFxxxx_CACR_INVI +# undef HAL_MCFxxxx_CACR_INVD +# undef HAL_MCFxxxx_CACR_EUSP + +// The UARTs. Five additional registers and some extra bits. +// Baud rates can be set more precisely using the fractional +// register. +# define HAL_MCFxxxx_UARTx_UABU 0x20 +# define HAL_MCFxxxx_UARTx_UABL 0x24 +# define HAL_MCFxxxx_UARTx_UTF 0x28 +# define HAL_MCFxxxx_UARTx_URF 0x2C +# define HAL_MCFxxxx_UARTx_UFPD 0x30 + +#define HAL_MCFxxxx_UARTx_UCR_ENAB (0x01 << 7) + +#define HAL_MCFxxxx_UARTx_UISR_ABC (0x01 << 6) +#define HAL_MCFxxxx_UARTx_UISR_RXFIFO (0x01 << 5) +#define HAL_MCFxxxx_UARTx_UISR_TXFIFO (0x01 << 4) +#define HAL_MCFxxxx_UARTx_UISR_RXFTO (0x01 << 3) + +#define HAL_MCFxxxx_UARTx_UIMR_ABC (0x01 << 6) +#define HAL_MCFxxxx_UARTx_UIMR_RXFIFO (0x01 << 5) +#define HAL_MCFxxxx_UARTx_UIMR_TXFIFO (0x01 << 4) +#define HAL_MCFxxxx_UARTx_UIMR_RXFTO (0x01 << 3) + +// Automatic RTS control depending on fifo levels +#define HAL_MCFxxxx_UARTx_UACR_RTSL_MASK (0x03 << 1) +#define HAL_MCFxxxx_UARTx_UACR_RTSL_DISABLED (0x00 << 1) +#define HAL_MCFxxxx_UARTx_UACR_RTSL_25 (0x01 << 1) +#define HAL_MCFxxxx_UARTx_UACR_RTSL_50 (0x02 << 1) +#define HAL_MCFxxxx_UARTx_UACR_RTSL_75 (0x03 << 1) + +// Fifo control +#define HAL_MCFxxxx_UARTx_UTF_TXS_MASK (0x03 << 6) +#define HAL_MCFxxxx_UARTx_UTF_TXS_INHIBIT (0x00 << 6) +#define HAL_MCFxxxx_UARTx_UTF_TXS_25 (0x01 << 6) +#define HAL_MCFxxxx_UARTx_UTF_TXS_50 (0x02 << 6) +#define HAL_MCFxxxx_UARTx_UTF_TXS_75 (0x03 << 6) +#define HAL_MCFxxxx_UARTx_UTF_FULL (0x01 << 5) +#define HAL_MCFxxxx_UARTx_UTF_TXB_MASK (0x1F << 0) + +#define HAL_MCFxxxx_UARTx_URF_RXS_MASK (0x03 << 6) +#define HAL_MCFxxxx_UARTx_URF_RXS_INHIBIT (0x00 << 6) +#define HAL_MCFxxxx_UARTx_URF_RXS_25 (0x01 << 6) +#define HAL_MCFxxxx_UARTx_URF_RXS_50 (0x02 << 6) +#define HAL_MCFxxxx_UARTx_URF_RXS_75 (0x03 << 6) +#define HAL_MCFxxxx_UARTx_URF_FULL (0x01 << 5) +#define HAL_MCFxxxx_UARTx_URF_RXB_MASK (0x1F << 0) + +#define HAL_MCFxxxx_UARTx_UFPD_FD_MASK (0x0F << 0) + +#undef HAL_MCFxxxx_UARTx_SET_BAUD +#define HAL_MCFxxxx_UARTx_SET_BAUD(_base_, _baud_) \ + CYG_MACRO_START \ + cyg_uint8 _udu_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (32 * (_baud_))) >> 8)); \ + cyg_uint8 _udl_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (32 * (_baud_))) & 0x00FF)); \ + cyg_uint8 _ufpd_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * (_baud_))) & 0x000F)); \ + HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG1, _udu_); \ + HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG2, _udl_); \ + HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UFPD, _ufpd_); \ + CYG_MACRO_END + +// QSPI. It is not clear the QWR CPTQP bits are defined. Otherwise the device +// matches the 5282's exactly. + +// Ethernet. There are many differences between the 5272 and the 5282 +// implementations. +# undef HAL_MCFxxxx_ETHx_ECR +# define HAL_MCFxxxx_ETHx_ECR 0x0000 +# define HAL_MCFxxxx_ETHx_IVSR 0x000C +# undef HAL_MCFxxxx_ETHx_MIBC +# undef HAL_MCFxxxx_ETHx_RCR +# define HAL_MCFxxxx_ETHx_RCR 0x0104 +# define HAL_MCFxxxx_ETHx_MFLR 0x0108 +# undef HAL_MCFxxxx_ETHx_TCR +# define HAL_MCFxxxx_ETHx_TCR 0x0144 +# undef HAL_MCFxxxx_ETHx_PALR +# define HAL_MCFxxxx_ETHx_PALR 0x03C0 +# undef HAL_MCFxxxx_ETHx_PAUR +# define HAL_MCFxxxx_ETHx_PAUR 0x03C4 +# undef HAL_MCFxxxx_ETHx_OPD +# undef HAL_MCFxxxx_ETHx_IAUR +# undef HAL_MCFxxxx_ETHx_IALR +# undef HAL_MCFxxxx_ETHx_GAUR +# define HAL_MCFxxxx_ETHx_GAUR 0x03C8 +# undef HAL_MCFxxxx_ETHx_GALR +# define HAL_MCFxxxx_ETHx_GALR 0x03CC +# define HAL_MCFxxxx_ETHx_TFSR 0x00AC +# undef HAL_MCFxxxx_ETHx_TFWR +# define HAL_MCFxxxx_ETHx_TFWR 0x00A4 +# undef HAL_MCFxxxx_ETHx_FRBR +# define HAL_MCFxxxx_ETHx_FRBR 0x008C +# undef HAL_MCFxxxx_ETHx_FRSR +# define HAL_MCFxxxx_ETHx_FRSR 0x0090 +# undef HAL_MCFxxxx_ETHx_ERDSR +# define HAL_MCFxxxx_ETHx_ERDSR 0x03D0 +# undef HAL_MCFxxxx_ETHx_ETDSR +# define HAL_MCFxxxx_ETHx_ETDSR 0x03D4 +# undef HAL_MCFxxxx_ETHx_EMRBR +# define HAL_MCFxxxx_ETHx_EMRBR 0x03D8 + +# undef HAL_MCFxxxx_ETHx_RMON_T_DROP +# undef HAL_MCFxxxx_ETHx_RMON_T_PACKETS +# undef HAL_MCFxxxx_ETHx_RMON_T_BC_PKT +# undef HAL_MCFxxxx_ETHx_RMON_T_MC_PKT +# undef HAL_MCFxxxx_ETHx_RMON_T_CRC_ALIGN +# undef HAL_MCFxxxx_ETHx_RMON_T_UNDERSIZE +# undef HAL_MCFxxxx_ETHx_RMON_T_OVERSIZE +# undef HAL_MCFxxxx_ETHx_RMON_T_FRAG +# undef HAL_MCFxxxx_ETHx_RMON_T_JAB +# undef HAL_MCFxxxx_ETHx_RMON_T_COL +# undef HAL_MCFxxxx_ETHx_RMON_T_P64 +# undef HAL_MCFxxxx_ETHx_RMON_T_P65TO127 +# undef HAL_MCFxxxx_ETHx_RMON_T_P128TO255 +# undef HAL_MCFxxxx_ETHx_RMON_T_P256TO511 +# undef HAL_MCFxxxx_ETHx_RMON_T_P512TO1023 +# undef HAL_MCFxxxx_ETHx_RMON_T_P1024TO2047 +# undef HAL_MCFxxxx_ETHx_RMON_T_PGTE2048 +# undef HAL_MCFxxxx_ETHx_RMON_T_OCTETS +# undef HAL_MCFxxxx_ETHx_IEEE_T_DROP +# undef HAL_MCFxxxx_ETHx_IEEE_T_FRAME_OK +# undef HAL_MCFxxxx_ETHx_IEEE_T_1COL +# undef HAL_MCFxxxx_ETHx_IEEE_T_MCOL +# undef HAL_MCFxxxx_ETHx_IEEE_T_DEF +# undef HAL_MCFxxxx_ETHx_IEEE_T_LCOL +# undef HAL_MCFxxxx_ETHx_IEEE_T_EXCOL +# undef HAL_MCFxxxx_ETHx_IEEE_T_MACERR +# undef HAL_MCFxxxx_ETHx_IEEE_T_CSERR +# undef HAL_MCFxxxx_ETHx_IEEE_T_SQE +# undef HAL_MCFxxxx_ETHx_IEEE_T_FDXFC +# undef HAL_MCFxxxx_ETHx_IEEE_T_OCTETS_OK +# undef HAL_MCFxxxx_ETHx_RMON_R_PACKETS +# undef HAL_MCFxxxx_ETHx_RMON_R_BC_PKT +# undef HAL_MCFxxxx_ETHx_RMON_R_MC_PKT +# undef HAL_MCFxxxx_ETHx_RMON_R_CRC_ALIGN +# undef HAL_MCFxxxx_ETHx_RMON_R_UNDERSIZE +# undef HAL_MCFxxxx_ETHx_RMON_R_OVERSIZE +# undef HAL_MCFxxxx_ETHx_RMON_R_FRAG +# undef HAL_MCFxxxx_ETHx_RMON_R_JAB +# undef HAL_MCFxxxx_ETHx_RMON_R_RESVD_0 +# undef HAL_MCFxxxx_ETHx_RMON_R_P64 +# undef HAL_MCFxxxx_ETHx_RMON_R_P65TO127 +# undef HAL_MCFxxxx_ETHx_RMON_R_P128TO255 +# undef HAL_MCFxxxx_ETHx_RMON_R_P256TO511 +# undef HAL_MCFxxxx_ETHx_RMON_R_P512TO1023 +# undef HAL_MCFxxxx_ETHx_RMON_R_P1024TO2047 +# undef HAL_MCFxxxx_ETHx_RMON_R_GTE2048 +# undef HAL_MCFxxxx_ETHx_RMON_R_OCTETS +# undef HAL_MCFxxxx_ETHx_IEEE_R_DROP +# undef HAL_MCFxxxx_ETHx_IEEE_R_FRAME_OK +# undef HAL_MCFxxxx_ETHx_IEEE_R_CRC +# undef HAL_MCFxxxx_ETHx_IEEE_R_ALIGN +# undef HAL_MCFxxxx_ETHx_IEEE_R_MACERR +# undef HAL_MCFxxxx_ETHx_IEEE_R_FDXFC +# undef HAL_MCFxxxx_ETHx_IEEE_R_OCTETS_OK + +# undef HAL_MCFxxxx_ETHx_EIR_LC +# undef HAL_MCFxxxx_ETHx_EIR_RL +# undef HAL_MCFxxxx_ETHx_EIR_UN +# define HAL_MCFxxxx_ETHx_EIR_UMINT (0x01 << 21) + +# undef HAL_MCFxxxx_ETHx_EIMR_LC +# undef HAL_MCFxxxx_ETHx_EIMR_RL +# undef HAL_MCFxxxx_ETHx_EIMR_UN + +# undef HAL_MCFxxxx_ETHx_MIBC_MIB_DISABLE +# undef HAL_MCFxxxx_ETHx_MIBC_MIB_IDLE + +# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_MASK +# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_SHIFT +# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_VALUE +# undef HAL_MCFxxxx_ETHx_RCR_FCE +# undef HAL_MCFxxxx_ETHx_RCR_BC_REJ + +# undef HAL_MCFxxxx_ETHx_TCR_RFC_PAUSE +# undef HAL_MCFxxxx_ETHx_TCR_TFC_PAUSE + +# undef HAL_MCFxxxx_ETHx_OPD_OPCODE_MASK +# undef HAL_MCFxxxx_ETHx_OPD_OPCODE_SHIFT +# undef HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_MASK +# undef HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_SHIFT + +# define HAL_MCFxxxx_ETHx_RXBD_SH (0x01 << 3) + +# undef HAL_MCFxxxx_ETHx_TXBD_ABC +# define HAL_MCFxxxx_ETHx_TXBD_DEF (0x01 << 9) +# define HAL_MCFxxxx_ETHx_TXBD_HB (0x01 << 8) +# define HAL_MCFxxxx_ETHx_TXBD_LC (0x01 << 7) +# define HAL_MCFxxxx_ETHx_TXBD_RL (0x01 << 6) +# define HAL_MCFxxxx_ETHx_TXBD_RC_MASK (0x0F << 2) +# define HAL_MCFxxxx_ETHx_TXBD_RC_SHIFT 2 +# define HAL_MCFxxxx_ETHx_TXBD_UN (0x01 << 1) +# define HAL_MCFxxxx_ETHx_TXBD_CSL (0x01 << 0) + +// ---------------------------------------------------------------------------- +// ---------------------------------------------------------------------------- +// Next the units specific to the 5272 + +// The ROM base address register. The ROM size depends on the particular +// processor, and that controls how many of bits 9 to 31 are significant. +#define HAL_MCF5272_ROMBAR_WP (0x01 << 8) +// Mask cpu space and interrupt acknowledge accesses +#define HAL_MCF5272_ROMBAR_AS5 (0x01 << 5) +// Mask supervisor code accesses +#define HAL_MCF5272_ROMBAR_AS4 (0x01 << 4) +// Mask supervisor data accesses +#define HAL_MCF5272_ROMBAR_AS3 (0x01 << 3) +// Mask user code accesses +#define HAL_MCF5272_ROMBAR_AS2 (0x01 << 2) +// Mask user data accesses +#define HAL_MCF5272_ROMBAR_AS1 (0x01 << 1) +// Has the ROMBAR register been initialized yet? +#define HAL_MCF5272_ROMBAR_VALID (0x01 << 0) + +// ---------------------------------------------------------------------------- +// System registers in the system integration module. PMR and DIR are +// 32-bit. SCR, SPR, and ALPR are 16-bit. + +#define HAL_MCF5272_SCR 0x0004 +#define HAL_MCF5272_SPR 0x0006 +#define HAL_MCF5272_PMR 0x0008 +#define HAL_MCF5272_ALPR 0x000E +#define HAL_MCF5272_DIR 0x0010 + +// System configuration register +#define HAL_MCF5272_SCR_RSTSRC_MASK (0x03 << 12) +#define HAL_MCF5272_SCR_RSTSRC_RSTI (0x01 << 12) +#define HAL_MCF5272_SCR_RSTSRC_WATCHDOG (0x02 << 12) +#define HAL_MCF5272_SCR_RSTSRC_RSTI_DRESETEN (0x03 << 12) +#define HAL_MCF5272_SCR_PRIORITY_MASK (0x01 << 8) +#define HAL_MCF5272_SCR_PRIORITY_ETHERNET (0x00 << 8) +#define HAL_MCF5272_SCR_PRIORITY_CPU (0x01 << 8) +#define HAL_MCF5272_SCR_AR_MASK (0x01 << 7) +#define HAL_MCF5272_SCR_AR_RELINQUISH (0x00 << 7) +#define HAL_MCF5272_SCR_AR_INCLUDE (0x01 << 7) +#define HAL_MCF5272_SCR_AR_SOFTRST (0x01 << 6) +#define HAL_MCF5272_SCR_BUSLOCK_MASK (0x01 << 3) +#define HAL_MCF5272_SCR_BUSLOCK_ARBITRATION (0x00 << 3) +#define HAL_MCF5272_SCR_BUSLOCK_RETAIN (0x01 << 3) +#define HAL_MCF5272_SCR_HWR_MASK (0x07 << 0) +#define HAL_MCF5272_SCR_HWR_128 (0x00 << 0) +#define HAL_MCF5272_SCR_HWR_256 (0x01 << 0) +#define HAL_MCF5272_SCR_HWR_512 (0x02 << 0) +#define HAL_MCF5272_SCR_HWR_1024 (0x03 << 0) +#define HAL_MCF5272_SCR_HWR_2048 (0x04 << 0) +#define HAL_MCF5272_SCR_HWR_4096 (0x05 << 0) +#define HAL_MCF5272_SCR_HWR_8192 (0x06 << 0) +#define HAL_MCF5272_SCR_HWR_16384 (0x07 << 0) + +// System protection register +#define HAL_MCF5272_SPR_ADC (0x01 << 15) +#define HAL_MCF5272_SPR_WPV (0x01 << 14) +#define HAL_MCF5272_SPR_SMV (0x01 << 13) +#define HAL_MCF5272_SPR_PE (0x01 << 12) +#define HAL_MCF5272_SPR_HWT (0x01 << 11) +#define HAL_MCF5272_SPR_RPV (0x01 << 10) +#define HAL_MCF5272_SPR_EXT (0x01 << 9) +#define HAL_MCF5272_SPR_SUV (0x01 << 8) +#define HAL_MCF5272_SPR_ADCEN (0x01 << 7) +#define HAL_MCF5272_SPR_WPVEN (0x01 << 6) +#define HAL_MCF5272_SPR_SMVEN (0x01 << 5) +#define HAL_MCF5272_SPR_PEEN (0x01 << 4) +#define HAL_MCF5272_SPR_HWTEN (0x01 << 3) +#define HAL_MCF5272_SPR_RPVEN (0x01 << 2) +#define HAL_MCF5272_SPR_EXTEN (0x01 << 1) +#define HAL_MCF5272_SPR_SUVEN (0x01 << 0) + +// Power management register. For power-down, 0 is enabled, 1 disabled. +// For wakeup 0 is disabled, 1 enabled +#define HAL_MCF5272_PMR_BDMPDN (0x01 << 31) +#define HAL_MCF5272_PMR_ENETPDN (0x01 << 26) +#define HAL_MCF5272_PMR_PLIPDN (0x01 << 25) +#define HAL_MCF5272_PMR_DRAMPDN (0x01 << 24) +#define HAL_MCF5272_PMR_DMAPDN (0x01 << 23) +#define HAL_MCF5272_PMR_PWMPDN (0x01 << 22) +#define HAL_MCF5272_PMR_QSPIPDN (0x01 << 21) +#define HAL_MCF5272_PMR_TIMERPDN (0x01 << 20) +#define HAL_MCF5272_PMR_GPIOPDN (0x01 << 19) +#define HAL_MCF5272_PMR_USBPDN (0x01 << 18) +#define HAL_MCF5272_PMR_UART1PDN (0x01 << 17) +#define HAL_MCF5272_PMR_UART0PDN (0x01 << 16) +#define HAL_MCF5272_PMR_USBWK (0x01 << 10) +#define HAL_MCF5272_PMR_UART1WK (0x01 << 9) +#define HAL_MCF5272_PMR_UART0WK (0x01 << 8) +#define HAL_MCF5272_PMR_MOS (0x01 << 5) +#define HAL_MCF5272_PMR_SLPEN (0x01 << 4) + +// Device identification register +#define HAL_MCF5272_DIR_VERSION_MASK (0x0F << 28) +#define HAL_MCF5272_DIR_VERSION_SHIFT 28 +#define HAL_MCF5272_DIR_DESIGN_CENTER_MASK (0x3F << 22) +#define HAL_MCF5272_DIR_DESIGN_CENTER_SHIFT 22 +#define HAL_MCF5272_DIR_DEVICE_NUMBER_MASK (0x3FF << 12) +#define HAL_MCF5272_DIR_DEVICE_NUMBER_SHIFT 12 +#define HAL_MCF5272_DIR_JEDEC_ID_MASK (0x7FF << 1) +#define HAL_MCF5272_DIR_JEDEC_ID_SHIFT 1 + +// ---------------------------------------------------------------------------- +// The software watchdog. All registers are 2-bytes wide. + +#define HAL_MCF5272_WRRR 0x0280 +#define HAL_MCF5272_WIRR 0x0284 +#define HAL_MCF5272_WCR 0x0288 +#define HAL_MCF5272_WER 0x028C + +// ---------------------------------------------------------------------------- +// The interrupt controller. PIVR is a single byte, the others are 32-bit. +// The bits within the registers are defined by the ISR numbers in proc_intr.h +#define HAL_MCF5272_ICR1 0x0020 +#define HAL_MCF5272_ICR2 0x0024 +#define HAL_MCF5272_ICR3 0x0028 +#define HAL_MCF5272_ICR4 0x002C +#define HAL_MCF5272_ISR 0x0030 +#define HAL_MCF5272_PITR 0x0034 +#define HAL_MCF5272_PIWR 0x0038 +#define HAL_MCF5272_PIVR 0x003F + +// ---------------------------------------------------------------------------- +// Chip select module. All registers are 32-bit +#define HAL_MCF5272_CSBR0 0x0040 +#define HAL_MCF5272_CSOR0 0x0044 +#define HAL_MCF5272_CSBR1 0x0048 +#define HAL_MCF5272_CSOR1 0x004C +#define HAL_MCF5272_CSBR2 0x0050 +#define HAL_MCF5272_CSOR2 0x0054 +#define HAL_MCF5272_CSBR3 0x0058 +#define HAL_MCF5272_CSOR3 0x005C +#define HAL_MCF5272_CSBR4 0x0060 +#define HAL_MCF5272_CSOR4 0x0064 +#define HAL_MCF5272_CSBR5 0x0068 +#define HAL_MCF5272_CSOR5 0x006C +#define HAL_MCF5272_CSBR6 0x0070 +#define HAL_MCF5272_CSOR6 0x0074 +#define HAL_MCF5272_CSBR7 0x0078 +#define HAL_MCF5272_CSOR7 0x007C + +#define HAL_MCF5272_CSBR_BA_MASK (0xFFFFF000) +#define HAL_MCF5272_CSBR_EBI_MASK (0x03 << 10) +#define HAL_MCF5272_CSBR_EBI_16_32 (0x00 << 10) +#define HAL_MCF5272_CSBR_EBI_SDRAM (0x01 << 10) +#define HAL_MCF5272_CSBR_EBI_8 (0x03 << 10) +#define HAL_MCF5272_CSBR_BW_MASK (0x03 << 8) +#define HAL_MCF5272_CSBR_BW_32 (0x00 << 8) +#define HAL_MCF5272_CSBR_BW_8 (0x01 << 8) +#define HAL_MCF5272_CSBR_BW_16 (0x02 << 8) +#define HAL_MCF5272_CSBR_BW_CACHELINE (0x03 << 8) +#define HAL_MCF5272_CSBR_SUPER (0x01 << 7) +#define HAL_MCF5272_CSBR_TT_MASK (0x03 << 5) +#define HAL_MCF5272_CSBR_TM_MASK (0x07 << 2) +#define HAL_MCF5272_CSBR_CTM (0x01 << 1) +#define HAL_MCF5272_CSBR_ENABLE (0x01 << 0) + +#define HAL_MCF5272_CSOR_BA_MASK (0xFFFFF000) +#define HAL_MCF5272_CSOR_ASET (0x01 << 11) +#define HAL_MCF5272_CSOR_WRAH (0x01 << 10) +#define HAL_MCF5272_CSOR_RDAH (0x01 << 9) +#define HAL_MCF5272_CSOR_EXTBURST (0x01 << 8) +#define HAL_MCF5272_CSOR_WS_MASK (0x1F << 2) +#define HAL_MCF5272_CSOR_WS_SHIFT 2 +#define HAL_MCF5272_CSOR_RW (0x01 << 1) +#define HAL_MCF5272_CSOR_MRW (0x01 << 0) + +// ---------------------------------------------------------------------------- +// SDRAM controller. Two 16-bit registers. + +#define HAL_MCF5272_SDCR 0x0180 +#define HAL_MCF5272_SDTR 0x0184 + +#define HAL_MCF5272_SDCR_MCAS_MASK (0x03 << 13) +#define HAL_MCF5272_SDCR_MCAS_A7 (0x00 << 13) +#define HAL_MCF5272_SDCR_MCAS_A8 (0x01 << 13) +#define HAL_MCF5272_SDCR_MCAS_A9 (0x02 << 13) +#define HAL_MCF5272_SDCR_MCAS_A10 (0x03 << 13) +#define HAL_MCF5272_SDCR_BALOC_MASK (0x07 << 8) +#define HAL_MCF5272_SDCR_BALOC_A21_A20 (0x01 << 8) +#define HAL_MCF5272_SDCR_BALOC_A22_A21 (0x02 << 8) +#define HAL_MCF5272_SDCR_BALOC_A23_A22 (0x03 << 8) +#define HAL_MCF5272_SDCR_BALOC_A24_A23 (0x04 << 8) +#define HAL_MCF5272_SDCR_BALOC_A25_A24 (0x05 << 8) +#define HAL_MCF5272_SDCR_GSL (0x01 << 7) +#define HAL_MCF5272_SDCR_REG (0x01 << 4) +#define HAL_MCF5272_SDCR_INV (0x01 << 3) +#define HAL_MCF5272_SDCR_SLEEP (0x01 << 2) +#define HAL_MCF5272_SDCR_ACT (0x01 << 1) +#define HAL_MCF5272_SDCR_INIT (0x01 << 0) + +#define HAL_MCF5272_SDTR_RTP_MASK (0x3F << 10) +#define HAL_MCF5272_SDTR_RTP_66 (0x3D << 10) +#define HAL_MCF5272_SDTR_RTP_48 (0x2B << 10) +#define HAL_MCF5272_SDTR_RTP_33 (0x1D << 10) +#define HAL_MCF5272_SDTR_RTP_25 (0x15 << 10) +#define HAL_MCF5272_SDTR_RTP_5 (0x04 << 10) +#define HAL_MCF5272_SDTR_RC_MASK (0x03 << 8) +#define HAL_MCF5272_SDTR_RC_5 (0x00 << 8) +#define HAL_MCF5272_SDTR_RC_6 (0x01 << 8) +#define HAL_MCF5272_SDTR_RC_7 (0x02 << 8) +#define HAL_MCF5272_SDTR_RC_8 (0x03 << 8) +#define HAL_MCF5272_SDTR_RP_MASK (0x03 << 4) +#define HAL_MCF5272_SDTR_RP_1 (0x00 << 4) +#define HAL_MCF5272_SDTR_RP_2 (0x01 << 4) +#define HAL_MCF5272_SDTR_RP_3 (0x02 << 4) +#define HAL_MCF5272_SDTR_RP_4 (0x03 << 4) +#define HAL_MCF5272_SDTR_RCD_MASK (0x03 << 2) +#define HAL_MCF5272_SDTR_RCD_1 (0x00 << 2) +#define HAL_MCF5272_SDTR_RCD_2 (0x01 << 2) +#define HAL_MCF5272_SDTR_RCD_3 (0x02 << 2) +#define HAL_MCF5272_SDTR_RCD_4 (0x03 << 2) +#define HAL_MCF5272_SDTR_CLT_MASK (0x03 << 0) +#define HAL_MCF5272_SDTR_CLT_2 (0x01 << 0) + +// ---------------------------------------------------------------------------- +// DMA controller. DCIR is 16-bit, the rest 32-bit +#define HAL_MCF5272_DMA_DCMR 0x00E0 +#define HAL_MCF5272_DMA_DCIR 0x00E6 +#define HAL_MCF5272_DMA_DBCR 0x00E8 +#define HAL_MCF5272_DMA_DSAR 0x00EC +#define HAL_MCF5272_DMA_DDAR 0x00F0 + +#define HAL_MCF5272_DMA_DCMR_RESET (0x01 << 31) +#define HAL_MCF5272_DMA_DCMR_EN (0x01 << 30) +#define HAL_MCF5272_DMA_DCMR_RQM_MASK (0x03 << 18) +#define HAL_MCF5272_DMA_DCMR_RQM_DUAL (0x03 << 18) +#define HAL_MCF5272_DMA_DCMR_DSTM_MASK (0x03 << 13) +#define HAL_MCF5272_DMA_DCMR_DSTM_STATIC (0x00 << 13) +#define HAL_MCF5272_DMA_DCMR_DSTM_INCREMENT (0x01 << 13) +#define HAL_MCF5272_DMA_DCMR_DSTT_MASK (0x07 << 10) +#define HAL_MCF5272_DMA_DCMR_DSTT_UDA (0x01 << 10) +#define HAL_MCF5272_DMA_DCMR_DSTT_UCA (0x02 << 10) +#define HAL_MCF5272_DMA_DCMR_DSTT_SDA (0x05 << 10) +#define HAL_MCF5272_DMA_DCMR_DSTT_SCA (0x06 << 10) +#define HAL_MCF5272_DMA_DCMR_DSTS_MASK (0x03 << 8) +#define HAL_MCF5272_DMA_DCMR_DSTS_4 (0x00 << 8) +#define HAL_MCF5272_DMA_DCMR_DSTS_1 (0x01 << 8) +#define HAL_MCF5272_DMA_DCMR_DSTS_2 (0x02 << 8) +#define HAL_MCF5272_DMA_DCMR_DSTS_16 (0x03 << 8) +#define HAL_MCF5272_DMA_DCMR_SRCM_MASK (0x01 << 5) +#define HAL_MCF5272_DMA_DCMR_SRCM_STATIC (0x00 << 5) +#define HAL_MCF5272_DMA_DCMR_SRCM_INCREMENT (0x01 << 5) +#define HAL_MCF5272_DMA_DCMR_SRCT_MASK (0x07 << 2) +#define HAL_MCF5272_DMA_DCMR_SRCT_UDA (0x01 << 2) +#define HAL_MCF5272_DMA_DCMR_SRCT_UCA (0x02 << 2) +#define HAL_MCF5272_DMA_DCMR_SRCT_SDA (0x05 << 2) +#define HAL_MCF5272_DMA_DCMR_SRCT_SCA (0x06 << 2) +#define HAL_MCF5272_DMA_DCMR_SRCS_MASK (0x03 << 0) +#define HAL_MCF5272_DMA_DCMR_SRCS_4 (0x00 << 0) +#define HAL_MCF5272_DMA_DCMR_SRCS_1 (0x01 << 0) +#define HAL_MCF5272_DMA_DCMR_SRCS_2 (0x02 << 0) +#define HAL_MCF5272_DMA_DCMR_SRCS_16 (0x03 << 0) + +#define HAL_MCF5272_DMA_DIR_INVEN (0x01 << 12) +#define HAL_MCF5272_DMA_DIR_ASCEN (0x01 << 11) +#define HAL_MCF5272_DMA_DIR_TEEN (0x01 << 9) +#define HAL_MCF5272_DMA_DIR_TCEN (0x01 << 8) +#define HAL_MCF5272_DMA_DIR_INV (0x01 << 4) +#define HAL_MCF5272_DMA_DIR_ASC (0x01 << 3) +#define HAL_MCF5272_DMA_DIR_TE (0x01 << 1) +#define HAL_MCF5272_DMA_DIR_TC (0x01 << 0) + +// ---------------------------------------------------------------------------- +// USB +#define HAL_MCF5272_USB_FNR 0x1002 +#define HAL_MCF5272_USB_FNMR 0x1006 +#define HAL_MCF5272_USB_RFMR 0x100A +#define HAL_MCF5272_USB_RFMMR 0x100E +#define HAL_MCF5272_USB_FAR 0x1013 +#define HAL_MCF5272_USB_ASR 0x1014 +#define HAL_MCF5272_USB_DDR1 0x1018 +#define HAL_MCF5272_USB_DDR2 0x101C +#define HAL_MCF5272_USB_SPECR 0x1022 +#define HAL_MCF5272_USB_EP0SR 0x1026 +#define HAL_MCF5272_USB_IEP0CFG 0x1028 +#define HAL_MCF5272_USB_OEP0CFG 0x102C +#define HAL_MCF5272_USB_EP1CFG 0x1030 +#define HAL_MCF5272_USB_EP2CFG 0x1034 +#define HAL_MCF5272_USB_EP3CFG 0x1038 +#define HAL_MCF5272_USB_EP4CFG 0x103C +#define HAL_MCF5272_USB_EP5CFG 0x1040 +#define HAL_MCF5272_USB_EP6CFG 0x1044 +#define HAL_MCF5272_USB_EP7CFG 0x1048 +#define HAL_MCF5272_USB_EP0CTL 0x104C +#define HAL_MCF5272_USB_EP1CTL 0x1052 +#define HAL_MCF5272_USB_EP2CTL 0x1056 +#define HAL_MCF5272_USB_EP3CTL 0x105A +#define HAL_MCF5272_USB_EP4CTL 0x105E +#define HAL_MCF5272_USB_EP5CTL 0x1062 +#define HAL_MCF5272_USB_EP6CTL 0x1066 +#define HAL_MCF5272_USB_EP7CTL 0x106A +#define HAL_MCF5272_USB_EP0ISR 0x106C +#define HAL_MCF5272_USB_EP1ISR 0x1072 +#define HAL_MCF5272_USB_EP2ISR 0x1076 +#define HAL_MCF5272_USB_EP3ISR 0x107A +#define HAL_MCF5272_USB_EP4ISR 0x107E +#define HAL_MCF5272_USB_EP5ISR 0x1082 +#define HAL_MCF5272_USB_EP6ISR 0x1086 +#define HAL_MCF5272_USB_EP7ISR 0x108A +#define HAL_MCF5272_USB_EP0IMR 0x108C +#define HAL_MCF5272_USB_EP1IMR 0x1092 +#define HAL_MCF5272_USB_EP2IMR 0x1096 +#define HAL_MCF5272_USB_EP3IMR 0x109A +#define HAL_MCF5272_USB_EP4IMR 0x109E +#define HAL_MCF5272_USB_EP5IMR 0x10A2 +#define HAL_MCF5272_USB_EP6IMR 0x10A6 +#define HAL_MCF5272_USB_EP7IMR 0x10AA +#define HAL_MCF5272_USB_EP0DR 0x10AC +#define HAL_MCF5272_USB_EP1DR 0x10B0 +#define HAL_MCF5272_USB_EP2DR 0x10B4 +#define HAL_MCF5272_USB_EP3DR 0x10B8 +#define HAL_MCF5272_USB_EP4DR 0x10BC +#define HAL_MCF5272_USB_EP5DR 0x10C0 +#define HAL_MCF5272_USB_EP6DR 0x10C4 +#define HAL_MCF5272_USB_EP7DR 0x10C8 +#define HAL_MCF5272_USB_EP0DPR 0x10CE +#define HAL_MCF5272_USB_EP1DPR 0x10D2 +#define HAL_MCF5272_USB_EP2DPR 0x10D6 +#define HAL_MCF5272_USB_EP3DPR 0x10DA +#define HAL_MCF5272_USB_EP4DPR 0x10DE +#define HAL_MCF5272_USB_EP5DPR 0x10E2 +#define HAL_MCF5272_USB_EP6DPR 0x10E6 +#define HAL_MCF5272_USB_EP7DPR 0x10EA +#define HAL_MCF5272_USB_CONFIG 0x1400 + +#define HAL_MCF5272_USB_ASR_IF15_MASK (0x03 << 30) +#define HAL_MCF5272_USB_ASR_IF15_SHIFT 30 +#define HAL_MCF5272_USB_ASR_IF14_MASK (0x03 << 28) +#define HAL_MCF5272_USB_ASR_IF14_SHIFT 28 +#define HAL_MCF5272_USB_ASR_IF13_MASK (0x03 << 26) +#define HAL_MCF5272_USB_ASR_IF13_SHIFT 26 +#define HAL_MCF5272_USB_ASR_IF12_MASK (0x03 << 24) +#define HAL_MCF5272_USB_ASR_IF12_SHIFT 24 +#define HAL_MCF5272_USB_ASR_IF11_MASK (0x03 << 22) +#define HAL_MCF5272_USB_ASR_IF11_SHIFT 22 +#define HAL_MCF5272_USB_ASR_IF10_MASK (0x03 << 20) +#define HAL_MCF5272_USB_ASR_IF10_SHIFT 20 +#define HAL_MCF5272_USB_ASR_IF9_MASK (0x03 << 18) +#define HAL_MCF5272_USB_ASR_IF9_SHIFT 18 +#define HAL_MCF5272_USB_ASR_IF8_MASK (0x03 << 16) +#define HAL_MCF5272_USB_ASR_IF8_SHIFT 16 +#define HAL_MCF5272_USB_ASR_IF7_MASK (0x03 << 14) +#define HAL_MCF5272_USB_ASR_IF7_SHIFT 14 +#define HAL_MCF5272_USB_ASR_IF6_MASK (0x03 << 12) +#define HAL_MCF5272_USB_ASR_IF6_SHIFT 12 +#define HAL_MCF5272_USB_ASR_IF5_MASK (0x03 << 10) +#define HAL_MCF5272_USB_ASR_IF5_SHIFT 10 +#define HAL_MCF5272_USB_ASR_IF4_MASK (0x03 << 8) +#define HAL_MCF5272_USB_ASR_IF4_SHIFT 8 +#define HAL_MCF5272_USB_ASR_IF3_MASK (0x03 << 6) +#define HAL_MCF5272_USB_ASR_IF3_SHIFT 6 +#define HAL_MCF5272_USB_ASR_IF2_MASK (0x03 << 4) +#define HAL_MCF5272_USB_ASR_IF2_SHIFT 4 +#define HAL_MCF5272_USB_ASR_IF1_MASK (0x03 << 2) +#define HAL_MCF5272_USB_ASR_IF1_SHIFT 2 +#define HAL_MCF5272_USB_ASR_IF0_MASK (0x03 << 0) +#define HAL_MCF5272_USB_ASR_IF0_SHIFT 0 + +#define HAL_MCF5272_USB_DDR1_wValue_MASK (0x0FFFF << 16) +#define HAL_MCF5272_USB_DDR1_wValue_SHIFT 16 +#define HAL_MCF5272_USB_DDR1_bRequest_MASK (0x0FF << 8) +#define HAL_MCF5272_USB_DDR1_bRequest_SHIFT 8 +#define HAL_MCF5272_USB_DDR1_bmRequestType_MASK (0x0FF << 0) +#define HAL_MCF5272_USB_DDR1_bmRequestType_SHIFT 0 +#define HAL_MCF5272_USB_DDR2_wLength_MASK (0x0FFFF << 16) +#define HAL_MCF5272_USB_DDR2_wLength_SHIFT 16 +#define HAL_MCF5272_USB_DDR2_wIndex_MASK (0x0FFFF << 0) +#define HAL_MCF5272_USB_DDR2_wIndex_SHIFT 0 + +#define HAL_MCF5272_USB_SPECR_SPEC_MASK (0x0FFF0 << 4) +#define HAL_MCF5272_USB_SPECR_SPEC_SHIFT 4 +#define HAL_MCF5272_USB_SPECR_MRN_MASK (0x0F << 0) +#define HAL_MCF5272_USB_SPECR_MRN_SHIFT (0x0F << 0) + +#define HAL_MCF5272_USB_EP0SR_CONFIG_MASK (0x0F << 12) +#define HAL_MCF5272_USB_EP0SR_CONFIG_SHIFT 12 +#define HAL_MCF5272_USB_EP0SR_WAKE_ST (0x01 << 11) +#define HAL_MCF5272_USB_EP0SR_HALT_ST (0x01 << 2) +#define HAL_MCF5272_USB_EP0SR_DIR_MASK (0x01 << 1) +#define HAL_MCF5272_USB_EP0SR_DIR_IN (0x01 << 1) +#define HAL_MCF5272_USB_EP0SR_DIR_OUT (0x00 << 1) + +#define HAL_MCF5272_USB_IEP0CFG_MAX_PACKET_MASK (0x03FF << 22) +#define HAL_MCF5272_USB_IEP0CFG_MAX_PACKET_SHIFT 22 +#define HAL_MCF5272_USB_IEP0CFG_FIFO_SIZE_MASK (0x03FF << 11) +#define HAL_MCF5272_USB_IEP0CFG_FIFO_SIZE_SHIFT 11 +#define HAL_MCF5272_USB_IEP0CFG_FIFO_ADDR_MASK (0x03FF << 0) +#define HAL_MCF5272_USB_IEP0CFG_FIFO_ADDR_SHIFT 0 + +#define HAL_MCF5272_USB_OEP0CFG_MAX_PACKET_MASK (0x03FF << 22) +#define HAL_MCF5272_USB_OEP0CFG_MAX_PACKET_SHIFT 22 +#define HAL_MCF5272_USB_OEP0CFG_FIFO_SIZE_MASK (0x03FF << 11) +#define HAL_MCF5272_USB_OEP0CFG_FIFO_SIZE_SHIFT 11 +#define HAL_MCF5272_USB_OEP0CFG_FIFO_ADDR_MASK (0x03FF << 0) +#define HAL_MCF5272_USB_OEP0CFG_FIFO_ADDR_SHIFT 0 + +#define HAL_MCF5272_USB_EPnCFG_MAX_PACKET_MASK (0x03FF << 22) +#define HAL_MCF5272_USB_EPnCFG_MAX_PACKET_SHIFT 22 +#define HAL_MCF5272_USB_EPnCFG_FIFO_SIZE_MASK (0x03FF << 11) +#define HAL_MCF5272_USB_EPnCFG_FIFO_SIZE_SHIFT 11 +#define HAL_MCF5272_USB_EPnCFG_FIFO_ADDR_MASK (0x03FF << 0) +#define HAL_MCF5272_USB_EPnCFG_FIFO_ADDR_SHIFT 0 + +#define HAL_MCF5272_USB_EP0CTL_DEBUG (0x01 << 18) +#define HAL_MCF5272_USB_EP0CTL_WOR_LVL (0x01 << 17) +#define HAL_MCF5272_USB_EP0CTL_WOR_EN (0x01 << 16) +#define HAL_MCF5272_USB_EP0CTL_CLK_SEL (0x01 << 15) +#define HAL_MCF5272_USB_EP0CTL_RESUME (0x01 << 14) +#define HAL_MCF5272_USB_EP0CTL_AFE_EN (0x01 << 13) +#define HAL_MCF5272_USB_EP0CTL_BUS_PWR (0x01 << 12) +#define HAL_MCF5272_USB_EP0CTL_USB_EN (0x01 << 11) +#define HAL_MCF5272_USB_EP0CTL_CFG_RAM_VAL (0x01 << 10) +#define HAL_MCF5272_USB_EP0CTL_CMD_ERR (0x01 << 9) +#define HAL_MCF5272_USB_EP0CTL_CMD_OVER (0x01 << 8) +#define HAL_MCF5272_USB_EP0CTL_CMD_CRC_ERR (0x01 << 7) +#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_MASK (0x03 << 4) +#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_25 (0x00 << 4) +#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_50 (0x01 << 4) +#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_75 (0x02 << 4) +#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_100 (0x03 << 4) +#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_MASK (0x03 << 2) +#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_25 (0x00 << 2) +#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_50 (0x01 << 2) +#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_75 (0x02 << 2) +#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_100 (0x03 << 2) +#define HAL_MCF5272_USB_EP0CTL_IN_DONE (0x01 << 1) + +#define HAL_MCF5272_USB_EPnCR_CRC_ERR (0x01 << 7) +#define HAL_MCF5272_USB_EPnCR_ISO_MODE (0x01 << 6) +#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_MASK (0x03 << 2) +#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_25 (0x00 << 2) +#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_50 (0x01 << 2) +#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_75 (0x02 << 2) +#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_100 (0x03 << 2) +#define HAL_MCF5272_USB_EPnCR_IN_DONE (0x01 << 1) +#define HAL_MCF5272_USB_EPnCR_STALL (0x01 << 0) + +#define HAL_MCF5272_USB_EP0IMR_DEV_CFG (0x01 << 16) +#define HAL_MCF5272_USB_EP0IMR_VEND_REQ (0x01 << 15) +#define HAL_MCF5272_USB_EP0IMR_FRM_MAT (0x01 << 14) +#define HAL_MCF5272_USB_EP0IMR_ASOF (0x01 << 13) +#define HAL_MCF5272_USB_EP0IMR_SOF (0x01 << 12) +#define HAL_MCF5272_USB_EP0IMR_WAKE_CHG (0x01 << 11) +#define HAL_MCF5272_USB_EP0IMR_RESUME (0x01 << 10) +#define HAL_MCF5272_USB_EP0IMR_SUSPEND (0x01 << 9) +#define HAL_MCF5272_USB_EP0IMR_RESET (0x01 << 8) +#define HAL_MCF5272_USB_EP0IMR_OUT_EOT (0x01 << 7) +#define HAL_MCF5272_USB_EP0IMR_OUT_EOP (0x01 << 6) +#define HAL_MCF5272_USB_EP0IMR_OUT_LVL (0x01 << 5) +#define HAL_MCF5272_USB_EP0IMR_IN_EOT (0x01 << 4) +#define HAL_MCF5272_USB_EP0IMR_IN_EOP (0x01 << 3) +#define HAL_MCF5272_USB_EP0IMR_UNHALT (0x01 << 2) +#define HAL_MCF5272_USB_EP0IMR_HALT (0x01 << 1) +#define HAL_MCF5272_USB_EP0IMR_IN_LVL (0x01 << 0) + +#define HAL_MCF5272_USB_EP0ISR_DEV_CFG HAL_MCF5272_USB_EP0IMR_DEV_CFG +#define HAL_MCF5272_USB_EP0ISR_VEND_REQ HAL_MCF5272_USB_EP0IMR_VEND_REQ +#define HAL_MCF5272_USB_EP0ISR_FRM_MAT HAL_MCF5272_USB_EP0IMR_FRM_MAT +#define HAL_MCF5272_USB_EP0ISR_ASOF HAL_MCF5272_USB_EP0IMR_ASOF +#define HAL_MCF5272_USB_EP0ISR_SOF HAL_MCF5272_USB_EP0IMR_SOF +#define HAL_MCF5272_USB_EP0ISR_WAKE_CHG HAL_MCF5272_USB_EP0IMR_WAKE_CHG +#define HAL_MCF5272_USB_EP0ISR_RESUME HAL_MCF5272_USB_EP0IMR_RESUME +#define HAL_MCF5272_USB_EP0ISR_SUSPEND HAL_MCF5272_USB_EP0IMR_SUSPEND +#define HAL_MCF5272_USB_EP0ISR_RESET HAL_MCF5272_USB_EP0IMR_RESET +#define HAL_MCF5272_USB_EP0ISR_OUT_EOT HAL_MCF5272_USB_EP0IMR_OUT_EOT +#define HAL_MCF5272_USB_EP0ISR_OUT_EOP HAL_MCF5272_USB_EP0IMR_OUT_EOP +#define HAL_MCF5272_USB_EP0ISR_OUT_LVL HAL_MCF5272_USB_EP0IMR_OUT_LVL +#define HAL_MCF5272_USB_EP0ISR_IN_EOT HAL_MCF5272_USB_EP0IMR_IN_EOT +#define HAL_MCF5272_USB_EP0ISR_IN_EOP HAL_MCF5272_USB_EP0IMR_IN_EOP +#define HAL_MCF5272_USB_EP0ISR_UNHALT HAL_MCF5272_USB_EP0IMR_UNHALT +#define HAL_MCF5272_USB_EP0ISR_HALT HAL_MCF5272_USB_EP0IMR_HALT +#define HAL_MCF5272_USB_EP0ISR_IN_LVL HAL_MCF5272_USB_EP0IMR_IN_LVL + +#define HAL_MCF5272_USB_EPnISR_HALT_ST (0x01 << 15) +#define HAL_MCF5272_USB_EPnISR_DIR (0x01 << 14) +#define HAL_MCF5272_USB_EPnISR_PRES (0x01 << 13) +#define HAL_MCF5272_USB_EPnISR_EOT (0x01 << 4) +#define HAL_MCF5272_USB_EPnISR_EOP (0x01 << 3) +#define HAL_MCF5272_USB_EPnISR_UNHALT (0x01 << 2) +#define HAL_MCF5272_USB_EPnISR_HALT (0x01 << 1) +#define HAL_MCF5272_USB_EPnISR_FIFO_LVL (0x01 << 0) + +#define HAL_MCF5272_USB_EPnIMR_EOT HAL_MCF5272_USB_EPnISR_EOT +#define HAL_MCF5272_USB_EPnIMR_EOP HAL_MCF5272_USB_EPnISR_EOP +#define HAL_MCF5272_USB_EPnIMR_UNHALT HAL_MCF5272_USB_EPnISR_UNHALT +#define HAL_MCF5272_USB_EPnIMR_HALT HAL_MCF5272_USB_EPnISR_HALT +#define HAL_MCF5272_USB_EPnIMR_FIFO_LVL HAL_MCF5272_USB_EPnISR_FIFO_LVL + +// ---------------------------------------------------------------------------- +// PLIC + +#define HAL_MCF5272_PLIC_P0B1RR 0x0300 +#define HAL_MCF5272_PLIC_P1B1RR 0x0304 +#define HAL_MCF5272_PLIC_P2B1RR 0x0308 +#define HAL_MCF5272_PLIC_P3B1RR 0x030C +#define HAL_MCF5272_PLIC_P0B2RR 0x0310 +#define HAL_MCF5272_PLIC_P1B2RR 0x0314 +#define HAL_MCF5272_PLIC_P2B2RR 0x0318 +#define HAL_MCF5272_PLIC_P3B2RR 0x031C +#define HAL_MCF5272_PLIC_P0DDR 0x0320 +#define HAL_MCF5272_PLIC_P1DDR 0x0321 +#define HAL_MCF5272_PLIC_P2DDR 0x0322 +#define HAL_MCF5272_PLIC_P3DDR 0x0323 +#define HAL_MCF5272_PLIC_P0B1TR 0x0328 +#define HAL_MCF5272_PLIC_P1B1TR 0x032C +#define HAL_MCF5272_PLIC_P2B1TR 0x0330 +#define HAL_MCF5272_PLIC_P3B1TR 0x0334 +#define HAL_MCF5272_PLIC_P0B2TR 0x0338 +#define HAL_MCF5272_PLIC_P1B2TR 0x033C +#define HAL_MCF5272_PLIC_P2B2TR 0x0340 +#define HAL_MCF5272_PLIC_P3B2TR 0x0344 +#define HAL_MCF5272_PLIC_P0DTR 0x0348 +#define HAL_MCF5272_PLIC_P1DTR 0x0349 +#define HAL_MCF5272_PLIC_P2DTR 0x034A +#define HAL_MCF5272_PLIC_P3DTR 0x034B +#define HAL_MCF5272_PLIC_P0CR 0x0350 +#define HAL_MCF5272_PLIC_P1CR 0x0352 +#define HAL_MCF5272_PLIC_P2CR 0x0354 +#define HAL_MCF5272_PLIC_P3CR 0x0356 +#define HAL_MCF5272_PLIC_P0ICR 0x0358 +#define HAL_MCF5272_PLIC_P1ICR 0x035A +#define HAL_MCF5272_PLIC_P2ICR 0x035C +#define HAL_MCF5272_PLIC_P3ICR 0x035E +#define HAL_MCF5272_PLIC_P0GMR 0x0360 +#define HAL_MCF5272_PLIC_P1GMR 0x0362 +#define HAL_MCF5272_PLIC_P2GMR 0x0364 +#define HAL_MCF5272_PLIC_P3GMR 0x0366 +#define HAL_MCF5272_PLIC_P0GMT 0x0368 +#define HAL_MCF5272_PLIC_P1GMT 0x036A +#define HAL_MCF5272_PLIC_P2GMT 0x036C +#define HAL_MCF5272_PLIC_P3GMT 0x036E +#define HAL_MCF5272_PLIC_PGMTS 0x0371 +#define HAL_MCF5272_PLIC_PGMTA 0x0372 +#define HAL_MCF5272_PLIC_P0GCIR 0x0374 +#define HAL_MCF5272_PLIC_P1GCIR 0x0375 +#define HAL_MCF5272_PLIC_P2GCIR 0x0376 +#define HAL_MCF5272_PLIC_P3GCIR 0x0377 +#define HAL_MCF5272_PLIC_P0GCIT 0x0378 +#define HAL_MCF5272_PLIC_P1GCIT 0x0379 +#define HAL_MCF5272_PLIC_P2GCIT 0x037A +#define HAL_MCF5272_PLIC_P3GCIT 0x037B +#define HAL_MCF5272_PLIC_PGCITSR 0x037F +#define HAL_MCF5272_PLIC_PDCSR 0x0383 +#define HAL_MCF5272_PLIC_P0PSR 0x0384 +#define HAL_MCF5272_PLIC_P1PSR 0x0386 +#define HAL_MCF5272_PLIC_P2PSR 0x0388 +#define HAL_MCF5272_PLIC_P3PSR 0x038A +#define HAL_MCF5272_PLIC_PASR 0x038C +#define HAL_MCF5272_PLIC_PLCR 0x038F +#define HAL_MCF5272_PLIC_PDRQR 0x0392 +#define HAL_MCF5272_PLIC_P0SDR 0x0394 +#define HAL_MCF5272_PLIC_P1SDR 0x0396 +#define HAL_MCF5272_PLIC_P2SDR 0x0398 +#define HAL_MCF5272_PLIC_P3SDR 0x039A +#define HAL_MCF5272_PLIC_PCSR 0x039E + +#define HAL_MCF5272_PLIC_PnCR_ON_OFF (0x01 << 15) +#define HAL_MCF5272_PLIC_PnCR_M_MASK (0x07 << 12) +#define HAL_MCF5272_PLIC_PnCR_M_SHIFT 12 +#define HAL_MCF5272_PLIC_PnCR_IDL8 (0x00 << 12) +#define HAL_MCF5272_PLIC_PnCR_IDL10 (0x01 << 12) +#define HAL_MCF5272_PLIC_PnCR_GCI (0x02 << 12) +#define HAL_MCF5272_PLIC_PnCR_M_S (0x01 << 11) +#define HAL_MCF5272_PLIC_PnCR_G_S (0x01 << 10) +#define HAL_MCF5272_PLIC_PnCR_FSM (0x01 << 9) +#define HAL_MCF5272_PLIC_PnCR_ACT (0x01 << 8) +#define HAL_MCF5272_PLIC_PnCR_DMX (0x01 << 7) +#define HAL_MCF5272_PLIC_PnCR_SHB2 (0x01 << 3) +#define HAL_MCF5272_PLIC_PnCR_SHB1 (0x01 << 2) +#define HAL_MCF5272_PLIC_PnCR_ENB2 (0x01 << 1) +#define HAL_MCF5272_PLIC_PnCR_ENB1 (0x01 << 0) + +#define HAL_MCF5272_PLIC_PLCR_LM3_MASK (0x03 << 6) +#define HAL_MCF5272_PLIC_PLCR_LM3_SHIFT 6 +#define HAL_MCF5272_PLIC_PLCR_LM2_MASK (0x03 << 4) +#define HAL_MCF5272_PLIC_PLCR_LM2_SHIFT 4 +#define HAL_MCF5272_PLIC_PLCR_LM1_MASK (0x03 << 2) +#define HAL_MCF5272_PLIC_PLCR_LM1_SHIFT 2 +#define HAL_MCF5272_PLIC_PLCR_LM0_MASK (0x03 << 0) +#define HAL_MCF5272_PLIC_PLCR_LM0_SHIFT 0 +#define HAL_MCF5272_PLIC_PLCR_LMn_NORMAL (0x00) +#define HAL_MCF5272_PLIC_PLCR_LMn_AUTO_ECHO (0x01) +#define HAL_MCF5272_PLIC_PLCR_LMn_LOCAL_LOOPBACK (0x02) +#define HAL_MCF5272_PLIC_PLCR_LMn_REMOTE_LOOPBACK (0x03) +#define HAL_MCF5272_PLIC_PLCR_LM3_NORMAL (0x00 << 6) +#define HAL_MCF5272_PLIC_PLCR_LM3_AUTO_ECHO (0x01 << 6) +#define HAL_MCF5272_PLIC_PLCR_LM3_LOCAL_LOOPBACK (0x02 << 6) +#define HAL_MCF5272_PLIC_PLCR_LM3_REMOTE_LOOPBACK (0x03 << 6) +#define HAL_MCF5272_PLIC_PLCR_LM2_NORMAL (0x00 << 4) +#define HAL_MCF5272_PLIC_PLCR_LM2_AUTO_ECHO (0x01 << 4) +#define HAL_MCF5272_PLIC_PLCR_LM2_LOCAL_LOOPBACK (0x02 << 4) +#define HAL_MCF5272_PLIC_PLCR_LM2_REMOTE_LOOPBACK (0x03 << 4) +#define HAL_MCF5272_PLIC_PLCR_LM1_NORMAL (0x00 << 2) +#define HAL_MCF5272_PLIC_PLCR_LM1_AUTO_ECHO (0x01 << 2) +#define HAL_MCF5272_PLIC_PLCR_LM1_LOCAL_LOOPBACK (0x02 << 2) +#define HAL_MCF5272_PLIC_PLCR_LM1_REMOTE_LOOPBACK (0x03 << 2) +#define HAL_MCF5272_PLIC_PLCR_LM0_NORMAL (0x00 << 0) +#define HAL_MCF5272_PLIC_PLCR_LM0_AUTO_ECHO (0x01 << 0) +#define HAL_MCF5272_PLIC_PLCR_LM0_LOCAL_LOOPBACK (0x02 << 0) +#define HAL_MCF5272_PLIC_PLCR_LM0_REMOTE_LOOPBACK (0x03 << 0) + +#define HAL_MCF5272_PLIC_PnICR_IE (0x01 << 15) +#define HAL_MCF5272_PLIC_PnICR_GCR (0x01 << 11) +#define HAL_MCF5272_PLIC_PnICR_GCT (0x01 << 10) +#define HAL_MCF5272_PLIC_PnICR_GMR (0x01 << 9) +#define HAL_MCF5272_PLIC_PnICR_GMT (0x01 << 8) +#define HAL_MCF5272_PLIC_PnICR_DTIE (0x01 << 5) +#define HAL_MCF5272_PLIC_PnICR_B2TIE (0x01 << 4) +#define HAL_MCF5272_PLIC_PnICR_B1TIE (0x01 << 3) +#define HAL_MCF5272_PLIC_PnICR_DRIE (0x01 << 2) +#define HAL_MCF5272_PLIC_PnICR_B2RIE (0x01 << 1) +#define HAL_MCF5272_PLIC_PnICR_B1RIE (0x01 << 0) + +#define HAL_MCF5272_PLIC_PnPSR_DTUE (0x01 << 11) +#define HAL_MCF5272_PLIC_PnPSR_B2TUE (0x01 << 10) +#define HAL_MCF5272_PLIC_PnPSR_B1TUE (0x01 << 9) +#define HAL_MCF5272_PLIC_PnPSR_DROE (0x01 << 8) +#define HAL_MCF5272_PLIC_PnPSR_B2ROE (0x01 << 7) +#define HAL_MCF5272_PLIC_PnPSR_B1ROE (0x01 << 6) +#define HAL_MCF5272_PLIC_PnPSR_DTDE (0x01 << 5) +#define HAL_MCF5272_PLIC_PnPSR_B2TDE (0x01 << 4) +#define HAL_MCF5272_PLIC_PnPSR_B1TDE (0x01 << 3) +#define HAL_MCF5272_PLIC_PnPSR_DRDF (0x01 << 2) +#define HAL_MCF5272_PLIC_PnPSR_B2RDE (0x01 << 1) +#define HAL_MCF5272_PLIC_PnPSR_B1RDE (0x01 << 0) + +#define HAL_MCF5272_PLIC_PASR_3_MASK (0x0F << 12) +#define HAL_MCF5272_PLIC_PASR_3_SHIFT 12 +#define HAL_MCF5272_PLIC_PASR_2_MASK (0x0F << 8) +#define HAL_MCF5272_PLIC_PASR_2_SHIFT 8 +#define HAL_MCF5272_PLIC_PASR_1_MASK (0x0F << 4) +#define HAL_MCF5272_PLIC_PASR_1_SHIFT 4 +#define HAL_MCF5272_PLIC_PASR_0_MASK (0x0F << 0) +#define HAL_MCF5272_PLIC_PASR_0_SHIFT 0 +#define HAL_MCF5272_PLCI_PASR_GCRn (0x01 << 3) +#define HAL_MCF5272_PLIC_PASR_GCTn (0x01 << 2) +#define HAL_MCF5272_PLIC_PASR_GMRn (0x01 << 1) +#define HAL_MCF5272_PLIC_PASR_GMTn (0x01 << 0) +#define HAL_MCF5272_PLIC_PASR_GCR3 (0x01 << 15) +#define HAL_MCF5272_PLIC_PASR_GCT3 (0x01 << 14) +#define HAL_MCF5272_PLIC_PASR_GMR3 (0x01 << 13) +#define HAL_MCF5272_PLIC_PASR_GMT3 (0x01 << 12) +#define HAL_MCF5272_PLIC_PASR_GCR2 (0x01 << 11) +#define HAL_MCF5272_PLIC_PASR_GCT2 (0x01 << 10) +#define HAL_MCF5272_PLIC_PASR_GMR2 (0x01 << 9) +#define HAL_MCF5272_PLIC_PASR_GMT2 (0x01 << 8) +#define HAL_MCF5272_PLIC_PASR_GCR1 (0x01 << 7) +#define HAL_MCF5272_PLIC_PASR_GCT1 (0x01 << 6) +#define HAL_MCF5272_PLIC_PASR_GMR1 (0x01 << 5) +#define HAL_MCF5272_PLIC_PASR_GMT1 (0x01 << 4) +#define HAL_MCF5272_PLIC_PASR_GCR0 (0x01 << 3) +#define HAL_MCF5272_PLIC_PASR_GCT0 (0x01 << 2) +#define HAL_MCF5272_PLIC_PASR_GMR0 (0x01 << 1) +#define HAL_MCF5272_PLIC_PASR_GMT0 (0x01 << 0) + +#define HAL_MCF5272_PLIC_PnGMR_EOM (0x01 << 10) +#define HAL_MCF5272_PLIC_PnGMR_AB (0x01 << 9) +#define HAL_MCF5272_PLIC_PnGMR_MC (0x01 << 8) +#define HAL_MCF5272_PLIC_PnGMR_M_MASK (0x0FF << 0) +#define HAL_MCF5272_PLIC_PnGMR_M_SHIFT 0 + +#define HAL_MCF5272_PLIC_PnGMT_L (0x01 << 9) +#define HAL_MCF5272_PLIC_PnGMT_R (0x01 << 8) +#define HAL_MCF5272_PLIC_PnGMT_M_MASK (0x0FF << 0) +#define HAL_MCF5272_PLIC_PnGMT_M_SHIFT 0 + +#define HAL_MCF5272_PLIC_PGMTA_AR3 (0x01 << 7) +#define HAL_MCF5272_PLIC_PGMTA_AR2 (0x01 << 6) +#define HAL_MCF5272_PLIC_PGMTA_AR1 (0x01 << 5) +#define HAL_MCF5272_PLIC_PGMTA_AR0 (0x01 << 4) + +#define HAL_MCF5272_PLIC_PGMTS_ACKn (0x01 << 4) +#define HAL_MCF5272_PLIC_PGMTS_ABn (0x01 << 0) +#define HAL_MCF5272_PLIC_PGMTS_3_SHIFT 3 +#define HAL_MCF5272_PLIC_PGMTS_2_SHIFT 2 +#define HAL_MCF5272_PLIC_PGMTS_1_SHIFT 1 +#define HAL_MCF5272_PLIC_PGMTS_0_SHIFT 0 +#define HAL_MCF5272_PLIC_PGMTS_ACK3 (0x01 << 7) +#define HAL_MCF5272_PLIC_PGMTS_ACK2 (0x01 << 6) +#define HAL_MCF5272_PLIC_PGMTS_ACK1 (0x01 << 5) +#define HAL_MCF5272_PLIC_PGMTS_ACK0 (0x01 << 4) +#define HAL_MCF5272_PLIC_PGMTS_AB3 (0x01 << 3) +#define HAL_MCF5272_PLIC_PGMTS_AB2 (0x01 << 2) +#define HAL_MCF5272_PLIC_PGMTS_AB1 (0x01 << 1) +#define HAL_MCF5272_PLIC_PGMTS_AB0 (0x01 << 0) + +#define HAL_MCF5272_PLIC_PnGCIR_F (0x01 << 4) +#define HAL_MCF5272_PLIC_PnGCIR_C3 (0x01 << 3) +#define HAL_MCF5272_PLIC_PnGCIR_C2 (0x01 << 2) +#define HAL_MCF5272_PLIC_PnGCIR_C1 (0x01 << 1) +#define HAL_MCF5272_PLIC_PnGCIR_C0 (0x01 << 0) + +#define HAL_MCF5272_PLIC_PnGCIT_R (0x01 << 4) +#define HAL_MCF5272_PLIC_PnGCIT_C3 (0x01 << 3) +#define HAL_MCF5272_PLIC_PnGCIT_C2 (0x01 << 2) +#define HAL_MCF5272_PLIC_PnGCIT_C1 (0x01 << 1) +#define HAL_MCF5272_PLIC_PnGCIT_C0 (0x01 << 0) + +#define HAL_MCF5272_PLIC_PGCITSR_ACK3 (0x01 << 3) +#define HAL_MCF5272_PLIC_PGCITSR_ACK2 (0x01 << 2) +#define HAL_MCF5272_PLIC_PGCITSR_ACK1 (0x01 << 1) +#define HAL_MCF5272_PLIC_PGCITSR_ACK0 (0x01 << 0) + +#define HAL_MCF5272_PLIC_PDCSR_DG1 (0x01 << 5) +#define HAL_MCF5272_PLIC_PDCSR_DG0 (0x01 << 4) +#define HAL_MCF5272_PLIC_PDCSR_DC3 (0x01 << 3) +#define HAL_MCF5272_PLIC_PDCSR_DC2 (0x01 << 2) +#define HAL_MCF5272_PLIC_PDCSR_DC1 (0x01 << 1) +#define HAL_MCF5272_PLIC_PDCSR_DC0 (0x01 << 0) + +#define HAL_MCF5272_PLIC_PDRQR_SHDD1 (0x01 << 11) +#define HAL_MCF5272_PLIC_PDRQR_DCNT1 (0x01 << 10) +#define HAL_MCF5272_PLIC_PDRQR_SHDD0 (0x01 << 9) +#define HAL_MCF5272_PLIC_PDRQR_DCNT0 (0x01 << 8) +#define HAL_MCF5272_PLIC_PDRQR_DRQ_MASK (0x03 << 0) +#define HAL_MCF5272_PLIC_PDRQR_DRQ_SHIFT 0 + +#define HAL_MCF5272_PLIC_PnSDR_FSW_MASK (0x03 << 14) +#define HAL_MCF5272_PLIC_PnSDR_FSW_SHIFT 14 +#define HAL_MCF5272_PLIC_PnSDR_FSW_1 (0x00 << 14) +#define HAL_MCF5272_PLIC_PnSDR_FSW_2 (0x01 << 14) +#define HAL_MCF5272_PLIC_PnSDR_FSW_8 (0x02 << 14) +#define HAL_MCF5272_PLIC_PnSDR_FSW_16 (0x03 << 14) +#define HAL_MCF5272_PLIC_PnSDR_SD_MASK (0x03FF << 0) +#define HAL_MCF5272_PLIC_PnSDR_SD_SHIFT 0 + +#define HAL_MCF5272_PLIC_PCSR_NBP (0x01 << 15) +#define HAL_MCF5272_PLIC_PCSR_CKI_MASK (0x03 << 6) +#define HAL_MCF5272_PLIC_PCSR_CKI_SHIFT 6 +#define HAL_MCF5272_PLIC_PCSR_CKI_DCL0 (0x00 << 6) +#define HAL_MCF5272_PLIC_PCSR_CKI_FSC0 (0x01 << 6) +#define HAL_MCF5272_PLIC_PCSR_FDIV_MASK (0x07 << 3) +#define HAL_MCF5272_PLIC_PCSR_FDIV_SHIFT 3 +#define HAL_MCF5272_PLIC_PCSR_FDIV_4 (0x00 << 3) +#define HAL_MCF5272_PLIC_PCSR_FDIV_8 (0x01 << 3) +#define HAL_MCF5272_PLIC_PCSR_FDIV_16 (0x02 << 3) +#define HAL_MCF5272_PLIC_PCSR_FDIV_32 (0x03 << 3) +#define HAL_MCF5272_PLIC_PCSR_FDIV_64 (0x04 << 3) +#define HAL_MCF5272_PLIC_PCSR_FDIV_128 (0x05 << 3) +#define HAL_MCF5272_PLIC_PCSR_FDIV_192 (0x06 << 3) +#define HAL_MCF5272_PLIC_PCSR_FDIV_256 (0x07 << 3) +#define HAL_MCF5272_PLIC_PCSR_CMULT_MASK (0x07 << 0) +#define HAL_MCF5272_PLIC_PCSR_CMULT_SHIFT 0 +#define HAL_MCF5272_PLIC_PCSR_CMULT_2 (0x00 << 0) +#define HAL_MCF5272_PLIC_PCSR_CMULT_4 (0x01 << 0) +#define HAL_MCF5272_PLIC_PCSR_CMULT_8 (0x02 << 0) +#define HAL_MCF5272_PLIC_PCSR_CMULT_16 (0x03 << 0) +#define HAL_MCF5272_PLIC_PCSR_CMULT_32 (0x04 << 0) +#define HAL_MCF5272_PLIC_PCSR_CMULT_64 (0x05 << 0) +#define HAL_MCF5272_PLIC_PCSR_CMULT_128 (0x06 << 0) +#define HAL_MCF5272_PLIC_PCSR_CMULT_256 (0x07 << 0) + +// ---------------------------------------------------------------------------- +// The system timers. There are four timers at different MBAR offsets +// +// Some of these definitions could be re-used on other xxxx processors, but +// recent ones from the 5282 onwards have very different timer support. + +#define HAL_MCF5272_TIMER0_BASE 0x0200 +#define HAL_MCF5272_TIMER1_BASE 0x0220 +#define HAL_MCF5272_TIMER2_BASE 0x0240 +#define HAL_MCF5272_TIMER3_BASE 0x0260 + +// The register offsets for each timer. All registers are 16 bits +#define HAL_MCF5272_TIMER_TMR 0x0000 +#define HAL_MCF5272_TIMER_TRR 0x0004 +#define HAL_MCF5272_TIMER_TCR 0x0008 +#define HAL_MCF5272_TIMER_TCN 0x000C +#define HAL_MCF5272_TIMER_TER 0x0010 + +// The bits +#define HAL_MCF5272_TIMER_TMR_PS_MASK 0xFF00 +#define HAL_MCF5272_TIMER_TMR_PS_SHIFT 8 +#define HAL_MCF5272_TIMER_TMR_CE_MASK (0x0003 << 6) +// OM is only available for timers 0 and 1 +#define HAL_MCF5272_TIMER_TMR_OM (0x0001 << 5) +#define HAL_MCF5272_TIMER_TMR_ORI (0x0001 << 4) +#define HAL_MCF5272_TIMER_TMR_FRR (0x0001 << 3) +#define HAL_MCF5272_TIMER_TMR_CLK_MASK (0x0003 << 1) +#define HAL_MCF5272_TIMER_TMR_CLK_STOP (0x0000 << 1) +#define HAL_MCF5272_TIMER_TMR_CLK_MASTER (0x0001 << 1) +#define HAL_MCF5272_TIMER_TMR_CLK_MASTER_DIV_16 (0x0002 << 1) +#define HAL_MCF5272_TIMER_TMR_CLK_TIN (0x0003 << 1) +#define HAL_MCF5272_TIMER_TMR_RST (0x0001 << 0) + +#define HAL_MCF5272_TIMER_TER_REF (0x0001 << 1) +#define HAL_MCF5272_TIMER_TER_CAP (0x0001 << 0) + +// ---------------------------------------------------------------------------- +// GPIO pins. PACNT/PBCNT/PDCNT are 32-bit. The others are 16-bit. + +#define HAL_MCF5272_PACNT 0x0080 +#define HAL_MCF5272_PADDR 0x0084 +#define HAL_MCF5272_PADAT 0x0086 +#define HAL_MCF5272_PBCNT 0x0088 +#define HAL_MCF5272_PBDDR 0x008C +#define HAL_MCF5272_PBDAT 0x008E +#define HAL_MCF5272_PCDDR 0x0094 +#define HAL_MCF5272_PCDAT 0x0096 +#define HAL_MCF5272_PDCNT 0x0098 + +// Then the bits. The direction and data registers are only +// relevant if the pin is controlled for GPIO, as per the +// appropriate 2-bit entry in the control register. +#define HAL_MCF5272_PACNT_PACNT15_MASK (0x03 << 30) +#define HAL_MCF5272_PACNT_PACNT15_PA15 (0x00 << 30) +#define HAL_MCF5272_PACNT_PACNT15_DGNT1 (0x01 << 30) +#define HAL_MCF5272_PACNT_PACNT14_MASK (0x03 << 28) +#define HAL_MCF5272_PACNT_PACNT14_PA14 (0x00 << 28) +#define HAL_MCF5272_PACNT_PACNT14_DREQ1 (0x01 << 28) +#define HAL_MCF5272_PACNT_PACNT13_MASK (0x03 << 26) +#define HAL_MCF5272_PACNT_PACNT13_PA13 (0x00 << 26) +#define HAL_MCF5272_PACNT_PACNT13_DFSC3 (0x01 << 26) +#define HAL_MCF5272_PACNT_PACNT12_MASK (0x03 << 24) +#define HAL_MCF5272_PACNT_PACNT12_PA12 (0x00 << 24) +#define HAL_MCF5272_PACNT_PACNT12_DFSC2 (0x01 << 24) +#define HAL_MCF5272_PACNT_PACNT11_MASK (0x03 << 22) +#define HAL_MCF5272_PACNT_PACNT11_PA11 (0x00 << 22) +#define HAL_MCF5272_PACNT_PACNT11_QSPI_CS1 (0x02 << 22) +#define HAL_MCF5272_PACNT_PACNT10_MASK (0x03 << 20) +#define HAL_MCF5272_PACNT_PACNT10_PA10 (0x00 << 20) +#define HAL_MCF5272_PACNT_PACNT10_DREQ0 (0x01 << 20) +#define HAL_MCF5272_PACNT_PACNT9_MASK (0x03 << 18) +#define HAL_MCF5272_PACNT_PACNT9_PA9 (0x00 << 18) +#define HAL_MCF5272_PACNT_PACNT9_DGNT0 (0x01 << 18) +#define HAL_MCF5272_PACNT_PACNT8_MASK (0x03 << 16) +#define HAL_MCF5272_PACNT_PACNT8_PA8 (0x00 << 16) +#define HAL_MCF5272_PACNT_PACNT8_FSC0_FSR0 (0x01 << 16) +#define HAL_MCF5272_PACNT_PACNT7_MASK (0x03 << 14) +#define HAL_MCF5272_PACNT_PACNT7_PA7 (0x00 << 14) +#define HAL_MCF5272_PACNT_PACNT7_QSPI_CS3 (0x01 << 14) +#define HAL_MCF5272_PACNT_PACNT7_DOUT3 (0x02 << 14) +#define HAL_MCF5272_PACNT_PACNT6_MASK (0x03 << 12) +#define HAL_MCF5272_PACNT_PACNT6_PA6 (0x00 << 12) +#define HAL_MCF5272_PACNT_PACNT6_USB_RXD (0x01 << 12) +#define HAL_MCF5272_PACNT_PACNT5_MASK (0x03 << 10) +#define HAL_MCF5272_PACNT_PACNT5_PA5 (0x00 << 10) +#define HAL_MCF5272_PACNT_PACNT5_USB_TXEN (0x01 << 10) +#define HAL_MCF5272_PACNT_PACNT4_MASK (0x03 << 8) +#define HAL_MCF5272_PACNT_PACNT4_PA4 (0x00 << 8) +#define HAL_MCF5272_PACNT_PACNT4_USB_SUSP (0x01 << 8) +#define HAL_MCF5272_PACNT_PACNT3_MASK (0x03 << 6) +#define HAL_MCF5272_PACNT_PACNT3_PA3 (0x00 << 6) +#define HAL_MCF5272_PACNT_PACNT3_USB_TN (0x01 << 6) +#define HAL_MCF5272_PACNT_PACNT2_MASK (0x03 << 4) +#define HAL_MCF5272_PACNT_PACNT2_PA2 (0x00 << 4) +#define HAL_MCF5272_PACNT_PACNT2_USB_RN (0x01 << 4) +#define HAL_MCF5272_PACNT_PACNT1_MASK (0x03 << 2) +#define HAL_MCF5272_PACNT_PACNT1_PA1 (0x00 << 2) +#define HAL_MCF5272_PACNT_PACNT1_USB_RP (0x01 << 2) +#define HAL_MCF5272_PACNT_PACNT0_MASK (0x03 << 0) +#define HAL_MCF5272_PACNT_PACNT0_PA0 (0x00 << 0) +#define HAL_MCF5272_PACNT_PACNT0_USB_TP (0x01 << 0) + +#define HAL_MCF5272_PBCNT_PBCNT15_MASK (0x03 << 30) +#define HAL_MCF5272_PBCNT_PBCNT15_PB15 (0x00 << 30) +#define HAL_MCF5272_PBCNT_PBCNT15_E_MDC (0x01 << 30) +#define HAL_MCF5272_PBCNT_PBCNT14_MASK (0x03 << 28) +#define HAL_MCF5272_PBCNT_PBCNT14_PB14 (0x00 << 28) +#define HAL_MCF5272_PBCNT_PBCNT14_E_RXER (0x01 << 28) +#define HAL_MCF5272_PBCNT_PBCNT13_MASK (0x03 << 26) +#define HAL_MCF5272_PBCNT_PBCNT13_PB13 (0x00 << 26) +#define HAL_MCF5272_PBCNT_PBCNT13_E_RXD1 (0x01 << 26) +#define HAL_MCF5272_PBCNT_PBCNT12_MASK (0x03 << 24) +#define HAL_MCF5272_PBCNT_PBCNT12_PB12 (0x00 << 24) +#define HAL_MCF5272_PBCNT_PBCNT12_E_RXD2 (0x01 << 24) +#define HAL_MCF5272_PBCNT_PBCNT11_MASK (0x03 << 22) +#define HAL_MCF5272_PBCNT_PBCNT11_PB11 (0x00 << 22) +#define HAL_MCF5272_PBCNT_PBCNT11_E_RXD3 (0x01 << 22) +// The original user manual defined QSPI_CS for 0x02. This has +// been removed in the errata. +#define HAL_MCF5272_PBCNT_PBCNT10_MASK (0x03 << 20) +#define HAL_MCF5272_PBCNT_PBCNT10_PB10 (0x00 << 20) +#define HAL_MCF5272_PBCNT_PBCNT10_E_TXD1 (0x01 << 20) +#define HAL_MCF5272_PBCNT_PBCNT9_MASK (0x03 << 18) +#define HAL_MCF5272_PBCNT_PBCNT9_PB9 (0x00 << 18) +#define HAL_MCF5272_PBCNT_PBCNT9_E_TXD2 (0x01 << 18) +#define HAL_MCF5272_PBCNT_PBCNT8_MASK (0x03 << 16) +#define HAL_MCF5272_PBCNT_PBCNT8_PB8 (0x00 << 16) +#define HAL_MCF5272_PBCNT_PBCNT8_E_TXD3 (0x01 << 16) +#define HAL_MCF5272_PBCNT_PBCNT7_MASK (0x03 << 14) +#define HAL_MCF5272_PBCNT_PBCNT7_PB7 (0x00 << 14) +#define HAL_MCF5272_PBCNT_PBCNT7_TOUT0 (0x01 << 14) +#define HAL_MCF5272_PBCNT_PBCNT6_MASK (0x03 << 12) +#define HAL_MCF5272_PBCNT_PBCNT6_PB6 (0x00 << 12) +#define HAL_MCF5272_PBCNT_PBCNT5_MASK (0x03 << 10) +#define HAL_MCF5272_PBCNT_PBCNT5_PB5 (0x00 << 10) +#define HAL_MCF5272_PBCNT_PBCNT5_TA (0x01 << 10) +#define HAL_MCF5272_PBCNT_PBCNT4_MASK (0x03 << 8) +#define HAL_MCF5272_PBCNT_PBCNT4_PB4 (0x00 << 8) +#define HAL_MCF5272_PBCNT_PBCNT4_URT0_CLK (0x01 << 8) +#define HAL_MCF5272_PBCNT_PBCNT3_MASK (0x03 << 6) +#define HAL_MCF5272_PBCNT_PBCNT3_PB3 (0x00 << 6) +#define HAL_MCF5272_PBCNT_PBCNT3_URT0_RTS (0x01 << 6) +#define HAL_MCF5272_PBCNT_PBCNT2_MASK (0x03 << 4) +#define HAL_MCF5272_PBCNT_PBCNT2_PB2 (0x00 << 4) +#define HAL_MCF5272_PBCNT_PBCNT2_URT0_CTS (0x01 << 4) +#define HAL_MCF5272_PBCNT_PBCNT1_MASK (0x03 << 2) +#define HAL_MCF5272_PBCNT_PBCNT1_PB1 (0x00 << 2) +#define HAL_MCF5272_PBCNT_PBCNT1_URT0_RXD (0x01 << 2) +#define HAL_MCF5272_PBCNT_PBCNT0_MASK (0x03 << 0) +#define HAL_MCF5272_PBCNT_PBCNT0_PB0 (0x00 << 0) +#define HAL_MCF5272_PBCNT_PBCNT0_URT0_TXD (0x01 << 0) + +#define HAL_MCF5272_PDCNT_PDCNT7_MASK (0x03 << 14) +#define HAL_MCF5272_PDCNT_PDCNT7_HIGH (0x00 << 14) +#define HAL_MCF5272_PDCNT_PDCNT7_PWM_OUT3 (0x01 << 14) +#define HAL_MCF5272_PDCNT_PDCNT7_TIN1 (0x02 << 14) +#define HAL_MCF5272_PDCNT_PDCNT6_MASK (0x03 << 12) +#define HAL_MCF5272_PDCNT_PDCNT6_HIGH (0x00 << 12) +#define HAL_MCF5272_PDCNT_PDCNT6_PWM_OUT2 (0x01 << 12) +#define HAL_MCF5272_PDCNT_PDCNT6_TOUT1 (0x02 << 12) +#define HAL_MCF5272_PDCNT_PDCNT5_MASK (0x03 << 10) +#define HAL_MCF5272_PDCNT_PDCNT5_HIGH (0x00 << 10) +#define HAL_MCF5272_PDCNT_PDCNT5_DIN3 (0x02 << 10) +#define HAL_MCF5272_PDCNT_PDCNT5_INT4 (0x03 << 10) +#define HAL_MCF5272_PDCNT_PDCNT4_MASK (0x03 << 8) +#define HAL_MCF5272_PDCNT_PDCNT4_HIGH (0x00 << 8) +#define HAL_MCF5272_PDCNT_PDCNT4_DOUT0 (0x01 << 8) +#define HAL_MCF5272_PDCNT_PDCNT4_URT1_TXD (0x02 << 8) +#define HAL_MCF5272_PDCNT_PDCNT3_MASK (0x03 << 6) +#define HAL_MCF5272_PDCNT_PDCNT3_HIGH (0x00 << 6) +#define HAL_MCF5272_PDCNT_PDCNT3_URT1_RTS (0x02 << 6) +#define HAL_MCF5272_PDCNT_PDCNT3_INT5 (0x03 << 6) +#define HAL_MCF5272_PDCNT_PDCNT2_MASK (0x03 << 4) +#define HAL_MCF5272_PDCNT_PDCNT2_HIGH (0x00 << 4) +#define HAL_MCF5272_PDCNT_PDCNT2_URT1_CTS (0x02 << 4) +#define HAL_MCF5272_PDCNT_PDCNT2_QSPI_CS2 (0x03 << 4) +#define HAL_MCF5272_PDCNT_PDCNT1_MASK (0x03 << 2) +#define HAL_MCF5272_PDCNT_PDCNT1_HIGH (0x00 << 2) +#define HAL_MCF5272_PDCNT_PDCNT1_DIN0 (0x01 << 2) +#define HAL_MCF5272_PDCNT_PDCNT1_URT1_RXD (0x02 << 2) +#define HAL_MCF5272_PDCNT_PDCNT0_MASK (0x03 << 0) +#define HAL_MCF5272_PDCNT_PDCNT0_HIGH (0x00 << 0) +#define HAL_MCF5272_PDCNT_PDCNT0_DCL0 (0x01 << 0) +#define HAL_MCF5272_PDCNT_PDCNT0_URT1_CLK (0x02 << 0) + +// ---------------------------------------------------------------------------- +// PWM: six 8-bit registers, in three pairs +#define HAL_MCF5272_PWCR0 0x00C0 +#define HAL_MCF5272_PWCR1 0x00C4 +#define HAL_MCF5272_PWCR2 0x00C8 +#define HAL_MCF5272_PWWD0 0x00D0 +#define HAL_MCF5272_PWWD1 0x00D4 +#define HAL_MCF5272_PWWD2 0x00D8 + +#define HAL_MCF5272_PWCR_EN (0x01 << 7) +#define HAL_MCF5272_PWCR_FRC1 (0x01 << 6) +#define HAL_MCF5272_PWCR_LVL (0x01 << 5) +#define HAL_MCF5272_PWCR_CKSL_MASK (0x0F << 0) +#define HAL_MCF5272_PWCR_CKSL_SHIFT 0 +#define HAL_MCF5272_PWCR_CKSL_1 (0x00 << 0) +#define HAL_MCF5272_PWCR_CKSL_2 (0x01 << 0) +#define HAL_MCF5272_PWCR_CKSL_4 (0x02 << 0) +#define HAL_MCF5272_PWCR_CKSL_8 (0x03 << 0) +#define HAL_MCF5272_PWCR_CKSL_16 (0x04 << 0) +#define HAL_MCF5272_PWCR_CKSL_32 (0x05 << 0) +#define HAL_MCF5272_PWCR_CKSL_64 (0x06 << 0) +#define HAL_MCF5272_PWCR_CKSL_128 (0x07 << 0) +#define HAL_MCF5272_PWCR_CKSL_256 (0x08 << 0) +#define HAL_MCF5272_PWCR_CKSL_512 (0x09 << 0) +#define HAL_MCF5272_PWCR_CKSL_1024 (0x0A << 0) +#define HAL_MCF5272_PWCR_CKSL_2048 (0x0B << 0) +#define HAL_MCF5272_PWCR_CKSL_4096 (0x0C << 0) +#define HAL_MCF5272_PWCR_CKSL_8192 (0x0D << 0) +#define HAL_MCF5272_PWCR_CKSL_16384 (0x0E << 0) +#define HAL_MCF5272_PWCR_CKSL_32768 (0x0F << 0) + +// ---------------------------------------------------------------------------- +// Now allow platform-specific overrides and additions +#include <cyg/hal/plf_io.h> + +#ifndef HAL_MCFxxxx_MBAR +# define HAL_MCFxxxx_MBAR 0x10000000 +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PROC_IO_H_FIRST_SECOND diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/gpio.c b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/gpio.c new file mode 100644 index 0000000..9242ca1 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/gpio.c @@ -0,0 +1,962 @@ +//========================================================================== +// +// gpio.c +// +// MCF5272 GPIO support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2006-09-05 +// +//####DESCRIPTIONEND#### +//============================================================================= + +// This file is just #include'd by the main mcf5272.c file. It serves +// to keep all the GPIO definitions in a separate file. GPIO +// initialization is all handled by configury, thus minimizing the +// amount of work explicitly needed in application code. + +#define A0_DAT 1 +#define A1_DAT 1 +#define A2_DAT 1 +#define A3_DAT 1 +#define A4_DAT 1 +#define A5_DAT 1 +#define A6_DAT 1 +#define A7_DAT 1 +#define A8_DAT 1 +#define A9_DAT 1 +#define A10_DAT 1 +#define A11_DAT 1 +#define A12_DAT 1 +#define A13_DAT 1 +#define A14_DAT 1 +#define A15_DAT 1 + +#define A0_DDR 0 +#define A1_DDR 0 +#define A2_DDR 0 +#define A3_DDR 0 +#define A4_DDR 0 +#define A5_DDR 0 +#define A6_DDR 0 +#define A7_DDR 0 +#define A8_DDR 0 +#define A9_DDR 0 +#define A10_DDR 0 +#define A11_DDR 0 +#define A12_DDR 0 +#define A13_DDR 0 +#define A14_DDR 0 +#define A15_DDR 0 + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0_usb_tp) +# define A0_PAR 1 +#else +# define A0_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0_in) +# undef A0_DDR +# define A0_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0_out0) +# undef A0_DAT +# define A0_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1_usb_rp) +# define A1_PAR 1 +#else +# define A1_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1_in) +# undef A1_DDR +# define A1_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1_out0) +# undef A1_DAT +# define A1_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2_usb_rn) +# define A2_PAR 1 +#else +# define A2_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2_in) +# undef A2_DDR +# define A2_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2_out0) +# undef A2_DAT +# define A2_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3_usb_tn) +# define A3_PAR 1 +#else +# define A3_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3_in) +# undef A3_DDR +# define A3_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3_out0) +# undef A3_DAT +# define A3_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4_usb_susp) +# define A4_PAR 1 +#else +# define A4_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4_in) +# undef A4_DDR +# define A4_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4_out0) +# undef A4_DAT +# define A4_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5_usb_txen) +# define A5_PAR 1 +#else +# define A5_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5_in) +# undef A5_DDR +# define A5_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5_out0) +# undef A5_DAT +# define A5_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6_usb_rxd) +# define A6_PAR 1 +#else +# define A6_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6_in) +# undef A6_DDR +# define A6_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6_out0) +# undef A6_DAT +# define A6_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_qspi_cs3) +# define A7_PAR 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_dout3) +# define A7_PAR 2 +#else +# define A7_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_in) +# undef A7_DDR +# define A7_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_out0) +# undef A7_DAT +# define A7_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8_fsc0_fsr0) +# define A8_PAR 1 +#else +# define A8_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8_in) +# undef A8_DDR +# define A8_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8_out0) +# undef A8_DAT +# define A8_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9_dgnt0) +# define A9_PAR 1 +#else +# define A9_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9_in) +# undef A9_DDR +# define A9_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9_out0) +# undef A9_DAT +# define A9_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10_dreq0) +# define A10_PAR 1 +#else +# define A10_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10_in) +# undef A10_DDR +# define A10_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10_out0) +# undef A10_DAT +# define A10_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11_qspi_cs1) +# define A11_PAR 2 +#else +# define A11_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11_in) +# undef A11_DDR +# define A11_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11_out0) +# undef A11_DAT +# define A11_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12_dfsc2) +# define A12_PAR 1 +#else +# define A12_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12_in) +# undef A12_DDR +# define A12_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12_out0) +# undef A12_DAT +# define A12_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13_dfsc3) +# define A13_PAR 1 +#else +# define A13_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13_in) +# undef A13_DDR +# define A13_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13_out0) +# undef A13_DAT +# define A13_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14_dreq1) +# define A14_PAR 1 +#else +# define A14_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14_in) +# undef A14_DDR +# define A14_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14_out0) +# undef A14_DAT +# define A14_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15_dgnt1) +# define A15_PAR 1 +#else +# define A15_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15_in) +# undef A15_DDR +# define A15_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15_out0) +# undef A15_DAT +# define A15_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#define A_DAT ((A0_DAT << 0) | (A1_DAT << 1) | (A2_DAT << 2) | (A3_DAT << 3) | \ + (A4_DAT << 4) | (A5_DAT << 5) | (A6_DAT << 6) | (A7_DAT << 7) | \ + (A8_DAT << 8) | (A9_DAT << 9) | (A10_DAT << 10) | (A11_DAT << 11) | \ + (A12_DAT << 12) | (A13_DAT << 13) | (A14_DAT << 14) | (A15_DAT << 15)) +#define A_DDR ((A0_DDR << 0) | (A1_DDR << 1) | (A2_DDR << 2) | (A3_DDR << 3) | \ + (A4_DDR << 4) | (A5_DDR << 5) | (A6_DDR << 6) | (A7_DDR << 7) | \ + (A8_DDR << 8) | (A9_DDR << 9) | (A10_DDR << 10) | (A11_DDR << 11) | \ + (A12_DDR << 12) | (A13_DDR << 13) | (A14_DDR << 14) | (A15_DDR << 15)) +#define A_PAR ((A0_PAR << 0) | (A1_PAR << 2) | (A2_PAR << 4) | (A3_PAR << 6) | \ + (A4_PAR << 8) | (A5_PAR << 10) | (A6_PAR << 12) | (A7_PAR << 14) | \ + (A8_PAR << 16) | (A9_PAR << 18) | (A10_PAR << 20) | (A11_PAR << 22) | \ + (A12_PAR << 24) | (A13_PAR << 26) | (A14_PAR << 28) | (A15_PAR << 30)) + +// ---------------------------------------------------------------------------- +#define B0_DAT 1 +#define B1_DAT 1 +#define B2_DAT 1 +#define B3_DAT 1 +#define B4_DAT 1 +#define B5_DAT 1 +#define B6_DAT 1 +#define B7_DAT 1 +#define B8_DAT 1 +#define B9_DAT 1 +#define B10_DAT 1 +#define B11_DAT 1 +#define B12_DAT 1 +#define B13_DAT 1 +#define B14_DAT 1 +#define B15_DAT 1 + +#define B0_DDR 0 +#define B1_DDR 0 +#define B2_DDR 0 +#define B3_DDR 0 +#define B4_DDR 0 +#define B5_DDR 0 +#define B6_DDR 0 +#define B7_DDR 0 +#define B8_DDR 0 +#define B9_DDR 0 +#define B10_DDR 0 +#define B11_DDR 0 +#define B12_DDR 0 +#define B13_DDR 0 +#define B14_DDR 0 +#define B15_DDR 0 + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0_txd0) +# define B0_PAR 1 +#else +# define B0_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0_in) +# undef B0_DDR +# define B0_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0_out0) +# undef B0_DAT +# define B0_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1_rxd0) +# define B1_PAR 1 +#else +# define B1_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1_in) +# undef B1_DDR +# define B1_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1_out0) +# undef B1_DAT +# define B1_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2_cts0) +# define B2_PAR 1 +#else +# define B2_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2_in) +# undef B2_DDR +# define B2_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2_out0) +# undef B2_DAT +# define B2_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3_rts0) +# define B3_PAR 1 +#else +# define B3_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3_in) +# undef B3_DDR +# define B3_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3_out0) +# undef B3_DAT +# define B3_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4_clk0) +# define B4_PAR 1 +#else +# define B4_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4_in) +# undef B4_DDR +# define B4_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4_out0) +# undef B4_DAT +# define B4_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5_ta) +# define B5_PAR 1 +#else +# define B5_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5_in) +# undef B5_DDR +# define B5_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5_out0) +# undef B5_DAT +# define B5_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +# define B6_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB6_in) +# undef B6_DDR +# define B6_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB6_out0) +# undef B6_DAT +# define B6_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB6_out1) +# error GPIO data mismatch +# endif +# endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_tout0) +# define B7_PAR 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_dout3) +# define B7_PAR 2 +#else +# define B7_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_in) +# undef B7_DDR +# define B7_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_out0) +# undef B7_DAT +# define B7_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8_etxd3) +# define B8_PAR 1 +#else +# define B8_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8_in) +# undef B8_DDR +# define B8_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8_out0) +# undef B8_DAT +# define B8_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9_etxd2) +# define B9_PAR 1 +#else +# define B9_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9_in) +# undef B9_DDR +# define B9_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9_out0) +# undef B9_DAT +# define B9_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10_etxd1) +# define B10_PAR 1 +#else +# define B10_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10_in) +# undef B10_DDR +# define B10_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10_out0) +# undef B10_DAT +# define B10_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11_erxd3) +# define B11_PAR 1 +#else +# define B11_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11_in) +# undef B11_DDR +# define B11_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11_out0) +# undef B11_DAT +# define B11_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12_erxd2) +# define B12_PAR 1 +#else +# define B12_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12_in) +# undef B12_DDR +# define B12_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12_out0) +# undef B12_DAT +# define B12_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13_erxd1) +# define B13_PAR 1 +#else +# define B13_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13_in) +# undef B13_DDR +# define B13_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13_out0) +# undef B13_DAT +# define B13_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14_erxer) +# define B14_PAR 1 +#else +# define B14_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14_in) +# undef B14_DDR +# define B14_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14_out0) +# undef B14_DAT +# define B14_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15_e_mdc) +# define B15_PAR 1 +#else +# define B15_PAR 0 +# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15_in) +# undef B15_DDR +# define B15_DDR 1 +# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15_out0) +# undef B15_DAT +# define B15_DAT 0 +# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15_out1) +# error GPIO data mismatch +# endif +# endif +#endif + +#define B_DAT ((B0_DAT << 0) | (B1_DAT << 1) | (B2_DAT << 2) | (B3_DAT << 3) | \ + (B4_DAT << 4) | (B5_DAT << 5) | (B6_DAT << 6) | (B7_DAT << 7) | \ + (B8_DAT << 8) | (B9_DAT << 9) | (B10_DAT << 10) | (B11_DAT << 11) | \ + (B12_DAT << 12) | (B13_DAT << 13) | (B14_DAT << 14) | (B15_DAT << 15)) +#define B_DDR ((B0_DDR << 0) | (B1_DDR << 1) | (B2_DDR << 2) | (B3_DDR << 3) | \ + (B4_DDR << 4) | (B5_DDR << 5) | (B6_DDR << 6) | (B7_DDR << 7) | \ + (B8_DDR << 8) | (B9_DDR << 9) | (B10_DDR << 10) | (B11_DDR << 11) | \ + (B12_DDR << 12) | (B13_DDR << 13) | (B14_DDR << 14) | (B15_DDR << 15)) +#define B_PAR ((B0_PAR << 0) | (B1_PAR << 2) | (B2_PAR << 4) | (B3_PAR << 6) | \ + (B4_PAR << 8) | (B5_PAR << 10) | (B6_PAR << 12) | (B7_PAR << 14) | \ + (B8_PAR << 16) | (B9_PAR << 18) | (B10_PAR << 20) | (B11_PAR << 22) | \ + (B12_PAR << 24) | (B13_PAR << 26) | (B14_PAR << 28) | (B15_PAR << 30)) + +// ---------------------------------------------------------------------------- + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC0_in) +# define C0_DDR 0 +# define C0_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC0_out0) +# define C0_DDR 1 +# define C0_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC0_out1) +# define C0_DDR 1 +# define C0_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC1_in) +# define C1_DDR 0 +# define C1_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC1_out0) +# define C1_DDR 1 +# define C1_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC1_out1) +# define C1_DDR 1 +# define C1_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC2_in) +# define C2_DDR 0 +# define C2_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC2_out0) +# define C2_DDR 1 +# define C2_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC2_out1) +# define C2_DDR 1 +# define C2_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC3_in) +# define C3_DDR 0 +# define C3_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC3_out0) +# define C3_DDR 1 +# define C3_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC3_out1) +# define C3_DDR 1 +# define C3_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC4_in) +# define C4_DDR 0 +# define C4_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC4_out0) +# define C4_DDR 1 +# define C4_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC4_out1) +# define C4_DDR 1 +# define C4_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC5_in) +# define C5_DDR 0 +# define C5_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC5_out0) +# define C5_DDR 1 +# define C5_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC5_out1) +# define C5_DDR 1 +# define C5_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC6_in) +# define C6_DDR 0 +# define C6_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC6_out0) +# define C6_DDR 1 +# define C6_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC6_out1) +# define C6_DDR 1 +# define C6_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC7_in) +# define C7_DDR 0 +# define C7_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC7_out0) +# define C7_DDR 1 +# define C7_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC7_out1) +# define C7_DDR 1 +# define C7_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC8_in) +# define C8_DDR 0 +# define C8_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC8_out0) +# define C8_DDR 1 +# define C8_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC8_out1) +# define C8_DDR 1 +# define C8_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC9_in) +# define C9_DDR 0 +# define C9_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC9_out0) +# define C9_DDR 1 +# define C9_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC9_out1) +# define C9_DDR 1 +# define C9_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC10_in) +# define C10_DDR 0 +# define C10_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC10_out0) +# define C10_DDR 1 +# define C10_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC10_out1) +# define C10_DDR 1 +# define C10_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC11_in) +# define C11_DDR 0 +# define C11_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC11_out0) +# define C11_DDR 1 +# define C11_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC11_out1) +# define C11_DDR 1 +# define C11_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC12_in) +# define C12_DDR 0 +# define C12_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC12_out0) +# define C12_DDR 1 +# define C12_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC12_out1) +# define C12_DDR 1 +# define C12_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC13_in) +# define C13_DDR 0 +# define C13_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC13_out0) +# define C13_DDR 1 +# define C13_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC13_out1) +# define C13_DDR 1 +# define C13_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC14_in) +# define C14_DDR 0 +# define C14_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC14_out0) +# define C14_DDR 1 +# define C14_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC14_out1) +# define C14_DDR 1 +# define C14_DAT 1 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC15_in) +# define C15_DDR 0 +# define C15_DAT 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC15_out0) +# define C15_DDR 1 +# define C15_DAT 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC0_out1) +# define C15_DDR 1 +# define C15_DAT 1 +#else +# error GPIO data mismatch +#endif + +#define C_DAT ((C0_DAT << 0) | (C1_DAT << 1) | (C2_DAT << 2) | (C3_DAT << 3) | \ + (C4_DAT << 4) | (C5_DAT << 5) | (C6_DAT << 6) | (C7_DAT << 7) | \ + (C8_DAT << 8) | (C9_DAT << 9) | (C10_DAT << 10) | (C11_DAT << 11) | \ + (C12_DAT << 12) | (C13_DAT << 13) | (C14_DAT << 14) | (C15_DAT << 15)) +#define C_DDR ((C0_DDR << 0) | (C1_DDR << 1) | (C2_DDR << 2) | (C3_DDR << 3) | \ + (C4_DDR << 4) | (C5_DDR << 5) | (C6_DDR << 6) | (C7_DDR << 7) | \ + (C8_DDR << 8) | (C9_DDR << 9) | (C10_DDR << 10) | (C11_DDR << 11) | \ + (C12_DDR << 12) | (C13_DDR << 13) | (C14_DDR << 14) | (C15_DDR << 15)) + +// ---------------------------------------------------------------------------- + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD0_none) +# define D0_PAR 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD0_dcl0) +# define D0_PAR 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD0_clk1) +# define D0_PAR 2 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1_none) +# define D1_PAR 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1_din0) +# define D1_PAR 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1_rxd1) +# define D1_PAR 2 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2_none) +# define D2_PAR 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2_cts1) +# define D2_PAR 2 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2_qspi_cs2) +# define D2_PAR 3 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3_none) +# define D3_PAR 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3_rts1) +# define D3_PAR 2 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3_int5) +# define D3_PAR 3 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4_none) +# define D4_PAR 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4_dout0) +# define D4_PAR 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4_txd1) +# define D4_PAR 2 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD5_none) +# define D5_PAR 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD5_din3) +# define D5_PAR 2 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD5_int4) +# define D5_PAR 3 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD6_none) +# define D6_PAR 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD6_pwm_out1) +# define D6_PAR 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD6_tout1) +# define D6_PAR 2 +#else +# error GPIO data mismatch +#endif + +#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD7_none) +# define D7_PAR 0 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD7_pwm_out2) +# define D7_PAR 1 +#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD7_tin1) +# define D7_PAR 2 +#else +# error GPIO data mismatch +#endif + +#define D_PAR ((D0_PAR << 0) | (D1_PAR << 2) | (D2_PAR << 4) | (D3_PAR << 6) | \ + (D4_PAR << 8) | (D5_PAR << 10) | (D6_PAR << 12) | (D7_PAR << 14)) diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/mcf5272.c b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/mcf5272.c new file mode 100644 index 0000000..0e5a1a5 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/mcf5272.c @@ -0,0 +1,195 @@ +//========================================================================== +// +// mcf5272.c +// +// MCF5272 processor support functions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> +#include <pkgconf/hal_m68k_mcf5272.h> +#include CYGBLD_HAL_PLATFORM_H +#include <cyg/hal/hal_intr.h> +#include <cyg/infra/cyg_type.h> + +#ifdef CYGHWR_HAL_M68K_MCF5272_GPIO +# include "gpio.c" +#endif + +// ---------------------------------------------------------------------------- +// Processor initialization. +void +hal_m68k_mcf5272_init(void) +{ + int i; + + hal_mcf5272_cacr = CYGNUM_HAL_M68K_MCF5272_CACR; + +#ifdef CYGNUM_HAL_M68K_MCF5272_SCR + // SCR. This is configurable since applications may want different + // bus arbitration schemes. The #ifdef is for backwards compatibility. + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_SCR, CYGNUM_HAL_M68K_MCF5272_SCR); +#endif + + // Set up the GPIO pins if the platform HAL defines the appropriate settings. +#ifdef CYGHWR_HAL_M68K_MCF5272_GPIO + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PADAT, A_DAT); + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PADDR, A_DDR); + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PACNT, A_PAR); + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBDAT, B_DAT); + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBDDR, B_DDR); + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBCNT, B_PAR); + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PCDAT, C_DAT); + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PCDDR, C_DDR); + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PDCNT, D_PAR); +#endif + + // Enable all exceptions. + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_SPR, 0x00FF); + + // If we should enter low power mode when idling, set the PMR here. + // Application programs may tweak it as required. +#if defined(CYGIMP_HAL_M68K_MCF5272_IDLE_run) + // Leave PMR to its default +#elif defined(CYGIMP_HAL_M68K_MCF5272_IDLE_sleep) + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PMR, HAL_MCF5272_PMR_SLPEN); +#elif defined(CYGIMP_HAL_M68K_MCF5272_IDLE_stop) + HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PMR, HAL_MCF5272_PMR_MOS); +#else +# error Unknown low power mode +#endif + + // Make sure that the interrupt controller matches the proc_intr.h + // vector definitions. + HAL_WRITE_UINT8( HAL_MCFxxxx_MBAR + HAL_MCF5272_PIVR, HAL_MCF5272_INT_VEC_BASE); + + // The interrupt controller. All interrupts are set to priority 0, + // disabled until configured. This cannot be done when running on + // top of RedBoot, it would interfere with any devices in use for + // communication e.g. ethernet. +#ifndef CYGSEM_HAL_USE_ROM_MONITOR + for (i = 0; i < 4; i++) { + hal_mcf5272_icr_pri_mirror[i] = 0x0; + } +#endif + + // Exception vectors. First the exceptions themselves. If running + // with a ROM monitor then leave these alone, otherwise claim the + // lot. +#ifndef CYGSEM_HAL_USE_ROM_MONITOR + HAL_VSR_SET(CYGNUM_HAL_VECTOR_SSP, (void*) 0, (void*) 0); + HAL_VSR_SET(CYGNUM_HAL_VECTOR_RESET, &hal_m68k_exception_reset, (void*) 0); + + for (i = CYGNUM_HAL_VECTOR_BUSERR; i < CYGNUM_HAL_VECTOR_SPURINT; i++) { + HAL_VSR_SET(i, &hal_m68k_exception_vsr, (void*) 0); + } + for (i = CYGNUM_HAL_VECTOR_TRAP0; i <= CYGNUM_HAL_VECTOR_TRAPLAST; i++) { + HAL_VSR_SET(i, &hal_m68k_exception_vsr, (void*) 0); + } +#endif + + // All the external interrupts can be handled by the same VSR, the default + // architectural one. + for (i = HAL_MCF5272_INT_VEC_BASE; i < CYGNUM_HAL_VECTOR_RES1; i++) { + HAL_VSR_SET(i, &hal_m68k_interrupt_vsr, (void*) 0); + } +} + +// ---------------------------------------------------------------------------- +// Profiling support. This requires a hardware timer set to interrupt at +// a rate determined by application code. The interrupt handler should +// call __profile_hit() with a single argument, the interrupted PC. +// Timer 2 is used to implement the profiling timer. Timer 3 is already +// allocated for the system clock. Timers 0 and 1 have some extra +// functionality so these are left for application code. +// +// Usually this would involve installing an ISR. However there is no +// easy way for an ISR to get hold of the interrupted PC. In some +// configurations the save state will be stored in hal_saved_interrupt_state, +// but not always. It might be possible to extract the PC from the stack, +// but that gets messy if a separate interrupt stack is used and would be +// vulnerable to changes in the architectural VSR. Instead a custom VSR +// is installed. + +#ifdef CYGFUN_HAL_M68K_MCF5272_PROFILE_TIMER + +extern void hal_mcf5272_profile_vsr(void); + +# include <cyg/profile/profile.h> + +int +hal_enable_profile_timer(int resolution) +{ + // Reset the timer + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TMR, 0); + + // The resolution is a time interval in microseconds. The clock is + // set to tick in microseconds by dividing by the system clock + // value. + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TRR, + resolution - 1); + + // Timer captures are of no interest, but reset them just in case. + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TCN, 0); + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TER, + HAL_MCF5272_TIMER_TER_REF | HAL_MCF5272_TIMER_TER_CAP); + + // Set up the interrupt handler. This is a high-priority interrupt + // so that we can get profiling information for other interrupt + // sources. + HAL_VSR_SET(CYGNUM_HAL_VECTOR_TMR2, &hal_mcf5272_profile_vsr, (cyg_uint32)0); + HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_ISR_TMR2, 6); + HAL_INTERRUPT_UNMASK(CYGNUM_HAL_ISR_TMR2); + + // Now start the timer running. + HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TMR, + ((CYGHWR_HAL_SYSTEM_CLOCK_MHZ - 1) << HAL_MCF5272_TIMER_TMR_PS_SHIFT) | + HAL_MCF5272_TIMER_TMR_ORI | HAL_MCF5272_TIMER_TMR_FRR | + HAL_MCF5272_TIMER_TMR_CLK_MASTER | HAL_MCF5272_TIMER_TMR_RST); + + // The desired resolution is always supported + return resolution; +} +#endif diff --git a/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/mcf5272_profile.S b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/mcf5272_profile.S new file mode 100644 index 0000000..1d3117e --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/mcf5272_profile.S @@ -0,0 +1,81 @@ +// #======================================================================== +// # +// # mcf5272_profile.S +// # +// # Support for gprof-style profiling on an mcf5272 +// # +// #======================================================================== +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================ +//###DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-09-01 +// +//###DESCRIPTIONEND#### +//======================================================================== + +#include <cyg/hal/arch.inc> +#include <cyg/hal/var_io.h> + + .file "mcf5272_profile.S" + + // This VSR should call __profile_hit() with a single argument, + // the interrupted PC. The VSR has been installed as a + // high-priority interrupt source, so there is no need to worry + // about nested interrupts or an interrupt stack. + .extern __profile_hit + + FUNC_START(hal_mcf5272_profile_vsr) + // On entry sp[0] holds sr and sp[1] holds the pc. + // Save the caller-save integer registers. There are no floating + // point registers to worry about. Make space for the argument + // to __profile_hit() while we are at it. + sub.l #20, %sp + movem.l %d0-%d1/%a0-%a1, 4(%sp) + + // Now pick up the interrupted PC from its new offset and push it + // on the stack for __profile_hit(). + move.l 24(%sp),(%sp) + jbsr __profile_hit + + // The timer runs in restart mode, but the interrupt bit has to be reset. + moveq.l # HAL_MCF5272_TIMER_TER_REF, %d0 + move.w %d0, HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TER + + movem.l 4(%sp), %d0-%d1/%a0-%a1 + add.l #20, %sp + rte + + .end diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/ChangeLog b/ecos/packages/hal/m68k/mcf52xx/var/current/ChangeLog new file mode 100644 index 0000000..bd6c529 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/ChangeLog @@ -0,0 +1,186 @@ +2009-04-21 Bart Veer <bartv@ecoscentric.com> + + * include/var_intr.h: fix a couple of typos + +2009-02-09 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h (HAL_MCFxxxx_SDRAMC_DACRx_CBM_xx): fix + definitions. + +2008-11-18 Bart Veer <bartv@ecoscentric.com> + + * whole package. Replace the original M68K port. + +2008-11-17 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl, doc/mcf52xx.sgml, include/hal_diag.h, + include/var_arch.h, include/var_cache.h, include/var_intr.h, + include/var_io.h, src/hal_diag.c, src/mcf52xx_asm.S: minor + clean-ups. + +2008-09-01 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h (HAL_MCF52xx_QSPIx_QCRn_QSPI_CS_CSn): fix typo + +2008-05-08 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h (HAL_MCF52xx_GPTx_PORT): fix typo. + +2008-03-18 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: add definitions for 32-bit CAN devices, PWM, + RTC, MDHA, RNG and SKHA modules which are now common to many + ColdFire processors. + +2008-02-28 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl, src/mcf52xx.c, src/mcf52xx_asm.S: add + variant-level support for a profiling timer using an + mcf5282-compatible PIT. + +2008-02-14 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h, include/var_intr.h: add support for interrupt + controllers with set/clear mask registers. + +2007-03-21 Nick Garnett <nickg@ecoscentric.com> + + * include/var_intr.h (HAL_INTERRUPT_SET_LEVEL): Two-controller + version of this macro was same as single controller version. Fixed + to deal with two controllers. + +2007-02-04 Bart Veer <bartv@ecoscentric.com> + + * src/hal_diag.c (hal_mcf52xx_diag_uart_init): in configurations + where the diag init code can get called multiple times, detect + this and skip reinitializations. + +2006-12-11 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl: add virtual vector support for dynamic + baud rates, for those platforms which support it. + +2006-12-03 Bart Veer <bartv@ecoscentric.com> + + * include/var_intr.h: fix support for processors with two + interrupt controllers. + +2006-10-02 John Dallaway <jld@ecoscentric.com> + + * doc/mcf52xx.sgml: Fix minor typographical errors. + +2006-09-25 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx.sgml: Bring up to date following recent changes in + M68K HALs. + +2006-09-08 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: fix ethernet and uart definitions. Add + QSPI_CS_CSn(). + + * include/var_arch.h: fix typo + + * src/hal_diag.c, include/hal_diag.h, cdl/hal_m68k_mcf52xx.cdl: + Sort out interaction with virtual vectors. + +2006-09-05 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: Use HZ rather than MHZ to calculate SPI baud + rates. + + * include/var_intr.h: HAL_VSR_SET() is now optional. + + * include/var_arch.h: improved versions of the LSBIT() and MSBIT() + HAL macros. + + * src/hal_diag.c, include/hal_diag.h, cdl/hal_m68k_mcf52xx.cdl: + Generalize HAL diagnostics support. + +2006-08-22 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: provide definitions for most of the mcf5282 + on-chip devices, since these are now regularly encountered on + other ColdFires so the definitions can be shared. + + * include/var_intr.h: provide default implementations of various + interrupt/clock/reset macros for processors that have + mcf5282-compatible on-chip devices. + + * include/var.inc: provide default implementations of + hal_context_extract_isr_vector here instead of the processor HALs + + * src/hal_diag.c, include/hal_diag.h: generalize the diagnostics + support, including a bitbucket option. + +2006-03-10 John Dallaway <jld@ecoscentric.com> + + * cdl/hal_m68k_mcf52xx.cdl: Add reference to MCF52xx variant + documentation. + +2005-04-15 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_m68k_mcf52xx.cdl: Define a HAL variant header in + <pkgconf/system.h> + +2004-03-03 Bart Veer <bartv@ecoscentric.com> + + * src/hal_diag.c (hal_mcf52xx_serial_control): Add support for + RedBoot's baudrate command, if appropriate for the platform. + +2004-02-11 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: move cacr/acr/rambar/rombar definitions to the + processor HAL. These are not as generic as initially thought. + + * include/var.inc: make it easier for processors to override + savestate settings. + + * doc/mcf52xx.sgml: update to reflect MCF5282 support + +2003-08-01 Bart Veer <bartv@ecoscentric.com> + + * include/var.inc: hal_context_extract_sr is no longer needed and + has been removed. + +2003-07-22 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx.sgml: fix various typos etc. + +2003-07-17 Bart Veer <bartv@ecoscentric.com> + + * doc/mcf52xx.sgml: Add documentation + +2003-07-08 Bart Veer <bartv@ecoscentric.com> + + * include/var_io.h: + Move some UART definitions to the processor HAL because they are + not available on all MCF52xx processors + +2003-06-04 Bart Veer <bartv@ecoscentric.com> + + * New version of the M68K support + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/cdl/hal_m68k_mcf52xx.cdl b/ecos/packages/hal/m68k/mcf52xx/var/current/cdl/hal_m68k_mcf52xx.cdl new file mode 100644 index 0000000..fe91a6f --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/cdl/hal_m68k_mcf52xx.cdl @@ -0,0 +1,271 @@ +# ==================================================================== +# +# hal_m68k_mcfxxxx.cdl +# +# mcfxxxx variant architectural HAL package configuration data +# +# ==================================================================== +# ####ECOSGPLCOPYRIGHTBEGIN#### +# ------------------------------------------- +# This file is part of eCos, the Embedded Configurable Operating System. +# Copyright (C) 2003, 2005, 2006, 2008 Free Software Foundation, Inc. +# +# eCos is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 or (at your option) any later +# version. +# +# eCos is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License +# along with eCos; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered by +# the GNU General Public License. However the source code for this file +# must still be made available in accordance with section (3) of the GNU +# General Public License v2. +# +# This exception does not invalidate any other reasons why a work based +# on this file might be covered by the GNU General Public License. +# ------------------------------------------- +# ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +#####DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Date: 2003-06-04 +# +#####DESCRIPTIONEND#### +#======================================================================== + +cdl_package CYGPKG_HAL_M68K_MCFxxxx { + display "M68k/ColdFire variant HAL" + doc ref/hal-m68k-mcfxxxx.html + parent CYGPKG_HAL_M68K + requires CYGPKG_HAL_M68K + hardware + include_dir cyg/hal + compile mcf52xx.c mcf52xx_asm.S + + description "The M68k/ColdFire variant HAL package provides + generic support for the Freescale ColdFire family of + processors." + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_m68k_mcfxxxx.h>" + } + + cdl_component CYGPKG_HAL_M68K_MCFxxxx_DIAGNOSTICS { + display "HAL diagnostics support" + flavor none + description " + The MCFxxxx variant HAL has support for outputting diagnostics via an + on-chip UART compatible with the ones found on the MCF5282, or for + discarding all diagnostic output. In some development environments the + diagnostics channel can also be used for communication between gdb + on the host and the gdb stubs on the target. In virtual vector + configurations where the application runs on top of RedBoot the + diagnostics channel is provided by RedBoot so changing the channel + requires reconfiguring RedBoot." + + cdl_interface CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT { + display "Platform uses default MCFxxxx diagnostics support" + flavor bool + description " + The MCFxxxx variant HAL has support for outputting diagnostics via + an on-chip UART compatible with the ones found on the MCF5282. + If a platform can use this default diagnostics support then the + platform HAL will implement this interface. If some other mechanism + should be used for generating diagnostics output, for example because + none of the UARTs are available, then the platform HAL can provide its + own facilities." + + define_proc { + puts $::cdl_header "\#define CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS\t1" + puts $::cdl_header "\#define CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL\t0" + puts $::cdl_header "\#define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL\t0" + } + } + + cdl_option CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT { + display "Port to use for HAL diagnostics" + flavor data + compile hal_diag.c + active_if !CYGSEM_HAL_USE_ROM_MONITOR || CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS + active_if CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT + legal_values { + (CYGHWR_HAL_M68K_MCFxxxx_UART0 ? "uart0" : "") + (CYGHWR_HAL_M68K_MCFxxxx_UART1 ? "uart1" : "") + (CYGHWR_HAL_M68K_MCFxxxx_UART2 ? "uart2" : "") + "<invalid>" + } + requires { CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT != "<invalid>" } + default_value { + CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_DEFAULT ? CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_DEFAULT : + CYGHWR_HAL_M68K_MCFxxxx_UART0 ? "uart0" : + CYGHWR_HAL_M68K_MCFxxxx_UART1 ? "uart1" : + CYGHWR_HAL_M68K_MCFxxxx_UART2 ? "uart2" : + "discard" + } + + description " + This option controls which of the on-chip UARTs will be used for + the HAL diagnostics channel. A UART connected to an RS232 transceiver + is required." + } + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD { + display "Baud rate to use for HAL diagnostics" + flavor data + active_if CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT + legal_values { 9600 19200 38400 115200 } + default_value { is_enabled(CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_DEFAULT_BAUD) ? + CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_DEFAULT_BAUD : 38400 + } + # For platforms which implement dynamic baud rates + define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option selects the baud rate used for the diagnostics port." + } + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_ISRPRI { + display "Interrupt priority for HAL diagnostics UART" + flavor data + active_if CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT + active_if CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + legal_values CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN to CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX + default_value { is_loaded(CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_DIAG) ? + CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_DIAG : CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX } + description " + When the HAL diagnostics channel is used for gdb traffic it may + at times be in interrupt-driven rather than polled mode, to allow + a ctrl-C to halt the application. This configuration option + selects the interrupt priority." + } + } + + + # This component will be filled in by the processor/platform HAL's. + cdl_component CYGPKG_HAL_M68K_MCFxxxx_REGISTERS { + display "Hardware configuration" + flavor none + no_define + description " + ColdFire processors usually have a number of on-chip memories: an + instruction cache, some RAM, and possibly some ROM. Some aspects of + these can be configured by selecting the values for certain key + registers, for example the RAMBAR internal ram base register." + } + + if { 0 } { + cdl_component CYGPKG_HAL_M68K_MCFxxxx_MAC { + display "Support for the MAC unit" + active_if CYGINT_HAL_M68K_MCFxxxx_HARDWARE_MAC + flavor none + description " + If the target processor has a hardware multiply/accumulate unit then + this component defines additional configuration options related + to that unit." + + cdl_option CYGIMP_HAL_M68K_MCFxxxx_MAC_SAVE { + display "Save MAC state during context switch" + default_value 1 + description " + By default the MAC context gets saved during a context switch and + whenever an interrupt occurs. This can be suppressed if the application + does not actually use this unit, or if it does so from only one + thread." + } + } + + cdl_component CYGPKG_HAL_M68K_MCFxxxx_EMAC { + display "Support for the enhanced MAC unit" + active_if CYGINT_HAL_M68K_MCFxxxx_HARDWARE_EMAC + flavor none + description " + If the target processor has an enhanced multiply/accumulate unit then + this component defines additional configuration options related + to that unit." + + cdl_option CYGIMP_HAL_M68K_MCFxxxx_EMAC_SAVE { + display "Save EMAC state during context switch" + default_value 1 + description " + By default the EMAC context gets saved during a context switch and + whenever an interrupt occurs. This can be suppressed if the application + does not actually use this unit, or if it does so from only one + thread." + } + } + } + + cdl_component CYGHWR_HAL_M68K_MCFxxxx_HARDWARE { + display "Optional hardware units" + flavor none + no_define + description " + Some ColdFire hardware units such as the multiply/accumulator are + optional. This component keeps track of which units are actually + available on the current target so that other configuration options + and the eCos source code can adapt accordingly." + + cdl_interface CYGINT_HAL_M68K_MCFxxxx_HARDWARE_MAC { + display "Multiply/accumulate unit" + flavor bool + description " + This interface will be implemented if the specific processor being + used has a MAC (multiply/accumulate) unit." + } + + cdl_interface CYGINT_HAL_M68K_MCFxxxx_HARDWARE_EMAC { + display "Enhanced multiply/accumulate unit" + flavor bool + description " + This interface will be implemented if the specific processor being + used has an EMAC (enhanced multiply/accumulate) unit." + } + } + + cdl_component CYGPKG_HAL_M68K_MCFxxxx_SOFTWARE { + display "Optional software units" + flavor none + no_define + description " + The MCFxxxx variant HAL can provide default implementations of some + software units such as profiling timer support for ColdFire processors + sharing appropriate characteristics." + + cdl_interface CYGINT_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER { + display "Use standard profile timer" + active_if CYGPKG_PROFILE_GPROF + implements CYGINT_PROFILE_HAL_TIMER + flavor bool + + description " + The MCFxxxx variant HAL can provide gprof profiling timer support + on all ColdFire processors with a spare MCF5282-compatible PIT timer." + } + + cdl_option CYGNUM_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER_ISR_PRIORITY { + display "Profile timer interrupt priority" + active_if CYGINT_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER + flavor data + legal_values CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN to CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX + default_value { is_loaded(CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_PROFILING_TIMER) ? + CYGNUM_HAL_M68K_MCFxxxx_ISR_DEFAULT_PRIORITY_PROFILING_TIMER : CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN } + description " + This configuration option controls the priority used for the + profiling timer interrupts. Typically this should be a high + priority, making it possible to get profiling info for lower + priority interrupt handlers when nested interrupt handling + is enabled." + } + } +} diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/doc/mcf52xx.sgml b/ecos/packages/hal/m68k/mcf52xx/var/current/doc/mcf52xx.sgml new file mode 100644 index 0000000..59b3712 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/doc/mcf52xx.sgml @@ -0,0 +1,482 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- mcfxxxx.sgml --> +<!-- --> +<!-- mcfxxxx variant HAL documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): bartv --> +<!-- Contact(s): bartv --> +<!-- Date: 2003/07/15 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<part id="hal-m68k-mcfxxxx"><title>Freescale MCFxxxx Variant Support</title> + +<refentry id="m68k-mcfxxxx"> + <refmeta> + <refentrytitle>MCFxxxx ColdFire Processors</refentrytitle> + </refmeta> + <refnamediv> + <refname><varname>CYGPKG_HAL_M68K_MCFxxxx</varname></refname> + <refpurpose>eCos Support for Freescale MCFxxxx Processors</refpurpose> + </refnamediv> + + <refsect1 id="m68k-mcfxxxx-description"><title>Description</title> + <para> +The Freescale ColdFire family is a range of processors including the +MCF5206 and the MCF5282. From a programmer's perspective these +processors all share basically the same processor core, albeit with +minor differences in the instruction set. They differ in areas like +performance, on-chip peripherals and caches. Even when it comes to +peripherals there is a lot of commonality. For example many but not +all Coldfire processors use the same basic interrupt controller(s) as +the MCF5282. Similarly the on-chip UARTs tend to use the same basic +design although there are variations in the number of UARTs, the fifo +sizes, and in certain details. + </para> + <para> + The MCFxxxx variant HAL package +<varname>CYGPKG_HAL_M68K_MCFxxxx</varname> provides support for +various features that are common to many but not all Coldfire +processors. This includes HAL diagnostics via an on-chip UART and +interrupt controller management for those processors which have +MCF5282-compatible controllers. The variant HAL complements the M68K +architectural HAL package. An eCos configuration should also include a +processor-specific HAL package such as +<varname>CYGPKG_HAL_M68K_MCF5272</varname> to support the +chip-specific peripherals and cache details, and a platform HAL +package such as <varname>CYGPKG_HAL_M68K_M5272C3</varname> to support +board-level details like external memory chips. The processor or +platform HAL can override the functionality provided by the variant +HAL. + </para> + </refsect1> + + <refsect1 id="m68k-mcfxxxx-config"><title>Configuration</title> + <para> +The MCFxxxx variant HAL package should be loaded automatically when +eCos is configured for appropriate target hardware. It should never be +necessary to load this package explicitly. Unloading the package +should only happen as a side effect of switching target hardware. + </para> + <para> +On most ColdFire platforms the variant HAL will provide the HAL +diagnostics support via one of the UARTs. Some platforms may provide +their own HAL diagnostics facility, for example output via an LCD. The +variant HAL diagnostics support is active if the processor or platform +implements the +<varname>CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT</varname> +interface. It is also active only in configurations which do not rely +on an underlying rom monitor such as RedBoot: +if <varname>CYGSEM_HAL_USE_ROM_MONITOR</varname> is enabled then the +default diagnostics channel will automatically be inherited from +RedBoot. The variant HAL then provides a number of configuration +options related to diagnostics: + </para> + <variablelist> + <varlistentry> + <term><varname>CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT</varname></term> + <listitem><para> +This selects the destination for HAL diagnostics. The number of UARTs +available depends on the processor, and on any given board some of the +UARTs may not be connected. Hence the variant HAL looks for +configuration options +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART0</varname>, +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART1</varname> and +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART2</varname> to see which on-chip +UARTs are actually available on the processor and target hardware, and +uses this information to let the user select a UART. + </para> + <para> +When a UART is in use as the HAL diagnostics channel, that UART +should not be used for any other purpose. In particular application +code should avoid using it for I/O via the serial driver. + </para></listitem> + </varlistentry> + <varlistentry> + <term><varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD</varname></term> + <listitem><para> +When a UART is selected for HAL diagnostics this option specifies the +default baud rate. The most common setting is 38400. That provides a +compromise between performance and reliability, especially in +electrically noisy environments such as an industrial environment or a +test farm. Some platforms may define +<varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_DEFAULT_BAUD</varname> +to handle scenarios where another default baud rate is preferable, +typically for compatibility with existing software. + </para></listitem> + </varlistentry> + <varlistentry> + <term><varname>CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_ISRPRI</varname></term> + <listitem><para> +Usually the HAL diagnostics channel is driven in polled mode but in +some scenarios interrupts are required. For example, when debugging an +application over a serial line on top of the gdb stubs provided by +RedBoot, the user should be able to interrupt the application with a +control-C. The application will not be polling the HAL diagnostics +UART at this point so instead the eCos interrupt management code +interacts with the gdb stubs to do the right thing. This configuration +option selects the interrupt priority. It should be noted that on some +processors with MCF5282-compatible interrupt controllers all +priorities for enabled interrupts should be unique, and it is the +responsibility of application developers to ensure this condition is +satisfied. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + + <refsect1 id="m68k-mcfxxxx-port"><title>The HAL Port</title> + <para> +This section describes how the MCFxxxx variant HAL package implements +parts of the eCos HAL specification. It should be read in conjunction +with similar sections from the architectural and processor HAL +documentation. + </para> + + <refsect2 id="m68k-mcfxxxx-port-io"><title>HAL I/O</title> + <para> +The <filename class="headerfile">cyg/hal/var_io.h</filename> header +provides various definitions for on-chip peripherals, where the +current processor has peripherals compatible with the MCF5282's. +This header is automatically included by the architectural +<filename class="headerfile">cyg/hal/hal_io.h</filename> so other +packages and application code will usually only include the latter. + </para> + <para> +It is up to the processor HAL to specify exactly what <filename +class="headerfile">var_io.h</filename> should export. For example the +MCF5213's <filename class="headerfile">proc_io.h</filename> header +contains the following: + </para> + <programlisting width=72> +# define HAL_MCFxxxx_HAS_MCF5282_INTC 1 +# define HAL_MCFxxxx_INTC0_BASE (HAL_MCF521x_IPSBAR + 0x00000C00) + </programlisting> + <para> +This enables support within the variant HAL for a single +MCF5282-compatible interrupt controller, and cases <filename +class="headerfile">var_io.h</filename> to export symbols such as: + </para> + <programlisting width=72> +#ifdef HAL_MCFxxxx_HAS_MCF5282_INTC +// Two 32-bit interrupt mask registers +# define HAL_MCFxxxx_INTCx_IMRH 0x0008 +# define HAL_MCFxxxx_INTCx_IMRL 0x000C +… +# define HAL_MCFxxxx_INTCx_ICRxx_IL_MASK (0x07 << 3) +# define HAL_MCFxxxx_INTCx_ICRxx_IL_SHIFT 3 + </programlisting> + <para> +Symbols such as <varname>HAL_MCFxxxx_INTCx_IMRH</varname> can be used +to access the relevant hardware registers via +<function>HAL_READ_UINT32</function> and +<function>HAL_WRITE_UINT32</function>. Symbols like +<varname>HAL_MCFxxxx_INTCx_ICRxx_IL_MASK</varname> can be used to +generate or decode the contents of the hardware registers. + </para> + <para> +The header file does mostly use a naming convention, but is not +guaranteed to be totally consistent. There may also be discrepancies +with the documentation because the manuals for the various Coldfire +processors are not always consistent about their naming schemes. +All I/O definitions provided by the variant HAL will start with +<literal>HAL_MCFxxxx_</literal>, followed by the name of the +peripheral. If a peripheral is likely to be a singleton, for example +an on-chip flash unit, then the name is unadorned. If there may be +several instances of the peripheral then the name will be followed by +a lower case x. For example: + </para> + <programlisting width=72> +# define HAL_MCFxxxx_CFM_CR 0x0000 +… +# define HAL_MCFxxxx_UARTx_UMR 0x00 + </programlisting> + <para> +Register names will be relative to some base address such as +<varname>HAL_MCFxxxx_CFM_BASE</varname> or +<varname>HAL_MCFxxxx_UART0_BASE</varname>, so code accessing a +register would look like: + </para> + <programlisting width=72> + HAL_READ_UINT32(HAL_MCFxxxx_CFM_BASE + HAL_MCFxxxx_CFM_PROT, reg); + … + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UTB, '*'); + </programlisting> + <para> +Usually the register names are singletons, but in some cases such as +the interrupt controller priority registers there may be multiple +instances of the register and the names will be suffixed +appropriately. For example +<varname>HAL_MCFxxxx_INTCx_ICRxx_IL_MASK</varname> indicates the field +<literal>IL</literal> within one of the <literal>ICR</literal> +registers within one of the interrupt controllers. + </para> + <para> +As mentioned earlier the processor HAL's <filename +class="headerfile">proc_io.h</filename> will control which definitions +are exported by <filename class="headerfile">var_io.h</filename>. +Sometimes the processor HAL will then go on to undefine or redefine +some of the symbols, to reflect incompatibilities between the +processor's devices and the equivalent devices on the MCF5282. There +may also be additional symbols for the devices, and there will be +additional definitions for any processor-specific hardware. In +particular GPIO pin handling is handled by the processor HAL, not by +the variant HAL. Application developers should examine <filename +class="headerfile">proc_io.h</filename> as well as +<filename class="headerfile">var_io.h</filename> and the +processor-specific documentation to see exactly what I/O definitions +are provided. When porting to a new Coldfire processor it is best to +start with an existing processor HAL and copy +code as appropriate. A search for <literal>_HAS_</literal> in +<filename class="headerfile">var_io.h</filename> will also be +informative. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-context"><title>Thread Contexts and Setjmp/Longjmp</title> + <para> +All MCFxxxx processors support interrupts and exceptions in a uniform +way. When an interrupt or exception occurs the hardware pushes the +current program counter, the status register, and an additional 16-bit +word containing information about the interrupt source, for a total of +64 bits. Hence the PCSR part of a thread context consists of two +32-bit integers, and the variant HAL provides appropriate C and +assembler macros to examine and manipulate these. + </para> + <para> +Not all MCFxxxx processors have hardware floating point, so support +for this is left to the processor HAL package. Some MCFxxxx processors +have additional hardware units such as a multiply-accumulator, but +these are not currently supported by eCos. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-diag"><title>HAL Diagnostics</title> + <para> +The various MCFxxxx processors usually have one or more UARTs based on +very similar hardware. The variant HAL package can provide HAL +diagnostic support using such a UART. There are some minor differences +such as fifo sizes, and the UARTs will be accessed at different memory +locations. These differences are handled by a small number of macros +provided by the processor and platform HAL. + </para> + <para> +The MCFxxxx variant HAL only provides HAL diagnostic support via a +UART if the processor or platform HAL does not provide an alternative +implementation. That copes with situations where the on-chip UARTs are +not actually accessible on the target board and an alternative +communication channel must be used. + </para> + <para> +If the variant HAL should implement HAL diagnostics then the processor +or platform HAL should implement the CDL interface +<varname>CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT</varname>. It +should also define one or more of +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART0</varname>, +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART1</varname> and +<varname>CYGHWR_HAL_M68K_MCFxxxx_UART2</varname>, and ensure that any +multi-purpose GPIO pins are set correctly. The variant HAL will take +care of the rest. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-cache"><title>Cache Handling</title> + <para> +The various MCFxxxx processors all have very different caches, so +support for these is deferred to the processor HAL. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-exceptions"><title>Exceptions</title> + <para> +All MCFxxxx processors support synchronous exceptions in a uniform +way, with the hardware pushing sufficient information on to the stack +to identify the nature of the exception. This means that the architectural +entry point <function>hal_m68k_exception_vsr</function> can be used as +the default VSR for all exceptions, with no need for separate +trampoline functions. + </para> + <para> +The variant HAL does not provide any special support for recovering +from exceptions. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-interrupts"><title>Interrupts</title> + <para> +All MCFxxxx processors supports interrupts in a uniform way. When an +interrupt occurs the hardware pushes sufficient information on to the +stack to identify the interrupt. Therefore the architectural entry +point <function>hal_m68k_interrupt_vsr</function> can be used as the +default VSR for all interrupts, with the variant just supplying a +small number of macros that allow the generic code to extract details of +the interrupt source. There is no need for separate trampoline +functions for every interrupt source. + </para> + <para> +On processors which have MCF5282-compatible interrupt and edge port +modules the variant HAL can provide the +<function>HAL_INTERRUPT_MASK</function>, +<function>HAL_INTERRUPT_UNMASK</function>, +<function>HAL_INTERRUPT_SET_LEVEL</function>, +<function>HAL_INTERRUPT_ACKNOWLEDGE</function> and +<function>HAL_INTERRUPT_CONFIGURE</function> macros. There is support +for processors with a single interrupt controller or with two separate +interrupt controllers. Otherwise these macros are left to the +processor HAL. The allocation of interrupt vectors to the various +on-chip devices is also a characteristic of the processor HAL. +<filename class="headerfile">proc_intr.h</filename> should be +consulted for appropriate definitions, for example +<varname>CYGNUM_HAL_ISR_UART0</varname>. + </para> + <para> +The mask and umask operations are straightforward: if the interrupt +controller has the <literal>SIMR</literal> and <literal>CIMR</literal> +registers those will be used; otherwise the <literal>IRM</literal> +registers will be updated by a read-modify-write cycle. The +acknowledge macro is only relevant for external interrupts coming in +via the edge port module and will clear the interrupt by writing to +the <literal>EPIER</literal> register. There is no simple way to clear +interrupts generated by the on-chip peripherals, so that is the +responsibility of the various device drivers or of application code. +The configure macro is only relevant for external interrupts and +involves manipulating the edge port module. + </para> + <para> +The <function>HAL_INTERRUPT_SET_LEVEL</function> macro is used +implicitly by higher level code such as +<function>cyg_interrupt_create</function>. With MCF5282-compatible +interrupt controllers the priority level corresponds to +the <literal>ICRxx</literal> register. The exact format depends on the +processor. Interrupt priorities corresponding to IPL level 7 are +non-maskable. Such interrupts cannot be managed safely by the usual +eCos ISR and DSR mechanisms. Instead application code will have to +install a custom VSR and manage the entire interrupt. + </para> + <para> +Some MCF5282-compatible interrupt controllers have a major +restriction: all interrupt priorities within each controller must be +unique. If two interrupts go off at the same time and have exactly the +same priority then the controllers' behaviour is undefined. In a +typical application some of the interrupts will be handled by eCos +device drivers while others will be handled directly by application +code. Since eCos cannot know which interrupts may get used, it cannot +allocate unique priorities. Instead this has to be left to the +application developer. eCos does provide configuration options such as +<varname>CYGNUM_KERNEL_COUNTERS_CLOCK_ISR_PRIORITY</varname> and +<varname>CYGNUM_DEVS_SERIAL_MCFxxxx_SERIAL0_ISR_PRIORITY</varname> to +provide control over the eCos-managed interrupts, and provides default +values for these which are unique. + </para> + <caution><para> +Non-unique interrupt priorities can lead to very confusing system +behaviour. For example on an MCF5282, if the PIT3 system clock +(interrupt 0x3a) and ethernet RX frame (interrupt 0x1b) are +accidentally given the same priority and go off at the same time, the +interrupt controller may actually issue an interrupt 0x3b, the bitwise +or of the two interrupt numbers. That interrupt belongs to the on-chip +flash module. There may not be an installed handler for that interrupt +at all, and even if there is a handler it will only manipulate the +flash hardware and not clear the system clock and ethernet interrupts. +Hence the system is likely to go into a spin, continually trying to +service the wrong interrupt. To track down such problems during +debugging it may prove useful to install a breakpoint on the +<function>hal_arch_default_isr</function> function. + </para></caution> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-clock"><title>Clock Support</title> + <para> +On processors with an MCF5282-compatible programmable interrupt timer +module or PIT, the variant HAL can provide the +<function>HAL_CLOCK_INITIALIZE</function>, +<function>HAL_CLOCK_RESET</function>, +<function>HAL_CLOCK_READ</function> and +<function>HAL_CLOCK_LATENCY</function> macros. These macros are used +by the eCos kernel to implement the system clock and may be used for +other purposes in non-kernel configurations. When multiple timers are +available it is up to the processor or platform HAL to select which +one gets used for the system clock. It is also up to the processor or +platform HAL to provide various clock-related configuration options +such as <varname>CYGNUM_HAL_RTC_PERIOD</varname>. Those options need +to take into account the processor clock speed, which is usually a +characteristic of the platform and hence not known to the variant HAL. + </para> + <para> +When porting to a new Coldfire processor, the processor or platform +HAL should define the symbols +<varname>CYGNUM_HAL_INTERRUPT_RTC</varname>, +<varname>_HAL_MCFxxxx_CLOCK_PIT_BASE_</varname>, and +<varname>_HAL_MCFxxxx_CLOCK_PIT_PRE_</varname>. Existing ports can be +examined for more details. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-reset"><title>Reset</title> + <para> +On processors with an MCF5282-compatible reset module or RST, the +variant HAL can provide the <function>HAL_PLATFORM_RESET</function> +macro. That macro is typically used by the gdb stubs support inside +RedBoot to reset the hardware between debug sessions, ensuring that +each session runs in as close to pristine hardware as possible. The +macro uses the <literal>SOFTRST</literal> bit of the +<varname>RCR</varname> register. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-bitindex"><title>Bit Indexing</title> + <para> +By default the variant HAL will provide versions of +<function>HAL_LSBIT_INDEX</function> and +<function>HAL_MSBIT_INDEX</function> which are more efficient than the +default ones in the architectural HAL. The implementation uses the +<command>ff1.l</command> and <command>bitrev.l</command> instructions. +If the Coldfire processor does not support these instructions then +the processor HAL should define +<varname>_HAL_M68K_MCFxxxx_NO_FF1_</varname>. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-other-hal"><title>Other Issues</title> + <para> +The MCFxxxx variant HAL does not affect the implementation of data +types, stack size definitions, idle thread processing, linker scripts, +SMP support, system startup, or debug support. + </para> + </refsect2> + + <refsect2 id="m68k-mcfxxxx-port-other"><title>Other Functionality</title> + <para> +The MCFxxxx variant HAL only implements functionality defined in the +eCos HAL specification and does not export any additional functions. + </para> + </refsect2> + </refsect1> +</refentry> + +</part> diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/include/hal_diag.h b/ecos/packages/hal/m68k/mcf52xx/var/current/include/hal_diag.h new file mode 100644 index 0000000..a9470a4 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/include/hal_diag.h @@ -0,0 +1,116 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// MCFxxxx HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_if.h> + +// On most ColdFire platforms the mcfxxxx variant HAL provides the HAL +// diagnostics support via a UART. The +// CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT interface +// enables this. +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) && !defined(CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS) +# include <cyg/hal/hal_if.h> +# define HAL_DIAG_INIT() hal_if_diag_init() +# define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +# define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#elif !defined(CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT) +// Allow the platform HAL to provide the diagnostics channel. +# include <cyg/hal/plf_diag.h> +#else + +externC void hal_mcfxxxx_diag_uart_init(cyg_uint8*, cyg_uint32); +externC void hal_mcfxxxx_diag_uart_putc(void*, char c); +externC cyg_uint8 hal_mcfxxxx_diag_uart_getc(void*); + +# if defined(CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_uart0) +# define _HAL_MCFxxxx_DIAG_UART_BASE_ HAL_MCFxxxx_UART0_BASE +# define _HAL_MCFxxxx_DIAG_UART_ISRVEC_ CYGNUM_HAL_ISR_UART0 +# elif defined(CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_uart1) +# define _HAL_MCFxxxx_DIAG_UART_BASE_ HAL_MCFxxxx_UART1_BASE +# define _HAL_MCFxxxx_DIAG_UART_ISRVEC_ CYGNUM_HAL_ISR_UART1 +# elif defined(CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT_uart2) +# define _HAL_MCFxxxx_DIAG_UART_BASE_ HAL_MCFxxxx_UART2_BASE +# define _HAL_MCFxxxx_DIAG_UART_ISRVEC_ CYGNUM_HAL_ISR_UART2 +# else +# error Diagnostics channel UART base not defined. +# endif + +// Even if the standard diagnostics facilities are enabled, allow the +// platform HAL to override things. +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() \ + CYG_MACRO_START \ + hal_mcfxxxx_diag_uart_init((cyg_uint8*) (_HAL_MCFxxxx_DIAG_UART_BASE_), \ + CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD); \ + CYG_MACRO_END +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(_c_) \ + CYG_MACRO_START \ + hal_mcfxxxx_diag_uart_putc((void*)_HAL_MCFxxxx_DIAG_UART_BASE_, _c_); \ + CYG_MACRO_END +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(_c_) \ + CYG_MACRO_START \ + (_c_) = hal_mcfxxxx_diag_uart_getc((void*)(_HAL_MCFxxxx_DIAG_UART_BASE_)); \ + CYG_MACRO_END +# endif + +#endif // VV/MCFxxxx_DIAGNOSTICS + +#endif /* CYGONCE_HAL_DIAG_H */ diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/include/var.inc b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var.inc new file mode 100644 index 0000000..9720976 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var.inc @@ -0,0 +1,116 @@ +##============================================================================= +## +## var.inc +## +## mcfxxxx variant assembler header file +## +##============================================================================= +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): bartv +## Date: 2003-06-04 +######DESCRIPTIONEND#### +##============================================================================= + +// ---------------------------------------------------------------------------- +// Generic support for the MAC and eMAC units. +// Not yet implemented. + +// ---------------------------------------------------------------------------- +// Now include the cpu-specific header, which can define context macros +// including the MAC, eMAC, and possibly other state +#include <cyg/hal/proc.inc> + +// ---------------------------------------------------------------------------- +// Thread context support. Usually this is generic for all ColdFires, +// but it is possible for processor or platform code to override +// these definitions. + +// The 68K exception and interrupt VSR's can be used directly since the +// vector number is part of the hardware state automatically pushed onto +// the stack. Since there are no trampolines there is no need to adjust +// the stack before returning. +#ifndef HAL_CONTEXT_PCSR_RTE_ADJUST +# define HAL_CONTEXT_PCSR_RTE_ADJUST 0 +#endif + +#ifndef HAL_CONTEXT_PCSR_SAVE_SR_DEFINED + .macro hal_context_pcsr_save_sr reg=%sp,off=0,scratch=%d0 + mov.l #0x40000000, \scratch + mov.w %sr, \scratch + mov.l \scratch, (hal_context_pcsr_offset+\off)(\reg) + .endm +#endif + +// Get the ISR vector out of the context. This is encoded in one +// byte in the exception frame. There are two versions depending +// on the number of ISR vectors. If < 64, i.e. if an interrupt +// falls in the range 64 <= isrvec < 128, then a simple mask +// will do the trick. If > 164, i.e. if an interrupt falls in +// the range 64 <= isrvec < 256, then a subtract is required. + +#ifndef HAL_CONTEXT_EXTRACT_ISR_DEFINED + +# if HAL_M68K_VSR_COUNT > 128 + + .macro hal_context_extract_isr_vector_shl2 reg=%sp,off=0,isr + mov.w (hal_context_pcsr_offset+\off)(\reg),\isr + andi.l #0x03FC, \isr + subi.l #0x0100, \isr + .endm + + .macro hal_context_extract_isr_vector reg=%sp,off=0,isr + mov.w (hal_context_pcsr_offset+\off)(\reg),\isr + andi.l #0x03FC, \isr + lsr.l #2, \isr + subi.l #0x040, \isr + .endm + +# else + .macro hal_context_extract_isr_vector_shl2 reg=%sp,off=0,isr + mov.w (hal_context_pcsr_offset+\off)(\reg),\isr + andi.l #0x00FC, \isr + .endm + + .macro hal_context_extract_isr_vector reg=%sp,off=0,isr + mov.w (hal_context_pcsr_offset+\off)(\reg),\isr + andi.l #0x0FC, \isr + lsr.l #2, \isr + .endm +# endif +#endif + +#------------------------------------------------------------------------------ +# end of var.inc diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_arch.h b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_arch.h new file mode 100644 index 0000000..9261c36 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_arch.h @@ -0,0 +1,145 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// Architecture variant specific abstractions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/proc_arch.h> + +// ---------------------------------------------------------------------------- +// Context support. ColdFire exceptions/interrupts are simpler than the +// 68000 variants, with a much more regular exception frame. Usually the +// hardware simply pushes two longs on to the stack. The program counter +// is at the top. Then the 16-bit status register. Then some extra +// information identifying the exception number etc. If the stack was not +// aligned when the exception occurred) (which should not happen for +// eCos code) then the hardware will do some extra stack alignment and +// store this information in a fmt field. That possibility is ignored +// for now. + +#define HAL_CONTEXT_PCSR \ + cyg_uint32 sr_vec; \ + CYG_ADDRESS pc; + +// An exception aligns the stack to a 32-bit boundary, and the fmt part +// of the exception frame encodes how much adjustment was done. The +// 0x40000000 specifies 0 bytes adjustment since the code should be +// running with stacks always aligned. +#define HAL_CONTEXT_PCSR_INIT(_regs_, _entry_, _sr_) \ + CYG_MACRO_START \ + (_regs_)->sr_vec = 0x40000000 | (cyg_uint32)(_sr_); \ + (_regs_)->pc = (CYG_ADDRESS)(_entry_); \ + CYG_MACRO_END + +#define HAL_CONTEXT_PCSR_GET_SR(_regs_, _sr_) \ + CYG_MACRO_START \ + _sr_ = (_regs_)->sr_vec & 0x0000FFFF; \ + CYG_MACRO_END + +#define HAL_CONTEXT_PCSR_GET_PC(_regs_, _pc_) \ + CYG_MACRO_START \ + _pc_ = (_regs_)->pc; \ + CYG_MACRO_END + +#define HAL_CONTEXT_PCSR_SET_SR(_regs_, _sr_) \ + CYG_MACRO_START \ + (_regs_)->sr_vec = ((_regs_)->sr_vec & 0xFFFF0000) | (_sr_); \ + CYG_MACRO_END + +#define HAL_CONTEXT_PCSR_SET_PC(_regs_, _pc_) \ + CYG_MACRO_START \ + (_regs_)->pc = (CYG_ADDRESS)(_pc_); \ + CYG_MACRO_END + +#define HAL_CONTEXT_PCSR_GET_EXCEPTION(_regs_, _code_) \ + CYG_MACRO_START \ + (_code_) = (((_regs_)->sr_vec) >> 18) & 0x000000FF; \ + CYG_MACRO_END + +// ---------------------------------------------------------------------------- +// LSBIT/MSBIT. Most ColdFires have ff1 and bitrev instructions which +// allow for more efficient implementations than the default ones in +// the architectural HAL. +#ifndef _HAL_M68K_MCFxxxx_NO_FF1_ +# define HAL_LSBIT_INDEX(_index_, _mask_) \ + CYG_MACRO_START \ + cyg_uint32 _tmp_ = (_mask_); \ + int _idx_; \ + if (0 == _tmp_) { \ + _idx_ = -1; \ + } else { \ + __asm__ volatile ( \ + "move.l %1, %0 ; \n" \ + "bitrev.l %0 ; \n" \ + "ff1.l %0 ; \n" \ + : "=d" (_idx_) \ + : "d" (_mask_) \ + ); \ + } \ + _index_ = _idx_; \ + CYG_MACRO_END + +# define HAL_MSBIT_INDEX(_index_, _mask_) \ + CYG_MACRO_START \ + cyg_uint32 _tmp_ = (_mask_); \ + int _idx_; \ + __asm__ volatile ( \ + "move.l %1, %0 ; \n" \ + "ff1.l %0\n" \ + : "=d" (_idx_) \ + : "d" (_tmp_) \ + ); \ + _index_ = 31 - _idx_; \ + CYG_MACRO_END + +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_ARCH_H + diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_cache.h b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_cache.h new file mode 100644 index 0000000..14adb46 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_cache.h @@ -0,0 +1,54 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H +//============================================================================= +// +// var_cache.h +// +// mcfxxxx cache details +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +// Most ColdFires have caches, but the details vary widely. For now +// always leave it up to the processor HAL. +#include <cyg/hal/proc_cache.h> + +#endif // ifndef CYGONCE_VAR_CACHE_H diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_intr.h b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_intr.h new file mode 100644 index 0000000..b07f0ee --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_intr.h @@ -0,0 +1,498 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// mcfxxxx Variant interrupt and clock support +// +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2006, 2007, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// Include any processor specific interrupt definitions. +#include <cyg/hal/proc_intr.h> + +// ColdFire defines some extra exceptions +// The debug vector is for hardware breakpoints. These are not used +// at present. +#define CYGNUM_HAL_VECTOR_DEBUG 12 +#define CYGNUM_HAL_VECTOR_FORMAT 14 + +// The following implementation should suffice for most platforms. If +// any of them need special VSR's then they can define their own version. +#if !defined(HAL_VSR_SET_TO_ECOS_HANDLER) && !defined(_HAL_M68K_NO_VSR_SET_) +# define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_) \ + CYG_MACRO_START \ + if ( (_vector_) <= CYGNUM_HAL_VECTOR_TRAPLAST) { \ + HAL_VSR_SET( (_vector_), &hal_m68k_exception_vsr, (_poldvsr_) ); \ + } else { \ + HAL_VSR_SET( (_vector_), &hal_m68k_interrupt_vsr, (_poldvsr_) ); \ + } \ + CYG_MACRO_END +#endif + +// ---------------------------------------------------------------------------- +// On ColdFires with 5282-style interrupt controllers, many of the +// interrupt-related macros can be provided here rather than duplicated +// in the processor HALs. Of course there complications, for example there +// may be one or two interrupt controllers. + +#ifdef HAL_MCFxxxx_HAS_MCF5282_INTC + +# ifndef HAL_INTERRUPT_MASK +// Masking interrupts is straightforward: there are 32-bit read-write +// mask registers. Often the vector argument will be a constant so the +// compiler gets a chance to optimise these macros. There is also some +// compile-time optimization based around the maximum number of +// interrupt vectors. to avoid worrying about interrupts 32-63 if only +// the bottom half of INTC0 is of interest, or interrupts 96-127 if +// only the bottom half of INTC1 is of interest. +// +// Some newer ColdFires have additional set/clear mask registers. + +# ifdef HAL_MCFxxxx_INTCx_SIMR +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_MASK(_vector_) \ + CYG_MACRO_START \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_SIMR, (_vector_)); \ + CYG_MACRO_END +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_MASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if (_vec_ < 64) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_SIMR, _vec_); \ + } else { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_SIMR, _vec_ - 64); \ + } \ + CYG_MACRO_END +# else +# error At most two interrupt controllers supported at present. +# endif +# else // ! SIMR +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_MASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _shift_ = (_vector_); \ + cyg_uint32 _reg_; \ + cyg_uint32 _bits_; \ + if ( (CYGNUM_HAL_ISR_MAX < 32) || (_shift_ < 32)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + } else { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + _shift_ -= 32; \ + } \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ |= (0x01 << _shift_); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + CYG_MACRO_END +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_MASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _shift_ = (_vector_); \ + cyg_uint32 _reg_; \ + cyg_uint32 _bits_; \ + if ( (CYGNUM_HAL_ISR_MAX < 32) || (_shift_ < 32)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + } else if ((CYGNUM_HAL_ISR_MAX < 64) || (_shift_ < 64)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + _shift_ -= 32; \ + } else if ((CYGNUM_HAL_ISR_MAX < 96) || (_shift_ < 96)) { \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + _shift_ -= 64; \ + } else { \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + _shift_ -= 96; \ + } \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ |= (0x01 << _shift_); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + CYG_MACRO_END +# else +# error At most two interrupt controllers supported at present. +# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many +# endif // SIMR +# endif // !defined(HAL_INTERRUPT_MASK) + +// Care has to be taken with bit 0 of the IMRL registers. Writing a 1 to +// this masks all interrupts. +# ifndef HAL_INTERRUPT_UNMASK +# ifdef HAL_MCFxxxx_INTCx_CIMR +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_UNMASK(_vector_) \ + CYG_MACRO_START \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_CIMR, (_vector_)); \ + CYG_MACRO_END +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_UNMASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if (_vec_ < 64) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_CIMR, _vec_); \ + } else { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_CIMR, _vec_ - 64); \ + } \ + CYG_MACRO_END +# else +# error At most two interrupt controllers supported at present. +# endif +# else +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_UNMASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + cyg_uint32 _reg_; \ + cyg_uint32 _bits_; \ + if ( (CYGNUM_HAL_ISR_MAX < 32) || (_vec_ < 32)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~((0x01 << _vec_) | 0x01); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } else { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~(0x01 << (_vec_ - 32)); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } \ + CYG_MACRO_END +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_UNMASK(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + cyg_uint32 _reg_; \ + cyg_uint32 _bits_; \ + if ( (CYGNUM_HAL_ISR_MAX < 32) || (_vec_ < 32)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~((0x01 << _vec_) | 0x01); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } else if ((CYGNUM_HAL_ISR_MAX < 64) || (_vec_ < 64)) { \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~(0x01 << (_vec_ - 32)); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } else if ((CYGNUM_HAL_ISR_MAX < 96) || (_vec_ < 96)) { \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRL; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~((0x01 << (_vec_ - 64)) | 0x01); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } else { \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRH; \ + HAL_READ_UINT32(_reg_, _bits_); \ + _bits_ &= ~(0x01 << (_vec_ - 96)); \ + HAL_WRITE_UINT32(_reg_, _bits_); \ + } \ + CYG_MACRO_END +# else +# error At most two interrupt controllers supported at present. +# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many +# endif // HAL_MCFxxxx_INTCx_CIMR +# endif // !defined(HAL_INTERRUPT_UNMASK) + +# ifndef HAL_INTERRUPT_SET_LEVEL +// Each interrupt vector has its own priority register. This consists +// of an M68K IPL level between 1 and 7, plus a priority within each +// level between 0 and 7, giving a total of 56 legal priorities. All +// active interrupt vectors within each interrupt vector must be given +// unique priorities, otherwise the system's behaviour is undefined +// (and can include the interrupt controller supplying the wrong +// interrupt vector in the IACK cycle). +# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC) + +# define HAL_INTERRUPT_SET_LEVEL(_vector_, _prilevel_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + cyg_uint32 _reg_; \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_; \ + HAL_WRITE_UINT8(_reg_, _prilevel_); \ + CYG_MACRO_END + +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC) +# define HAL_INTERRUPT_SET_LEVEL(_vector_, _prilevel_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + cyg_uint32 _reg_; \ + if( _vec_ < 64 ) \ + _reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_; \ + else \ + _reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_ - 64;\ + HAL_WRITE_UINT8(_reg_, _prilevel_); \ + CYG_MACRO_END + +# else +# error At most two interrupt controllers supported at present. +# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many +# endif // !defined(HAL_INTERRUPT_SET_LEVEL) + +#endif // HAL_MCFxxxx_HAS_MCF5282_INTC + +#ifdef HAL_MCFxxxx_HAS_MCF5282_EPORT +// There is no acknowledgement support inside the interrupt +// controller. Instead each device has its own way of clearing the +// interrupt, so it is left to device drivers to clear interrupts at +// an appropriate time. The exception is for the edge port interrupts +// which can be handled easily here. +# ifndef HAL_INTERRUPT_ACKNOWLEDGE +# if (1 == HAL_MCFxxxx_HAS_MCF5282_EPORT) + +# define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT0_BASE + HAL_MCFxxxx_EPORTx_EPFR, \ + 0x01 << (_vec_ - HAL_MCFxxxx_EPORT0_VECBASE)); \ + } \ + CYG_MACRO_END + +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_EPORT) +# define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT0_BASE + HAL_MCFxxxx_EPORTx_EPFR, \ + 0x01 << (_vec_ - HAL_MCFxxxx_EPORT0_VECBASE)); \ + } else if ((_vec_ >= HAL_MCFxxxx_EPORT1_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT1_VECMAX)) { \ + HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT1_BASE + HAL_MCFxxxx_EPORTx_EPFR, \ + 0x01 << (_vec_ - HAL_MCFxxxx_EPORT1_VECBASE)); \ + } \ + CYG_MACRO_END + + +# else +# error At most two edge port modules are supported at present. +# endif // HAL_MCFxxxx_HAS_MCF5282_EPORT == 1/2/many +# endif // !defined(HAL_INTERRUPT_ACKNOWLEDGE) + +# ifndef HAL_INTERRUPT_CONFIGURE + +// Interrupt level/edge control only applies to the edge port +// interrupts. It is possible to select level-low, rising edge, or +// falling edge. The hardware does not support level-high. It does +// support rising-or-falling edge, but the eCos API does not export +// that functionality. Instead code can manipulate the edge port +// registers directly. +// +// This macro also manipulates the edge port data direction and +// interrupt enable registers, to ensure that the edge port really +// will generate interrupts. + +# if (1 == HAL_MCFxxxx_HAS_MCF5282_EPORT) + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_triggered_, _up_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \ + cyg_uint32 _base_; \ + cyg_uint16 _reg16_; \ + cyg_uint8 _reg8_; \ + _base_ = HAL_MCFxxxx_EPORT0_BASE; \ + _vec_ -= HAL_MCFxxxx_EPORT0_VECBASE; \ + HAL_READ_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \ + _reg16_ &= ~(0x03 << (2 * _vec_)); \ + if (_level_triggered_) { \ + /* 00 is level-triggered so nothing to be done */ \ + } else if (_up_) { \ + _reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING << (2 * _vec_)); \ + } else { \ + _reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING << (2 * _vec_)); \ + } \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \ + HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \ + _reg8_ &= ~(0x01 << _vec_); \ + HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \ + HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \ + _reg8_ |= (0x01 << _vec_); \ + HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \ + } \ + CYG_MACRO_END + +# elif (2 == HAL_MCFxxxx_HAS_MCF5282_EPORT) + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_triggered_, _up_) \ + CYG_MACRO_START \ + cyg_uint32 _vec_ = (_vector_); \ + if (((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) || \ + ((_vec_ >= HAL_MCFxxxx_EPORT1_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT1_VECMAX))) { \ + cyg_uint32 _base_; \ + cyg_uint16 _reg16_; \ + cyg_uint8 _reg8_; \ + if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \ + _base_ = HAL_MCFxxxx_EPORT0_BASE; \ + _vec_ -= HAL_MCFxxxx_EPORT0_VECBASE; \ + } else { \ + _base_ = HAL_MCFxxxx_EPORT1_BASE; \ + _vec_ -= HAL_MCFxxxx_EPORT1_VECBASE; \ + } \ + HAL_READ_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \ + _reg16_ &= ~(0x03 << (2 * _vec_)); \ + if (_level_triggered_) { \ + /* 00 is level-triggered so nothing to be done */ \ + } else if (_up_) { \ + _reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING << (2 * _vec_)); \ + } else { \ + _reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING << (2 * _vec_)); \ + } \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \ + HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \ + _reg8_ &= ~(0x01 << _vec_); \ + HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \ + HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \ + _reg8_ |= (0x01 << _vec_); \ + HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \ + } \ + CYG_MACRO_END + +# else +# endif // HAL_MCFxxxx_HAS_MCF5282_EPORT == 1/2/many +# endif // !defined(HAL_INTERRUPT_CONFIGURE) + +#endif + +#ifndef HAL_INTERRUPT_MASK +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_MASK() macro +#endif +#ifndef HAL_INTERRUPT_UNMASK +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_UNMASK() macro +#endif +#ifndef HAL_INTERRUPT_SET_LEVEL +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_SET_LEVEL() macro +#endif +#ifndef HAL_INTERRUPT_ACKNOWLEDGE +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_ACKNOWLEDGE() macro +#endif +#ifndef HAL_INTERRUPT_CONFIGURE +# error Processor or platform HAL_ should have provided HAL_INTERRUPT_CONFIGURE() macro +#endif + +// ---------------------------------------------------------------------------- +// On ColdFires with 5282-style programmable interrupt timers, typically +// one of those will be used for the system clock. +#ifdef HAL_MCFxxxx_HAS_MCF5282_PIT + +# if (!defined(HAL_CLOCK_INIITALIZE) || !defined(HAL_CLOCK_RESET) || !defined(HAL_CLOCK_READ)) +# if !defined(_HAL_MCFxxxx_CLOCK_PIT_BASE_) +# error The processor HAL should specify the programmable interrupt timer used for the system clock +# elif !defined(_HAL_MCFxxxx_CLOCK_PIT_PRE_) +# error The processor or platform HAL should specify the timer prescaler +# else + +# if !defined(HAL_CLOCK_INITIALIZE) +# define HAL_CLOCK_INITIALIZE(_period_) \ + CYG_MACRO_START \ + cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \ + _HAL_MCFxxxx_CLOCK_PIT_PRE_ | \ + HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \ + HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD); \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PMR, _period_); \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \ + _HAL_MCFxxxx_CLOCK_PIT_PRE_ | \ + HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \ + HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD | \ + HAL_MCFxxxx_PITx_PCSR_EN); \ + CYG_MACRO_END +# endif + +# if !defined(HAL_CLOCK_RESET) +// The clock resets automatically but the interrupt must be cleared. This could +// be done by rewriting the period, but that introduces a risk of drift. A +// better approach is to write the PIF bit in the control register, which means +// writing all the other bits as well. +// +// Note: this could interfere with power management since the doze/halted +// bits may get cleared inadvertently. +# define HAL_CLOCK_RESET(_vector_, _period_) \ + CYG_MACRO_START \ + cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \ + HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \ + _HAL_MCFxxxx_CLOCK_PIT_PRE_ | \ + HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \ + HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD | \ + HAL_MCFxxxx_PITx_PCSR_EN); \ + CYG_MACRO_END +# endif + +# if !defined(HAL_CLOCK_READ) +# define HAL_CLOCK_READ(_pvalue_) \ + CYG_MACRO_START \ + cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \ + cyg_uint16 _period_, _counter_; \ + HAL_READ_UINT16(_base_ + HAL_MCFxxxx_PITx_PMR, _period_); \ + HAL_READ_UINT16(_base_ + HAL_MCFxxxx_PITx_PCNTR, _counter_); \ + *(_pvalue_) = _period_ - _counter_; \ + CYG_MACRO_END +# endif +# endif +# endif +#endif + +#ifndef HAL_CLOCK_INITIALIZE +# error Processor or platform HAL should have provided HAL_CLOCK_INITIALIZE() macro +#endif +#ifndef HAL_CLOCK_RESET +# error Processor or platform HAL should have provided HAL_CLOCK_RESET() macro +#endif +#ifndef HAL_CLOCK_READ +# error Processor or platform HAL should have provided HAL_CLOCK_READ() macro +#endif + +#ifndef HAL_CLOCK_LATENCY +# define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_) +#endif + +// ---------------------------------------------------------------------------- +// Where possible use a 5282-compatible reset controller to generate a +// software reset. The architectural HAL has a fall-back +// implementation which goes through the reset exception vector slot. +#if !defined(HAL_PLATFORM_RESET) && defined(HAL_MCFxxxx_HAS_MCF5282_RST) +# define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + HAL_WRITE_UINT8(HAL_MCFxxxx_RST_BASE + HAL_MCFxxxx_RST_RCR, \ + HAL_MCFxxxx_RST_RCR_SOFTRST); \ + CYG_MACRO_END +# endif + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_VAR_INTR_H diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_io.h b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_io.h new file mode 100644 index 0000000..0dd21df --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/include/var_io.h @@ -0,0 +1,2111 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H + +//============================================================================= +// +// var_io.h +// +// Details of mcfxxxx memory-mapped hardware +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2008, 2009 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//============================================================================= + +// Most coldfire processors share some/most of their on-chip +// peripherals with the mcf5282, so that is treated as the base +// device. The goal is to reduce the effort needed to support each +// ColdFire processor. The processor HAL still has the ability to +// override any of the settings to cope with differences between +// its processor and the 5282, with a small risk that device drivers +// are tied too closely to the 5282 implementation and need extra +// effort. The processor HAL also has to supply some information that +// is inherently too processor-specific, e.g. interrupt assignments +// and GPIO pin management. +// +// This header is #include'd by hal_io.h from the architectural HAL. +// It then #include's proc_io.h for the first time, giving the processor +// HAL a chance to define symbols such as: +// +// HAL_MCFxxxx_HAS_MCF5282_WD +// HAL_MCFxxxx_WD_BASE +// HAL_MCFxxxx_HAS_MCF5282_ETH +// HAL_MCFxxxx_ETH0_BASE +// +// The value of HAS_MCF5282_<module> corresponds to the number of +// devices. The _BASE symbols correspond to the absolute base +// addresses, e.g. (IPSBAR+0x0C00). For singleton devices there will +// be only a single base addresses, otherwise separate base addresses +// should be supplied for each device instance. +// +// Once the processor HAL has defined which mcf5282-compatible devices +// are present, this header file provides the appropriate I/O +// definitions. proc_io.h is then #include'd again so that it can undo +// some of these definitions, e.g. when some h/w functionality +// available on the 5282 is not present, or to extend the definitions +// if a device offers more than functionality than the 5282 +// equivalent. Definitions for devices not present on a 5282 can be +// provided by either the first or second pass of proc_io.h. Finally +// proc_io.h will include plf_io.h, allowing platform-specific code to +// override some of the definitions or to provide additional ones for +// off-chip devices. +// +// During the second pass through proc_io.h, if a processor HAL +// #undef's a var_io.h definition then that can cause problems with +// device driver portability. There is no perfect way to handle that, +// if h/w is not 100% compatible then device drivers will struggle. +// Additional symbols will typically not be used by device drivers so +// do not cause any portability problems, but eCos will not exploit +// the extra functionality either. +// +// Symbols take the form: +// HAL_MCFxxxx_<module>_<register> +// HAL_MCFxxxx_<module>x_<register> +// HAL_MCFxxxx_<module>_<register>_<field> +// HAL_MCFxxxx_<module>x_<register>_<field> +// +// The x version is used when there may be multiple instances of a +// given device, e.g. multiple UARTs or multiple interrupt +// controllers. + +// First read in the processor-specific header so we know which +// peripherals are common. The header will be read in again at +// the end to allow the processor HAL to override some of the +// settings defined here. +#include <cyg/hal/proc_io.h> + +// ---------------------------------------------------------------------------- +// System registers. Note that these are not memory-mapped, they are +// accessed via the movec instruction. + +// The cache control register and the access control registers +// go together. +#ifdef HAL_MCFxxxx_HAS_MCF5282_CACR_ACR +# define HAL_MCFxxxx_CACR 0x0002 +# define HAL_MCFxxxx_CACR_CENB (0x01 << 31) +# define HAL_MCFxxxx_CACR_CPD (0x01 << 28) +# define HAL_MCFxxxx_CACR_CPDI (0x01 << 28) +# define HAL_MCFxxxx_CACR_CFRZ (0x01 << 27) +# define HAL_MCFxxxx_CACR_CINV (0x01 << 24) +# define HAL_MCFxxxx_CACR_DISI (0x01 << 23) +# define HAL_MCFxxxx_CACR_DISD (0x01 << 22) +# define HAL_MCFxxxx_CACR_INVI (0x01 << 21) +# define HAL_MCFxxxx_CACR_INVD (0x01 << 20) +# define HAL_MCFxxxx_CACR_CEIB (0x01 << 10) +# define HAL_MCFxxxx_CACR_DCM (0x01 << 9) +# define HAL_MCFxxxx_CACR_DBWE (0x01 << 8) +# define HAL_MCFxxxx_CACR_DWP (0x01 << 5) +# define HAL_MCFxxxx_CACR_EUSP (0x01 << 4) +# define HAL_MCFxxxx_CACR_CLNF_MASK (0x03 << 0) +# define HAL_MCFxxxx_CACR_CLNF_SHIFT 0 + +// The two access control registers. These provide some control +// over external memory accesses. +# define HAL_MCFxxxx_ACR0 0x0004 +# define HAL_MCFxxxx_ACR1 0x0005 + +# define HAL_MCFxxxx_ACRx_AB_MASK (0x00FF << 24) +# define HAL_MCFxxxx_ACRx_AB_SHIFT 24 +# define HAL_MCFxxxx_ACRx_AM_MASK (0x00FF << 16) +# define HAL_MCFxxxx_ACRx_AM_SHIFT 16 +# define HAL_MCFxxxx_ACRx_EN (0x01 << 15) +# define HAL_MCFxxxx_ACRx_SM_MASK (0x03 << 13) +# define HAL_MCFxxxx_ACRx_SM_SHIFT 13 +# define HAL_MCFxxxx_ACRx_SM_USER_ONLY (0x00 << 13) +# define HAL_MCFxxxx_ACRx_SM_SUPERVISOR_ONLY (0x01 << 13) +# define HAL_MCFxxxx_ACRx_SM_ALWAYS (0x02 << 13) +# define HAL_MCFxxxx_ACRx_CM (0x01 << 6) +# define HAL_MCFxxxx_ACRx_BUFW (0x01 << 5) +# define HAL_MCFxxxx_ACRx_BWE (0x01 << 5) +# define HAL_MCFxxxx_ACRx_WP (0x01 << 2) +#endif // HAL_MCFxxxx_HAS_MCF5282_CACR_ACR + +#ifdef HAL_MCFxxxx_HAS_MCF5282_RAMBAR +# define HAL_MCFxxxx_RAMBAR 0x0C05 +# define HAL_MCFxxxx_RAMBAR_BA_MASK (0x00FFFF0000 << 0) +# define HAL_MCFxxxx_RAMBAR_BA_SHIFT 0 +# define HAL_MCFxxxx_RAMBAR_PRI_MASK (0x03 << 10) +# define HAL_MCFxxxx_RAMBAR_PRI_SHIFT 10 +# define HAL_MCFxxxx_RAMBAR_PRI_CPU_CPU (0x03 << 10) +# define HAL_MCFxxxx_RAMBAR_PRI_CPU_DMA (0x02 << 10) +# define HAL_MCFxxxx_RAMBAR_PRI_DMA_CPU (0x01 << 10) +# define HAL_MCFxxxx_RAMBAR_PRI_DMA_DMA (0x00 << 10) +# define HAL_MCFxxxx_RAMBAR_SPV (0x01 << 9) +# define HAL_MCFxxxx_RAMBAR_WP (0x01 << 8) +# define HAL_MCFxxxx_RAMBAR_CI (0x01 << 5) +# define HAL_MCFxxxx_RAMBAR_SC (0x01 << 4) +# define HAL_MCFxxxx_RAMBAR_SD (0x01 << 3) +# define HAL_MCFxxxx_RAMBAR_UC (0x01 << 2) +# define HAL_MCFxxxx_RAMBAR_UD (0x01 << 1) +# define HAL_MCFxxxx_RAMBAR_V (0x01 << 0) +#endif + +#ifdef HAL_MCFxxxx_HAS_MCF5282_FLASHBAR +# define HAL_MCFxxxx_FLASHBAR 0x0C04 +# define HAL_MCFxxxx_FLASHBAR_BA_MASK (0x00FFF80000 << 0) +# define HAL_MCFxxxx_FLASHBAR_BA_SHIFT 0 +# define HAL_MCFxxxx_FLASHBAR_WP (0x01 << 8) +# define HAL_MCFxxxx_FLASHBAR_CI (0x01 << 5) +# define HAL_MCFxxxx_FLASHBAR_SC (0x01 << 4) +# define HAL_MCFxxxx_FLASHBAR_SD (0x01 << 3) +# define HAL_MCFxxxx_FLASHBAR_UC (0x01 << 2) +# define HAL_MCFxxxx_FLASHBAR_UD (0x01 << 1) +# define HAL_MCFxxxx_FLASHBAR_V (0x01 << 0) +#endif + +#ifdef HAL_MCFxxxx_HAS_MCF5282_VBR +# define HAL_MCFxxxx_VBR 0x0801 +#endif + +// ---------------------------------------------------------------------------- +// SCM. For convenience this encapsulates the SCM system control +// module, the PMM power management module, the CCM chip configuration +// module, and the CLOCK clock module. These are interrelated in +// various ways, so are likely to be all present or all absent. + +#ifdef HAL_MCFxxxx_HAS_MCF5282_SCM_PMM_CLOCK_CCM +// IPSBAR, 32 bits, controls the base address of the on-chip +// peripherals. This is equivalent to the MBAR register on other +// processors, but is only accessible via IPSBAR rather than as a +// control register. This is a bit strange - in theory IPSBAR could be +// disabled, making it inaccessible without a reset. +# define HAL_MCFxxxx_SCM_IPSBAR 0x00000000 +// RAMBAR, 32 bits. In practise this should always be a copy of the +// control register, or rather of the bits that are supported in the SCM. +# define HAL_MCFxxxx_SCM_RAMBAR 0x00000008 +// Core reset status register, 8 bits. +# define HAL_MCFxxxx_SCM_CRSR 0x00000010 +// Core watchdog control register, 8 bits. +# define HAL_MCFxxxx_SCM_CWCR 0x00000011 +// Core watchdog service register, 8 bits +# define HAL_MCFxxxx_SCM_CWSR 0x00000013 +// Bus master park register, 32 bits +# define HAL_MCFxxxx_SCM_MPARK 0x0000001C +// Master privilege register, 8 bits +# define HAL_MCFxxxx_SCM_MPR 0x00000020 +// The access control registers, 9 * 8 bits. +# define HAL_MCFxxxx_SCM_PACR0 0x00000024 +# define HAL_MCFxxxx_SCM_PACR1 0x00000025 +# define HAL_MCFxxxx_SCM_PACR2 0x00000026 +# define HAL_MCFxxxx_SCM_PACR3 0x00000027 +# define HAL_MCFxxxx_SCM_PACR4 0x00000028 +# define HAL_MCFxxxx_SCM_PACR5 0x0000002A +# define HAL_MCFxxxx_SCM_PACR6 0x0000002B +# define HAL_MCFxxxx_SCM_PACR7 0x0000002C +# define HAL_MCFxxxx_SCM_PACR8 0x0000002E +# define HAL_MCFxxxx_SCM_GPACR0 0x00000030 +# define HAL_MCFxxxx_SCM_GPACR1 0x00000031 + + +# define HAL_MCFxxxx_SCM_IPSBAR_BA_MASK 0xC0000000 +# define HAL_MCFxxxx_SCM_IPSBAR_BA_SHIFT 30 +# define HAL_MCFxxxx_SCM_IPSBAR_V (0x01 << 0) + +# define HAL_MCFxxxx_SCM_RAMBAR_BA_MASK (0x00FFFF << 16) +# define HAL_MCFxxxx_SCM_RAMBAR_BA_SHIFT 16 +# define HAL_MCFxxxx_SCM_RAMBAR_BDE (0x01 << 9) + +# define HAL_MCFxxxx_SCM_CRSR_EXT (0x01 << 7) +# define HAL_MCFxxxx_SCM_CRSR_CWDR (0x01 << 5) + +# define HAL_MCFxxxx_SCM_CWCR_CWE (0x01 << 7) +# define HAL_MCFxxxx_SCM_CWCR_CWRI (0x01 << 6) +# define HAL_MCFxxxx_SCM_CWCR_CWT_MASK (0x07 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_SHIFT 3 +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_9 (0x00 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_11 (0x01 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_13 (0x02 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_15 (0x03 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_19 (0x04 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_23 (0x05 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_27 (0x06 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWT_2_31 (0x07 << 3) +# define HAL_MCFxxxx_SCM_CWCR_CWTA (0x01 << 2) +# define HAL_MCFxxxx_SCM_CWCR_CWTAVAL (0x01 << 1) +# define HAL_MCFxxxx_SCM_CWCR_CWTIF (0x01 << 0) + +// The magic values that should be written to the watchdog service register +# define HAL_MCFxxxx_SCM_CWSR_MAGIC0 0x0055 +# define HAL_MCFxxxx_SCM_CWSR_MAGIC1 0x00AA + +// Bus master parking. M3 is ethernet, M2 is DMA, M1 is internal, +// M0 is the ColdFire core. +# define HAL_MCFxxxx_SCM_MPARK_M2_P_EN (0x01 << 25) +# define HAL_MCFxxxx_SCM_MPARK_BCR24BIT (0x01 << 24) +# define HAL_MCFxxxx_SCM_MPARK_M3_PRTY_MASK (0x03 << 22) +# define HAL_MCFxxxx_SCM_MPARK_M3_PRTY_SHIFT 22 +# define HAL_MCFxxxx_SCM_MPARK_M2_PRTY_MASK (0x03 << 20) +# define HAL_MCFxxxx_SCM_MPARK_M2_PRTY_SHIFT 20 +# define HAL_MCFxxxx_SCM_MPARK_M0_PRTY_MASK (0x03 << 18) +# define HAL_MCFxxxx_SCM_MPARK_M0_PRTY_SHIFT 18 +# define HAL_MCFxxxx_SCM_MPARK_M1_PRTY_MASK (0x03 << 16) +# define HAL_MCFxxxx_SCM_MPARK_M1_PRTY_SHIFT 16 +# define HAL_MCFxxxx_SCM_MPARK_FIXED (0x01 << 14) +# define HAL_MCFxxxx_SCM_MPARK_TIMEOUT (0x01 << 13) +# define HAL_MCFxxxx_SCM_MPARK_PRKLAST (0x01 << 12) +# define HAL_MCFxxxx_SCM_MPARK_LCKOUT_TIME_MASK (0x0F << 8) +# define HAL_MCFxxxx_SCM_MPARK_LCKOUT_TIME_SHIFT 8 + +# define HAL_MCFxxxx_SCM_MPR_M3 (0x01 << 3) +# define HAL_MCFxxxx_SCM_MPR_M2 (0x01 << 2) +# define HAL_MCFxxxx_SCM_MPR_M1 (0x01 << 1) +# define HAL_MCFxxxx_SCM_MPR_M0 (0x01 << 0) + +// Each access control register is split into two nibbles +# define HAL_MCFxxxx_SCM_PACRx_LOCK1 (0x01 << 7) +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL1_MASK (0x07 << 4) +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL1_SHIFT 4 +# define HAL_MCFxxxx_SCM_PACRx_LOCK0 (0x01 << 3) +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL0_MASK (0x07 << 0) +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL0_SHIFT 0 + +// The access granted. Separated into supervisor and user. +// R for read access, W for write access, N for no-access. +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_RW 0x04 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_R 0x05 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_N 0x00 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_R_R 0x02 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_R_N 0x01 +# define HAL_MCFxxxx_SCM_PACRx_ACCESS_N_N 0x07 + +// Exactly which PACR nibbles control which on-chip peripherals +// is a processor property so defined in proc_io.h + +# define HAL_MCFxxxx_SCM_GPACR_LOCK (0x01 << 7) +# define HAL_MCFxxxx_SCM_GPACR_ACCESS_CTRL_MASK (0x0F << 0) +# define HAL_MCFxxxx_SCM_GPACR_ACCESS_CTRL_SHIFT 0 + +// Read/Write/eXecute/No access in supervisor and user modes +# define HAL_MCFxxxx_SCM_GPACR_RW_N 0x00 +# define HAL_MCFxxxx_SCM_GPACR_R_N 0x01 +# define HAL_MCFxxxx_SCM_GPACR_R_R 0x02 +# define HAL_MCFxxxx_SCM_GPACR_RW_RW 0x04 +# define HAL_MCFxxxx_SCM_GPACR_RW_R 0x05 +# define HAL_MCFxxxx_SCM_GPACR_N_N 0x07 +# define HAL_MCFxxxx_SCM_GPACR_RWX_N 0x08 +# define HAL_MCFxxxx_SCM_GPACR_RX_N 0x09 +# define HAL_MCFxxxx_SCM_GPACR_RX_RX 0x0A +# define HAL_MCFxxxx_SCM_GPACR_X_N 0x0B +# define HAL_MCFxxxx_SCM_GPACR_RWX_RWX 0x0C +# define HAL_MCFxxxx_SCM_GPACR_RWX_RX 0x0D +# define HAL_MCFxxxx_SCM_GPACR_RWX_X 0x0F + +// Power management. This can get confusing because there is an +// overlap with the chip configuration module, the reset module, and +// the system controller module. There are two registers, one in the +// SCM part of the address space, the other in the reset +// controller/chip configuration. Assume a single device. + +// 8-bit interrupt control register +# define HAL_MCFxxxx_PMM_LPICR 0x00000012 +// 8-bit control register. +# define HAL_MCFxxxx_PMM_LPCR 0x00110007 + +# define HAL_MCFxxxx_PMM_LPICR_ENBSTOP (0x01 << 7) +# define HAL_MCFxxxx_PMM_LPICR_XLPM_IPL_MASK (0x07 << 4) +# define HAL_MCFxxxx_PMM_LPICR_XLPM_IPL_SHIFT 4 + +# define HAL_MCFxxxx_PMM_LPCR_LPMD_MASK (0x03 << 6) +# define HAL_MCFxxxx_PMM_LPCR_LPMD_SHIFT 6 +# define HAL_MCFxxxx_PMM_LPCR_LPMD_STOP (0x03 << 6) +# define HAL_MCFxxxx_PMM_LPCR_LPMD_WAIT (0x02 << 6) +# define HAL_MCFxxxx_PMM_LPCR_LPMD_DOZE (0x01 << 6) +# define HAL_MCFxxxx_PMM_LPCR_LPMD_RUN (0x00 << 6) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_MASK (0x03 << 3) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_SHIFT 3 +# define HAL_MCFxxxx_PMM_LPCR_STPMD_CLKOUT_PLL_OSC_PMM (0x00 << 3) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_PLL_OSC_PMM (0x01 << 3) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_OSC_PMM (0x02 << 3) +# define HAL_MCFxxxx_PMM_LPCR_STPMD_PMM (0x03 << 3) +# define HAL_MCFxxxx_PMM_LPCR_LVDSE (0x01 << 1) + +// The clock module. Assume a single device. +// Synthesizer control register, 16 bits +# define HAL_MCFxxxx_CLOCK_SYNCR 0x00120000 +// Synthesizer status register, 8 bits +# define HAL_MCFxxxx_CLOCK_SYNSR 0x00120002 + +# define HAL_MCFxxxx_CLOCK_SYNCR_LOLRE (0x01 << 15) +# define HAL_MCFxxxx_CLOCK_SYNCR_MFD_MASK (0x07 << 12) +# define HAL_MCFxxxx_CLOCK_SYNCR_MFD_SHIFT 12 +# define HAL_MCFxxxx_CLOCK_SYNCR_LOCRE (0x01 << 11) +# define HAL_MCFxxxx_CLOCK_SYNCR_RFD_MASK (0x07 << 8) +# define HAL_MCFxxxx_CLOCK_SYNCR_RFD_SHIFT 8 +# define HAL_MCFxxxx_CLOCK_SYNCR_LOCEN (0x01 << 7) +# define HAL_MCFxxxx_CLOCK_SYNCR_DISCLK (0x01 << 6) +# define HAL_MCFxxxx_CLOCK_SYNCR_FWKUP (0x01 << 5) +# define HAL_MCFxxxx_CLOCK_SYNCR_STPMD_MASK (0x03 << 2) +# define HAL_MCFxxxx_CLOCK_SYNCR_STPMD_SHIFT 2 + +# define HAL_MCFxxxx_CLOCK_SYNSR_PLLMODE (0x01 << 7) +# define HAL_MCFxxxx_CLOCK_SYNSR_PLLSEL (0x01 << 6) +# define HAL_MCFxxxx_CLOCK_SYNSR_PLLREF (0x01 << 5) +# define HAL_MCFxxxx_CLOCK_SYNSR_LOCKS (0x01 << 4) +# define HAL_MCFxxxx_CLOCK_SYNSR_LOCK (0x01 << 3) +# define HAL_MCFxxxx_CLOCK_SYNSR_LOCS (0x01 << 2) + +// Chip configuration module +// Four 16-bit registers: chip configuration, low-power control, reset +// configuration, and chip identification. LPCR is described in the +// power management section. +# define HAL_MCFxxxx_CCM_CCR 0x00110004 +# define HAL_MCFxxxx_CCM_RCON 0x00110008 +# define HAL_MCFxxxx_CCM_CIR 0x0011000A + +# define HAL_MCFxxxx_CCM_CCR_LOAD (0x01 << 15) +# define HAL_MCFxxxx_CCM_CCR_MODE_MASK (0x07 << 8) +# define HAL_MCFxxxx_CCM_CCR_MODE_SHIFT 8 +# define HAL_MCFxxxx_CCM_CCR_MODE_SINGLE_CHIP (0x06 << 8) +# define HAL_MCFxxxx_CCM_CCR_MODE_MASTER (0x07 << 8) +# define HAL_MCFxxxx_CCM_CCR_SZEN (0x01 << 6) +# define HAL_MCFxxxx_CCM_CCR_PSTEN (0x01 << 5) +# define HAL_MCFxxxx_CCM_CCR_BME (0x01 << 3) +# define HAL_MCFxxxx_CCM_CCR_BMT_MASK (0x07 << 0) +# define HAL_MCFxxxx_CCM_CCR_BMT_SHIFT 0 +# define HAL_MCFxxxx_CCM_CCR_BMT_65536 0x00 +# define HAL_MCFxxxx_CCM_CCR_BMT_32768 0x01 +# define HAL_MCFxxxx_CCM_CCR_BMT_16384 0x02 +# define HAL_MCFxxxx_CCM_CCR_BMT_8192 0x03 +# define HAL_MCFxxxx_CCM_CCR_BMT_4096 0x04 +# define HAL_MCFxxxx_CCM_CCR_BMT_2048 0x05 +# define HAL_MCFxxxx_CCM_CCR_BMT_1024 0x06 +# define HAL_MCFxxxx_CCM_CCR_BMT_512 0x07 + +# define HAL_MCFxxxx_CCM_RCON_RCSC_MASK (0x03 << 8) +# define HAL_MCFxxxx_CCM_RCON_RCSC_SHIFT 8 +# define HAL_MCFxxxx_CCM_RCON_RPLLSEL (0x01 << 7) +# define HAL_MCFxxxx_CCM_RCON_RPLLREF (0x01 << 6) +# define HAL_MCFxxxx_CCM_RCON_RLOAD (0x01 << 5) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_MASK (0x03 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_SHIFT 3 +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_INTERNAL (0x00 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_16 (0x01 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_8 (0x02 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTPS_32 (0x03 << 3) +# define HAL_MCFxxxx_CCM_RCON_BOOTSEL (0x01 << 2) +# define HAL_MCFxxxx_CCM_RCON_MODE (0x01 << 0) + +# define HAL_MCF5282_CCM_CIR_PIN_MASK (0x00FF << 8) +# define HAL_MCF5282_CCM_CIR_PIN_SHIFT 8 +# define HAL_MCF5282_CCM_CIR_PRN_MASK (0x00FF << 0) +# define HAL_MCF5282_CCM_CIR_PRN_SHIFT 0 + +#endif // HAL_MCFxxxx_HAS_MCF5282_SCM_PMM_CLOCK_CCM + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_RST +// Reset controller +// Two 8-bit registers, reset control and reset status +# define HAL_MCFxxxx_RST_RCR 0x00000000 +# define HAL_MCFxxxx_RST_RSR 0x00000001 + +# define HAL_MCFxxxx_RST_RCR_SOFTRST (0x01 << 7) +# define HAL_MCFxxxx_RST_RCR_FRCRSTOUT (0x01 << 6) +# define HAL_MCFxxxx_RST_RCR_LVDF (0x01 << 4) +# define HAL_MCFxxxx_RST_RCR_LVDIE (0x01 << 3) +# define HAL_MCFxxxx_RST_RCR_LVDRE (0x01 << 2) +# define HAL_MCFxxxx_RST_RCR_LVDE (0x01 << 0) + +# define HAL_MCFxxxx_RST_RSR_LVD (0x01 << 6) +# define HAL_MCFxxxx_RST_RSR_SOFT (0x01 << 5) +# define HAL_MCFxxxx_RST_RSR_WDR (0x01 << 4) +# define HAL_MCFxxxx_RST_RSR_POR (0x01 << 3) +# define HAL_MCFxxxx_RST_RSR_EXT (0x01 << 2) +# define HAL_MCFxxxx_RST_RSR_LOC (0x01 << 1) +# define HAL_MCFxxxx_RST_RSR_LOL (0x01 << 0) +#endif + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_WD +// Watchdog timer. Only a single device. +// Four 16-bit registers: control, modulus, count and service +# define HAL_MCFxxxx_WD_WCR 0x00000000 +# define HAL_MCFxxxx_WD_WMR 0x00000002 +# define HAL_MCFxxxx_WD_WCNTR 0x00000004 +# define HAL_MCFxxxx_WD_WSR 0x00000006 + +# define HAL_MCFxxxx_WD_WCR_WAIT (0x01 << 3) +# define HAL_MCFxxxx_WD_WCR_DOZE (0x01 << 2) +# define HAL_MCFxxxx_WD_WCR_HALTED (0x01 << 1) +# define HAL_MCFxxxx_WD_WCR_EN (0x01 << 0) + +// The modulus and count registers are just 16 bits of counter data +// The magic numbers for the service register +# define HAL_MCF5282_WD_WSR_MAGIC0 0x5555 +# define HAL_MCF5282_WD_WSR_MAGIC1 0xAAAA + +#endif // HAL_MCFxxxx_HAS_MCF5282_WD + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_CS +// Chip select module. Assume a single device. + +// Seven sets of registers, a 16-bit address register, a 32-bit +// mask register and a 16-bit control register +# define HAL_MCFxxxx_CS_CSAR0 0x00000080 +# define HAL_MCFxxxx_CS_CSMR0 0x00000084 +# define HAL_MCFxxxx_CS_CSCR0 0x0000008A +# define HAL_MCFxxxx_CS_CSAR1 0x0000008C +# define HAL_MCFxxxx_CS_CSMR1 0x00000090 +# define HAL_MCFxxxx_CS_CSCR1 0x00000096 +# define HAL_MCFxxxx_CS_CSAR2 0x00000098 +# define HAL_MCFxxxx_CS_CSMR2 0x0000009C +# define HAL_MCFxxxx_CS_CSCR2 0x000000A2 +# define HAL_MCFxxxx_CS_CSAR3 0x000000A4 +# define HAL_MCFxxxx_CS_CSMR3 0x000000A8 +# define HAL_MCFxxxx_CS_CSCR3 0x000000AE +# define HAL_MCFxxxx_CS_CSAR4 0x000000B0 +# define HAL_MCFxxxx_CS_CSMR4 0x000000B4 +# define HAL_MCFxxxx_CS_CSCR4 0x000000BA +# define HAL_MCFxxxx_CS_CSAR5 0x000000BC +# define HAL_MCFxxxx_CS_CSMR5 0x000000C0 +# define HAL_MCFxxxx_CS_CSCR5 0x000000C6 +# define HAL_MCFxxxx_CS_CSAR6 0x000000C8 +# define HAL_MCFxxxx_CS_CSMR6 0x000000CC +# define HAL_MCFxxxx_CS_CSCR6 0x000000D2 + +// The address register is just the top 16 bits of the address. +# define HAL_MCFxxxx_CS_CSMRx_BAM_MASK (0x00FFFF << 16) +# define HAL_MCFxxxx_CS_CSMRx_BAM_SHIFT 16 +# define HAL_MCFxxxx_CS_CSMRx_WP (0x01 << 8) +# define HAL_MCFxxxx_CS_CSMRx_AM (0x01 << 6) +# define HAL_MCFxxxx_CS_CSMRx_CI (0x01 << 5) +# define HAL_MCFxxxx_CS_CSMRx_SC (0x01 << 4) +# define HAL_MCFxxxx_CS_CSMRx_SD (0x01 << 3) +# define HAL_MCFxxxx_CS_CSMRx_UC (0x01 << 2) +# define HAL_MCFxxxx_CS_CSMRx_UD (0x01 << 1) +# define HAL_MCFxxxx_CS_CSMRx_V (0x01 << 0) + +# define HAL_MCFxxxx_CS_CSCRx_WS_MASK (0x000F << 10) +# define HAL_MCFxxxx_CS_CSCRx_WS_SHIFT 10 +# define HAL_MCFxxxx_CS_CSCRx_AA (0x01 << 8) +# define HAL_MCFxxxx_CS_CSCRx_PS_MASK (0x03 << 6) +# define HAL_MCFxxxx_CS_CSCRx_PS_SHIFT 6 +# define HAL_MCFxxxx_CS_CSCRx_PS_32 (0x00 << 6) +# define HAL_MCFxxxx_CS_CSCRx_PS_8 (0x01 << 6) +# define HAL_MCFxxxx_CS_CSCRx_PS_16 (0x02 << 6) +# define HAL_MCFxxxx_CS_CSCRx_BEM (0x01 << 5) +# define HAL_MCFxxxx_CS_CSCRx_BSTR (0x01 << 4) +# define HAL_MCFxxxx_CS_CSCRx_BSTW (0x01 << 3) + +#endif // HAL_MCFxxxx_HAS_MCF5282_CS + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_SDRAMC +// SDRAM controller. Assume a single device. + +// A 16-bit overall control register +# define HAL_MCFxxxx_SDRAMC_DCR 0x00000040 +// Two sets of two 32-bit registers +# define HAL_MCFxxxx_SDRAMC_DACR0 0x00000048 +# define HAL_MCFxxxx_SDRAMC_DMR0 0x0000004C +# define HAL_MCFxxxx_SDRAMC_DACR1 0x00000050 +# define HAL_MCFxxxx_SDRAMC_DMR1 0x00000054 + +# define HAL_MCFxxxx_SDRAMC_DCR_NAM (0x01 << 13) +# define HAL_MCFxxxx_SDRAMC_DCR_COC (0x01 << 12) +# define HAL_MCFxxxx_SDRAMC_DCR_IS (0x01 << 11) +# define HAL_MCFxxxx_SDRAMC_DCR_RTIM_MASK (0x03 << 9) +# define HAL_MCFxxxx_SDRAMC_DCR_RTIM_SHIFT 9 +# define HAL_MCFxxxx_SDRAMC_DCR_RC_MASK (0x01FF << 0) +# define HAL_MCFxxxx_SDRAMC_DCR_RC_SHIFT 0 + +# define HAL_MCFxxxx_SDRAMC_DACRx_BA_MASK (0x03FFF << 18) +# define HAL_MCFxxxx_SDRAMC_DACRx_BA_SHIFT 18 +# define HAL_MCFxxxx_SDRAMC_DACRx_RE (0x01 << 15) +# define HAL_MCFxxxx_SDRAMC_DACRx_CASL_MASK (0x03 << 12) +# define HAL_MCFxxxx_SDRAMC_DACRx_CASL_SHIFT 12 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_MASK (0x07 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_SHIFT 8 +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_17 (0x00 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_18 (0x01 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_19 (0x02 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_20 (0x03 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_21 (0x04 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_22 (0x05 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_23 (0x06 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_24 (0x07 << 8) +# define HAL_MCFxxxx_SDRAMC_DACRx_IMRS (0x01 << 6) +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_MASK (0x03 << 4) +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_SHIFT 4 +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_32 (0x00 << 4) +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_8 (0x01 << 4) +# define HAL_MCFxxxx_SDRAMC_DACRx_PS_16 (0x02 << 4) +# define HAL_MCFxxxx_SDRAMC_DACRx_IP (0x01 << 3) + +# define HAL_MCFxxxx_SDRAMC_DMRx_BA_MASK (0x03FFF << 18) +# define HAL_MCFxxxx_SDRAMC_DMRx_BA_SHIFT 18 +# define HAL_MCFxxxx_SDRAMC_DMRx_WP (0x01 << 8) +# define HAL_MCFxxxx_SDRAMC_DMRx_CI (0x01 << 6) +# define HAL_MCFxxxx_SDRAMC_DMRx_AM (0x01 << 5) +# define HAL_MCFxxxx_SDRAMC_DMRx_SC (0x01 << 4) +# define HAL_MCFxxxx_SDRAMC_DMRx_SD (0x01 << 3) +# define HAL_MCFxxxx_SDRAMC_DMRx_UC (0x01 << 2) +# define HAL_MCFxxxx_SDRAMC_DMRx_UD (0x01 << 1) +# define HAL_MCFxxxx_SDRAMC_DMRx_V (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_SDRAMC + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_CFM + +// The CFM module - on-chip flash. Assume a single device. +// Configuration register, 16 bits. +# define HAL_MCFxxxx_CFM_CR 0x0000 +// Clock divider register, 8 bits. +# define HAL_MCFxxxx_CFM_CLKD 0x0002 +// Security register, 32 bits +# define HAL_MCFxxxx_CFM_SEC 0x0008 +// Protection register, 32 bits +# define HAL_MCFxxxx_CFM_PROT 0x0010 +// Supervisor access register, 32 bits +# define HAL_MCFxxxx_CFM_SACC 0x0014 +// Data access register, 32 bits +# define HAL_MCFxxxx_CFM_DACC 0x0018 +// User status register, 8 bits +# define HAL_MCFxxxx_CFM_USTAT 0x0020 +// Command register, 8 bits +# define HAL_MCFxxxx_CFM_CMD 0x0024 + +# define HAL_MCFxxxx_CFM_CR_LOCK (0x01 << 10) +# define HAL_MCFxxxx_CFM_CR_PVIE (0x01 << 9) +# define HAL_MCFxxxx_CFM_CR_AEIE (0x01 << 8) +# define HAL_MCFxxxx_CFM_CR_CBEIE (0x01 << 7) +# define HAL_MCFxxxx_CFM_CR_CCIE (0x01 << 6) +# define HAL_MCFxxxx_CFM_CR_KEYACC (0x01 << 5) + +# define HAL_MCFxxxx_CFM_CLKD_DIVLD (0x01 << 7) +# define HAL_MCFxxxx_CFM_CLKD_PRDIV8 (0x01 << 6) +# define HAL_MCFxxxx_CFM_CLKD_DIV_MASK (0x3F << 0) +# define HAL_MCFxxxx_CFM_CLKD_DIV_SHIFT 0 + +# define HAL_MCFxxxx_CFM_SEC_KEYEN (0x01 << 31) +# define HAL_MCFxxxx_CFM_SEC_SECSTAT (0x01 << 30) +# define HAL_MCFxxxx_CFM_SEC_SEC_MASK (0x0FFFF << 0) +# define HAL_MCFxxxx_CFM_SEC_SEC_SHIFT 0 +# define HAL_MCFxxxx_CFM_SEC_SEC_MAGIC 0x4AC8 + +// The PROT protection register is just 32 bits, each bit protecting +// one flash sector. 0 means not protected. + +// The SACC supervisor access register similarly is 32 bits controlling +// access to the flash. 0 allows access in both user and supervisor modes. + +// The DACC data access register is 32 bits determining whether or not +// each sector can contain code. 0 means code is possible. + +# define HAL_MCFxxxx_CFM_USTAT_CBEIF (0x01 << 7) +# define HAL_MCFxxxx_CFM_USTAT_CCIF (0x01 << 6) +# define HAL_MCFxxxx_CFM_USTAT_PVIOL (0x01 << 5) +# define HAL_MCFxxxx_CFM_USTAT_ACCERR (0x01 << 4) +# define HAL_MCFxxxx_CFM_USTAT_BLANK (0x01 << 2) + +# define HAL_MCFxxxx_CFM_CMD_RDARY1 0x05 +# define HAL_MCFxxxx_CFM_CMD_PGERSVER 0x06 +# define HAL_MCFxxxx_CFM_CMD_PGM 0x20 +# define HAL_MCFxxxx_CFM_CMD_PGERS 0x40 +# define HAL_MCFxxxx_CFM_CMD_MASERS 0x41 + +# if !defined(__ASSEMBLER__) && !defined(__LDI__) +// On reset some of the CFM settings are initialized from a structure +// @ offset 0x00000400 in the flash. When booting from the internal +// flash the FLASHBAR register is initialized to address 0, read-only +// and valid. Presumably it is expected that the first 1K will be +// filled with exception vectors, so the next 24 bytes are used for +// flash settings. Real code can follow afterwards. +typedef struct hal_mcfxxxx_cfm_security_settings { + cyg_uint64 cfm_backdoor_key; + cyg_uint32 cfm_prot; + cyg_uint32 cfm_sacc; + cyg_uint32 cfm_dacc; + cyg_uint32 cfm_sec; +} hal_mcfxxxx_cfm_security_settings; +# endif + +#endif // HAL_MCFxxxx_HAS_MCF5282_CFM + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_INTC +// Support one or more INTC controllers, depending on the number of +// interrup sources. + +// Two 32-bit interrupt pending registers +# define HAL_MCFxxxx_INTCx_IPRH 0x0000 +# define HAL_MCFxxxx_INTCx_IPRL 0x0004 +// Two 32-bit interrupt mask registers +# define HAL_MCFxxxx_INTCx_IMRH 0x0008 +# define HAL_MCFxxxx_INTCx_IMRL 0x000C +// Two 32-bit interrupt force registers +# define HAL_MCFxxxx_INTCx_INTFRCH 0x0010 +# define HAL_MCFxxxx_INTCx_INTFRCL 0x0014 +// 8-bit interrupt request level register +# define HAL_MCFxxxx_INTCx_IRLR 0x0018 +// 8-bit interrupt acknowledge level/priority register +# define HAL_MCFxxxx_INTCx_IACKLPR 0x0019 +// 64 8-bit interrupt control registers, determining the priorities +// of each interrupt source. ICR00 is actually invalid but useful for +// array indexing. +# define HAL_MCFxxxx_INTCx_ICR00 0x0040 +// 8-bit ACK registers. These can be checked in an interrupt handler +// to chain, avoiding the overheads of another interrupt, but at +// the cost of a couple of extra cycles even when no other interrupts +// are pending. Unless the interrupt load is very heavy this is +// likely to be a bad trade off. +# define HAL_MCFxxxx_INTCx_SWIACK 0x00E0 +# define HAL_MCFxxxx_INTCx_L1IACK 0x00E4 +# define HAL_MCFxxxx_INTCx_L2IACK 0x00E8 +# define HAL_MCFxxxx_INTCx_L3IACK 0x00EC +# define HAL_MCFxxxx_INTCx_L4IACK 0x00F0 +# define HAL_MCFxxxx_INTCx_L5IACK 0x00F4 +# define HAL_MCFxxxx_INTCx_L6IACK 0x00F8 +# define HAL_MCFxxxx_INTCx_L7IACK 0x00FC + +// Global IACK registers, all 8-bits +# define HAL_MCFxxxx_INTC_GSWACKR 0x0FE0 +# define HAL_MCFxxxx_INTC_GL1IACKR 0x0FE4 +# define HAL_MCFxxxx_INTC_GL2IACKR 0x0FE8 +# define HAL_MCFxxxx_INTC_GL3IACKR 0x0FEC +# define HAL_MCFxxxx_INTC_GL4IACKR 0x0FF0 +# define HAL_MCFxxxx_INTC_GL5IACKR 0x0FF4 +# define HAL_MCFxxxx_INTC_GL6IACKR 0x0FF8 +# define HAL_MCFxxxx_INTC_GL7IACKR 0x0FFC + +// The pending, mask and force registers are just 32 bits with one bit +// per interrupt source. +// +// The IRLR registers is just 8 bits with one bit per interrupt +// priority level. Priority level 0 corresponds to no pending +// interrupts, of course. + +# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_MASK (0x07 << 4) +# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_SHIFT 4 +# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_PRI_MASK (0x0F << 0) +# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_PRI_SHIFT 0 + +# define HAL_MCFxxxx_INTCx_ICRxx_IL_MASK (0x07 << 3) +# define HAL_MCFxxxx_INTCx_ICRxx_IL_SHIFT 3 +# define HAL_MCFxxxx_INTCx_ICRxx_IP_MASK (0x07 << 0) +# define HAL_MCFxxxx_INTCx_ICRxx_IP_SHIFT 0 + +# ifdef HAL_MCFxxxx_HAS_INTC_SIMCIMETC +# undef HAL_MCFxxxx_INTCx_IACKLPR +# define HAL_MCFxxxx_INTCx_ICONFIG 0x0000001A +# define HAL_MCFxxxx_INTCx_SIMR 0x0000001C +# define HAL_MCFxxxx_INTCx_CIMR 0x0000001D +# define HAL_MCFxxxx_INTCx_CLMASK 0x0000001E +# define HAL_MCFxxxx_INTCx_SLMASK 0x0000001F + +# define HAL_MCFxxxx_INTCx_ICONFIG_ELVLPRI_MASK (0x7F << 9) +# define HAL_MCFxxxx_INTCx_ICONFIG_ELVLPRI_SHIFT 9 +# define HAL_MCFxxxx_INTCx_ICONFIG_EMASK (0x01 << 5) +# endif + +#endif // HAL_MCFxxxx_HAS_MCF5282_INTC + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_EPORT +// Edge port module, pins which can be configured to trigger interrupts. + +// Pin assignment register, 16 bits +# define HAL_MCFxxxx_EPORTx_EPPAR 0x0000 +// Data direction register, 8 bits +# define HAL_MCFxxxx_EPORTx_EPDDR 0x0002 +// Interrupt enable register, 8 bits +# define HAL_MCFxxxx_EPORTx_EPIER 0x0003 +// Data register (output), 8 bits +# define HAL_MCFxxxx_EPORTx_EPDR 0x0004 +// Pin data register (input), 8 bits +# define HAL_MCFxxxx_EPORTx_EPPDR 0x0005 +// Flag register +# define HAL_MCFxxxx_EPORTx_EPFR 0x0006 + +// EPPAR is split into 2 bits per pin, the others use 1 bit per pin +// with bit 0 unused. +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA7_MASK (0x03 << 14) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA7_SHIFT 14 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA6_MASK (0x03 << 12) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA6_SHIFT 12 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA5_MASK (0x03 << 10) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA5_SHIFT 10 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA4_MASK (0x03 << 8) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA4_SHIFT 8 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA3_MASK (0x03 << 6) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA3_SHIFT 6 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA2_MASK (0x03 << 4) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA2_SHIFT 4 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA1_MASK (0x03 << 2) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA1_SHIFT 2 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA0_MASK (0x03 << 0) +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA0_SHIFT 0 + +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_LEVEL 0x00 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING 0x01 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING 0x02 +# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_BOTH 0x03 + +#endif // HAL_MCFxxxx_HAS_MCF5282_EPORT + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_DMA +// DMA. Support an arbitrary number of channels, although +// the DMA_REQC register effectively limits the number to 8. + +// DMA request controller, 1 32-bit register. This is assumed relative +// to SCM. It is in addition to the per-channel register definitions. +# define HAL_MCFxxxx_DMA_REQC 0x00000014 + +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 7) +# define HAL_MCFxxxx_DMA_REQC_DMAC7_MASK (0x0F << 28) +# define HAL_MCFxxxx_DMA_REQC_DMAC7_SHIFT 28 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 6) +# define HAL_MCFxxxx_DMA_REQC_DMAC6_MASK (0x0F << 24) +# define HAL_MCFxxxx_DMA_REQC_DMAC6_SHIFT 24 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 5) +# define HAL_MCFxxxx_DMA_REQC_DMAC5_MASK (0x0F << 20) +# define HAL_MCFxxxx_DMA_REQC_DMAC5_SHIFT 20 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 4) +# define HAL_MCFxxxx_DMA_REQC_DMAC4_MASK (0x0F << 16) +# define HAL_MCFxxxx_DMA_REQC_DMAC4_SHIFT 16 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 3) +# define HAL_MCFxxxx_DMA_REQC_DMAC3_MASK (0x0F << 12) +# define HAL_MCFxxxx_DMA_REQC_DMAC3_SHIFT 12 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 2) +# define HAL_MCFxxxx_DMA_REQC_DMAC2_MASK (0x0F << 8) +# define HAL_MCFxxxx_DMA_REQC_DMAC2_SHIFT 8 +#endif +#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 1) +# define HAL_MCFxxxx_DMA_REQC_DMAC1_MASK (0x0F << 4) +# define HAL_MCFxxxx_DMA_REQC_DMAC1_SHIFT 4 +#endif +# define HAL_MCFxxxx_DMA_REQC_DMAC0_MASK (0x0F << 0) +# define HAL_MCFxxxx_DMA_REQC_DMAC0_SHIFT 0 + +// Each DMA channel has 32-bit source, destination and control +// registers, a count register (up to 24 bits), and a 1-byte status +// register +# define HAL_MCFxxxx_DMAx_SARx 0x00000000 +# define HAL_MCFxxxx_DMAx_DARx 0x00000004 +# define HAL_MCFxxxx_DMAx_DCRx 0x00000008 +# define HAL_MCFxxxx_DMAx_BCRx 0x0000000C +# define HAL_MCFxxxx_DMAx_DSRx 0x00000010 + +# define HAL_MCFxxxx_DMAx_DCRx_INT (0x01 << 31) +# define HAL_MCFxxxx_DMAx_DCRx_EEXT (0x01 << 30) +# define HAL_MCFxxxx_DMAx_DCRx_CS (0x01 << 29) +# define HAL_MCFxxxx_DMAx_DCRx_AA (0x01 << 28) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_MASK (0x07 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_SHIFT 25 +# define HAL_MCFxxxx_DMAx_DCRx_BWC_PRIORITY (0x00 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_512_16384 (0x01 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_1024_32768 (0x02 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_2048_65536 (0x03 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_4096_131072 (0x04 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_8192_262144 (0x05 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_16384_524288 (0x06 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_BWC_32678_1048576 (0x07 << 25) +# define HAL_MCFxxxx_DMAx_DCRx_SINC (0x01 << 22) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_MASK (0x03 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_SHIFT 20 +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_LONGWORD (0x00 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_BYTE (0x01 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_WORD (0x02 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_LINE (0x03 << 20) +# define HAL_MCFxxxx_DMAx_DCRx_DINC (0x01 << 19) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_MASK (0x03 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_SHIFT 17 +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_LONGWORD (0x00 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_BYTE (0x01 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_WORD (0x02 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_LINE (0x03 << 17) +# define HAL_MCFxxxx_DMAx_DCRx_START (0x01 << 16) +# define HAL_MCFxxxx_DMAx_DCRx_AT (0x01 << 15) + +# define HAL_MCFxxxx_DMAx_DSRx_CE (0x01 << 6) +# define HAL_MCFxxxx_DMAx_DSRx_BES (0x01 << 5) +# define HAL_MCFxxxx_DMAx_DSRx_BED (0x01 << 4) +# define HAL_MCFxxxx_DMAx_DSRx_REQ (0x01 << 2) +# define HAL_MCFxxxx_DMAx_DSRx_BSY (0x01 << 1) +# define HAL_MCFxxxx_DMAx_DSRx_DONE (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_DMA + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_PIT +// Programmable interrupt timer modules + +# define HAL_MCFxxxx_PITx_PCSR 0x00000000 +# define HAL_MCFxxxx_PITx_PMR 0x00000002 +# define HAL_MCFxxxx_PITx_PCNTR 0x00000004 + +# define HAL_MCFxxxx_PITx_PCSR_PRE_MASK (0x0F < 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_SHIFT 8 +# define HAL_MCFxxxx_PITx_PCSR_PRE_2 (0x00 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_4 (0x01 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_8 (0x02 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_16 (0x03 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_32 (0x04 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_64 (0x05 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_128 (0x06 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_256 (0x07 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_512 (0x08 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_1024 (0x09 << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_2048 (0x0A << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_4096 (0x0B << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_8192 (0x0C << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_16384 (0x0D << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_32768 (0x0E << 8) +# define HAL_MCFxxxx_PITx_PCSR_PRE_65536 (0x0F << 8) +# define HAL_MCFxxxx_PITx_PCSR_DOZE (0x01 << 6) +# define HAL_MCFxxxx_PITx_PCSR_HALTED (0x01 << 5) +# define HAL_MCFxxxx_PITx_PCSR_DBG HAL_MCFxxxx_PITx_PCSR_HALTED +# define HAL_MCFxxxx_PITx_PCSR_OVW (0x01 << 4) +# define HAL_MCFxxxx_PITx_PCSR_PIE (0x01 << 3) +# define HAL_MCFxxxx_PITx_PCSR_PIF (0x01 << 2) +# define HAL_MCFxxxx_PITx_PCSR_RLD (0x01 << 1) +# define HAL_MCFxxxx_PITx_PCSR_EN (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_PIT + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_GPT + +// General purpose timer modules +// 8-bit input capture/output compare register +# define HAL_MCFxxxx_GPTx_IOS 0x0000 +// 8-bit compare force register +# define HAL_MCFxxxx_GPTx_CFORC 0x0001 +// 8-bit output compare 3 mask register +# define HAL_MCFxxxx_GPTx_OC3M 0x0002 +// 8-bit output compare 3 data register +# define HAL_MCFxxxx_GPTx_OC3D 0x0003 +// 16-bit counter registers +# define HAL_MCFxxxx_GPTx_CNT 0x0004 +// 8-bit system control register 1 +# define HAL_MCFxxxx_GPTx_SCR1 0x0006 +// 8-bit toggle-on-overflow register +# define HAL_MCFxxxx_GPTx_TOV 0x0008 +// 8-bit control register 1 +# define HAL_MCFxxxx_GPTx_CTL1 0x0009 +// 8-bit control register 2 +# define HAL_MCFxxxx_GPTx_CTL2 0x000B +// 8-bit interrupt enable register +# define HAL_MCFxxxx_GPTx_IE 0x000C +// 8-bit system control register 2 +# define HAL_MCFxxxx_GPTx_SCR2 0x000D +// 8-bit flag registers +# define HAL_MCFxxxx_GPTx_FLG1 0x000E +# define HAL_MCFxxxx_GPTx_FLG2 0x000F +// 16-bit channel registers +# define HAL_MCFxxxx_GPTx_C0 0x0010 +# define HAL_MCFxxxx_GPTx_C1 0x0012 +# define HAL_MCFxxxx_GPTx_C2 0x0014 +# define HAL_MCFxxxx_GPTx_C3 0x0016 +// 8-bit pulse accumulator control register +# define HAL_MCFxxxx_GPTx_PACTL 0x0018 +// 8-bit pulse accumulator flag register +# define HAL_MCFxxxx_GPTx_PAFLG 0x0019 +// 16-bit pulse accumulator counter register +# define HAL_MCFxxxx_GPTx_PACNT 0x001A +// 8-bit port data registers +# define HAL_MCFxxxx_GPTx_PORT 0x001D +// 8-bit port data direction register +# define HAL_MCFxxxx_GPTx_DDR 0x001E + +# define HAL_MCFxxxx_GPTx_SCR1_GPTEN (0x01 << 7) +# define HAL_MCFxxxx_GPTx_SCR1_TFFCA (0x01 << 4) + +# define HAL_MCFxxxx_GPTx_SCR2_TOI (0x01 << 7) +# define HAL_MCFxxxx_GPTx_SCR2_PUPT (0x01 << 5) +# define HAL_MCFxxxx_GPTx_SCR2_RDPT (0x01 << 4) +# define HAL_MCFxxxx_GPTx_SCR2_TCRE (0x01 << 3) +# define HAL_MCFxxxx_GPTx_SCR2_PR_MASK (0x07 << 0) +# define HAL_MCFxxxx_GPTx_SCR2_PR_SHIFT 0 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV1 0x00 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV2 0x01 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV4 0x02 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV8 0x03 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV16 0x04 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV32 0x05 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV64 0x06 +# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV128 0x07 + +# define HAL_MCFxxxx_GPTx_FLG2_TOF (0x01 << 7) + +# define HAL_MCFxxxx_GPTx_PACTL_PAE (0x01 << 6) +# define HAL_MCFxxxx_GPTx_PACTL_PAMOD (0x01 << 5) +# define HAL_MCFxxxx_GPTx_PACTL_PEDGE (0x01 << 4) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_MASK (0x03 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_SHIFT 2 +# define HAL_MCFxxxx_GPTx_PACTL_CLK_PRESCALER (0x00 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK (0x01 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK_256 (0x02 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK_65536 (0x03 << 2) +# define HAL_MCFxxxx_GPTx_PACTL_PAOVI (0x01 << 1) +# define HAL_MCFxxxx_GPTx_PACTL_PAI (0x01 << 0) + +# define HAL_MCFxxxx_GPTx_PAFLG_PAOVF (0x01 << 1) +# define HAL_MCFxxxx_GPTx_PAFLG_PAIF (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_GPT + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_DTMR + +// DMA timers +// 16-bit timer mode registers +# define HAL_MCFxxxx_DTMRx 0x0000 +// 8-bit extended mode registers +# define HAL_MCFxxxx_DTXMRx 0x0002 +// 8-bit event registers +# define HAL_MCFxxxx_DTERx 0x00003 +// 32-bit reference, capture and counter registers +# define HAL_MCFxxxx_DTRRx 0x0004 +# define HAL_MCFxxxx_DTCRx 0x0008 +# define HAL_MCFxxxx_DTCNx 0x000C + +# define HAL_MCFxxxx_DTMRx_PS_MASK (0x0FF << 8) +# define HAL_MCFxxxx_DTMRx_PS_SHIFT 8 +# define HAL_MCFxxxx_DTMRx_CE_MASK (0x03 << 6) +# define HAL_MCFxxxx_DTMRx_CE_SHIFT 6 +# define HAL_MCFxxxx_DTMRx_CE_DISABLE (0x00 << 6) +# define HAL_MCFxxxx_DTMRx_CE_RISING (0x01 << 6) +# define HAL_MCFxxxx_DTMRx_CE_FALLING (0x02 << 6) +# define HAL_MCFxxxx_DTMRx_CE_ANY (0x03 << 6) +# define HAL_MCFxxxx_DTMRx_OM (0x01 << 5) +# define HAL_MCFxxxx_DTMRx_ORRI (0x01 << 4) +# define HAL_MCFxxxx_DTMRx_FRR (0x01 << 3) +# define HAL_MCFxxxx_DTMRx_CLK_MASK (0x03 << 1) +# define HAL_MCFxxxx_DTMRx_CLK_SHIFT 1 +# define HAL_MCFxxxx_DTMRx_CLK_STOP (0x00 << 1) +# define HAL_MCFxxxx_DTMRx_CLK_DIV_1 (0x01 << 1) +# define HAL_MCFxxxx_DTMRx_CLK_DIV_16 (0x02 << 1) +# define HAL_MCFxxxx_DTMRx_CLK_DTINn (0x03 << 1) +# define HAL_MCFxxxx_DTMRx_RST (0x01 << 0) + +# define HAL_MCFxxxx_DTXMRx_DMAEN (0x01 << 7) +# define HAL_MCFxxxx_DTXMRx_MODE16 (0x01 << 1) + +# define HAL_MCFxxxx_DTERx_REF (0x01 << 1) +# define HAL_MCFxxxx_DTERx_CAP (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_DTMR + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_ETH +// Ethernet. Allow for multiple devices. + +# define HAL_MCFxxxx_ETHx_EIR 0x0004 +# define HAL_MCFxxxx_ETHx_EIMR 0x0008 +# define HAL_MCFxxxx_ETHx_RDAR 0x0010 +# define HAL_MCFxxxx_ETHx_TDAR 0x0014 +# define HAL_MCFxxxx_ETHx_ECR 0x0024 +# define HAL_MCFxxxx_ETHx_MDATA 0x0040 +# define HAL_MCFxxxx_ETHx_MMFR 0x0040 +# define HAL_MCFxxxx_ETHx_MSCR 0x0044 +# define HAL_MCFxxxx_ETHx_MIBC 0x0064 +# define HAL_MCFxxxx_ETHx_RCR 0x0084 +# define HAL_MCFxxxx_ETHx_TCR 0x00C4 +# define HAL_MCFxxxx_ETHx_PALR 0x00E4 +# define HAL_MCFxxxx_ETHx_PAUR 0x00E8 +# define HAL_MCFxxxx_ETHx_OPD 0x00EC +# define HAL_MCFxxxx_ETHx_IAUR 0x0118 +# define HAL_MCFxxxx_ETHx_IALR 0x011C +# define HAL_MCFxxxx_ETHx_GAUR 0x0120 +# define HAL_MCFxxxx_ETHx_GALR 0x0124 +# define HAL_MCFxxxx_ETHx_TFWR 0x0144 +# define HAL_MCFxxxx_ETHx_FRBR 0x014C +# define HAL_MCFxxxx_ETHx_FRSR 0x0150 +# define HAL_MCFxxxx_ETHx_ERDSR 0x0180 +# define HAL_MCFxxxx_ETHx_ETDSR 0x0184 +# define HAL_MCFxxxx_ETHx_EMRBR 0x0188 + +# define HAL_MCFxxxx_ETHx_RMON_T_DROP 0x0200 +# define HAL_MCFxxxx_ETHx_RMON_T_PACKETS 0x0204 +# define HAL_MCFxxxx_ETHx_RMON_T_BC_PKT 0x0208 +# define HAL_MCFxxxx_ETHx_RMON_T_MC_PKT 0x020C +# define HAL_MCFxxxx_ETHx_RMON_T_CRC_ALIGN 0x0210 +# define HAL_MCFxxxx_ETHx_RMON_T_UNDERSIZE 0x0214 +# define HAL_MCFxxxx_ETHx_RMON_T_OVERSIZE 0x0218 +# define HAL_MCFxxxx_ETHx_RMON_T_FRAG 0x021C +# define HAL_MCFxxxx_ETHx_RMON_T_JAB 0x0220 +# define HAL_MCFxxxx_ETHx_RMON_T_COL 0x0224 +# define HAL_MCFxxxx_ETHx_RMON_T_P64 0x0228 +# define HAL_MCFxxxx_ETHx_RMON_T_P65TO127 0x022C +# define HAL_MCFxxxx_ETHx_RMON_T_P128TO255 0x0230 +# define HAL_MCFxxxx_ETHx_RMON_T_P256TO511 0x0234 +# define HAL_MCFxxxx_ETHx_RMON_T_P512TO1023 0x0238 +# define HAL_MCFxxxx_ETHx_RMON_T_P1024TO2047 0x023C +# define HAL_MCFxxxx_ETHx_RMON_T_PGTE2048 0x0240 +# define HAL_MCFxxxx_ETHx_RMON_T_OCTETS 0x0244 +# define HAL_MCFxxxx_ETHx_IEEE_T_DROP 0x0248 +# define HAL_MCFxxxx_ETHx_IEEE_T_FRAME_OK 0x024C +# define HAL_MCFxxxx_ETHx_IEEE_T_1COL 0x0250 +# define HAL_MCFxxxx_ETHx_IEEE_T_MCOL 0x0254 +# define HAL_MCFxxxx_ETHx_IEEE_T_DEF 0x0258 +# define HAL_MCFxxxx_ETHx_IEEE_T_LCOL 0x025C +# define HAL_MCFxxxx_ETHx_IEEE_T_EXCOL 0x0260 +# define HAL_MCFxxxx_ETHx_IEEE_T_MACERR 0x0264 +# define HAL_MCFxxxx_ETHx_IEEE_T_CSERR 0x0268 +# define HAL_MCFxxxx_ETHx_IEEE_T_SQE 0x026C +# define HAL_MCFxxxx_ETHx_IEEE_T_FDXFC 0x0270 +# define HAL_MCFxxxx_ETHx_IEEE_T_OCTETS_OK 0x0274 +# define HAL_MCFxxxx_ETHx_RMON_R_PACKETS 0x0284 +# define HAL_MCFxxxx_ETHx_RMON_R_BC_PKT 0x0288 +# define HAL_MCFxxxx_ETHx_RMON_R_MC_PKT 0x028C +# define HAL_MCFxxxx_ETHx_RMON_R_CRC_ALIGN 0x0290 +# define HAL_MCFxxxx_ETHx_RMON_R_UNDERSIZE 0x0294 +# define HAL_MCFxxxx_ETHx_RMON_R_OVERSIZE 0x0298 +# define HAL_MCFxxxx_ETHx_RMON_R_FRAG 0x029C +# define HAL_MCFxxxx_ETHx_RMON_R_JAB 0x02A0 +# define HAL_MCFxxxx_ETHx_RMON_R_RESVD_0 0x02A4 +# define HAL_MCFxxxx_ETHx_RMON_R_P64 0x02A8 +# define HAL_MCFxxxx_ETHx_RMON_R_P65TO127 0x02AC +# define HAL_MCFxxxx_ETHx_RMON_R_P128TO255 0x02B0 +# define HAL_MCFxxxx_ETHx_RMON_R_P256TO511 0x02B4 +# define HAL_MCFxxxx_ETHx_RMON_R_P512TO1023 0x02B8 +# define HAL_MCFxxxx_ETHx_RMON_R_P1024TO2047 0x02BC +# define HAL_MCFxxxx_ETHx_RMON_R_GTE2048 0x02C0 +# define HAL_MCFxxxx_ETHx_RMON_R_OCTETS 0x02C4 +# define HAL_MCFxxxx_ETHx_IEEE_R_DROP 0x02C8 +# define HAL_MCFxxxx_ETHx_IEEE_R_FRAME_OK 0x02CC +# define HAL_MCFxxxx_ETHx_IEEE_R_CRC 0x02D0 +# define HAL_MCFxxxx_ETHx_IEEE_R_ALIGN 0x02D4 +# define HAL_MCFxxxx_ETHx_IEEE_R_MACERR 0x02D8 +# define HAL_MCFxxxx_ETHx_IEEE_R_FDXFC 0x02DC +# define HAL_MCFxxxx_ETHx_IEEE_R_OCTETS_OK 0x02E0 + +# define HAL_MCFxxxx_ETHx_EIR_HBERR (0x01 << 31) +# define HAL_MCFxxxx_ETHx_EIR_BABR (0x01 << 30) +# define HAL_MCFxxxx_ETHx_EIR_BABT (0x01 << 29) +# define HAL_MCFxxxx_ETHx_EIR_GRA (0x01 << 28) +# define HAL_MCFxxxx_ETHx_EIR_TXF (0x01 << 27) +# define HAL_MCFxxxx_ETHx_EIR_TXB (0x01 << 26) +# define HAL_MCFxxxx_ETHx_EIR_RXF (0x01 << 25) +# define HAL_MCFxxxx_ETHx_EIR_RXB (0x01 << 24) +# define HAL_MCFxxxx_ETHx_EIR_MII (0x01 << 23) +# define HAL_MCFxxxx_ETHx_EIR_EBERR (0x01 << 22) +# define HAL_MCFxxxx_ETHx_EIR_LC (0x01 << 21) +# define HAL_MCFxxxx_ETHx_EIR_RL (0x01 << 20) +# define HAL_MCFxxxx_ETHx_EIR_UN (0x01 << 19) + +# define HAL_MCFxxxx_ETHx_EIMR_HBERR HAL_MCFxxxx_ETHx_EIR_HBERR +# define HAL_MCFxxxx_ETHx_EIMR_BABR HAL_MCFxxxx_ETHx_EIR_BABR +# define HAL_MCFxxxx_ETHx_EIMR_BABT HAL_MCFxxxx_ETHx_EIR_BABT +# define HAL_MCFxxxx_ETHx_EIMR_GRA HAL_MCFxxxx_ETHx_EIR_GRA +# define HAL_MCFxxxx_ETHx_EIMR_TXF HAL_MCFxxxx_ETHx_EIR_TXF +# define HAL_MCFxxxx_ETHx_EIMR_TXB HAL_MCFxxxx_ETHx_EIR_TXB +# define HAL_MCFxxxx_ETHx_EIMR_RXF HAL_MCFxxxx_ETHx_EIR_RXF +# define HAL_MCFxxxx_ETHx_EIMR_RXB HAL_MCFxxxx_ETHx_EIR_RXB +# define HAL_MCFxxxx_ETHx_EIMR_MII HAL_MCFxxxx_ETHx_EIR_MII +# define HAL_MCFxxxx_ETHx_EIMR_EBERR HAL_MCFxxxx_ETHx_EIR_EBERR +# define HAL_MCFxxxx_ETHx_EIMR_LC HAL_MCFxxxx_ETHx_EIR_LC +# define HAL_MCFxxxx_ETHx_EIMR_RL HAL_MCFxxxx_ETHx_EIR_RL +# define HAL_MCFxxxx_ETHx_EIMR_UN HAL_MCFxxxx_ETHx_EIR_UN + +# define HAL_MCFxxxx_ETHx_RDAR_R_DES_ACTIVE (0x01 << 24) +# define HAL_MCFxxxx_ETHx_TDAR_X_DES_ACTIVE (0x01 << 24) + +# define HAL_MCFxxxx_ETHx_ECR_ETHER_EN (0x01 << 1) +# define HAL_MCFxxxx_ETHx_ECR_RESET (0x01 << 0) + +# define HAL_MCFxxxx_ETHx_MMFR_ST_MASK (0x03 << 30) +# define HAL_MCFxxxx_ETHx_MMFR_ST_SHIFT 30 +# define HAL_MCFxxxx_ETHx_MMFR_ST_VALUE (0x01 << 30) +# define HAL_MCFxxxx_ETHx_MMFR_OP_MASK (0x03 << 28) +# define HAL_MCFxxxx_ETHx_MMFR_OP_READ (0x02 << 28) +# define HAL_MCFxxxx_ETHx_MMFR_OP_WRITE (0x01 << 28) +# define HAL_MCFxxxx_ETHx_MMFR_PA_MASK (0x1F << 23) +# define HAL_MCFxxxx_ETHx_MMFR_PA_SHIFT 23 +# define HAL_MCFxxxx_ETHx_MMFR_RA_MASK (0x1F << 18) +# define HAL_MCFxxxx_ETHx_MMFR_RA_SHIFT 18 +# define HAL_MCFxxxx_ETHx_MMFR_TA_MASK (0x03 << 16) +# define HAL_MCFxxxx_ETHx_MMFR_TA_SHIFT 16 +# define HAL_MCFxxxx_ETHx_MMFR_TA_VALUE (0x02 << 16) +# define HAL_MCFxxxx_ETHx_MMFR_DATA_MASK (0x0FFFF << 0) +# define HAL_MCFxxxx_ETHx_MMFR_DATA_SHIFT 0 + +# define HAL_MCFxxxx_ETHx_MSCR_DIS_PREAMBLE (0x01 << 7) +# define HAL_MCFxxxx_ETHx_MSCR_MII_SPEED_MASK (0x3F << 1) +# define HAL_MCFxxxx_ETHx_MSCR_MII_SPEED_SHIFT 1 + +# define HAL_MCFxxxx_ETHx_MIBC_MIB_DISABLE (0x01 << 31) +# define HAL_MCFxxxx_ETHx_MIBC_MIB_IDLE (0x01 << 30) + +# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_MASK (0x03FFF << 16) +# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_SHIFT 16 +# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_VALUE (1518 << 16) +# define HAL_MCFxxxx_ETHx_RCR_FCE (0x01 << 5) +# define HAL_MCFxxxx_ETHx_RCR_BC_REJ (0x01 << 4) +# define HAL_MCFxxxx_ETHx_RCR_PROM (0x01 << 3) +# define HAL_MCFxxxx_ETHx_RCR_MII_MODE (0x01 << 2) +# define HAL_MCFxxxx_ETHx_RCR_DRT (0x01 << 1) +# define HAL_MCFxxxx_ETHx_RCR_LOOP (0x01 << 0) + +# define HAL_MCFxxxx_ETHx_TCR_RFC_PAUSE (0x01 << 4) +# define HAL_MCFxxxx_ETHx_TCR_TFC_PAUSE (0x01 << 3) +# define HAL_MCFxxxx_ETHx_TCR_FDEN (0x01 << 2) +# define HAL_MCFxxxx_ETHx_TCR_HBC (0x01 << 1) +# define HAL_MCFxxxx_ETHx_TCR_GTS (0x01 << 0) + +# define HAL_MCFxxxx_ETHx_OPD_OPCODE_MASK (0x0FFFF << 16) +# define HAL_MCFxxxx_ETHx_OPD_OPCODE_SHIFT 16 +# define HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_MASK (0x0FFFF << 0) +# define HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_SHIFT 0 + +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_MASK (0x03 << 0) +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_SHIFT 0 +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_64 (0x00 << 0) +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_128 (0x02 << 0) +# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_192 (0x03 << 0) + +// This is the data structure for a buffer descriptor. +# if !defined( __ASSEMBLER__) && !defined(__LDI__) +typedef struct hal_mcfxxxx_eth_buffer_descriptor { + cyg_uint16 ethbd_flags; + cyg_uint16 ethbd_length; + cyg_uint8* ethbd_buffer; +} hal_mcfxxxx_eth_buffer_descriptor; +# endif + +# define HAL_MCFxxxx_ETHx_RXBD_E (0x01 << 15) +# define HAL_MCFxxxx_ETHx_RXBD_RO1 (0x01 << 14) +# define HAL_MCFxxxx_ETHx_RXBD_W (0x01 << 13) +# define HAL_MCFxxxx_ETHx_RXBD_RO2 (0x01 << 12) +# define HAL_MCFxxxx_ETHx_RXBD_L (0x01 << 11) +# define HAL_MCFxxxx_ETHx_RXBD_M (0x01 << 8) +# define HAL_MCFxxxx_ETHx_RXBD_BC (0x01 << 7) +# define HAL_MCFxxxx_ETHx_RXBD_MC (0x01 << 6) +# define HAL_MCFxxxx_ETHx_RXBD_LG (0x01 << 5) +# define HAL_MCFxxxx_ETHx_RXBD_NO (0x01 << 4) +# define HAL_MCFxxxx_ETHx_RXBD_CR (0x01 << 2) +# define HAL_MCFxxxx_ETHx_RXBD_OV (0x01 << 1) +# define HAL_MCFxxxx_ETHx_RXBD_TR (0x01 << 0) + +# define HAL_MCFxxxx_ETHx_TXBD_R (0x01 << 15) +# define HAL_MCFxxxx_ETHx_TXBD_TO1 (0x01 << 14) +# define HAL_MCFxxxx_ETHx_TXBD_W (0x01 << 13) +# define HAL_MCFxxxx_ETHx_TXBD_TO2 (0x01 << 12) +# define HAL_MCFxxxx_ETHx_TXBD_L (0x01 << 11) +# define HAL_MCFxxxx_ETHx_TXBD_TC (0x01 << 10) +# define HAL_MCFxxxx_ETHx_TXBD_ABC (0x01 << 9) + +#endif // HAL_MCFxxxx_HAS_MCF5282_ETH + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_QSPI + +// QSPI +// Six 16-bit registers: mode, delay, wrap, interrupt, address and data +# define HAL_MCFxxxx_QSPIx_QMR 0x0000 +# define HAL_MCFxxxx_QSPIx_QDLYR 0x0004 +# define HAL_MCFxxxx_QSPIx_QWR 0x0008 +# define HAL_MCFxxxx_QSPIx_QIR 0x000C +# define HAL_MCFxxxx_QSPIx_QAR 0x0010 +# define HAL_MCFxxxx_QSPIx_QDR 0x0014 + +# define HAL_MCFxxxx_QSPIx_QMR_MSTR (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QMR_DOHIE (0x01 << 14) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_MASK (0x0F << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_SHIFT 10 +# define HAL_MCFxxxx_QSPIx_QMR_BITS_16 (0x00 << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_8 (0x08 << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_9 (0x09 << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_10 (0x0A << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_11 (0x0B << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_12 (0x0C << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_13 (0x0D << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_14 (0x0E << 10) +# define HAL_MCFxxxx_QSPIx_QMR_BITS_15 (0x0F << 10) +# define HAL_MCFxxxx_QSPIx_QMR_CPOL (0x01 << 9) +# define HAL_MCFxxxx_QSPIx_QMR_CPHA (0x01 << 8) +# define HAL_MCFxxxx_QSPIx_QMR_BAUD_MASK (0x0FF << 0) +# define HAL_MCFxxxx_QSPIx_QMR_BAUD_SHIFT 0 + +# define HAL_MCFxxxx_QSPIx_QDLYR_SPE (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QDLYR_QCD_MASK (0x07F << 8) +# define HAL_MCFxxxx_QSPIx_QDLYR_QCD_SHIFT 8 +# define HAL_MCFxxxx_QSPIx_QDLYR_DTL_MASK (0x0FF << 0) +# define HAL_MCFxxxx_QSPIx_QDLYR_DTL_SHIFT 0 + +# define HAL_MCFxxxx_QSPIx_QWR_HALT (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QWR_WREN (0x01 << 14) +# define HAL_MCFxxxx_QSPIx_QWR_WRTO (0x01 << 13) +# define HAL_MCFxxxx_QSPIx_QWR_CSIV (0x01 << 12) +# define HAL_MCFxxxx_QSPIx_QWR_ENDQP_MASK (0x0F << 8) +# define HAL_MCFxxxx_QSPIx_QWR_ENDQP_SHIFT 8 +# define HAL_MCFxxxx_QSPIx_QWR_CPTQP_MASK (0x0F << 4) +# define HAL_MCFxxxx_QSPIx_QWR_CPTQP_SHIFT 4 +# define HAL_MCFxxxx_QSPIx_QWR_NEWQP_MASK (0x0F << 0) +# define HAL_MCFxxxx_QSPIx_QWR_NEWQP_SHIFT 0 + +# define HAL_MCFxxxx_QSPIx_QIR_WCEFB (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QIR_ABRTB (0x01 << 14) +# define HAL_MCFxxxx_QSPIx_QIR_ABRTL (0x01 << 12) +# define HAL_MCFxxxx_QSPIx_QIR_WCEFE (0x01 << 11) +# define HAL_MCFxxxx_QSPIx_QIR_ABRTE (0x01 << 10) +# define HAL_MCFxxxx_QSPIx_QIR_SPIFE (0x01 << 8) +# define HAL_MCFxxxx_QSPIx_QIR_WCEF (0x01 << 3) +# define HAL_MCFxxxx_QSPIx_QIR_ABRT (0x01 << 2) +# define HAL_MCFxxxx_QSPIx_QIR_SPIF (0x01 << 0) + +# define HAL_MCFxxxx_QSPIx_QCRn_CONT (0x01 << 15) +# define HAL_MCFxxxx_QSPIx_QCRn_BITSE (0x01 << 14) +# define HAL_MCFxxxx_QSPIx_QCRn_DT (0x01 << 13) +# define HAL_MCFxxxx_QSPIx_QCRn_DSCK (0x01 << 12) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_MASK (0x0F << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_SHIFT 8 +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS0 (0x01 << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS1 (0x02 << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS2 (0x04 << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS3 (0x08 << 8) +# define HAL_MCFxxxx_QSPI_QCRn_QSPI_CS_CSn(__n) ((__n) << 8) +# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CSn(__n) ((__n) << 8) + +# define HAL_MCFxxxx_QSPIx_QAR_TX_BASE 0x0000 +# define HAL_MCFxxxx_QSPIx_QAR_RX_BASE 0x0010 +# define HAL_MCFxxxx_QSPIx_QAR_COMMAND_BASE 0x0020 + +# define HAL_MCFxxxx_QSPIx_DEV_TO_BAUD(_dev_setting_arg_, _baud_) \ + CYG_MACRO_START \ + cyg_uint32 _dev_setting_ = (cyg_uint32) (_dev_setting_arg_); \ + cyg_uint32 _result_; \ + if (0 == _dev_setting_) { \ + _result_ = 0; \ + } else { \ + _result_ = CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _dev_setting_); \ + } \ + _baud_ = _result_; \ + CYG_MACRO_END + +// When calculating a device setting, if the baud rate cannot be supported exactly +// then switch to the next slowest setting. +# define HAL_MCFxxxx_QSPIx_BAUD_TO_DEV(_baud_arg_, _dev_setting_) \ + CYG_MACRO_START \ + cyg_uint32 _baud_ = (cyg_uint32) (_baud_arg_); \ + cyg_uint32 _result_; \ + if (0 == _baud_) { \ + _result_ = 0; \ + } else { \ + _result_ = CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _baud_); \ + if (_baud_ != (CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _result_))) { \ + _result_++; \ + } \ + if (_result_ < 2) { \ + _result_ = 2; \ + } else if (_result_ > 255) { \ + _result_ = 255; \ + } \ + } \ + _dev_setting_ = _result_; \ + CYG_MACRO_END + +#endif // HAL_MCFxxxx_HAS_MCF5282_QSPI + +// ---------------------------------------------------------------------------- + +#ifdef HAL_MCFxxxx_HAS_MCF5282_UART +// All registers are a single byte. +# define HAL_MCFxxxx_UARTx_UMR 0x00 +# define HAL_MCFxxxx_UARTx_USR 0x04 +# define HAL_MCFxxxx_UARTx_UCSR 0x04 +# define HAL_MCFxxxx_UARTx_UCR 0x08 +# define HAL_MCFxxxx_UARTx_URB 0x0C +# define HAL_MCFxxxx_UARTx_UTB 0x0C +# define HAL_MCFxxxx_UARTx_UIPCR 0x10 +# define HAL_MCFxxxx_UARTx_UACR 0x10 +# define HAL_MCFxxxx_UARTx_UISR 0x14 +# define HAL_MCFxxxx_UARTx_UIMR 0x14 +# define HAL_MCFxxxx_UARTx_UBG1 0x18 +# define HAL_MCFxxxx_UARTx_UBG2 0x1C + +# define HAL_MCFxxxx_UARTx_UIP 0x34 +# define HAL_MCFxxxx_UARTx_UOP1 0x38 +# define HAL_MCFxxxx_UARTx_UOP0 0x3C + +# define HAL_MCFxxxx_UARTx_UMR1_RXRTS (0x01 << 7) +# define HAL_MCFxxxx_UARTx_UMR1_FFULL (0x01 << 6) +# define HAL_MCFxxxx_UARTx_UMR1_ERR (0x01 << 5) +# define HAL_MCFxxxx_UARTx_UMR1_PM_MASK (0x03 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PM_SHIFT 3 +# define HAL_MCFxxxx_UARTx_UMR1_PM_WITH (0x00 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PM_FORCE (0x01 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PM_NO (0x02 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PM_MULTIDROP (0x03 << 3) +# define HAL_MCFxxxx_UARTx_UMR1_PT (0x01 << 2) +# define HAL_MCFxxxx_UARTx_UMR1_BC_MASK (0x03 << 0) +# define HAL_MCFxxxx_UARTx_UMR1_BC_SHIFT 0 +# define HAL_MCFxxxx_UARTx_UMR1_BC_5 (0x00 << 0) +# define HAL_MCFxxxx_UARTx_UMR1_BC_6 (0x01 << 0) +# define HAL_MCFxxxx_UARTx_UMR1_BC_7 (0x02 << 0) +# define HAL_MCFxxxx_UARTx_UMR1_BC_8 (0x03 << 0) + +# define HAL_MCFxxxx_UARTx_UMR2_CM_MASK (0x03 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_CM_SHIFT 6 +# define HAL_MCFxxxx_UARTx_UMR2_CM_NORMAL (0x00 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_CM_AUTO (0x01 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_CM_LOCAL (0x02 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_CM_REMOTE (0x03 << 6) +# define HAL_MCFxxxx_UARTx_UMR2_TXRTS (0x01 << 5) +# define HAL_MCFxxxx_UARTx_UMR2_TXCTS (0x01 << 4) +# define HAL_MCFxxxx_UARTx_UMR2_SB_MASK (0x0f << 0) +# define HAL_MCFxxxx_UARTx_UMR2_SB_SHIFT 0 +// These two constants are only valid for 6-8 bits. 5 bit needs +// to be treated specially. +# define HAL_MCFxxxx_UARTx_UMR2_SB_1 (0x07 << 0) +# define HAL_MCFxxxx_UARTx_UMR2_SB_2 (0x0f << 0) + +# define HAL_MCFxxxx_UARTx_USR_RB (0x01 << 7) +# define HAL_MCFxxxx_UARTx_USR_FE (0x01 << 6) +# define HAL_MCFxxxx_UARTx_USR_PE (0x01 << 5) +# define HAL_MCFxxxx_UARTx_USR_OE (0x01 << 4) +# define HAL_MCFxxxx_UARTx_USR_TXEMP (0x01 << 3) +# define HAL_MCFxxxx_UARTx_USR_TXRDY (0x01 << 2) +# define HAL_MCFxxxx_UARTx_USR_FFULL (0x01 << 1) +# define HAL_MCFxxxx_UARTx_USR_RXRDY (0x01 << 0) + +# define HAL_MCFxxxx_UARTx_UCSR_RCS_MASK (0x0f << 4) +# define HAL_MCFxxxx_UARTx_UCSR_RCS_SHIFT 4 +# define HAL_MCFxxxx_UARTx_UCSR_RCS_CLKIN (0x0D << 4) +# define HAL_MCFxxxx_UARTx_UCSR_RCS_DTINDIV16 (0x0E << 4) +# define HAL_MCFxxxx_UARTx_UCSR_RCS_DTIN (0x0F << 4) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_MASK (0x0f << 0) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_SHIFT (0x0f << 0) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_CLKIN (0x0D << 0) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_DTINDIV16 (0x0E << 0) +# define HAL_MCFxxxx_UARTx_UCSR_TCS_DTIN (0x0F << 0) + +# define HAL_MCFxxxx_UARTx_UCR_MISC_MASK (0x07 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_SHIFT 4 +# define HAL_MCFxxxx_UARTx_UCR_MISC_NOP (0x00 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RMRP (0x01 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RR (0x02 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RT (0x03 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RES (0x04 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_RBCI (0x05 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_STARTB (0x06 << 4) +# define HAL_MCFxxxx_UARTx_UCR_MISC_STOPB (0x07 << 4) +# define HAL_MCFxxxx_UARTx_UCR_TC_MASK (0x03 << 2) +# define HAL_MCFxxxx_UARTx_UCR_TC_SHIFT 2 +# define HAL_MCFxxxx_UARTx_UCR_TC_NOP (0x00 << 2) +# define HAL_MCFxxxx_UARTx_UCR_TC_TE (0x01 << 2) +# define HAL_MCFxxxx_UARTx_UCR_TC_TD (0x02 << 2) +# define HAL_MCFxxxx_UARTx_UCR_RC_MASK (0x03 << 0) +# define HAL_MCFxxxx_UARTx_UCR_RC_SHIFT 0 +# define HAL_MCFxxxx_UARTx_UCR_RC_NOP (0x00 << 0) +# define HAL_MCFxxxx_UARTx_UCR_RC_RE (0x01 << 0) +# define HAL_MCFxxxx_UARTx_UCR_RC_RD (0x02 << 0) + +# define HAL_MCFxxxx_UARTx_UIPCR_COS (0x01 << 4) +# define HAL_MCFxxxx_UARTx_UIPCR_CTS (0x01 << 0) + +# define HAL_MCFxxxx_UARTx_UACR_IEC (0x01 << 0) + +// ABC, RXFIFO, TXFIFO and RXFTO are not always available +# define HAL_MCFxxxx_UARTx_UISR_COS (0x01 << 7) +# define HAL_MCFxxxx_UARTx_UISR_DB (0x01 << 2) +# define HAL_MCFxxxx_UARTx_UISR_FFUL (0x01 << 1) +# define HAL_MCFxxxx_UARTx_UISR_RXRDY (0x01 << 1) +# define HAL_MCFxxxx_UARTx_UISR_TXRDY (0x01 << 0) + +# define HAL_MCFxxxx_UARTx_UIMR_COS (0x01 << 7) +# define HAL_MCFxxxx_UARTx_UIMR_DB (0x01 << 2) +# define HAL_MCFxxxx_UARTx_UIMR_FFUL (0x01 << 1) +# define HAL_MCFxxxx_UARTx_UIMR_RXRDY (0x01 << 1) +# define HAL_MCFxxxx_UARTx_UIMR_TXRDY (0x01 << 0) + +# define HAL_MCFxxxx_UARTx_UIP_CTS (0x01 << 0) +# define HAL_MCFxxxx_UARTx_UOP_RTS (0x01 << 0) + +// The baud rate depends on the system clock. There is no fractional +// precision register. +# define HAL_MCFxxxx_UARTx_SET_BAUD(_base_, _baud_) \ + CYG_MACRO_START \ + cyg_uint8 _udu_ = ((cyg_uint8) (((CYGHWR_HAL_SYSTEM_CLOCK_MHZ * 1000000) / (32 * (_baud_))) >> 8)); \ + cyg_uint8 _udl_ = ((cyg_uint8) (((CYGHWR_HAL_SYSTEM_CLOCK_MHZ * 1000000) / (32 * (_baud_))) & 0x00FF)); \ + HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG1, _udu_); \ + HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG2, _udl_); \ + CYG_MACRO_END + +#endif // HAL_MCFxxxx_HAS_MCF5282_UART + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_I2C +// I2C +// Five 8-bit registers: address, frequency divider, control, status, data +# define HAL_MCFxxxx_I2Cx_ADR 0x0000 +# define HAL_MCFxxxx_I2Cx_FDR 0x0004 +# define HAL_MCFxxxx_I2Cx_CR 0x0008 +# define HAL_MCFxxxx_I2Cx_SR 0x000C +# define HAL_MCFxxxx_I2Cx_DR 0x0010 + +# define HAL_MCFxxxx_I2Cx_CR_IEN (0x01 << 7) +# define HAL_MCFxxxx_I2Cx_CR_IIEN (0x01 << 6) +# define HAL_MCFxxxx_I2Cx_CR_MSTA (0x01 << 5) +# define HAL_MCFxxxx_I2Cx_CR_MTX (0x01 << 4) +# define HAL_MCFxxxx_I2Cx_CR_TXAK (0x01 << 3) +# define HAL_MCFxxxx_I2Cx_CR_RSTA (0x01 << 2) + +# define HAL_MCFxxxx_I2Cx_SR_ICF (0x01 << 7) +# define HAL_MCFxxxx_I2Cx_SR_IAAS (0x01 << 6) +# define HAL_MCFxxxx_I2Cx_SR_IBB (0x01 << 5) +# define HAL_MCFxxxx_I2Cx_SR_IAL (0x01 << 4) +# define HAL_MCFxxxx_I2Cx_SR_SRW (0x01 << 2) +# define HAL_MCFxxxx_I2Cx_SR_IIF (0x01 << 1) +# define HAL_MCFxxxx_I2Cx_SR_RXAK (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_I2C + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_CAN +// FLEXCAN +// 16-bit module configuration register +# define HAL_MCFxxxx_CANx_MCR 0x0000 +// Three 8-bit control registers and an 8-bit prescaler +# define HAL_MCFxxxx_CANx_CTRL0 0x0006 +# define HAL_MCFxxxx_CANx_CTRL1 0x0007 +# define HAL_MCFxxxx_CANx_PRESDIV 0x0008 +# define HAL_MCFxxxx_CANx_CTRL2 0x0009 +// 16-bit free runxxng timer +# define HAL_MCFxxxx_CANx_TIMER 0x000A +// 32-bit global and buffer mask registers +# define HAL_MCFxxxx_CANx_RXGMASK 0x0010 +# define HAL_MCFxxxx_CANx_RX14MASK 0x0014 +# define HAL_MCFxxxx_CANx_RX15MASK 0x0018 +// 16-bit error and status +# define HAL_MCFxxxx_CANx_ESTAT 0x0020 +// 16-bit interrup mask and flags +# define HAL_MCFxxxx_CANx_IMASK 0x0022 +# define HAL_MCFxxxx_CANx_IFLAG 0x0024 +// Two 8-bit error counters +# define HAL_MCFxxxx_CANx_RXECTR 0x0026 +# define HAL_MCFxxxx_CANx_TXECTR 0x0027 +// 16 32-bit message buffers start here +# define HAL_MCFxxxx_CANx_BUF 0x0080 + +# define HAL_MCFxxxx_CANx_MCR_STOP (0x01 << 15) +# define HAL_MCFxxxx_CANx_MCR_FRZ (0x01 << 14) +# define HAL_MCFxxxx_CANx_MCR_HALT (0x01 << 12) +# define HAL_MCFxxxx_CANx_MCR_NOTRDY (0x01 << 11) +# define HAL_MCFxxxx_CANx_MCR_WAKEMSK (0x01 << 10) +# define HAL_MCFxxxx_CANx_MCR_SOFTRST (0x01 << 9) +# define HAL_MCFxxxx_CANx_MCR_FRZACK (0x01 << 8) +# define HAL_MCFxxxx_CANx_MCR_SUPV (0x01 << 7) +# define HAL_MCFxxxx_CANx_MCR_SELFWAKE (0x01 << 6) +# define HAL_MCFxxxx_CANx_MCR_APS (0x01 << 5) +# define HAL_MCFxxxx_CANx_MCR_STOPACK (0x01 << 4) + +# define HAL_MCFxxxx_CANx_CTRL0_BOFFMSK (0x01 << 7) +# define HAL_MCFxxxx_CANx_CTRL0_ERRMASK (0x01 << 6) +# define HAL_MCFxxxx_CANx_CTRL0_RXMODE (0x01 << 2) +# define HAL_MCFxxxx_CANx_CTRL0_RXMODE_0_DOMINANT (0x00 << 2) +# define HAL_MCFxxxx_CANx_CTRL0_RXMODE_1_DOMINANT (0x01 << 2) +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_MASK (0x03 << 0) +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_SHIFT 0 +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_FULL_0_DOMINANT (0x00 << 0) +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_FULL_1_DOMINANT (0x01 << 0) +# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_OPEN_0_DOMINANT (0x02 << 0) + +# define HAL_MCFxxxx_CANx_CTRL1_SAMP (0x01 << 7) +# define HAL_MCFxxxx_CANx_CTRL1_TSYNC (0x01 << 5) +# define HAL_MCFxxxx_CANx_CTRL1_LBUF (0x01 << 4) +# define HAL_MCFxxxx_CANx_CTRL1_LOM (0x01 << 3) +# define HAL_MCFxxxx_CANx_CTRL1_PROPSEG_MASK (0x07 << 0) +# define HAL_MCFxxxx_CANx_CTRL1_PROPSEG_SHIFT 0 + +# define HAL_MCFxxxx_CANx_CTRL2_RJW_MASK (0x03 << 6) +# define HAL_MCFxxxx_CANx_CTRL2_RJW_SHIFT 6 +# define HAL_MCFxxxx_CANx_CTRL2_PSEG1_MASK (0x07 << 3) +# define HAL_MCFxxxx_CANx_CTRL2_PSEG1_SHIFT 3 +# define HAL_MCFxxxx_CANx_CTRL2_PSEG2_MASK (0x07 << 0) +# define HAL_MCFxxxx_CANx_CTRL2_PSEG2_SHIFT 0 + +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_MASK (0x03 << 14) +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_SHIFT 14 +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_NONE (0x00 << 14) +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_DOMINANT_RECESSIVE (0x01 << 14) +# define HAL_MCFxxxx_CANx_ESTAT_BITERR_RECESSIVE_DOMINANT (0x02 << 14) +# define HAL_MCFxxxx_CANx_ESTAT_ACKERR (0x01 << 13) +# define HAL_MCFxxxx_CANx_ESTAT_CRCERR (0x01 << 12) +# define HAL_MCFxxxx_CANx_ESTAT_FORMERR (0x01 << 11) +# define HAL_MCFxxxx_CANx_ESTAT_STUFFERR (0x01 << 10) +# define HAL_MCFxxxx_CANx_ESTAT_TXWARN (0x01 << 9) +# define HAL_MCFxxxx_CANx_ESTAT_RXWARN (0x01 << 8) +# define HAL_MCFxxxx_CANx_ESTAT_IDLE (0x01 << 7) +# define HAL_MCFxxxx_CANx_ESTAT_TX_RX (0x01 << 6) +# define HAL_MCFxxxx_CANx_ESTAT_FCS_MASK (0x03 << 4) +# define HAL_MCFxxxx_CANx_ESTAT_FCS_SHIFT 4 +# define HAL_MCFxxxx_CANx_ESTAT_FCS_ERROR_ACTIVE (0x00 << 4) +# define HAL_MCFxxxx_CANx_ESTAT_FCS_ERROR_PASSIVE (0x01 << 4) +# define HAL_MCFxxxx_CANx_ESTAT_BOFFINT (0x01 << 2) +# define HAL_MCFxxxx_CANx_ESTAT_ERRINT (0x01 << 1) +# define HAL_MCFxxxx_CANx_ESTAT_WAKEINT (0x01 << 0) + +#endif // HAL_MCFxxxx_HAS_MCF5282_CAN + +// Some ColdFire processors have a variation of the CAN device where all +// the registers are 32-bit. +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_CAN_32BIT_REGS +# define HAL_MCFxxxx_CANx_MCR 0x0000 +# define HAL_MCFxxxx_CANx_CTRL 0x0004 +# define HAL_MCFxxxx_CANx_TIMER 0x0008 +# define HAL_MCFxxxx_CANx_RXGMASK 0x0010 +# define HAL_MCFxxxx_CANx_RX14MASK 0x0014 +# define HAL_MCFxxxx_CANx_RX15MASK 0x0018 +# define HAL_MCFxxxx_CANx_ERRCNT 0x001C +# define HAL_MCFxxxx_CANx_ERRSTAT 0x0020 +# define HAL_MCFxxxx_CANx_IMASK 0x0028 +# define HAL_MCFxxxx_CANx_IFLAG 0x0030 +# define HAL_MCFxxxx_CANx_BUF 0x0080 + +# define HAL_MCFxxxx_CANx_MCR_MDIS (0x01 << 31) +# define HAL_MCFxxxx_CANx_MCR_FRZ (0x01 << 30) +# define HAL_MCFxxxx_CANx_MCR_HALT (0x01 << 28) +# define HAL_MCFxxxx_CANx_MCR_NOTRDY (0x01 << 27) +# define HAL_MCFxxxx_CANx_MCR_SOFTRST (0x01 << 25) +# define HAL_MCFxxxx_CANx_MCR_FRZACK (0x01 << 24) +# define HAL_MCFxxxx_CANx_MCR_SUPV (0x01 << 23) +# define HAL_MCFxxxx_CANx_MCR_LPMACK (0x01 << 20) +# define HAL_MCFxxxx_CANx_MCR_MAXMB_MASK (0x0F << 0) +# define HAL_MCFxxxx_CANx_MCR_MAXMB_SHIFT 0 + +# define HAL_MCFxxxx_CANx_CTRL_PRESDIV_MASK (0x00FF << 24) +# define HAL_MCFxxxx_CANx_CTRL_PRESDIV_SHIFT 24 +# define HAL_MCFxxxx_CANx_CTRL_RJW_MASK (0x03 << 22) +# define HAL_MCFxxxx_CANx_CTRL_RJW_SHIFT 22 +# define HAL_MCFxxxx_CANx_CTRL_PSEG1_MASK (0x07 << 19) +# define HAL_MCFxxxx_CANx_CTRL_PSEG1_SHIFT 19 +# define HAL_MCFxxxx_CANx_CTRL_PSEG2_MASK (0x07 << 16) +# define HAL_MCFxxxx_CANx_CTRL_PSEG2_SHIFT 16 +# define HAL_MCFxxxx_CANx_CTRL_BOFFMSK (0x01 << 15) +# define HAL_MCFxxxx_CANx_CTRL_ERRMSK (0x01 << 14) +# define HAL_MCFxxxx_CANx_CTRL_CLKSRC (0x01 << 13) +# define HAL_MCFxxxx_CANx_CTRL_LPB (0x01 << 12) +# define HAL_MCFxxxx_CANx_CTRL_SMP (0x01 << 7) +# define HAL_MCFxxxx_CANx_CTRL_BOFFREC (0x01 << 6) +# define HAL_MCFxxxx_CANx_CTRL_TSYN (0x01 << 5) +# define HAL_MCFxxxx_CANx_CTRL_LBUF (0x01 << 4) +# define HAL_MCFxxxx_CANx_CTRL_LOM (0x01 << 3) +# define HAL_MCFxxxx_CANx_CTRL_PROPSEG_MASK (0x07 << 0) +# define HAL_MCFxxxx_CANx_CTRL_PROPSEG_SHIFT 0 + +# define HAL_MCFxxxx_CANx_ERRCNT_RXECTR_MASK (0x00FF << 8) +# define HAL_MCFxxxx_CANx_ERRCNT_RXECTR_SHIFT 8 +# define HAL_MCFxxxx_CANx_ERRCNT_TXECTR_MASK (0x00FF << 0) +# define HAL_MCFxxxx_CANx_ERRCNT_TXECTR_SHIFT 0 + +# define HAL_MCFxxxx_CANx_ERRSTAT_BIT1ERR (0x01 << 15) +# define HAL_MCFxxxx_CANx_ERRSTAT_BIT0ERR (0x01 << 14) +# define HAL_MCFxxxx_CANx_ERRSTAT_ACKERR (0x01 << 13) +# define HAL_MCFxxxx_CANx_ERRSTAT_CRCERR (0x01 << 12) +# define HAL_MCFxxxx_CANx_ERRSTAT_FRMERR (0x01 << 11) +# define HAL_MCFxxxx_CANx_ERRSTAT_STFERR (0x01 << 10) +# define HAL_MCFxxxx_CANx_ERRSTAT_TXWRN (0x01 << 9) +# define HAL_MCFxxxx_CANx_ERRSTAT_RXWRN (0x01 << 8) +# define HAL_MCFxxxx_CANx_ERRSTAT_IDLE (0x01 << 7) +# define HAL_MCFxxxx_CANx_ERRSTAT_TXRX (0x01 << 6) +# define HAL_MCFxxxx_CANx_ERRSTAT_FLTCONF_MASK (0x03 << 4) +# define HAL_MCFxxxx_CANx_ERRSTAT_FLTCONF_SHIFT 4 +# define HAL_MCFxxxx_CANx_ERRSTAT_BOFFINT (0x01 << 2) +# define HAL_MCFxxxx_CANx_ERRSTAT_ERRINT (0x01 << 1) +#endif + +// ---------------------------------------------------------------------------- +#ifdef HAL_MCFxxxx_HAS_MCF5282_QADC +// Queued analog-to-digital converter + +// Configuration register, 16 bits +# define HAL_MCFxxxx_QADC_QADCMCR 0x0000 +// Test register, 16 bits. This is only usable in factory test mode +# define HAL_MCFxxxx_QADC_QADCTEST 0x0002 +// Two port data registers, 8 bits each +# define HAL_MCFxxxx_QADC_PORTQA 0x0006 +# define HAL_MCFxxxx_QADC_PORTQB 0x0007 +// Two port direction registers, 8 bits each +# define HAL_MCFxxxx_QADC_DDRQA 0x0008 +# define HAL_MCFxxxx_QADC_DDRQB 0x0009 +// Three control registers, 16 bits each +# define HAL_MCFxxxx_QADC_QACR0 0x000A +# define HAL_MCFxxxx_QADC_QACR1 0x000C +# define HAL_MCFxxxx_QADC_QACR2 0x000E +// Two status registers, 16 bits each +# define HAL_MCFxxxx_QADC_QASR0 0x0010 +# define HAL_MCFxxxx_QADC_QASR1 0x0012 +// Command word table, 64 entries * 16 bits each +# define HAL_MCFxxxx_QADC_CCW 0x0200 +// Right-justified unsigned results, 64 entries * 16 bits +# define HAL_MCFxxxx_QADC_RJURR 0x0280 +// Left-justified signed results, 64 entries * 16 bits +# define HAL_MCFxxxx_QADC_LJSRR 0x0300 +// Left-justified unsigned results, 64 entries * 16 bits +# define HAL_MCFxxxx_QADC_LJURR 0x0380 + +# define HAL_MCFxxxx_QADC_QADCMCR_QSTOP (0x01 << 15) +# define HAL_MCFxxxx_QADC_QADCMCR_QDBG (0x01 << 14) +# define HAL_MCFxxxx_QADC_QADCMCR_QSUPV (0x01 << 7) + +// The port data and direction registers just provide control +// over four signals apiece. + +# define HAL_MCFxxxx_QADC_QACR0_MUX (0x01 << 15) +# define HAL_MCFxxxx_QADC_QACR0_TRG (0x01 << 14) +# define HAL_MCFxxxx_QADC_QACR0_QPR_MASK (0x7F << 0) +# define HAL_MCFxxxx_QADC_QACR0_QPR_SHIFT 0 +// The actual prescaler is (2 * (QPR+1)), except for a QPR value +// of 0 which gives a prescaler of 4. + +// QACR1 and QACR2 control queues 1 and 2 respectively +# define HAL_MCFxxxx_QADC_QACRn_CIE (0x01 << 15) +# define HAL_MCFxxxx_QADC_QACRn_PIE (0x01 << 14) +# define HAL_MCFxxxx_QADC_QACRn_SSE (0x01 << 13) +# define HAL_MCFxxxx_QADC_QACRn_MQ_MASK (0x1F << 8) +# define HAL_MCFxxxx_QADC_QACRn_MQ_SHIFT 8 +// There are 32 different modes, see the manual for details. + +// QACR2 has some additional bits to support resume operations +# define HAL_MCFxxxx_QADC_QACR2_RESUME (0x01 << 7) +# define HAL_MCFxxxx_QADC_QACR2_BQ_MASK (0x7F << 0) +# define HAL_MCFxxxx_QADC_QACR2_BQ_SHIFT 0 + +# define HAL_MCFxxxx_QADC_QASR0_CF1 (0x01 << 15) +# define HAL_MCFxxxx_QADC_QASR0_PF1 (0x01 << 14) +# define HAL_MCFxxxx_QADC_QASR0_CF2 (0x01 << 13) +# define HAL_MCFxxxx_QADC_QASR0_PF2 (0x01 << 12) +# define HAL_MCFxxxx_QADC_QASR0_TOR1 (0x01 << 11) +# define HAL_MCFxxxx_QADC_QASR0_TOR2 (0x01 << 10) +# define HAL_MCFxxxx_QADC_QASR0_QS_MASK (0x0F << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_SHIFT 6 +# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_IDLE (0x00 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_PAUSED (0x01 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_ACTIVE (0x02 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_PENDING (0x03 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_IDLE (0x04 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_PAUSED (0x05 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_ACTIVE (0x06 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_PENDING (0x07 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_IDLE (0x08 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_PAUSED (0x09 << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_SUSPENDED (0x0A << 6) +# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_PENDING (0x0B << 6) +# define HAL_MCFxxxx_QADC_QASR0_CWP_MASK (0x3F << 0) +# define HAL_MCFxxxx_QADC_QASR0_CWP_SHIFT 0 + +# define HAL_MCFxxxx_QADC_QASR1_CWPQ1_MASK (0x3F << 8) +# define HAL_MCFxxxx_QADC_QASR1_CWPQ1_SHIFT 8 +# define HAL_MCFxxxx_QADC_QASR1_CWPQ_MASK (0x3F << 0) +# define HAL_MCFxxxx_QADC_QASR1_CWPQ_SHIFT 0 + +# define HAL_MCFxxxx_QADC_CCW_PAUSE (0x01 << 9) +# define HAL_MCFxxxx_QADC_CCW_BYP (0x01 << 8) +# define HAL_MCFxxxx_QADC_CCW_IST_MASK (0x03 << 6) +# define HAL_MCFxxxx_QADC_CCW_IST_SHIFT 6 +# define HAL_MCFxxxx_QADC_CCW_IST_2 (0x00 << 6) +# define HAL_MCFxxxx_QADC_CCW_IST_4 (0x01 << 6) +# define HAL_MCFxxxx_QADC_CCW_IST_8 (0x02 << 6) +# define HAL_MCFxxxx_QADC_CCW_IST_16 (0x03 << 6) +# define HAL_MCFxxxx_QADC_CCW_CHAN_MASK (0x3F << 0) +# define HAL_MCFxxxx_QADC_CCW_CHAN_SHIFT 0 + +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN0 0 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN1 1 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN2 2 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN3 3 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN52 52 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN53 53 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN55 55 +# define HAL_MCFxxxx_QADC_CCW_CHAN_AN56 56 +# define HAL_MCFxxxx_QADC_CCW_CHAN_ETRIG1 55 +# define HAL_MCFxxxx_QADC_CCW_CHAN_ETRIG2 56 +# define HAL_MCFxxxx_QADC_CCW_CHAN_LOWREF 60 +# define HAL_MCFxxxx_QADC_CCW_CHAN_HIGHREF 61 +# define HAL_MCFxxxx_QADC_CCW_CHAN_MIDREF 62 +# define HAL_MCFxxxx_QADC_CCW_CHAN_EOQ 63 + +#endif // HAL_MCFxxxx_HAS_MCF5282_QADC + +// ---------------------------------------------------------------------------- +// Pulse width modulation unit. +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_PWM +# define HAL_MCFxxxx_PWMx_PWME 0x0000 +# define HAL_MCFxxxx_PWMx_PWMPOL 0x0001 +# define HAL_MCFxxxx_PWMx_PWMCLK 0x0002 +# define HAL_MCFxxxx_PWMx_PWMPRCLK 0x0003 +# define HAL_MCFxxxx_PWMx_PWMCAE 0x0004 +# define HAL_MCFxxxx_PWMx_PWMCTL 0x0005 +# define HAL_MCFxxxx_PWMx_PWMSCLA 0x0008 +# define HAL_MCFxxxx_PWMx_PWMSCLB 0x0009 +# define HAL_MCFxxxx_PWMx_PWMCNT0 0x000C +# define HAL_MCFxxxx_PWMx_PWMCNT1 0x000D +# define HAL_MCFxxxx_PWMx_PWMCNT2 0x000E +# define HAL_MCFxxxx_PWMx_PWMCNT3 0x000F +# define HAL_MCFxxxx_PWMx_PWMCNT4 0x0010 +# define HAL_MCFxxxx_PWMx_PWMCNT5 0x0011 +# define HAL_MCFxxxx_PWMx_PWMCNT6 0x0012 +# define HAL_MCFxxxx_PWMx_PWMCNT7 0x0013 +# define HAL_MCFxxxx_PWMx_PWMPER0 0x0014 +# define HAL_MCFxxxx_PWMx_PWMPER1 0x0015 +# define HAL_MCFxxxx_PWMx_PWMPER2 0x0016 +# define HAL_MCFxxxx_PWMx_PWMPER3 0x0017 +# define HAL_MCFxxxx_PWMx_PWMPER4 0x0018 +# define HAL_MCFxxxx_PWMx_PWMPER5 0x0019 +# define HAL_MCFxxxx_PWMx_PWMPER6 0x001A +# define HAL_MCFxxxx_PWMx_PWMPER7 0x001B +# define HAL_MCFxxxx_PWMx_PWMDTY0 0x001C +# define HAL_MCFxxxx_PWMx_PWMDTY1 0x001D +# define HAL_MCFxxxx_PWMx_PWMDTY2 0x001E +# define HAL_MCFxxxx_PWMx_PWMDTY3 0x001F +# define HAL_MCFxxxx_PWMx_PWMDTY4 0x0020 +# define HAL_MCFxxxx_PWMx_PWMDTY5 0x0021 +# define HAL_MCFxxxx_PWMx_PWMDTY6 0x0022 +# define HAL_MCFxxxx_PWMx_PWMDTY7 0x0023 +# define HAL_MCFxxxx_PWMx_PWMSDN 0x0024 + +# define HAL_MCFxxxx_PWMx_PWME_PWME7 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWME_PWME5 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWME_PWME3 (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWME_PWME1 (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL7 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL5 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL3 (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL1 (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK7 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK5 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK3 (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK1 (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKB_MASK (0x07 << 4) +# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKB_SHIFT 4 +# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKA_MASK (0x07 << 0) +# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKA_SHIFT 0 +# define HAL_MCFxxxx_PWMx_PWMCAE_CAE7 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMCAE_CAE5 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMCAE_CAE3 (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWMCAE_CAE1 (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMCTL_CON67 (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMCTL_CON45 (0x01 << 6) +# define HAL_MCFxxxx_PWMx_PWMCTL_CON23 (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMCTL_CON01 (0x01 << 4) +# define HAL_MCFxxxx_PWMx_PWMCTL_PSWAI (0x01 << 3) +# define HAL_MCFxxxx_PWMx_PWMCTL_PFRZ (0x01 << 2) +# define HAL_MCFxxxx_PWMx_PWMSDN_IF (0x01 << 7) +# define HAL_MCFxxxx_PWMx_PWMSDN_IE (0x01 << 6) +# define HAL_MCFxxxx_PWMx_PWMSDN_RESTART (0x01 << 5) +# define HAL_MCFxxxx_PWMx_PWMSDN_LVL (0x01 << 4) +# define HAL_MCFxxxx_PWMx_PWMSDN_PWM7IN (0x01 << 2) +# define HAL_MCFxxxx_PWMx_PWMSDN_PWM7IL (0x01 << 1) +# define HAL_MCFxxxx_PWMx_PWMSDN_SDNEN (0x01 << 0) +#endif // HAS_MCFxxxx_PWM + +// ---------------------------------------------------------------------------- +// Real-time clock. +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_RTC +# define HAL_MCFxxxx_RTC_HOURMIN 0x00 +# define HAL_MCFxxxx_RTC_SECONDS 0x04 +# define HAL_MCFxxxx_RTC_ALRM_HM 0x08 +# define HAL_MCFxxxx_RTC_ALRM_SEC 0x0C +# define HAL_MCFxxxx_RTC_CR 0x10 +# define HAL_MCFxxxx_RTC_ISR 0x14 +# define HAL_MCFxxxx_RTC_IER 0x18 +# define HAL_MCFxxxx_RTC_STPWCH 0x1C +# define HAL_MCFxxxx_RTC_DAYS 0x20 +# define HAL_MCFxxxx_RTC_ALRM_DAY 0x24 + +# define HAL_MCFxxxx_RTC_HOURMIN_HOURS_MASK (0x1F << 8) +# define HAL_MCFxxxx_RTC_HOURMIN_HOURS_SHIFT 8 +# define HAL_MCFxxxx_RTC_HOURMIN_MINUTES_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_HOURMIN_MINUTES_SHIFT 0 +# define HAL_MCFxxxx_RTC_SECONDS_SECONDS_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_SECONDS_SECONDS_SHIFT 0 +# define HAL_MCFxxxx_RTC_ALRM_HM_HOURS_MASK (0x1F << 8) +# define HAL_MCFxxxx_RTC_ALRM_HM_HOURS_SHIFT 8 +# define HAL_MCFxxxx_RTC_ALRM_HM_MINUTES_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_ALRM_HM_MINUTES_SHIFT 0 +# define HAL_MCFxxxx_RTC_ALRM_SEC_SECONDS_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_ALARM_SEC_SECONDS_SHIFT 0 +# define HAL_MCFxxxx_RTC_CR_EN (0x01 << 7) +# define HAL_MCFxxxx_RTC_CR_XTL_MASK (0x03 << 5) +# define HAL_MCFxxxx_RTC_CR_XTL_SHIFT 5 +# define HAL_MCFxxxx_RTC_CR_XTL_32768 (0x00 << 5) +# define HAL_MCFxxxx_RTC_CR_XTL_32000 (0x01 << 5) +# define HAL_MCFxxxx_RTC_CR_XTL_38400 (0x02 << 5) +# define HAL_MCFxxxx_RTC_CR_SWR (0x01 << 0) +# define HAL_MCFxxxx_RTC_ISR_SAM7 (0x01 << 15) +# define HAL_MCFxxxx_RTC_ISR_SAM6 (0x01 << 14) +# define HAL_MCFxxxx_RTC_ISR_SAM5 (0x01 << 13) +# define HAL_MCFxxxx_RTC_ISR_SAM4 (0x01 << 12) +# define HAL_MCFxxxx_RTC_ISR_SAM3 (0x01 << 11) +# define HAL_MCFxxxx_RTC_ISR_SAM2 (0x01 << 10) +# define HAL_MCFxxxx_RTC_ISR_SAM1 (0x01 << 9) +# define HAL_MCFxxxx_RTC_ISR_SAM0 (0x01 << 8) +# define HAL_MCFxxxx_RTC_ISR_2HZ (0x01 << 7) +# define HAL_MCFxxxx_RTC_ISR_HR (0x01 << 5) +# define HAL_MCFxxxx_RTC_ISR_1HZ (0x01 << 4) +# define HAL_MCFxxxx_RTC_ISR_DAY (0x01 << 3) +# define HAL_MCFxxxx_RTC_ISR_ALM (0x01 << 2) +# define HAL_MCFxxxx_RTC_ISR_MIN (0x01 << 1) +# define HAL_MCFxxxx_RTC_ISR_SW (0x01 << 0) +# define HAL_MCFxxxx_RTC_IER_SAM7 (0x01 << 15) +# define HAL_MCFxxxx_RTC_IER_SAM6 (0x01 << 14) +# define HAL_MCFxxxx_RTC_IER_SAM5 (0x01 << 13) +# define HAL_MCFxxxx_RTC_IER_SAM4 (0x01 << 12) +# define HAL_MCFxxxx_RTC_IER_SAM3 (0x01 << 11) +# define HAL_MCFxxxx_RTC_IER_SAM2 (0x01 << 10) +# define HAL_MCFxxxx_RTC_IER_SAM1 (0x01 << 9) +# define HAL_MCFxxxx_RTC_IER_SAM0 (0x01 << 8) +# define HAL_MCFxxxx_RTC_IER_2HZ (0x01 << 7) +# define HAL_MCFxxxx_RTC_IER_HR (0x01 << 5) +# define HAL_MCFxxxx_RTC_IER_1HZ (0x01 << 4) +# define HAL_MCFxxxx_RTC_IER_DAY (0x01 << 3) +# define HAL_MCFxxxx_RTC_IER_ALM (0x01 << 2) +# define HAL_MCFxxxx_RTC_IER_MIN (0x01 << 1) +# define HAL_MCFxxxx_RTC_IER_SW (0x01 << 0) +# define HAL_MCFxxxx_RTC_STPWCH_CNT_MASK (0x3F << 0) +# define HAL_MCFxxxx_RTC_STPWCH_CNT_SHIFT 0 +# define HAL_MCFxxxx_RTC_DAYS_DAYS_MASK (0x00FFFF << 0) +# define HAL_MCFxxxx_RTC_DAYS_DAYS_SHIFT 0 +# define HAL_MCFxxxx_RTC_ALRM_DAY_DAYS_MASK (0x00FFFF << 0) +# define HAL_MCFxxxx_RTC_ALRM_DAY_DAYS_SHIFT 0 +#endif // HAS_MCFxxxx_RTC + +// ---------------------------------------------------------------------------- +// Message digest hardware +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_MDHA +# define HAL_MCFxxxx_MDHA_MR 0x0000 +# define HAL_MCFxxxx_MDHA_CR 0x0004 +# define HAL_MCFxxxx_MDHA_CMR 0x0008 +# define HAL_MCFxxxx_MDHA_SR 0x000C +# define HAL_MCFxxxx_MDHA_ISR 0x0010 +# define HAL_MCFxxxx_MDHA_IMR 0x0014 +# define HAL_MCFxxxx_MDHA_DSR 0x001C +# define HAL_MCFxxxx_MDHA_MIN 0x0020 +# define HAL_MCFxxxx_MDHA_A0 0x0030 +# define HAL_MCFxxxx_MDHA_B0 0x0034 +# define HAL_MCFxxxx_MDHA_C0 0x0038 +# define HAL_MCFxxxx_MDHA_D0 0x003C +# define HAL_MCFxxxx_MDHA_E0 0x0040 +# define HAL_MCFxxxx_MDHA_MDS 0x0044 +# define HAL_MCFxxxx_MDHA_A1 0x0070 +# define HAL_MCFxxxx_MDHA_B1 0x0074 +# define HAL_MCFxxxx_MDHA_C1 0x0078 +# define HAL_MCFxxxx_MDHA_D1 0x007C +# define HAL_MCFxxxx_MDHA_E1 0x0080 + +# define HAL_MCFxxxx_MDHA_MR_SSL (0x01 << 10) +# define HAL_MCFxxxx_MDHA_MR_MACFULL (0x01 << 9) +# define HAL_MCFxxxx_MDHA_MR_SWAP (0x01 << 8) +# define HAL_MCFxxxx_MDHA_MR_OPAD (0x01 << 7) +# define HAL_MCFxxxx_MDHA_MR_IPAD (0x01 << 6) +# define HAL_MCFxxxx_MDHA_MR_INIT (0x01 << 5) +# define HAL_MCFxxxx_MDHA_MR_MAC_MASK (0x03 << 3) +# define HAL_MCFxxxx_MDHA_MR_MAC_SHIFT 3 +# define HAL_MCFxxxx_MDHA_MR_MAC_NONE (0x00 << 3) +# define HAL_MCFxxxx_MDHA_MR_MAC_HMAC (0x01 << 3) +# define HAL_MCFxxxx_MDHA_MR_MAC_EHMAC (0x02 << 3) +# define HAL_MCFxxxx_MDHA_MR_PDATA (0x01 << 2) +# define HAL_MCFxxxx_MDHA_MR_ALG (0x01 << 0) +# define HAL_MCFxxxx_MDHA_CR_DMAL_MASK (0x1F << 16) +# define HAL_MCFxxxx_MDHA_CR_DMAL_SHIFT 16 +# define HAL_MCFxxxx_MDHA_CR_END (0x01 << 2) +# define HAL_MCFxxxx_MDHA_CR_DMA (0x01 << 2) +# define HAL_MCFxxxx_MDHA_CR_IE (0x01 << 2) +# define HAL_MCFxxxx_MDHA_CMR_GO (0x01 << 3) +# define HAL_MCFxxxx_MDHA_CMR_CI (0x01 << 2) +# define HAL_MCFxxxx_MDHA_CMR_RI (0x01 << 1) +# define HAL_MCFxxxx_MDHA_CMR_SWR (0x01 << 0) +# define HAL_MCFxxxx_MDHA_SR_IFL_MASK (0x00FF << 16) +# define HAL_MCFxxxx_MDHA_SR_IFL_SHIFT 16 +# define HAL_MCFxxxx_MDHA_SR_APD_MASK (0x07 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_SHIFT 13 +# define HAL_MCFxxxx_MDHA_SR_APD_STANDARD (0x00 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_PAD_LAST_WORD (0x01 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_ADD_A_WORD (0x02 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_LAST_HASH (0x03 << 13) +# define HAL_MCFxxxx_MDHA_SR_APD_STALL_STATE (0x04 << 13) +# define HAL_MCFxxxx_MDHA_SR_FS_MASK (0x07 << 8) +# define HAL_MCFxxxx_MDHA_SR_FS_SHIFT 8 +# define HAL_MCFxxxx_MDHA_SR_GNW (0x01 << 7) +# define HAL_MCFxxxx_MDHA_SR_HSH (0x01 << 6) +# define HAL_MCFxxxx_MDHA_SR_BUSY (0x01 << 4) +# define HAL_MCFxxxx_MDHA_SR_RD (0x01 << 3) +# define HAL_MCFxxxx_MDHA_SR_ERR (0x01 << 2) +# define HAL_MCFxxxx_MDHA_SR_DONE (0x01 << 1) +# define HAL_MCFxxxx_MDHA_SR_INT (0x01 << 0) +# define HAL_MCFxxxx_MDHA_ISR_DRL (0x01 << 10) +# define HAL_MCFxxxx_MDHA_ISR_GTDS (0x01 << 9) +# define HAL_MCFxxxx_MDHA_ISR_ERE (0x01 << 8) +# define HAL_MCFxxxx_MDHA_ISR_RMDP (0x01 << 7) +# define HAL_MCFxxxx_MDHA_ISR_DSE (0x01 << 5) +# define HAL_MCFxxxx_MDHA_ISR_IME (0x01 << 4) +# define HAL_MCFxxxx_MDHA_ISR_NEIF (0x01 << 2) +# define HAL_MCFxxxx_MDHA_ISR_IFO (0x01 << 0) +# define HAL_MCFxxxx_MDHA_IMR_DRL (0x01 << 10) +# define HAL_MCFxxxx_MDHA_IMR_GTDS (0x01 << 9) +# define HAL_MCFxxxx_MDHA_IMR_ERE (0x01 << 8) +# define HAL_MCFxxxx_MDHA_IMR_RMDP (0x01 << 7) +# define HAL_MCFxxxx_MDHA_IMR_DSE (0x01 << 5) +# define HAL_MCFxxxx_MDHA_IMR_IME (0x01 << 4) +# define HAL_MCFxxxx_MDHA_IMR_NEIF (0x01 << 2) +# define HAL_MCFxxxx_MDHA_IMR_IFO (0x01 << 0) +#endif // HAS_MCFxxxx_MDHA + +// ---------------------------------------------------------------------------- +// Random number generation +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_RNG +# define HAL_MCFxxxx_RNG_CR 0x00000000 +# define HAL_MCFxxxx_RNG_SR 0x00000004 +# define HAL_MCFxxxx_RNG_ER 0x00000008 +# define HAL_MCFxxxx_RNG_OUT 0x0000000C + +# define HAL_MCFxxxx_RNG_CR_CI (0x01 << 3) +# define HAL_MCFxxxx_RNG_CR_IM (0x01 << 2) +# define HAL_MCFxxxx_RNG_CR_HA (0x01 << 1) +# define HAL_MCFxxxx_RNG_CR_GO (0x01 << 0) +# define HAL_MCFxxxx_RNG_SR_OFS_MASK (0x00FF << 16) +# define HAL_MCFxxxx_RNG_SR_OFS_SHIFT 16 +# define HAL_MCFxxxx_RNG_SR_OFL_MASK (0x00FF << 8) +# define HAL_MCFxxxx_RNG_SR_OFL_SHIFT 8 +# define HAL_MCFxxxx_RNG_SR_EI (0x01 << 3) +# define HAL_MCFxxxx_RNG_SR_FUF (0x01 << 2) +# define HAL_MCFxxxx_RNG_SR_LRS (0x01 << 1) +# define HAL_MCFxxxx_RNG_SR_SR (0x01 << 0) +#endif // HAS_MCFxxxx_RNG + +// ---------------------------------------------------------------------------- +// Symmetric key hardware +#ifdef HAL_MCFxxxx_HAS_MCFxxxx_SKHA + +# define HAL_MCFxxxx_SKHA_MR 0x00000000 +# define HAL_MCFxxxx_SKHA_CR 0x00000004 +# define HAL_MCFxxxx_SKHA_CMR 0x00000008 +# define HAL_MCFxxxx_SKHA_SR 0x0000000C +# define HAL_MCFxxxx_SKHA_ESR 0x00000010 +# define HAL_MCFxxxx_SKHA_EMR 0x00000014 +# define HAL_MCFxxxx_SKHA_KSR 0x00000018 +# define HAL_MCFxxxx_SKHA_DSR 0x0000001C +# define HAL_MCFxxxx_SKHA_IN 0x00000020 +# define HAL_MCFxxxx_SKHA_OUT 0x00000024 +# define HAL_MCFxxxx_SKHA_KDR1 0x00000030 +# define HAL_MCFxxxx_SKHA_KDR2 0x00000034 +# define HAL_MCFxxxx_SKHA_KDR3 0x00000038 +# define HAL_MCFxxxx_SKHA_KDR4 0x0000003C +# define HAL_MCFxxxx_SKHA_KDR5 0x00000040 +# define HAL_MCFxxxx_SKHA_KDR6 0x00000044 +# define HAL_MCFxxxx_SKHA_C1 0x00000070 +# define HAL_MCFxxxx_SKHA_C2 0x00000074 +# define HAL_MCFxxxx_SKHA_C3 0x00000078 +# define HAL_MCFxxxx_SKHA_C4 0x0000007C +# define HAL_MCFxxxx_SKHA_C5 0x00000080 +# define HAL_MCFxxxx_SKHA_C6 0x00000084 +# define HAL_MCFxxxx_SKHA_C7 0x00000088 +# define HAL_MCFxxxx_SKHA_C8 0x0000008C +# define HAL_MCFxxxx_SKHA_C9 0x00000090 +# define HAL_MCFxxxx_SKHA_C10 0x00000094 +# define HAL_MCFxxxx_SKHA_C11 0x00000098 + +# define HAL_MCFxxxx_SKHA_MR_CTRM_MASK (0x0F << 9) +# define HAL_MCFxxxx_SKHA_MR_CTRM_SHIFT 9 +# define HAL_MCFxxxx_SKHA_MR_DKP (0x01 << 8) +# define HAL_MCFxxxx_SKHA_MR_CM_MASK (0x03 << 3) +# define HAL_MCFxxxx_SKHA_MR_CM_SHIFT 3 +# define HAL_MCFxxxx_SKHA_MR_CM_ECB (0x00 << 3) +# define HAL_MCFxxxx_SKHA_MR_CM_CBC (0x01 << 3) +# define HAL_MCFxxxx_SKHA_MR_CM_CTR (0x03 << 3) +# define HAL_MCFxxxx_SKHA_MR_DIR (0x01 << 2) +# define HAL_MCFxxxx_SKHA_MR_ALG_MASK (0x03 << 0) +# define HAL_MCFxxxx_SKHA_MR_ALG_SHIFT 0 +# define HAL_MCFxxxx_SKHA_MR_ALG_AES (0x00 << 0) +# define HAL_MCFxxxx_SKHA_MR_ALG_DES (0x01 << 0) +# define HAL_MCFxxxx_SKHA_MR_ALG_3DES (0x02 << 0) +# define HAL_MCFxxxx_SKHA_CR_ODMAL_MASK (0x3F << 24) +# define HAL_MCFxxxx_SKHA_CR_ODMAL_SHIFT 24 +# define HAL_MCFxxxx_SKHA_CR_IDMAL_MASK (0x3F << 16) +# define HAL_MCFxxxx_SKHA_CR_IDMAL_SHIFT 16 +# define HAL_MCFxxxx_SKHA_CR_END (0x01 << 3) +# define HAL_MCFxxxx_SKHA_CR_ODMA (0x01 << 2) +# define HAL_MCFxxxx_SKHA_CR_IDMA (0x01 << 1) +# define HAL_MCFxxxx_SKHA_CR_IE (0x01 << 0) +# define HAL_MCFxxxx_SKHA_CMR_GO (0x01 << 3) +# define HAL_MCFxxxx_SKHA_CMR_CI (0x01 << 2) +# define HAL_MCFxxxx_SKHA_CMR_RI (0x01 << 1) +# define HAL_MCFxxxx_SKHA_CMR_SWR (0x01 << 0) +# define HAL_MCFxxxx_SKHA_SR_OFL_MASK (0x00FF << 24) +# define HAL_MCFxxxx_SKHA_SR_OFL_SHIFT 24 +# define HAL_MCFxxxx_SKHA_SR_IFL_MASK (0x00FF << 16) +# define HAL_MCFxxxx_SKHA_SR_IFL_SHIFT 16 +# define HAL_MCFxxxx_SKHA_SR_BUSY (0x01 << 4) +# define HAL_MCFxxxx_SKHA_SR_RD (0x01 << 3) +# define HAL_MCFxxxx_SKHA_SR_ERR (0x01 << 2) +# define HAL_MCFxxxx_SKHA_SR_DONE (0x01 << 1) +# define HAL_MCFxxxx_SKHA_SR_INT (0x01 << 0) +# define HAL_MCFxxxx_SKHA_ESR_DRL (0x01 << 11) +# define HAL_MCFxxxx_SKHA_ESR_KRE (0x01 << 10) +# define HAL_MCFxxxx_SKHA_ESR_KPE (0x01 << 9) +# define HAL_MCFxxxx_SKHA_ESR_ERE (0x01 << 8) +# define HAL_MCFxxxx_SKHA_ESR_RMDP (0x01 << 7) +# define HAL_MCFxxxx_SKHA_ESR_KSE (0x01 << 6) +# define HAL_MCFxxxx_SKHA_ESR_DSE (0x01 << 5) +# define HAL_MCFxxxx_SKHA_ESR_IME (0x01 << 4) +# define HAL_MCFxxxx_SKHA_ESR_NEOF (0x01 << 3) +# define HAL_MCFxxxx_SKHA_ESR_NEIF (0x01 << 2) +# define HAL_MCFxxxx_SKHA_ESR_OFU (0x01 << 1) +# define HAL_MCFxxxx_SKHA_ESR_IFO (0x01 << 0) +# define HAL_MCFxxxx_SKHA_EMR_DRL (0x01 << 11) +# define HAL_MCFxxxx_SKHA_EMR_KRE (0x01 << 10) +# define HAL_MCFxxxx_SKHA_EMR_KPE (0x01 << 9) +# define HAL_MCFxxxx_SKHA_EMR_ERE (0x01 << 8) +# define HAL_MCFxxxx_SKHA_EMR_RMDP (0x01 << 7) +# define HAL_MCFxxxx_SKHA_EMR_KSE (0x01 << 6) +# define HAL_MCFxxxx_SKHA_EMR_DSE (0x01 << 5) +# define HAL_MCFxxxx_SKHA_EMR_IME (0x01 << 4) +# define HAL_MCFxxxx_SKHA_EMR_NEOF (0x01 << 3) +# define HAL_MCFxxxx_SKHA_EMR_NEIF (0x01 << 2) +# define HAL_MCFxxxx_SKHA_EMR_OFU (0x01 << 1) +# define HAL_MCFxxxx_SKHA_EMR_IFO (0x01 << 0) +#endif // HAS_MCFxxxx_SKHA + +// ---------------------------------------------------------------------------- +// Allow the processor-specific header to override some of the above, if +// necessary, or to extend the definitions. +#include <cyg/hal/proc_io.h> + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_IO_H diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/src/hal_diag.c b/ecos/packages/hal/m68k/mcf52xx/var/current/src/hal_diag.c new file mode 100644 index 0000000..e28e717 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/src/hal_diag.c @@ -0,0 +1,289 @@ +/*============================================================================= +// +// hal_diag.c +// +// ColdFire MCFxxxx HAL diagnostics support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2003-06-04 +// +//####DESCRIPTIONEND#### +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> +#ifdef CYGPKG_REDBOOT +# include <pkgconf/redboot.h> +#endif +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_if.h> +#include <cyg/hal/hal_misc.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/drv_api.h> + +// There are two main possibilities: +// 1) the platform uses the standard MCFxxxx diagnostics support, by +// enabling CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT, and +// the user has selected an available uart. +// 2) or the platform may provide its own diagnostics facilities. + +#if defined(CYGINT_HAL_M68K_MCFxxxx_DIAGNOSTICS_USE_DEFAULT) + +// Output goes via one of the UARTs. hal_diag.h will have provided +// _HAL_MCFxxxx_DIAG_UART_BASE_ and _HAL_MCFxxxx_DIAG_UART_ISRVEC_. +// Optionally the platform HAL can provide an extra INIT macro. + +void +hal_mcfxxxx_diag_uart_init(cyg_uint8* base, cyg_uint32 baud) +{ +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS) || defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) + static int initialized; + if (initialized) { + return; + } + initialized = 1; +#endif + +#ifdef HAL_MCFxxxx_UART_DIAG_PLATFORM_INIT + HAL_MCFxxxx_UART_DIAG_PLATFORM_INIT(); +#endif + + // Various resets to get the UART in a known good state + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RMRP); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RR); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RT); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RES); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_MISC_RBCI); + + // Assume that this code will only run during system startup and with + // interrupts disabled, so that imr1 and imr2 can be poked in succession. + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UMR, HAL_MCFxxxx_UARTx_UMR1_PM_NO | HAL_MCFxxxx_UARTx_UMR1_BC_8); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UMR, HAL_MCFxxxx_UARTx_UMR2_CM_NORMAL | HAL_MCFxxxx_UARTx_UMR2_SB_1); + + // Assert RTS, just in case the other side is interested + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UOP1, HAL_MCFxxxx_UARTx_UOP_RTS); + + // No hardware flow control based on fifo contents, no interrupts for change-of-state + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UACR, 0); + + // The IMR is write-only, so it is going to be difficult to set or clear just the + // rxrdy bit. Instead leave the serial interrupt enabled here but mask/unmask it + // inside the interrupt controller. + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UIMR, HAL_MCFxxxx_UARTx_UIMR_RXRDY); + + // Baud rate. Always use the internal prescaled CLKIN. The baud rate is + // determined by the platform. + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCSR, HAL_MCFxxxx_UARTx_UCSR_RCS_CLKIN | HAL_MCFxxxx_UARTx_UCSR_TCS_CLKIN); + HAL_MCFxxxx_UARTx_SET_BAUD(base, baud); + + // Enable both RX and TX + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UCR, HAL_MCFxxxx_UARTx_UCR_TC_TE | HAL_MCFxxxx_UARTx_UCR_RC_RE); +} + +void +hal_mcfxxxx_diag_uart_putc(void* channel_data, char c) +{ + cyg_uint8* base = (cyg_uint8*)channel_data; + cyg_uint8 usr; + + do { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_USR, usr); + } while (!(usr & HAL_MCFxxxx_UARTx_USR_TXRDY) ); + HAL_WRITE_UINT8(base + HAL_MCFxxxx_UARTx_UTB, c); +} + +cyg_uint8 +hal_mcfxxxx_diag_uart_getc(void* channel_data) +{ + cyg_uint8* base = (cyg_uint8*)channel_data; + cyg_uint8 usr, data; + do { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_USR, usr); + } while (!(usr & HAL_MCFxxxx_UARTx_USR_RXRDY)); + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_URB, data); + return data; +} + +// Additional routines needed in virtual vector configurations. +# if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +// State manipulated by the _control() function. Support for dynamic +// baud rates is optional. Some platforms may choose to provide this +// by implementing CYGSEM_REDBOOT_VARIABLE_BAUD_RATE +static int msec_timeout = 1; +static int irq_enabled = 0; +# ifdef CYGSEM_REDBOOT_VARIABLE_BAUD_RATE +static cyg_uint32 baud_rate = _HAL_MCFxxxx_DIAG_UART_BAUD_; +# endif + +static void +hal_mcfxxxx_diag_uart_write(void* channel_data, const cyg_uint8* buf, cyg_uint32 len) +{ + while (len-- > 0) { + hal_mcfxxxx_diag_uart_putc(channel_data, *buf++); + } +} + +static void +hal_mcfxxxx_diag_uart_read(void* channel_data, cyg_uint8* buf, cyg_uint32 len) +{ + while (len-- > 0) { + *buf++ = hal_mcfxxxx_diag_uart_getc(channel_data); + } +} + +static cyg_bool +hal_mcfxxxx_diag_uart_getc_timeout(void* channel_data, cyg_uint8* ch) +{ + cyg_uint8* base = (cyg_uint8*)channel_data; + cyg_uint8 usr; + cyg_uint8 data; + int delay_count = msec_timeout * 10; + + while (delay_count-- > 0) { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_USR, usr); + if (usr & HAL_MCFxxxx_UARTx_USR_RXRDY) { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_URB, data); + *ch = data; + return 1; + } + HAL_DELAY_US(100); + } + return 0; +} + +static int +hal_mcfxxxx_diag_uart_isr(void* channel_data, int* ctrl_c, CYG_ADDRWORD isr_vector, CYG_ADDRWORD isr_data) +{ + cyg_uint8* base = (cyg_uint8*)channel_data; + cyg_uint8 usr; + cyg_uint8 data; + + *ctrl_c = 0; + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_USR, usr); + if (usr & HAL_MCFxxxx_UARTx_USR_RXRDY) { + HAL_READ_UINT8(base + HAL_MCFxxxx_UARTx_URB, data); + if (cyg_hal_is_break((char*)&data, 1)) { + *ctrl_c = 1; + } + } + return CYG_ISR_HANDLED; +} + +static int +hal_mcfxxxx_diag_uart_control(void* channel_data, __comm_control_cmd_t func, ...) +{ + int result = -1; + va_list args; + + va_start(args, func); + switch(func) { + case __COMMCTL_IRQ_ENABLE: + result = 0; + irq_enabled = 1; + HAL_INTERRUPT_UNMASK(_HAL_MCFxxxx_DIAG_UART_ISRVEC_); + break; + case __COMMCTL_IRQ_DISABLE: + result = irq_enabled; + irq_enabled = 0; + HAL_INTERRUPT_MASK(_HAL_MCFxxxx_DIAG_UART_ISRVEC_); + break; + case __COMMCTL_DBG_ISR_VECTOR: + result = _HAL_MCFxxxx_DIAG_UART_ISRVEC_; + break; + case __COMMCTL_SET_TIMEOUT: + result = msec_timeout; + msec_timeout = va_arg(args,cyg_uint32); + break; +#ifdef CYGSEM_REDBOOT_VARIABLE_BAUD_RATE + case __COMMCTL_GETBAUD: + result = baud_rate; + break; + case __COMMCTL_SETBAUD: + baud_rate = va_arg(args, cyg_uint32); + HAL_MCFxxxx_UARTx_SET_BAUD(_HAL_MCFxxxx_DIAG_UART_BASE_, baud_rate); + result = 0; + break; +#endif + default: + break; + } + + CYG_UNUSED_PARAM(void*, channel_data); + return result; +} + +void +cyg_hal_plf_comms_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur; + + hal_mcfxxxx_diag_uart_init((cyg_uint8*)_HAL_MCFxxxx_DIAG_UART_BASE_, CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_BAUD); + // For the diag channel we may want interrupts without explicitly installing + // an interrupt handler, so the priority has to be set manually. + HAL_INTERRUPT_SET_LEVEL(_HAL_MCFxxxx_DIAG_UART_ISRVEC_, CYGNUM_HAL_M68K_MCFxxxx_DIAGNOSTICS_ISRPRI); + + cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, (void*)(_HAL_MCFxxxx_DIAG_UART_BASE_)); + CYGACC_COMM_IF_WRITE_SET(*comm, hal_mcfxxxx_diag_uart_write); + CYGACC_COMM_IF_READ_SET(*comm, hal_mcfxxxx_diag_uart_read); + CYGACC_COMM_IF_PUTC_SET(*comm, hal_mcfxxxx_diag_uart_putc); + CYGACC_COMM_IF_GETC_SET(*comm, hal_mcfxxxx_diag_uart_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, hal_mcfxxxx_diag_uart_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_mcfxxxx_diag_uart_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_mcfxxxx_diag_uart_getc_timeout); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} +# endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +#else +// The platform HAL must provide its own diagnostics routines. +#endif + +/* End of hal_diag.c */ diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/src/mcf52xx.c b/ecos/packages/hal/m68k/mcf52xx/var/current/src/mcf52xx.c new file mode 100644 index 0000000..5f5e3df --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/src/mcf52xx.c @@ -0,0 +1,124 @@ +/*============================================================================= +// +// mcfxxxx.c +// +// ColdFire MCFxxxx miscellaneous support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2008-01-14 +// +//####DESCRIPTIONEND#### +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_m68k_mcfxxxx.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_if.h> +#include <cyg/hal/hal_misc.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/drv_api.h> + +#ifdef CYGINT_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER +// ---------------------------------------------------------------------------- +// Profiling support. This requires a hardware timer set to interrupt +// at a rate determined by application code. The interrupt handler +// should call __profile_hit() with a single argument, the interrupted +// PC. One of the PIT timers, determined by the processor or platform +// HAL is used to implement the profiling timer. +// +// Usually this would involve installing an ISR. However there is no +// easy way for an ISR to get hold of the interrupted PC. In some +// configurations the save state will be stored in hal_saved_interrupt_state, +// but not always. It might be possible to extract the PC from the stack, +// but that gets messy if a separate interrupt stack is used and would be +// vulnerable to changes in the architectural VSR. Instead a custom VSR +// is installed. + +extern void hal_mcfxxxx_profile_vsr(void); + +# include <cyg/profile/profile.h> + +int +hal_enable_profile_timer(int resolution) +{ + cyg_uint16 ticks; + + // Make sure the clock is not running but is otherwise initialized. + HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PCSR, + HAL_MCFxxxx_PITx_PCSR_PRE_64 | HAL_MCFxxxx_PITx_PCSR_OVW | + HAL_MCFxxxx_PITx_PCSR_PIE | HAL_MCFxxxx_PITx_PCSR_PIF | + HAL_MCFxxxx_PITx_PCSR_RLD); + + // The resolution is a time interval in microseconds. The actual + // cpu clock frequency is determined by the platform. This is divided + // by 64, which means it may not be possible to get the exact resolution. + ticks = ((resolution * CYGHWR_HAL_SYSTEM_CLOCK_MHZ) / 64) - 1; + HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PMR, ticks); + + // Convert back to microseconds. This may actually increase rounding + // errors for some arguments and platforms, but the result should + // still be accurate enough for practical purposes. + resolution = ((ticks + 1) * 64) / CYGHWR_HAL_SYSTEM_CLOCK_MHZ; + + // Set up the interrupt handler. This is usually a high-priority + // interrupt so that we can get profiling information for other + // interrupt sources. +#ifdef HAL_VSR_SET + HAL_VSR_SET(HAL_MCFxxxx_PROFILE_TIMER_VECTOR, &hal_mcfxxxx_profile_vsr, (cyg_uint32)0); +#endif + HAL_INTERRUPT_SET_LEVEL(HAL_MCFxxxx_PROFILE_TIMER_ISR, CYGNUM_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER_ISR_PRIORITY); + HAL_INTERRUPT_UNMASK(HAL_MCFxxxx_PROFILE_TIMER_ISR); + + // Now start the timer running. + HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PCSR, + HAL_MCFxxxx_PITx_PCSR_PRE_64 | HAL_MCFxxxx_PITx_PCSR_OVW | + HAL_MCFxxxx_PITx_PCSR_PIE | HAL_MCFxxxx_PITx_PCSR_PIF | + HAL_MCFxxxx_PITx_PCSR_RLD | HAL_MCFxxxx_PITx_PCSR_EN); + + // Return the actual resolution. + return resolution; +} + +#endif // Profiling timer + +/* End of mcfxxxx.c */ diff --git a/ecos/packages/hal/m68k/mcf52xx/var/current/src/mcf52xx_asm.S b/ecos/packages/hal/m68k/mcf52xx/var/current/src/mcf52xx_asm.S new file mode 100644 index 0000000..3b59765 --- /dev/null +++ b/ecos/packages/hal/m68k/mcf52xx/var/current/src/mcf52xx_asm.S @@ -0,0 +1,88 @@ +// #======================================================================== +// # +// # mcfxxxx_asm.S +// # +// # Miscellaneous assembler support functions for an mcfxxxx +// # +// #======================================================================== +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================ +//###DESCRIPTIONBEGIN#### +// +// Author(s): bartv +// Date: 2008-01-14 +// +//###DESCRIPTIONEND#### +//======================================================================== + +#include <pkgconf/hal_m68k_mcfxxxx.h> +#include <cyg/hal/arch.inc> +#include <cyg/hal/var_io.h> + + .file "mcfxxxx_asm.S" + +#ifdef CYGINT_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER + // See also hal_enable_profile_timer() in mcfxxxx.c + + // This VSR should call __profile_hit() with a single argument, + // the interrupted PC. The VSR has been installed as a + // high-priority interrupt source, so there is no need to worry + // about nested interrupts or an interrupt stack. + .extern __profile_hit + + FUNC_START(hal_mcfxxxx_profile_vsr) + // On entry sp[0] holds sr and sp[1] holds the pc. + // Save the caller-save integer registers. There are no floating + // point registers to worry about. Make space for the argument + // to __profile_hit() while we are at it. + sub.l #20, %sp + movem.l %d0-%d1/%a0-%a1, 4(%sp) + + // Now pick up the interrupted PC from its new offset and push it + // on the stack for __profile_hit(). + move.l 24(%sp),(%sp) + jbsr __profile_hit + + // The timer runs in restart mode, but the interrupt bit has to be reset. + move.l # (HAL_MCFxxxx_PITx_PCSR_PRE_64 + HAL_MCFxxxx_PITx_PCSR_OVW + \ + HAL_MCFxxxx_PITx_PCSR_PIE + HAL_MCFxxxx_PITx_PCSR_PIF + \ + HAL_MCFxxxx_PITx_PCSR_RLD + HAL_MCFxxxx_PITx_PCSR_EN), %d0 + move.w %d0, HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PCSR + + movem.l 4(%sp), %d0-%d1/%a0-%a1 + add.l #20, %sp + rte +#endif + + .end |