Added the OS files

11 files changed, 1840 insertions, 0 deletions

diff --git a/ecos/packages/hal/misc/freescale/edma/current/ChangeLog b/ecos/packages/hal/misc/freescale/edma/current/ChangeLog
new file mode 100644
index 0000000..1da1b1d
--- /dev/null
+++ b/ecos/packages/hal/misc/freescale/edma/current/ChangeLog
@@ -0,0 +1,67 @@
+2014-02-13  Ilija Kocho <ilijak@siva.com.mk>
+
+	* misc/freescale/edma/current/doc/edma.sgml
+	* misc/freescale/edma/current/doc/freescale_begin.sgml
+	* misc/freescale/edma/current/doc/freescale_end.sgml
+	New: Add Freescale eDMA to eCos reference manual.
+
+2013-08-26  Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/freescale_edma.h: Fix FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES_M bug
+	[ Bugzilla 1001896 ]
+
+2013-05-04  Ilija Kocho <ilijak@siva.com.mk>
+
+	* cdl/hal_freescale_edma.cdl: Remove requirement for WRITETHRU cache mode
+	that raised conflict when cache was disabled. Bug reported by Mike Jones.
+	[ Bugzilla 1001838 ]
+
+2013-04-01  Ilija Kocho <ilijak@siva.com.mk>
+
+	* src/hal_freescale_edma.c:	Add clock gating enable.
+
+2013-02-06  Stefan Singer <stefan.singer@freescale.com>
+		    Ilija Kocho <ilijak@siva.com.mk>
+
+	* include/freescale_edma.h src/hal_freescale_edma.c:	
+	enhanced endianness support for devices with big and little endian
+	added support for MPC5xxx in addition to Kinetis
+	(see Bugzilla 1001752).
+	
+2012-05-04  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_freescale_edma.cdl
+	* include/freescale_edma.h
+	* src/hal/freescale_edma.c
+	Add support for 32 channel eDMA [Bugzilla 1001579]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+    * cdl/hal_freescale_edma.cdl
+	* include/freescale_edma.h
+	* src/hal/freescale_edma.c
+	New package -- Freescale eDMA DMA controller support [Bugzilla 1001450]
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/ecos/packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl b/ecos/packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl
new file mode 100644
index 0000000..7fd1c43
--- /dev/null
+++ b/ecos/packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl
@@ -0,0 +1,146 @@
+##==========================================================================
+##
+##      hal_freescale_edma.cdl
+##
+##      Cortex-M Freescale Kinetis eDMA
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    Ilija Kocho <ilijak@siva.com.mk>
+## Date:         2011-12-11
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_FREESCALE_EDMA {
+    display "Freescale eDMA controller"
+    hardware
+
+    include_dir cyg/hal
+    compile hal_freescale_edma.c
+    
+    active_if CYGINT_HAL_DMA
+
+    cdl_option CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM {
+        display "Number of DMA channels"
+        flavor data
+        legal_values { 16 32 }
+        default_value 16
+    }
+
+    cdl_option CYGOPT_HAL_FREESCALE_EDMA_ERCA {
+        display "Round robin channel arbitration"
+        flavor bool
+        default_value 0
+    }
+
+    cdl_option CYGOPT_HAL_FREESCALE_EDMA_EMLM {
+        display "Enable minor loop mapping"
+        flavor bool
+        default_value 1
+    }
+
+    cdl_option CYGOPT_HAL_FREESCALE_EDMA_CLM {
+        display "Continuous link mode"
+        flavor bool
+        active_if CYGOPT_HAL_FREESCALE_EDMA_EMLM
+        default_value 0
+    }
+
+    cdl_option CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE {
+        display "Number of channels in DMA group"
+        flavor data
+        calculated  16
+    }
+
+    cdl_component CYGHWR_HAL_FREESCALE_EDMA_GROPS {
+        display "Groups"
+        flavor none
+        no_define
+        active_if { CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM >
+            CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE }
+
+        cdl_option CYGNUM_HAL_FREESCALE_EDMA_GROUP_NUM {
+            display "Number of DMA groups"
+            flavor data
+            calculated  { CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE ?
+                CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM /
+                CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE : 0}
+        }
+
+        cdl_option CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO {
+            display "Group 0 priority"
+            flavor data
+            legal_values 0 1
+            default_value 0
+        }
+
+        cdl_option CYGNUM_HAL_FREESCALE_EDMA_GR1_PRIO {
+            display "Group 1 priority"
+            flavor data
+            legal_values 0 1
+            calculated { CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO ? 0 : 1 }
+        }
+
+        cdl_option CYGOPT_HAL_FREESCALE_EDMA_ERGA {
+            display "Round robin group arbitration"
+            active_if { CYGNUM_HAL_FREESCALE_EDMA_GROUP_NUM > 1 }
+            flavor bool
+            default_value 0
+        }
+    }
+
+    cdl_option CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM {
+        display "Channels per DMAMUX"
+        flavor data
+        calculated 16
+    }
+
+    cdl_component CYGNUM_HAL_FREESCALE_DMAMUX_NUM {
+        display "Number of DMAMUX units"
+        flavor data
+        active_if { CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM >
+            CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM
+        }
+        calculated { CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ?
+           ( CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM /
+            CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ) : 0
+        }
+    }
+}
+
+# EOF hal_freescale_dma.cdl
diff --git a/ecos/packages/hal/misc/freescale/edma/current/doc/edma.sgml b/ecos/packages/hal/misc/freescale/edma/current/doc/edma.sgml
new file mode 100644
index 0000000..b7a5962
--- /dev/null
+++ b/ecos/packages/hal/misc/freescale/edma/current/doc/edma.sgml
@@ -0,0 +1,179 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     edma.sgml                                                -->
+<!--                                                                 -->
+<!--     EDMA          documentation.                             -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2014 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2014/02/12                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<!-- <part id="hal-freescale-edma"><title>Freescale eDMA Family Support</title> -->
+
+<refentry id="hal-freescale-edma">
+  <refmeta>
+    <refentrytitle>Freescale eDMA </refentrytitle>
+  </refmeta>
+  <refnamediv>
+    <refname><literal>CYGPKG_HAL_FREESCALE_EDMA</literal></refname>
+    <refpurpose>eCos Support for Freescale eDMA Direct Memory Access controller</refpurpose>
+  </refnamediv>
+  
+  <refsect1 id="hal-freescale-edma-description"><title>Description</title>
+    <para>
+    <emphasis>eDMA</emphasis> is enhanced Direct Memory Access controller found on various Freescale
+    microcontroller families. It is combined with different architectures such as Power Architecture,
+    Coldfire/M68K, ARM, Cortex-M, etc.
+    </para>
+    <para>
+    The eDMA  HAL library provides generic support for module configuration and initialization as well as for executing of DMA transfers.
+    Most common usage of eDMA is as an enhancement of other device. eDMA acts as a cross-bar master and executes fast data
+    transfers on behalf of slave devices.
+    DMA can also perform memory to memory transfers on direct request by the application.
+    In following text the devices and applications 
+    that use DMA shall be referenced as <emphasis>[DMA] users</emphasis>.
+    </para>
+  </refsect1>
+  <refsect1 id="edma-config"><title>Configuration</title>
+    <para>The eDMA package <literal>CYGPKG_HAL_FREESCALE_EDMA</literal> is activated by implementing <literal>CYGINT_HAL_DMA</literal> interface.
+    The CDL provides configuration of DMA multiplexer, channel priorities and interrupt priorities.
+    For the systems with more than 16 channels also there is a provision for configuration of group priorities.
+    Please refer to CDL and eDMA reference manual for details of module operation.
+    </para>
+    <refsect2 id="edma-api"><title>eDMA API</title>
+      <refsect3 id="hal-freescale-edma-init-chanset">
+      <title>hal_freescale_edma_init_chanset</title>
+      <programlisting>
+      void hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p);
+      </programlisting>
+      <para>
+      Initialise <parameter>inidat_p</parameter> channel set. A channel set consists of
+      one or more DMA channels.
+      </para>
+      <para>
+      The initialisation parameters are provided by following structure:
+      <programlisting>
+      // DMA Channel set
+      typedef struct cyghwr_hal_freescale_dma_set_s {
+        cyghwr_hal_freescale_edma_t* edma_p;                // eDMA controller [register set]
+        const cyghwr_hal_freescale_dma_chan_set_t *chan_p;  // Channel configuration data
+        cyg_uint8 chan_n;                                   // Number of channels
+      } cyghwr_hal_freescale_dma_set_t;     
+      </programlisting>
+      
+      where:
+      
+      <structfield>chan_p</structfield> points to an array of
+      <structfield>chan_n</structfield> channels.
+      </para>
+      <para>
+      Channel configuration is provided by following structure.
+      <programlisting>
+      // DMA Channel data
+      typedef struct cyghwr_hal_freescale_dma_chan_set_s {
+        cyg_uint8 dma_src;      // Data source
+        cyg_uint8 dma_chan_i;   // Channel index
+        cyg_uint8 dma_prio;     // DMA channel priority
+        cyg_uint8 isr_prio;     // Interrupt priority
+        cyg_uint8 isr_num;      // Interrupt vector
+        cyg_uint8 isr_ena;      // Interruot enable
+      } cyghwr_hal_freescale_dma_chan_set_t;
+      </programlisting>
+      
+      The DMA channel priority <structfield>dma_chan_i</structfield> must be unique for every channel.
+      In order to satisfy this requirement the channel that previously had the given priority shall
+      be assigned with the previous prioruty of the target channel.
+      As a special (and most common case) <literal>FREESCALE_EDMA_DCHPRI_ASIS</literal> shall keep the
+      priority unchanged.
+      </para>
+      </refsect3>
+      
+      <refsect3 id="hal-freescale-edma-transfer-init">
+      <title>hal_freescale_edma_transfer_init</title>
+      <programlisting>
+      void hal_freescale_edma_transfer_init(cyghwr_hal_freescale_dma_set_t *inidat_p,
+                                            cyg_uint8 chan_i,
+                                            const cyghwr_hal_freescale_edma_tcd_t *tcd_cfg_p
+                                            );
+      </programlisting>
+      <para>
+      Initialise transfer. trannsfer on <parameter>chan_i</parameter> channel of
+      <parameter>edma_p</parameter> shall be initialised. with transfer control descriptor
+      <parameter>tcd_cfg_p</parameter>.
+      </para>
+      </refsect3>
+    
+      <refsect3 id="hal-freescale-edma-transfer-diag">
+      <title>hal_freescale_edma_transfer_diag</title>
+      <programlisting>
+      void hal_freescale_edma_transfer_diag(cyghwr_hal_freescale_edma_t
+                                      *edma_p, cyg_uint8 chan_i, cyg_bool recurse);
+      </programlisting>
+      <para>
+      Show contents of a transfer control descriptor set.
+      </para>
+      </refsect3>
+      
+      <refsect3 id="hal-freescale-edma-oper">
+      <title>eDMA operations</title>
+      <para>
+      Following inline functions and macros initiate or stop respective DMA operations.
+      </para>
+      <programlisting>
+      void hal_freescale_edma_erq_enable(cyghwr_hal_freescale_edma_t *edma_p,
+                                         cyg_uint8 chan_i);
+      void hal_freescale_edma_erq_disable(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_erq_cleardone(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_irq_enable(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_irq_disable(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_irq_clear(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_transfer_clear(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      void hal_freescale_edma_transfer_start(cyghwr_hal_freescale_edma_t *edma_p,
+                                          cyg_uint8 chan_i);
+      
+      #define HAL_DMA_TRANSFER_STOP(__edma,__chan)  \
+              hal_freescale_edma_erq_disable(__edma, __chan)
+      #define HAL_DMA_TRANSFER_START(__edma,__chan) \
+              hal_freescale_edma_erq_enable(__edma, __chan)
+      #define HAL_DMA_TRANSFER_CLEAR(__edma,__chan) \
+              hal_freescale_edma_cleardone(__edma, __chan)
+      </programlisting>
+      </refsect3>
+    </refsect2>
+    </refsect1>
+    
+  </refentry>
+  
+  <!--</part>-->
diff --git a/ecos/packages/hal/misc/freescale/edma/current/doc/freescale_begin.sgml b/ecos/packages/hal/misc/freescale/edma/current/doc/freescale_begin.sgml
new file mode 100644
index 0000000..7fdf00b
--- /dev/null
+++ b/ecos/packages/hal/misc/freescale/edma/current/doc/freescale_begin.sgml
@@ -0,0 +1,37 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     freescale_begin.sgml                                          -->
+<!--                                                                 -->
+<!--     Freescale documentation.                                      -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2014 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2014/02/19                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<part id="hal-misc-freescale"><title>Freescale Peripheral Collection Support</title>
diff --git a/ecos/packages/hal/misc/freescale/edma/current/doc/freescale_end.sgml b/ecos/packages/hal/misc/freescale/edma/current/doc/freescale_end.sgml
new file mode 100644
index 0000000..7d0e07c
--- /dev/null
+++ b/ecos/packages/hal/misc/freescale/edma/current/doc/freescale_end.sgml
@@ -0,0 +1,37 @@
+<!-- DOCTYPE part  PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner                                                     -->
+
+<!-- =============================================================== -->
+<!--                                                                 -->
+<!--     freescale_end.sgml                                             -->
+<!--                                                                 -->
+<!--     Freescale documentation.                                      -->
+<!--                                                                 -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTBEGIN####                                   -->
+<!-- =============================================================== -->
+<!-- Copyright (C) 2014 Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms      -->
+<!-- and conditions set forth in the Open Publication License, v1.0  -->
+<!-- or later (the latest version is presently available at          -->
+<!-- http://www.opencontent.org/openpub/)                            -->
+<!-- Distribution of the work or derivative of the work in any       -->
+<!-- standard (paper) book form is prohibited unless prior           -->
+<!-- permission obtained from the copyright holder                   -->
+<!-- =============================================================== -->
+<!-- ####ECOSDOCCOPYRIGHTEND####                                     -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN####                                       -->
+<!--                                                                 -->
+<!-- Author(s):   Ilija Kocho                                        -->
+<!-- Contact(s):  ilijak@siva.com.mk                                 -->
+<!-- Date:        2014/02/19                                         -->
+<!-- Version:     0.01                                               -->
+<!--                                                                 -->
+<!-- ####DESCRIPTIONEND####                                          -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+</part>
diff --git a/ecos/packages/hal/misc/freescale/edma/current/include/freescale_edma.h b/ecos/packages/hal/misc/freescale/edma/current/include/freescale_edma.h
new file mode 100644
index 0000000..456e2a2
--- /dev/null
+++ b/ecos/packages/hal/misc/freescale/edma/current/include/freescale_edma.h
@@ -0,0 +1,542 @@
+#ifndef CYGONCE_FREESCALE_EDMA_H
+#define CYGONCE_FREESCALE_EDMA_H
+//===========================================================================
+//
+//      freescale_edma.h
+//
+//      Freescale eDMA specific registers
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-11-04
+// Purpose:       Freescale eDMA specific registers
+// Description:
+// Usage:         #include <cyg/hal/freescale_edma.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <pkgconf/hal.h>
+#if defined CYGHWR_HAL_EDMA_TCD_SECTION || defined CYGHWR_HAL_EDMA_MEM_SECTION
+# include <cyg/infra/cyg_type.h>
+#endif
+
+// ----------------------------------------------------------------------------
+// DMAMUX DMA Multiplexer
+
+// DMAMUX - Peripheral register structure
+typedef volatile struct cyghwr_hal_freescale_dmamux_s {
+    cyg_uint8 chcfg[CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM];   // Channel Configuration Register
+} cyghwr_hal_freescale_dmamux_t;
+
+// DMAMUX - Peripheral instance base addresses - defined in HAL (typically var_io_devs.h)
+// CYGHWR_IO_FREESCALE_DMAMUX0_P defined in HAL
+// CYGHWR_IO_FREESCALE_DMAMUX1_P defined in HAL
+
+
+// ----------------------------------------------------------------------------
+// DMAMUX Register Masks
+
+// CHCFG Bit Fields
+#define FREESCALE_DMAMUX_CHCFG_SOURCE_M      0x3F
+#define FREESCALE_DMAMUX_CHCFG_SOURCE(__val) \
+            (__val & FREESCALE_DMAMUX_CHCFG_SOURCE_M)
+#define FREESCALE_DMAMUX_CHCFG_TRIG_M        0x40
+#define FREESCALE_DMAMUX_CHCFG_TRIG_S        6
+#define FREESCALE_DMAMUX_CHCFG_ENBL_M        0x80
+#define FREESCALE_DMAMUX_CHCFG_ENBL_S        7
+#define FREESCALE_DMAMUX_CHCFG_ASIS          FREESCALE_DMAMUX_CHCFG_ENBL_M
+
+// DMAMUX DMA request sources
+// Provided by HAL (typically var_io_devs.h)
+#define FREESCALE_DMAMUX_SRC(__src) (_src)
+
+//---------------------------------------------------------------------------
+// eDMA
+
+// Transfer control descriptor
+typedef volatile struct cyghwr_hal_freescale_edma_tcd_s
+                           cyghwr_hal_freescale_edma_tcd_t;
+#define CYGBLD_FREESCALE_EDMA_TCD_ALIGN CYGBLD_ATTRIB_ALIGN(32)
+struct cyghwr_hal_freescale_edma_tcd_s {
+    volatile void* saddr;             //  Source Address
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    cyg_uint16 attr;         //  Transfer Attributes
+    cyg_uint16 soff;         //  Signed Source Address Offset
+#else // AKA Little endian
+    cyg_uint16 soff;         //  Signed Source Address Offset
+    cyg_uint16 attr;         //  Transfer Attributes
+#endif
+
+    union {
+        cyg_uint32 mlno;     //  Minor Byte Count (Minor Loop Dis)
+        //  Signed Minor Loop Off:
+        cyg_uint32 mloffyes; //    MinoL Eena and Off Dis
+        cyg_uint32 mloffno;  //    Minor Loop and Off Ena
+    } nbytes;
+    cyg_uint32 slast;         //  Last Source Address Adjustment
+    volatile void *daddr;              //  Destination Address
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+
+    union {                   //  Current Minor Loop Link:
+        cyg_uint16 elinkyes;  //  Major Loop Count (Ch Lnkng Ena)
+        cyg_uint16 elinkno;   //  Major Loop Count (Ch Lnkng Dis)
+    } citer;
+    cyg_uint16 doff;          //  Signed Destination Address Offset
+#else // AKA Little endian
+    cyg_uint16 doff;          //  Signed Destination Address Offset
+    union {                   //  Current Minor Loop Link:
+        cyg_uint16 elinkyes;  //  Major Loop Count (Ch Lnkng Ena)
+        cyg_uint16 elinkno;   //  Major Loop Count (Ch Lnkng Dis)
+    } citer;
+#endif
+
+    union {
+        cyg_uint32 dlast;     //  Last Dst Addr Adj/Scat Gath Addr
+        cyghwr_hal_freescale_edma_tcd_t *sga;  //  Last Dst Addr Adj/Scat Gath Addr
+    } dlast_sga;
+
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    union {                   //  Beginning Minor Loop Link:
+        cyg_uint16 elinkno;   //  Major Loop Cnt (Ch Lnkng Dis)
+        cyg_uint16 elinkyes;  //  Major Loop Cnt (Ch Lnkng Ena)
+    } biter;
+    cyg_uint16 csr;           //  Control and Status
+#else // AKA Little endian
+    cyg_uint16 csr;           //  Control and Status
+    union {                   //  Beginning Minor Loop Link:
+        cyg_uint16 elinkno;   //  Major Loop Cnt (Ch Lnkng Dis)
+        cyg_uint16 elinkyes;  //  Major Loop Cnt (Ch Lnkng Ena)
+    } biter;
+#endif
+};
+
+// DMA - Peripheral register structure
+typedef volatile struct cyghwr_hal_freescale_edma_s {
+    cyg_uint32 cr;                   // Control Register			// 0x0000
+    cyg_uint32 es;                   // Error Status Register			// 0x0004
+    cyg_uint32 reserved_0;							// 0x0008
+    cyg_uint32 erq;                  // Enable Request Register			// 0x000C
+    cyg_uint32 reserved_1;							// 0x0010
+    cyg_uint32 eei;                  // Enable Error Interrupt Register		// 0x0014
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+    cyg_uint8  serq;                 // Set Enable Request Register		// 0x0018
+    cyg_uint8  cerq;                 // Clear Enable Request Register		// 0x0019
+    cyg_uint8  seei;                 // Set Enable Error Interrupt Register	// 0x001A  
+    cyg_uint8  ceei;                 // Clear Enable Error Interrupt Register	// 0x001B
+    cyg_uint8  cint;                 // Clear Interrupt Request Register	// 0x001C
+    cyg_uint8  cerr;                 // Clear Error Register			// 0x001D
+    cyg_uint8  ssrt;                 // Set START Bit Register			// 0x001E
+    cyg_uint8  cdne;                 // Clear DONE Status Bit Register		// 0x001F
+#else // AKA Little endian
+    cyg_uint8  ceei;                 // Clear Enable Error Interrupt Register	
+    cyg_uint8  seei;                 // Set Enable Error Interrupt Register	
+    cyg_uint8  cerq;                 // Clear Enable Request Register		
+    cyg_uint8  serq;                 // Set Enable Request Register		
+    cyg_uint8  cdne;                 // Clear DONE Status Bit Register		
+    cyg_uint8  ssrt;                 // Set START Bit Register			
+    cyg_uint8  cerr;                 // Clear Error Register			
+    cyg_uint8  cint;                 // Clear Interrupt Request Register	
+#endif    
+    cyg_uint32 reserved_2;							// 0x0020
+    cyg_uint32 irq;                  // Interrupt Request Register		// 0x0024
+    cyg_uint32 reserved_3;							// 0x0028
+    cyg_uint32 err;                  // Error Register				// 0x002C
+    cyg_uint32 reserved_4;							// 0x0030
+    cyg_uint32 hrs;                  // Hardware Request Status Register	// 0x0034
+    cyg_uint8  reserved_5[0x8100 - (0x8034 + 4)];
+    cyg_uint8  dchpri[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Priorities
+    cyg_uint8  reserved_6[0x9000 - 0x8100 - CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM];
+    cyghwr_hal_freescale_edma_tcd_t
+          tcd[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Transfer control descriptors
+} cyghwr_hal_freescale_edma_t;
+
+// CYGHWR_IO_FREESCALE_EDMA0_P is defined by HAL
+// #define CYGHWR_IO_FREESCALE_EDMA0_P
+
+// ----------------------------------------------------------------------------
+//  DMA Register Bits
+
+// CR Bit Fields
+#define FREESCALE_EDMA_CR_EDBG_M                        0x2
+#define FREESCALE_EDMA_CR_EDBG_S                        1
+#define FREESCALE_EDMA_CR_ERCA_M                        0x4
+#define FREESCALE_EDMA_CR_ERCA_S                        2
+#define FREESCALE_EDMA_CR_ERGA_M                        0x8
+#define FREESCALE_EDMA_CR_ERGA_S                        3
+#define FREESCALE_EDMA_CR_HOE_M                         0x10
+#define FREESCALE_EDMA_CR_HOE_S                         4
+#define FREESCALE_EDMA_CR_HALT_M                        0x20
+#define FREESCALE_EDMA_CR_HALT_S                        5
+#define FREESCALE_EDMA_CR_CLM_M                         0x40
+#define FREESCALE_EDMA_CR_CLM_S                         6
+#define FREESCALE_EDMA_CR_EMLM_M                        0x80
+#define FREESCALE_EDMA_CR_EMLM_S                        7
+#define FREESCALE_EDMA_CR_ECX_M                         0x10000
+#define FREESCALE_EDMA_CR_ECX_S                         16
+#define FREESCALE_EDMA_CR_CX_M                          0x20000
+#define FREESCALE_EDMA_CR_CX_S                          17
+
+#define FREESCALE_EDMA_GR_PRI(_gr_, _pr_) VALUE_((8 + 2 * _gr_), (_pr_ & 0x3))
+
+// ES Bit Fields
+#define FREESCALE_EDMA_ES_DBE_M                         0x1
+#define FREESCALE_EDMA_ES_DBE_S                         0
+#define FREESCALE_EDMA_ES_SBE_M                         0x2
+#define FREESCALE_EDMA_ES_SBE_S                         1
+#define FREESCALE_EDMA_ES_SGE_M                         0x4
+#define FREESCALE_EDMA_ES_SGE_S                         2
+#define FREESCALE_EDMA_ES_NCE_M                         0x8
+#define FREESCALE_EDMA_ES_NCE_S                         3
+#define FREESCALE_EDMA_ES_DOE_M                         0x10
+#define FREESCALE_EDMA_ES_DOE_S                         4
+#define FREESCALE_EDMA_ES_DAE_M                         0x20
+#define FREESCALE_EDMA_ES_DAE_S                         5
+#define FREESCALE_EDMA_ES_SOE_M                         0x40
+#define FREESCALE_EDMA_ES_SOE_S                         6
+#define FREESCALE_EDMA_ES_SAE_M                         0x80
+#define FREESCALE_EDMA_ES_SAE_S                         7
+#define FREESCALE_EDMA_ES_ERRCHN_M                      0xF00
+#define FREESCALE_EDMA_ES_ERRCHN_S                      8
+#define FREESCALE_EDMA_ES_ERRCHN(__val)                 \
+            VALUE_(FREESCALE_EDMA_ES_ERRCHN_S, __val)
+#define FREESCALE_EDMA_ES_CPE_M                         0x4000
+#define FREESCALE_EDMA_ES_CPE_S                         14
+#define FREESCALE_EDMA_ES_GPE_M                         0x8000
+#define FREESCALE_EDMA_ES_GPE_S                         15
+#define FREESCALE_EDMA_ES_ECX_M                         0x10000
+#define FREESCALE_EDMA_ES_ECX_S                         16
+#define FREESCALE_EDMA_ES_VLD_M                         0x80000000
+#define FREESCALE_EDMA_ES_VLD_S                         31
+// ERQ Bit Fields
+#define FREESCALE_EDMA_ERQ(__rq)                        BIT(__rq)
+// EEI Bit Fields
+#define FREESCALE_EDMA_EEI(__rq)                        BIT(__rq)
+#define FREESCALE_EDMA_CHAN_M                           0x1F
+// CEEI Bit Fields
+#define FREESCALE_EDMA_CEEI_CEEI(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CEEI_CAEE_M                      0x40
+#define FREESCALE_EDMA_CEEI_CAEE_S                      6
+#define FREESCALE_EDMA_CEEI_NOP_M                       0x80
+#define FREESCALE_EDMA_CEEI_NOP_S                       7
+// SEEI Bit Fields
+#define FREESCALE_EDMA_SEEI_SEEI(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_SEEI_SAEE_M                      0x40
+#define FREESCALE_EDMA_SEEI_SAEE_S                      6
+#define FREESCALE_EDMA_SEEI_NOP_M                       0x80
+#define FREESCALE_EDMA_SEEI_NOP_S                       7
+// CERQ Bit Fields
+#define FREESCALE_EDMA_CERQ_CERQ(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CERQ_CAER_M                      0x40
+#define FREESCALE_EDMA_CERQ_CAER_S                      6
+#define FREESCALE_EDMA_CERQ_NOP_M                       0x80
+#define FREESCALE_EDMA_CERQ_NOP_S                       7
+// SERQ Bit Fields
+#define FREESCALE_EDMA_SERQ_SERQ(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_SERQ_SAER_M                      0x40
+#define FREESCALE_EDMA_SERQ_SAER_S                      6
+#define FREESCALE_EDMA_SERQ_NOP_M                       0x80
+#define FREESCALE_EDMA_SERQ_NOP_S                       7
+// CDNE Bit Fields
+#define FREESCALE_EDMA_CDNE_CDNE(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CDNE_CADN_M                      0x40
+#define FREESCALE_EDMA_CDNE_CADN_S                      6
+#define FREESCALE_EDMA_CDNE_NOP_M                       0x80
+#define FREESCALE_EDMA_CDNE_NOP_S                       7
+// SSRT Bit Fields
+#define FREESCALE_EDMA_SSRT_SSRT(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_SSRT_SAST_M                      0x40
+#define FREESCALE_EDMA_SSRT_SAST_S                      6
+#define FREESCALE_EDMA_SSRT_NOP_M                       0x80
+#define FREESCALE_EDMA_SSRT_NOP_S                       7
+// CERR Bit Fields
+#define FREESCALE_EDMA_CERR_CERR(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CERR_CAEI_M                      0x40
+#define FREESCALE_EDMA_CERR_CAEI_S                      6
+#define FREESCALE_EDMA_CERR_NOP_M                       0x80
+#define FREESCALE_EDMA_CERR_NOP_S                       7
+// CINT Bit Fields
+#define FREESCALE_EDMA_CINT_CINT(__val) (__val & FREESCALE_EDMA_CHAN_M)
+#define FREESCALE_EDMA_CINT_CAIR_M                      0x40
+#define FREESCALE_EDMA_CINT_CAIR_S                      6
+#define FREESCALE_EDMA_CINT_NOP_M                       0x80
+#define FREESCALE_EDMA_CINT_NOP_S                       7
+// INT Bit Fields
+#define FREESCALE_EDMA_INT(__ch)                        BIT(__ch)
+// ERR Bit Fields
+#define FREESCALE_EDMA_ERR(__ch)                        BIT(__ch)
+// HRS Bit Fields
+#define FREESCALE_EDMA_HRS(__ch)                        BIT(__ch)
+// DCHPRI Bit Fields
+
+#define FREESCALE_EDMA_DCHPRI_CHPRI_M                   0xF
+
+#define FREESCALE_EDMA_DCHPRI_CHPRI(__val)              \
+        (__val & FREESCALE_EDMA_DCHPRI_CHPRI_M)
+#define FREESCALE_EDMA_DCHPRI_DPA_M                     0x40
+#define FREESCALE_EDMA_DCHPRI_DPA_S                     6
+#define FREESCALE_EDMA_DCHPRI_ECP_M                     0x80
+#define FREESCALE_EDMA_DCHPRI_ECP_S                     7
+#define FREESCALE_EDMA_DCHPRI_ASIS                      0x20
+// SOFF Bit Fields
+#define FREESCALE_EDMA_SOFF_SOFF_M                      0xFFFF
+#define FREESCALE_EDMA_SOFF_SOFF(__val)                 \
+        (__val & FREESCALE_EDMA_SOFF_SOFF_M)
+// ATTR Bit Fields
+#define FREESCALE_EDMA_ATTR_DSIZE_M                     0x7
+#define FREESCALE_EDMA_ATTR_DSIZE(__val)                \
+        (__val & FREESCALE_EDMA_ATTR_DSIZE_M)
+#define FREESCALE_EDMA_ATTR_DMOD_M                      0xF8
+#define FREESCALE_EDMA_ATTR_DMOD_S                      3
+#define FREESCALE_EDMA_ATTR_DMOD(__val)                 \
+        VALUE_(FREESCALE_EDMA_ATTR_DMOD_S, __val)
+#define FREESCALE_EDMA_ATTR_SSIZE_M                     0x700
+#define FREESCALE_EDMA_ATTR_SSIZE_S                     8
+#define FREESCALE_EDMA_ATTR_SSIZE(__val)                \
+        VALUE_(FREESCALE_EDMA_ATTR_SSIZE_S, __val)
+#define FREESCALE_EDMA_ATTR_SMOD_M                      0xF800
+#define FREESCALE_EDMA_ATTR_SMOD_S                      11
+#define FREESCALE_EDMA_ATTR_SMOD(__val)                 \
+        VALUE_(FREESCALE_EDMA_ATTR_SMOD_S, __val)
+#define FREESCALE_EDMA_ATTR_SIZE_8       0
+#define FREESCALE_EDMA_ATTR_SIZE_16      1
+#define FREESCALE_EDMA_ATTR_SIZE_32      2
+#define FREESCALE_EDMA_ATTR_SIZE_16B     4
+// NBYTES_MLOFFNO Bit Fields
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES_M          0x3FFFFFFF
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES(__val)     \
+        (__val & FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES_M)
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_DMLOE_M           0x40000000
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_DMLOE_S           30
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_SMLOE_M           0x80000000
+#define FREESCALE_EDMA_NBYTES_MLOFFNO_SMLOE_S           31
+// NBYTES_MLOFFYES Bit Fields
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES_M         0x3FF
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES(__val)    \
+        (__val & FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES_M)
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_M          0x3FFFFC00
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_S          10
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF(__val)     \
+        VALUE_(FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_S, __val)
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_DMLOE_M          0x40000000
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_DMLOE_S          30
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_SMLOE_M          0x80000000
+#define FREESCALE_EDMA_NBYTES_MLOFFYES_SMLOE_S          31
+// DOFF Bit Fields
+#define FREESCALE_EDMA_DOFF_DOFF_M                      0xFFFF
+#define FREESCALE_EDMA_DOFF_DOFF(__val) (__val & FREESCALE_EDMA_DOFF_DOFF_M)
+// CITER_ELINKYES Bit Fields
+#define FREESCALE_EDMA_CITER_ELINKYES_CITER_M           0x1FF
+#define FREESCALE_EDMA_CITER_ELINKYES_CITER(__val)      \
+            (__val & FREESCALE_EDMA_CITER_ELINKYES_CITER_M)
+#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH_M          0x1E00
+#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH_S          9
+#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH(__val)     \
+            VALUE_(FREESCALE_EDMA_CITER_ELINKYES_LINKCH_S, __val)
+#define FREESCALE_EDMA_CITER_ELINKYES_ELINK_M           0x8000
+#define FREESCALE_EDMA_CITER_ELINKYES_ELINK_S           15
+// CITER_ELINKNO Bit Fields
+#define FREESCALE_EDMA_CITER_ELINKNO_CITER_M            0x7FFF
+#define FREESCALE_EDMA_CITER_ELINKNO_CITER(__val)       \
+            (__val & FREESCALE_EDMA_CITER_ELINKNO_CITER_M)
+#define FREESCALE_EDMA_CITER_ELINKNO_ELINK_M            0x8000
+#define FREESCALE_EDMA_CITER_ELINKNO_ELINK_S            15
+// CSR Bit Fields
+#define FREESCALE_EDMA_CSR_START_M                      0x1
+#define FREESCALE_EDMA_CSR_START_S                      0
+#define FREESCALE_EDMA_CSR_INTMAJOR_M                   0x2
+#define FREESCALE_EDMA_CSR_INTMAJOR_S                   1
+#define FREESCALE_EDMA_CSR_INTHALF_M                    0x4
+#define FREESCALE_EDMA_CSR_INTHALF_S                    2
+#define FREESCALE_EDMA_CSR_DREQ_M                       0x8
+#define FREESCALE_EDMA_CSR_DREQ_S                       3
+#define FREESCALE_EDMA_CSR_ESG_M                        0x10
+#define FREESCALE_EDMA_CSR_ESG_S                        4
+#define FREESCALE_EDMA_CSR_MAJORELINK_M                 0x20
+#define FREESCALE_EDMA_CSR_MAJORELINK_S                 5
+#define FREESCALE_EDMA_CSR_ACTIVE_M                     0x40
+#define FREESCALE_EDMA_CSR_ACTIVE_S                     6
+#define FREESCALE_EDMA_CSR_DONE_M                       0x80
+#define FREESCALE_EDMA_CSR_DONE_S                       7
+#define FREESCALE_EDMA_CSR_MAJORLINKCH_M                0xF00
+#define FREESCALE_EDMA_CSR_MAJORLINKCH_S                8
+#define FREESCALE_EDMA_CSR_MAJORLINKCH(__val)           \
+            VALUE_(FREESCALE_EDMA_CSR_MAJORLINKCH_S, __val)
+#define FREESCALE_EDMA_CSR_BWC_M                        0xC000
+#define FREESCALE_EDMA_CSR_BWC_S                        14
+#define FREESCALE_EDMA_CSR_BWC(__val)                   \
+        VALUE_(FREESCALE_EDMA_CSR_BWC_S, __val)
+#define FREESCALE_EDMA_CSR_BWC_0      0
+#define FREESCALE_EDMA_CSR_BWC_MEDIUM FREESCALE_EDMA_CSR_BWC(2)
+#define FREESCALE_EDMA_CSR_BWC_NICE   FREESCALE_EDMA_CSR_BWC(3)
+
+// BITER_ELINKNO Bit Fields
+#define FREESCALE_EDMA_BITER_ELINKNO_BITER_M            0x7FFF
+#define FREESCALE_EDMA_BITER_ELINKNO_BITER(__val)       \
+            (__val FREESCALE_EDMA_BITER_ELINKNO_BITER_M)
+#define FREESCALE_EDMA_BITER_ELINKNO_ELINK_M            0x8000
+#define FREESCALE_EDMA_BITER_ELINKNO_ELINK_S            15
+// BITER_ELINKYES Bit Fields
+#define FREESCALE_EDMA_BITER_ELINKYES_BITER_M           0x1FF
+#define FREESCALE_EDMA_BITER_ELINKYES_BITER(__val)      \
+            (__val & FREESCALE_EDMA_BITER_ELINKYES_BITER_M)
+#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH_M          0x1E00
+#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH_S          9
+#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH(__val)     \
+            VALUE_(FREESCALE_EDMA_BITER_ELINKYES_LINKCH_S, __val)
+#define FREESCALE_EDMA_BITER_ELINKYES_ELINK_M           0x8000
+#define FREESCALE_EDMA_BITER_ELINKYES_ELINK_S           15
+
+// EDMA buffer descriptor memory section
+#ifdef CYGHWR_HAL_EDMA_TCD_SECTION
+# define EDMA_RAM_TCD_SECTION CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_EDMA_TCD_SECTION)
+#else
+# define EDMA_RAM_MEM_SECTION
+#endif // CYGHWR_HAL_EDMA_MEM_SECTION
+
+// EDMA buffer memory section
+#ifdef CYGHWR_HAL_EDMA_BUF_SECTION
+# define EDMA_RAM_BUF_SECTION CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_EDMA_BUF_SECTION)
+#else
+# define EDMA_RAM_BUF_SECTION
+#endif // CYGHWR_HAL_EDMA_BUF_SECTION
+
+//-----------------------------------------------------------------------------
+
+// DMA Channel data
+typedef struct cyghwr_hal_freescale_dma_chan_set_s {
+    cyg_uint8 dma_src;      // Data source
+    cyg_uint8 dma_chan_i;   // Channel index
+    cyg_uint8 dma_prio;     // DMA channel priority
+    cyg_uint8 isr_prio;     // Interrupt priority
+    cyg_uint8 isr_num;      // Interrupt vector
+    cyg_uint8 isr_ena;      // Interruot enable
+} cyghwr_hal_freescale_dma_chan_set_t;
+
+// DMA Channel set
+typedef struct cyghwr_hal_freescale_dma_set_s {
+    cyghwr_hal_freescale_edma_t* edma_p;
+    const cyghwr_hal_freescale_dma_chan_set_t *chan_p;
+    cyg_uint8 chan_n;
+} cyghwr_hal_freescale_dma_set_t;
+
+
+__externC void
+hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p);
+
+__externC void
+hal_freescale_edma_diag(const cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask);
+
+__externC void
+hal_freescale_edma_transfer_init(cyghwr_hal_freescale_edma_t *edma_p,
+                                 cyg_uint8 chan_i,
+                                 const cyghwr_hal_freescale_edma_tcd_t *tcd_cfg_p);
+__externC void
+hal_freescale_edma_tcd_diag(cyghwr_hal_freescale_edma_tcd_t *tcd_p, cyg_int32 chan_i, const char *prefix);
+
+__externC void
+hal_freescale_edma_transfer_diag (cyghwr_hal_freescale_edma_t *edma_p,
+                                  cyg_uint8 chan_i, cyg_bool recurse);
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_erq_enable(cyghwr_hal_freescale_edma_t *edma_p,
+                              cyg_uint8 chan_i)
+{
+    edma_p->serq = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_erq_disable(cyghwr_hal_freescale_edma_t *edma_p,
+                               cyg_uint8 chan_i)
+{
+    edma_p->cerq = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_cleardone(cyghwr_hal_freescale_edma_t *edma_p,
+                              cyg_uint8 chan_i)
+{
+    edma_p->cdne = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_irq_enable(cyghwr_hal_freescale_edma_t *edma_p,
+                              cyg_uint8 chan_i)
+{
+    edma_p->seei = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_irq_disable(cyghwr_hal_freescale_edma_t *edma_p,
+                               cyg_uint8 chan_i)
+{
+    edma_p->ceei = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_irq_clear(cyghwr_hal_freescale_edma_t *edma_p,
+                               cyg_uint8 chan_i)
+{
+    edma_p->cint = chan_i;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_transfer_clear(cyghwr_hal_freescale_edma_t *edma_p,
+                                  cyg_uint8 chan_i)
+{
+    edma_p->tcd[chan_i].csr &= ~FREESCALE_EDMA_CSR_DONE_M;
+}
+
+CYGBLD_FORCE_INLINE void
+hal_freescale_edma_transfer_start(cyghwr_hal_freescale_edma_t *edma_p,
+                                  cyg_uint8 chan_i)
+{
+    edma_p->ssrt = chan_i;
+}
+
+#define HAL_DMA_TRANSFER_STOP(__edma,__chan)   \
+        hal_freescale_edma_erq_disable(__edma, __chan)
+#define HAL_DMA_TRANSFER_START(__edma,__chan)  \
+        hal_freescale_edma_erq_enable(__edma, __chan)
+#define HAL_DMA_TRANSFER_CLEAR(__edma,__chan)  \
+        hal_freescale_edma_cleardone(__edma, __chan)
+
+// end of var_io_dma.h
+#endif // CYGONCE_FREESCALE_EDMA_H
diff --git a/ecos/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c b/ecos/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
new file mode 100644
index 0000000..b063d3c
--- /dev/null
+++ b/ecos/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c
@@ -0,0 +1,359 @@
+//===========================================================================
+//
+//      hal_freescale_edma.c
+//
+//      Freescale eDMA support library
+//
+//===========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011, 2013 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//===========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     Ilija Kocho <ilijak@siva.com.mk>
+// Date:          2011-11-04
+// Purpose:       Freescale eDMA specific functions
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_freescale_edma.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_if.h>             // HAL header
+#include <cyg/hal/freescale_edma.h>     // Freescale eDMA defs
+
+// Channel priority register indexing
+#if (CYG_BYTEORDER == CYG_MSBFIRST)  // AKA Big endian
+
+#define EDMA_CHAN_PRIORITY_I(__chan_i) (__chan_i)
+
+#else  // AKA Big endian
+// Indices for cyghwr_hal_freescale_edma_t::dchpri[]
+enum {
+    FREESCALE_DMA_PRI_CH3,  FREESCALE_DMA_PRI_CH2,
+    FREESCALE_DMA_PRI_CH1,  FREESCALE_DMA_PRI_CH0,
+    FREESCALE_DMA_PRI_CH7,  FREESCALE_DMA_PRI_CH6,
+    FREESCALE_DMA_PRI_CH5,  FREESCALE_DMA_PRI_CH4,
+    FREESCALE_DMA_PRI_CH11, FREESCALE_DMA_PRI_CH10,
+    FREESCALE_DMA_PRI_CH9,  FREESCALE_DMA_PRI_CH8,
+    FREESCALE_DMA_PRI_CH15, FREESCALE_DMA_PRI_CH14,
+    FREESCALE_DMA_PRI_CH13, FREESCALE_DMA_PRI_CH12
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+    ,
+    FREESCALE_DMA_PRI_CH19, FREESCALE_DMA_PRI_CH18,
+    FREESCALE_DMA_PRI_CH17, FREESCALE_DMA_PRI_CH16,
+    FREESCALE_DMA_PRI_CH23, FREESCALE_DMA_PRI_CH22,
+    FREESCALE_DMA_PRI_CH21, FREESCALE_DMA_PRI_CH20,
+    FREESCALE_DMA_PRI_CH27, FREESCALE_DMA_PRI_CH26,
+    FREESCALE_DMA_PRI_CH25, FREESCALE_DMA_PRI_CH24,
+    FREESCALE_DMA_PRI_CH31, FREESCALE_DMA_PRI_CH30,
+    FREESCALE_DMA_PRI_CH29, FREESCALE_DMA_PRI_CH28
+#endif
+};
+
+const cyg_uint8 const PRICHAN_I[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM] =
+{
+    FREESCALE_DMA_PRI_CH0,  FREESCALE_DMA_PRI_CH1,
+    FREESCALE_DMA_PRI_CH2,  FREESCALE_DMA_PRI_CH3,
+    FREESCALE_DMA_PRI_CH4,  FREESCALE_DMA_PRI_CH5,
+    FREESCALE_DMA_PRI_CH6,  FREESCALE_DMA_PRI_CH7,
+    FREESCALE_DMA_PRI_CH8,  FREESCALE_DMA_PRI_CH9,
+    FREESCALE_DMA_PRI_CH10, FREESCALE_DMA_PRI_CH11,
+    FREESCALE_DMA_PRI_CH12, FREESCALE_DMA_PRI_CH13,
+    FREESCALE_DMA_PRI_CH14, FREESCALE_DMA_PRI_CH15
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+    ,
+    FREESCALE_DMA_PRI_CH16, FREESCALE_DMA_PRI_CH17,
+    FREESCALE_DMA_PRI_CH18, FREESCALE_DMA_PRI_CH19,
+    FREESCALE_DMA_PRI_CH20, FREESCALE_DMA_PRI_CH21,
+    FREESCALE_DMA_PRI_CH22, FREESCALE_DMA_PRI_CH23,
+    FREESCALE_DMA_PRI_CH24, FREESCALE_DMA_PRI_CH25,
+    FREESCALE_DMA_PRI_CH26, FREESCALE_DMA_PRI_CH27,
+    FREESCALE_DMA_PRI_CH28, FREESCALE_DMA_PRI_CH29,
+    FREESCALE_DMA_PRI_CH30, FREESCALE_DMA_PRI_CH31
+#endif
+};
+
+#define EDMA_CHAN_PRIORITY_I(__chan_i) (PRICHAN_I[__chan_i])
+
+#endif
+
+// Find an eDMA channel with given priority
+static volatile cyg_uint8*
+hal_freescale_edma_find_chan_with_pri(cyghwr_hal_freescale_edma_t *edma_p,
+                                 cyg_uint32 pri, cyg_uint32 group_i)
+{
+    volatile cyg_uint8 *chan_p;
+
+    for(chan_p = &edma_p->dchpri[group_i * CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE];
+        chan_p < &edma_p->dchpri[group_i * CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE +
+                                 CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE];
+        chan_p++)
+    {
+        if((*chan_p & FREESCALE_EDMA_DCHPRI_CHPRI_M) == pri) break;
+    }
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+    if(0 == group_i){
+        if(chan_p >= &edma_p->dchpri[CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE])
+            chan_p = NULL;
+    }
+#endif
+    if(chan_p >= &edma_p->dchpri[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM])
+        chan_p = NULL;
+
+    return chan_p;
+}
+
+// Initialize an eDMA channel
+// If DMA prority change is required than old priority is assigned to the channel
+// that before this call had requested priority.
+void
+hal_freescale_edma_init_1chan(
+                           cyghwr_hal_freescale_edma_t *edma_p,
+                           const cyghwr_hal_freescale_dma_chan_set_t *chan_p)
+{
+    cyg_uint8 oldprio;
+    cyghwr_hal_freescale_dmamux_t *dmamux_p;
+    volatile cyg_uint8 *prev_ch_reqprio_p; // Previous chan with req. prio.
+    volatile cyg_uint8 *chcfg_p;
+    cyg_uint32         group_i;
+
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+    dmamux_p = chan_p->dma_chan_i < CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ?
+                                         CYGHWR_IO_FREESCALE_DMAMUX0_P :
+                                         CYGHWR_IO_FREESCALE_DMAMUX1_P;
+#else
+    dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P;
+#endif
+    chcfg_p = &dmamux_p->chcfg[chan_p->dma_chan_i % CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM];
+    edma_p->cerq = chan_p->dma_chan_i;
+
+    if(chan_p->dma_src & FREESCALE_DMAMUX_CHCFG_SOURCE_M) {
+        *chcfg_p = chan_p->dma_src;
+    } else if(!(chan_p->dma_src & FREESCALE_DMAMUX_CHCFG_ASIS)) {
+        *chcfg_p = 0;
+    }
+
+    if((chan_p->dma_prio != FREESCALE_EDMA_DCHPRI_ASIS) &&
+       (edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)] != chan_p->dma_prio))
+    {
+        group_i = chan_p->dma_chan_i >= CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE ? 1 : 0;
+        if((prev_ch_reqprio_p =
+            hal_freescale_edma_find_chan_with_pri(edma_p, chan_p->dma_prio, group_i)))
+        {
+            oldprio = edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)];
+            edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_p->dma_chan_i)] = chan_p->dma_prio;
+            *prev_ch_reqprio_p = oldprio;
+        }
+    }
+}
+
+// Init DMA controller
+
+const cyg_uint32 FREESCALE_EDMA_CR_INI = 0
+#ifdef CYGOPT_HAL_FREESCALE_EDMA_EMLM
+       | FREESCALE_EDMA_CR_EMLM_M
+#endif
+#ifdef CYGOPT_HAL_FREESCALE_EDMA_CLM
+       | FREESCALE_EDMA_CR_CLM_M
+#endif
+#ifdef CYGOPT_HAL_FREESCALE_EDMA_ERCA
+       | FREESCALE_EDMA_CR_ERCA_M
+#endif
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+#ifdef CYGOPT_HAL_FREESCALE_EDMA_ERGA
+       | FREESCALE_EDMA_CR_ERGA_M
+#endif
+       | FREESCALE_EDMA_GR_PRI(0, CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO)
+       | FREESCALE_EDMA_GR_PRI(1, CYGNUM_HAL_FREESCALE_EDMA_GR1_PRIO)
+#endif
+      ;
+
+void
+hal_freescale_edma_init(cyghwr_hal_freescale_edma_t *edma_p)
+{
+    cyg_uint32 regval;
+    
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_EDMA0_CLK);
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_DMAMUX0_CLK);
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+    CYGHWR_IO_CLOCK_ENABLE(CYGHWR_IO_FREESCALE_DMAMUX1_CLK);
+#endif
+    regval = edma_p->cr;
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16
+    regval &= ~(FREESCALE_EDMA_GR_PRI(0, 3) | FREESCALE_EDMA_GR_PRI(1, 3));
+#endif
+    regval |= FREESCALE_EDMA_CR_INI;
+    edma_p->cr = regval;
+}
+
+// Initialize a set of DMA channels
+void
+hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p)
+{
+    cyghwr_hal_freescale_edma_t *edma_p;
+    const cyghwr_hal_freescale_dma_chan_set_t *chan_p;
+
+    edma_p = inidat_p->edma_p = CYGHWR_HAL_FREESCALE_EDMA0_P;
+
+    hal_freescale_edma_init(edma_p);
+
+    for(chan_p = inidat_p->chan_p;
+        chan_p < inidat_p->chan_p + inidat_p->chan_n;
+        chan_p++)
+    {
+        hal_freescale_edma_init_1chan(edma_p, chan_p);
+    }
+    edma_p->es = 0;
+}
+
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32
+# define DMA_CHANMASK_FORMAT "0x%08x"
+#else
+# define DMA_CHANMASK_FORMAT "0x%04x"
+#endif
+
+#define EDMA_DIAG_PRINTF_FORMAT(__mf) "CR=0x%08x ES=0x%08x ERQ=" __mf \
+        " INT=" __mf " ERR=" __mf " HRS=" __mf "\n"
+
+// Display DMA configuration
+void
+hal_freescale_edma_diag(const cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask)
+{
+    cyghwr_hal_freescale_edma_t *edma_p;
+    cyghwr_hal_freescale_dmamux_t *dmamux_p;
+    const cyghwr_hal_freescale_dma_chan_set_t *chan_p;
+    cyg_uint8 chan_i;
+    cyg_uint32 chan_p_i;
+
+    edma_p = inidat_p->edma_p;
+    diag_printf(EDMA_DIAG_PRINTF_FORMAT(DMA_CHANMASK_FORMAT),
+                edma_p->cr, edma_p->es,
+                edma_p->erq, edma_p->irq, edma_p->err, edma_p->hrs);
+
+    for(chan_i = 0; chan_i < CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM; chan_i++){
+        if(mask & 0x1){
+            chan_p = inidat_p->chan_p;
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+            dmamux_p = chan_i < CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ?
+                                    CYGHWR_IO_FREESCALE_DMAMUX0_P :
+                                    CYGHWR_IO_FREESCALE_DMAMUX1_P;
+#else
+            dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P;
+#endif
+            diag_printf("Chan %2d: CHCFG=0x%02x (%2d) DCHPRI=0x%02x dmamux[%c]=%p", chan_i,
+                        dmamux_p->chcfg[chan_i % 16],
+                        FREESCALE_DMAMUX_CHCFG_SOURCE(dmamux_p->chcfg[chan_i % 16]),
+                        edma_p->dchpri[EDMA_CHAN_PRIORITY_I(chan_i)],
+                        CYGHWR_IO_FREESCALE_DMAMUX0_P == dmamux_p ? '0' : (
+#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE
+                        CYGHWR_IO_FREESCALE_DMAMUX1_P == dmamux_p ? '1' :
+#endif
+                        '?'), dmamux_p);
+            for(chan_p_i = 0; chan_p_i < inidat_p->chan_n; chan_p_i++){
+                if(chan_p->dma_chan_i == chan_i){
+                    diag_printf(" ISR_NUM=%2d[0x%02x] ISR_PRI=%3d[0x%02x]",
+                                chan_p->isr_num, chan_p->isr_num,
+                                chan_p->isr_prio, chan_p->isr_prio);
+                }
+                chan_p++;
+            }
+            diag_printf("\n");
+        }
+        mask >>= 1;
+    }
+}
+
+// Initialize eDMA channel TCD
+void
+hal_freescale_edma_transfer_init(cyghwr_hal_freescale_edma_t *edma_p,
+                                 cyg_uint8 chan_i,
+                                 const cyghwr_hal_freescale_edma_tcd_t *tcd_cfg_p)
+{
+    HAL_DMA_TRANSFER_CLEAR(edma_p, chan_i);
+    edma_p->tcd[chan_i] = *tcd_cfg_p;
+}
+
+// Show eDMA TCD
+void hal_freescale_edma_tcd_diag(cyghwr_hal_freescale_edma_tcd_t *tcd_p, cyg_int32 chan_i, const char *prefix)
+{
+    if(chan_i < 0) {
+        diag_printf("TCD %p chan %s:\n", tcd_p, prefix);
+        prefix = "";
+    } else {
+        diag_printf("%sTCD %p chan %d:\n", "", tcd_p, chan_i);
+    }
+
+        diag_printf("%s    saddr=%p soff=0x%04x, attr=0x%04x\n", prefix,
+                    tcd_p->saddr, tcd_p->soff, tcd_p->attr);
+        diag_printf("%s    daddr=%p doff=0x%04x\n", prefix,
+                    tcd_p->daddr, tcd_p->doff);
+        diag_printf("%s    nbytes=%d [0x%08x], slast=%d [0x%08x]\n", prefix,
+                    tcd_p->nbytes.mlno, tcd_p->nbytes.mlno,
+                    tcd_p->slast, tcd_p->slast);
+        diag_printf("%s    %s=%d [%p]\n", prefix,
+                    (tcd_p->csr & FREESCALE_EDMA_CSR_ESG_M) ? "sga" : "dlast",
+                    tcd_p->dlast_sga.dlast, tcd_p->dlast_sga.sga);
+        diag_printf("%s    biter = %d, citer = %d\n", prefix,
+                    tcd_p->biter.elinkno, tcd_p->citer.elinkno);
+        diag_printf("%s    CSR=0x%04x\n", prefix, tcd_p->csr);
+}
+
+// Show eDMA TCD set
+void hal_freescale_edma_transfer_diag(cyghwr_hal_freescale_edma_t
+                                      *edma_p, cyg_uint8 chan_i, cyg_bool recurse)
+{
+    cyghwr_hal_freescale_edma_tcd_t *tcd_p;
+    const char *prefix = "";
+
+    for(tcd_p = &edma_p->tcd[chan_i]; tcd_p; tcd_p = tcd_p->dlast_sga.sga){
+        hal_freescale_edma_tcd_diag(tcd_p, chan_i, prefix);
+        if(!(recurse && (tcd_p->csr & FREESCALE_EDMA_CSR_ESG_M)))
+            break;
+        prefix = "  ";
+    }
+}
+
+// end of freescale_dma.h
diff --git a/ecos/packages/hal/misc/ram/micron/cellularram/current/ChangeLog b/ecos/packages/hal/misc/ram/micron/cellularram/current/ChangeLog
new file mode 100644
index 0000000..99de9cf
--- /dev/null
+++ b/ecos/packages/hal/misc/ram/micron/cellularram/current/ChangeLog
@@ -0,0 +1,36 @@
+2013-04-28  Ilija Kocho  <ilijak@siva.com.mk>
+
+	*cdl/ram_micron_cellularram.cdl: RAM size format changed to decimal.
+	[ Bugzilla 1001837 ]
+
+2012-01-06  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/ram_micron_cellularram.cdl
+	* include/ram_micron_cellularram.h
+	* src/ram_micron_cellularram.c:
+	New package -- Micron CellularRam [Bugzilla 1001450]
+
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2012 Free Software Foundation, Inc.
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the
+// Free Software Foundation, Inc., 51 Franklin Street,
+// Fifth Floor, Boston, MA  02110-1301, USA.
+// -------------------------------------------
+// ####GPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/ecos/packages/hal/misc/ram/micron/cellularram/current/cdl/ram_micron_cellularram.cdl b/ecos/packages/hal/misc/ram/micron/cellularram/current/cdl/ram_micron_cellularram.cdl
new file mode 100644
index 0000000..4e9f5e0
--- /dev/null
+++ b/ecos/packages/hal/misc/ram/micron/cellularram/current/cdl/ram_micron_cellularram.cdl
@@ -0,0 +1,277 @@
+# ====================================================================
+#
+#      ram_micron_cellularram.cdl
+#
+#      RAM memory - Hardware support for Micron Cellularram
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2011 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      ilijak
+# Contributors:
+# Date:           2011-10-05
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_RAM_MICRON_CELLULARRAM {
+    display       "Micron CellularRam 1.5 support"
+
+    parent        CYGPKG_HAL_EXTRN_MEMORY
+    active_if	  CYGPKG_HAL_EXTRN_MEMORY
+
+    include_dir   cyg/devs
+    compile       -library=libextras.a ram_micron_cellularram.c
+
+    description   "
+        RAM memory device support for Micron CellularRam 1.5
+        Micron CellularRam supports Asynchronous and Sybchronous/Burst bus
+        modes."
+
+    define_proc {
+        puts $::cdl_header "#include <pkgconf/system.h>";
+    }
+
+    cdl_interface CYGINT_DEVS_RAM0_MICRON_CELLULAR {
+    }
+
+    cdl_component CYGHWR_DEVS_RAM0_MICRON_CELLULAR {
+        display "Micron Cellular Ram 1.5 chip 0"
+        flavor bool
+        default_value CYGINT_DEVS_RAM0_MICRON_CELLULAR
+        no_define
+
+        active_if CYGINT_DEVS_RAM0_MICRON_CELLULAR
+
+        cdl_option CYGHWR_RAM0_MICRON_CELLULAR_SIZE {
+            display "RAM size \[Bytes\]"
+            flavor data
+            default_value 16 * 1024 * 1024
+        }
+        cdl_component CYGHWR_RAM0_MICRON_BCR_SETTO {
+            display "Bus Configuration Register"
+            flavor data
+
+            calculated {
+                0x0 +
+                ((CYGHWR_RAM0_MICRON_BCR_ASYNC == "ASYNC" ? 1 : 0) << 15) +
+                ((CYGHWR_RAM0_MICRON_BCR_IL == "VARIABLE" ? 0 : 1) << 14) +
+                ((CYGHWR_RAM0_MICRON_BCR_LC & 0x7) << 11)                 +
+                ((CYGHWR_RAM0_MICRON_BCR_WP == "HIGH"     ? 1 : 0) << 10) +
+                ((CYGHWR_RAM0_MICRON_BCR_WC == "1"        ? 1 : 0) << 8)  +
+
+                ((CYGHWR_RAM0_MICRON_BCR_DS == "FULL" ? 0 :
+                  CYGHWR_RAM0_MICRON_BCR_DS == "1/2"  ? 1 : 2) << 4)      +
+
+                ((CYGHWR_RAM0_MICRON_BCR_BW == "NOWRAP"   ? 1 : 0) << 3)  +
+
+                (CYGHWR_RAM0_MICRON_BCR_BL ==  4   ? 1 :
+                 CYGHWR_RAM0_MICRON_BCR_BL ==  8   ? 2 :
+                 CYGHWR_RAM0_MICRON_BCR_BL ==  16  ? 3 :
+                 CYGHWR_RAM0_MICRON_BCR_BL ==  32  ? 4 : 7)
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_ASYNC {
+                display "Asynchronous/Synchronous mode"
+                flavor data
+                no_define
+                default_value { "SYNC" }
+                legal_values { "SYNC" "ASYNC" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_IL {
+                display "Initial latency"
+                flavor data
+                no_define
+                default_value { "FIXED" }
+                legal_values { "VARIABLE" "FIXED" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_LC {
+                display "Latency code"
+                flavor data
+                no_define
+                default_value 2
+                legal_values { 2 3 4 5 6 8 }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_WP {
+                display "Active WAIT polarity"
+                flavor data
+                no_define
+                default_value { "LOW" }
+                legal_values { "HIGH" "LOW" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_WC {
+                display "WAIT configuration"
+                flavor data
+                no_define
+                default_value 1
+                legal_values { 0 1 }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_DS {
+                display "Drive strength"
+                flavor data
+                no_define
+                default_value { "FULL" }
+                legal_values { "FULL" "1/2" "1/4" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_BW {
+                display "Burst wrap"
+                flavor data
+                no_define
+                default_value { "NOWRAP" }
+                legal_values { "WRAP" "NOWRAP" }
+            }
+
+            cdl_option CYGHWR_RAM0_MICRON_BCR_BL {
+                display "Burst length"
+                flavor data
+                no_define
+                default_value { "PERMANENT" }
+                legal_values { 4 8 16 32 "PERMANENT" }
+            }
+        }
+    }
+
+    cdl_interface CYGINT_DEVS_RAM1_MICRON_CELLULAR {
+    }
+
+    cdl_component CYGHWR_DEVS_RAM1_MICRON_CELLULAR {
+        display "Micron Cellular Ram 1.5 chip 1"
+        flavor bool
+        default_value CYGINT_DEVS_RAM1_MICRON_CELLULAR
+        no_define
+
+        active_if CYGINT_DEVS_RAM1_MICRON_CELLULAR
+
+        cdl_option CYGHWR_RAM1_MICRON_CELLULAR_SIZE {
+            display "RAM size \[Bytes\]"
+            flavor data
+            default_value 0x00100000
+        }
+        cdl_component CYGHWR_RAM1_MICRON_BCR_SETTO {
+            display "Bus Configuration Register"
+            flavor data
+
+            calculated {
+                0x0 +
+                ((CYGHWR_RAM1_MICRON_BCR_ASYNC == "ASYNC" ? 1 : 0) << 15) +
+                ((CYGHWR_RAM1_MICRON_BCR_IL == "VARIABLE" ? 0 : 1) << 14) +
+                ((CYGHWR_RAM1_MICRON_BCR_LC & 0x7) << 11)                 +
+                ((CYGHWR_RAM1_MICRON_BCR_WP == "HIGH"     ? 1 : 0) << 10) +
+                ((CYGHWR_RAM1_MICRON_BCR_WC == "1"        ? 1 : 0) << 8)  +
+
+                ((CYGHWR_RAM1_MICRON_BCR_DS == "FULL" ? 0 :
+                  CYGHWR_RAM1_MICRON_BCR_DS == "1/2"  ? 1 : 2) << 4)      +
+
+                ((CYGHWR_RAM1_MICRON_BCR_BW == "NOWRAP"   ? 1 : 0) << 3)  +
+
+                (CYGHWR_RAM1_MICRON_BCR_BL ==  4   ? 1 :
+                 CYGHWR_RAM1_MICRON_BCR_BL ==  8   ? 2 :
+                 CYGHWR_RAM1_MICRON_BCR_BL ==  16  ? 3 :
+                 CYGHWR_RAM1_MICRON_BCR_BL ==  32  ? 4 : 7)
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_ASYNC {
+                display "Asynchronous/Synchronous mode"
+                flavor data
+                no_define
+                default_value { "SYNC" }
+                legal_values { "SYNC" "ASYNC" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_IL {
+                display "Initial latency"
+                flavor data
+                no_define
+                default_value { "FIXED" }
+                legal_values { "VARIABLE" "FIXED" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_LC {
+                display "Latency code"
+                flavor data
+                no_define
+                default_value 2
+                legal_values { 2 3 4 5 6 8 }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_WP {
+                display "Active WAIT polarity"
+                flavor data
+                no_define
+                default_value { "LOW" }
+                legal_values { "HIGH" "LOW" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_WC {
+                display "WAIT configuration"
+                flavor data
+                no_define
+                default_value 1
+                legal_values { 0 1 }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_DS {
+                display "Drive strength"
+                flavor data
+                no_define
+                default_value { "FULL" }
+                legal_values { "FULL" "1/2" "1/4" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_BW {
+                display "Burst wrap"
+                flavor data
+                no_define
+                default_value { "NOWRAP" }
+                legal_values { "WRAP" "NOWRAP" }
+            }
+
+            cdl_option CYGHWR_RAM1_MICRON_BCR_BL {
+                display "Burst length"
+                flavor data
+                no_define
+                default_value { "PERMANENT" }
+                legal_values { 4 8 16 32 "PERMANENT" }
+            }
+        }
+    }
+}
diff --git a/ecos/packages/hal/misc/ram/micron/cellularram/current/include/ram_micron_cellularram.h b/ecos/packages/hal/misc/ram/micron/cellularram/current/include/ram_micron_cellularram.h
new file mode 100644
index 0000000..0196f2c
--- /dev/null
+++ b/ecos/packages/hal/misc/ram/micron/cellularram/current/include/ram_micron_cellularram.h
@@ -0,0 +1,74 @@
+#ifndef CYGONCE_DEVS_RAM_MICRON_CELLULAR_H
+#define CYGONCE_DEVS_RAM_MICRON_CELLULAR_H
+//==========================================================================
+//
+//      ram_micron_cellularram.h
+//
+//      Micron CellularRam 1.5
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    ilijak
+// Contributors:
+// Date:         2011-10-05
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/devs_ram_micron_cellularram.h>
+
+#define CYGHWR_DEVS_RAM_MICRON_RCR  0
+#define CYGHWR_DEVS_RAM_MICRON_BCR  1
+#define CYGHWR_DEVS_RAM_MICRON_DIDR 2
+
+#ifndef __ASSEMBLER__
+
+__externC cyg_uint16 ram_micron_reg_get(cyg_uint16 mem_reg_i,
+                                        volatile cyg_uint16 *ram_base_p,
+                                        cyg_uint32 ram_size);
+
+__externC void ram_micron_reg_set(cyg_uint16 mem_reg_i, cyg_uint16 setting,
+                                  volatile cyg_uint16 *ram_base_p,
+                                  cyg_uint32 ram_size);
+#endif
+
+#endif  // CYGONCE_DEVS_RAM_MICRON_CELLULAR_H
+// ------------------------------------------------------------------------
+// EOF ram_micron_cellularram.h
diff --git a/ecos/packages/hal/misc/ram/micron/cellularram/current/src/ram_micron_cellularram.c b/ecos/packages/hal/misc/ram/micron/cellularram/current/src/ram_micron_cellularram.c
new file mode 100644
index 0000000..67bf7d8
--- /dev/null
+++ b/ecos/packages/hal/misc/ram/micron/cellularram/current/src/ram_micron_cellularram.c
@@ -0,0 +1,86 @@
+//==========================================================================
+//
+//      ram_micron_cellularram.c
+//
+//      Micron CellularRam 1.5 support functions.
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      ilijak
+// Contributor(s):
+// Date:           2011-02-05
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_arch.h>           // HAL header
+
+#include <cyg/devs/ram_micron_cellularram.h>
+
+cyg_uint16 ram_micron_reg_get(cyg_uint16 mem_reg_i,
+                              volatile cyg_uint16 *mem_base_p,
+                              cyg_uint32 ram_size)
+{
+    mem_base_p +=  (ram_size/2) - 1;
+    cyg_uint16 reg_val __attribute__((unused));
+
+    reg_val = *mem_base_p;
+    reg_val = *mem_base_p;
+    *mem_base_p = mem_reg_i;
+    mem_reg_i = *mem_base_p;
+    reg_val = mem_base_p[-16];
+    return mem_reg_i;
+}
+
+void ram_micron_reg_set(cyg_uint16 mem_reg_i, cyg_uint16 setting,
+                       volatile cyg_uint16 *mem_base_p, cyg_uint32 ram_size)
+{
+    mem_base_p += (ram_size/2) - 1;
+    cyg_uint16 reg_val __attribute__((unused));
+
+    reg_val = *mem_base_p;
+    reg_val = *mem_base_p;
+    *mem_base_p = mem_reg_i;
+    *mem_base_p = setting;
+    reg_val = mem_base_p[-16];
+}
+
+//==========================================================================
+// EOF ram_micron_cellularram.c