diff options
| author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
|---|---|---|
| committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
| commit | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch) | |
| tree | f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/sparclite | |
| parent | f157da5337118d3c5cd464266796de4262ac9dbd (diff) | |
Added the OS files
Diffstat (limited to 'ecos/packages/hal/sparclite')
49 files changed, 11003 insertions, 0 deletions
diff --git a/ecos/packages/hal/sparclite/arch/current/ChangeLog b/ecos/packages/hal/sparclite/arch/current/ChangeLog new file mode 100644 index 0000000..02ea5c6 --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/ChangeLog @@ -0,0 +1,695 @@ +2011-01-02 Sergei Gavrikov <sergei.gavrikov@gmail.com> + + * cdl/hal_sparclite.cdl: Eliminate some warnings. [ Bugzilla + 1001083 ] + +2004-04-22 Jani Monoses <jani@iv.ro> + + * cdl/hal_sparclite.cdl : + Invoke tail with stricter syntax that works in latest coreutils. + +2003-04-10 Nick Garnett <nickg@balti.calivar.com> + + * src/sparclite.ld: + Added libsupc++.a to GROUP() directive for GCC versions later than + 3.0. + +2002-04-29 Jonathan Larmour <jlarmour@redhat.com> + + * src/vectors.S: + * src/vec_xvsr.S: + * src/vec_ivsr.S: + Don't use .file as it can confuse debugging since the .file + doesn't contain the path and therefore the debugger will never + know where it lives! This conflicts with using -Wa,--gstabs. + +2000-10-16 Jonathan Larmour <jlarmour@redhat.com> + + * include/hal_arch.h (CYGARC_JMP_BUF_SIZE): Define hal_jmp_buf in + terms of this. + +2000-08-07 Jonathan Larmour <jlarmour@redhat.co.uk> + + * src/sparclite.ld: Remove extra underscore from below. It was + correct before. + +2000-06-21 Nick Garnett <nickg@cygnus.co.uk> + + * include/basetype.h: + Removed definition of CYG_LABEL_NAME(). Now dealt with by default + definition in cyg_type.h. + + * src/sparclite.ld: + Added extra underscore to _stext and _etext. + Switched over to new table creation mechanism. + +2000-06-08 Jesper Skov <jskov@redhat.com> + + * include/hal_arch.h (CYGARC_HAL_SAVE_GP, CYGARC_HAL_RESTORE_GP): + Added. + +2000-02-16 Jesper Skov <jskov@redhat.com> + + * src/vectors.S: + * src/hal_boot.c: + CYG_HAL_SPARCLITE_ > CYGPKG_HAL_SPARCELITE_ + +2000-02-16 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sparclite.cdl: removed fix me + +2000-01-28 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite.ld: Add support for network package. + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +1999-12-02 John Dallaway <jld@cygnus.co.uk> + + * cdl/hal_sparclite.cdl: + + Use the <PACKAGE> token in custom rules. + +1999-12-01 John Dallaway <jld@cygnus.co.uk> + + * cdl/hal_sparclite.cdl: + + Use the <PREFIX> token in custom rules. + +1999-11-04 John Dallaway <jld@cygnus.co.uk> + + * cdl/hal_sparclite.cdl: + + Output custom rule dependency information to .deps files in + the current directory. + + Dispense with the need to create a 'src' sub-directory. + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/hal_sparclite.cdl: Define build options. + +1999-11-01 Jesper Skov <jskov@cygnus.co.uk> + + * cdl/hal_sparclite.cdl: Addded. + +1999-10-15 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vectors.S (not_window_overflow): Actually the dispatcher + into exception VSRs. Bugfix: wrong number was placed in %l3 for + call to xvsr, so for *some* types of trap, including user traps + other than those handled directly in-HAL, a vector way off the end + of the array would be used. Apparently those other types of trap + never happen, but just in case... + +1999-10-13 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vectors.S: Optionally implement Multiple (rather than + Single) Vector Trapping. The config options to control this are + in the platform HAL because some SPARCs do not support SVT, where + it is optional the platform says so. This demands a variable + sized region be reserved for trampoline code or the vectors in + RAM, which is done via section .ram_vectors, defined herein. + + * src/sparclite.ld: Define SECTION_ram_vectors(...) to deal with + the new .ram_vectors section. This is to provide a variable sized + area at the start of RAM to hold either trampoline code when SVT + is selected, or a fill 4k + handlers of vectors when MVT is + selected. Previously this was bodged by pretending RAM starts at + 0x4000200 in ROM startup builds. + (comment from the example .ldi files...) + The ram_vectors section is to allow some free space to copy + vectors into from the ROM. This is required to be variable size + to accomodate SVT or MVT; 80 bytes vs 4kB. Copying is not + necessary with MVT, but it is optional because it may offer + performance gains. Copying is required for SVT because the + (aligned) start of ROM contains initialization instructions. RAM + copy is used rather than leave a big gap in the ROM to get an + aligned address for the trampoline code. For RAM startup, + ram_vectors will usually be of size zero, unless MVT and copying + are enabled for memory estimation reasons. + +1999-09-29 Hugo Tyson <hmt@cygnus.co.uk> + + [src/vectors.S: needed no change!] + + * include/vectors.h: Potentially accept a register window count + from the platform HAL, or according to platform selection. Make + more of the dependent macros computed. + + * src/vec_ivsr.S (hal_default_interrupt_vsr): Handle other register + window sizes correctly; particularly when handling underflow trap + by hand. + + * src/vec_xvsr.S (hal_default_exception_vsr): Handle other register + window sizes correctly; particularly when handling underflow trap + by hand. + + * src/context.S (hal_thread_load_context): Handle other register + window sizes correctly. + + * src/icontext.c (cyg_hal_sparc_get_gdb_regs): Handle other register + window sizes correctly; set up initial context differently. + +1999-06-07 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (hal_jmp_buf): force this to be 64-bit + aligned so that std ops in hal_setjmp(), hal_longjmp() work. + +1999-06-03 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_boot.c: Add a dummy __gccmain() to prevent ctors being + called twice. This seems to be a recent compiler change: + [from gcc/ChangeLog] + Sat May 22 18:18:43 1999 Jason Merrill <jason@yorick.cygnus.com> + * sparc/liteelf.h: Handle ctors like MIPS crosses. + * sparc/lite.h (STARTFILE_SPEC, LIB_SPEC): Define to "". + * configure.in: Don't use libgloss.h on sparclite-elf. + Use collect2 on sparclite-aout. + +1999-05-20 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_intr.h (HAL_INTERRUPT_STACK_CALL_PENDING_DSRS): + Define this if CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK; + ie. we are running a separate interrupt stack. Also define + symbols for it so that we can monitor its usage easily. + + * src/vec_ivsr.S (hal_interrupt_stack_call_pending_DSRs): Add this + function to run DSRs on the interrupt stack (if using it). Switch + over to executing on the interrupt stack when needed. + + * src/vectors.S (cyg_interrupt_stack_base): Define the interrupt + stack either if we need it as an interrupt stack or if we need it + as a bootup stack (simulator); if it's there, use it as a bootup + stack anyway. + + * src/context.S (hal_thread_load_context): Install the PSR that + was saved in its entirety, including the interrupt and trap enable + state. This is needed for running a separate interrupt stack, but + harmless when not so doing. + + * src/icontext.c (hal_thread_init_context): Install an initial PSR + which includes ET, S and PS (Enable traps, Supermode, prevSuper) + and a PIL (processor interrupt level) of 15 (maximum) + so that a context switch which preserves interrupt mode will work. + +1999-05-13 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Align stack + (rather conservatively) before use. + +1999-04-28 Bart Veer <bartv@cygnus.co.uk> + + * src/PKGconf.mak: + Remove the -n argument to tail, it does not appear to be required + on any supported host and causes problems with some + implementations of tail. + +1999-04-15 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/sparclite.ld: Define __bss_end at the end of the BSS + * src/hal_boot.c (hal_zero_bss): Stop at __bss_end rather than _end + when clearing BSS + + These fix PR 19750 + +1999-04-14 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/PKGconf.mak (EXTRAS): Don't generate extras.o here any more + But do define EXTRAS every time for the linker script. + +1999-04-09 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_intr.h (HAL_RESTORE_INTERRUPTS et al): Put in 3 nops + after any writes to the psr; TBH I don't think they're strictly + necessary when not altering the window state, but for complete + safety and adherence to the book of words.... + +1999-04-08 John Dallaway <jld@cygnus.co.uk> + + * src/*.ld: Revised SECTION_* macro arguments to + avoid padded output sections (PR 19787) + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_io.h: If not the simulator, get hal_hwio.h too - + which describes board-and-CPUvariant-specific IO needs. + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_intr.h (HAL_VSR_SET_TO_ECOS_HANDLER): Define this + macro for use in tests that are interested in exception diddling. + Redefine CYGNUM_HAL_ISR_MIN to describe the number of interrupt + sources; while there are XSRs too, this definition is better for + the error checking in kernel interrupt stuff. Changed the symbols + used for defining tables sizes to match, since there are still 27 + VSRs and ISRs/XSRs and their data. + + * src/hal_intr.c: Use the correct symbol for the size of the + isr/vsr/their-data tables. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/sparc_ex.c (cyg_[user_]start): + If there is no kernel, cyg_user_start() is never called, main gets + in and steals the CPU. So we hang. So if there is no kernel, + define cyg_start() instead to wrest control. + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h (CYGNUM_HAL_STACK_SIZE_TYPICAL): + And this time make the edit correctly ;-/ + +1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_arch.h: + Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of + CYGNUM_HAL_MINIMUM_STACK_SIZE. + +1999-03-17 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vectors.S (rom_vectors_end, rom_vectors): Add two new + symbols for copying trampoline code into RAM in ROM startup. This + keeps ROM startup as similar as possible to RAM, for simplicity; + no re-ordering of vectors.S's contents. + + * src/hal_boot.c (hal_copy_data): Copy in long sized units rather + than long longs, better to cope with ROM data alignment. + Also add some LED output (if SLEB hardware) for startup to help + with debugging ROM start. + +1999-03-17 John Dallaway <jld@cygnus.co.uk> + + * src/PKGconf.mak: Remove dependence on echo '-e' switch. + +1999-03-16 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vectors.S (genuine_reset): Add a little extra debug to SLEB + LEDs, and use the genuine top-of-memory stack when running on + hardware; only define cyg_bootup_stack in the simulator case. + + * src/sparclite.ld: Define rom_data_start, regardless of start + type, no harm is done. + +1999-03-12 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/hal_sparclite.h: + * include/hal_arch.h: Moved definition of 'CYGNUM_HAL_MINIMUM_STACK_SIZE' + +1999-03-11 Hugo Tyson <hmt@cygnus.co.uk> + + * src/icontext.c (cyg_hal_sparc_[gs]et_gdb_regs): + Two new routines to communicate our nice, optimized stack save + states to a reg list for GDB. My maximal register saves are not + really suitable for passing to GDB in any case, they're for humans + to debug the interrupt code more than anything else, and my + minimal save sets naturally contain pointers and ways of finding + the rest of the reg set, but it depends on whether it's an + interrupt save or a synchronous one, and given the SPARClite's + stack layout, it's a bit hairy. + + * src/vec_ivsr.S (hal_default_interrupt_vsr): + Do save %g0 even in a minimal context, so that the code for + communicating register state with GDB can tell it's a minimum + context. Costs one store cycle per interrupt. + + * include/hal_arch.h (HAL_[GS]ET_GDB_REGISTERS): + Define and call routines cyg_hal_sparc_[gs]et_gdb_regs for + communicating register state of a thread to GDB. + + * src/vectors.S (real_vector): Reinstate the anullment of the + instructions that were blamed for register corruption earlier; + they are correct and safe. + +1999-03-10 Jesper Skov <jskov@cygnus.co.uk> + + * include/hal_intr.h (HAL_INTERRUPT_IN_USE): Added. + +1999-03-09 Gary Thomas <gthomas@cygnus.co.uk> + + * src/hal_boot.c: Added missing <cyg/infra/cyg_type.h> include file. + +1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> + + * src/sparclite.ld: + * src/PKGconf.mak: Clean up I/O package changes. + +1999-03-04 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/sparclite.ld: + Unconditionalize use of libextras.a and add to GROUP() + +1999-03-04 Gary Thomas <gthomas@cygnus.co.uk> + + * src/PKGconf.mak: + * src/sparclite.ld: New I/O package support. + + * src/vectors.S: Fix register corruption problem - stems from + use of annulled instructions in window overflow/underflow code. + +1999-02-25 Hugo Tyson <hmt@cygnus.co.uk> + + These log entries from 1999-02-22 to 1999-02-24 were executed in + a branch; this change is a merge of that branch into the trunk. + + (1999-02-24 Hugo Tyson <hmt@cygnus.co.uk>) + + * tests/sparc_ex.c (sparc_ex_main): + For all traps except the USER_TRAP, install the default VSR + hal_default_exception_vsr(); this is so that this test catches + exception ie. is able to work, even when we are playing nice with + CygMon and GDB. The USER_TRAP is left so that breakpoints work, + for the test infrastructure. + + (1999-02-22 Hugo Tyson <hmt@cygnus.co.uk>) + + * src/vectors.S (real_vector): Remove old testing code. Add delay + NOPs after writes to %wim and %psr for safety. Leave installing + the trap vector to platform-specific code, along with RAM control + and cache initialization. + + * src/vec_ivsr.S (hal_default_interrupt_vsr): Add delay NOPs after + writing the %wim before doing a restore; that was a bug that was. + + * src/vec_xvsr.S (hal_default_exception_vsr): same change. + + * src/hal_intr.c: Remove platform-specific clock period variable; it + happens that both platforms sim and sleb have one, but it's not a + requirement of the target architecture. + + * src/hal_boot.c (cyg_hal_start): Move diddling the sim-specific + watchdog into platform-specific startup code viz. new routines + hal_board_{pre/post}start(). + + * src/context.S: a couple of extra NOPs to ensure that %wim and + %psr changes work on real hardware. + + (1999-02-22 Hugo Tyson <hmt@cygnus.co.uk>) + + * include/hal_arch.h (HAL_SET_GDB_REGISTERS): + Remove warning about unused var 'cos of the incompleteness of + these macros; gdb interworking is not yet supported. + +1999-02-25 Nick Garnett <nickg@cygnus.co.uk> + + * include/vectors.h: + Changed label used to access scheduler lock to one that is not + mangled by C++. This is intended to make support for interrupt + handling in non-kernel configurations easier. + +1999-02-20 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/hal_arch.h: + Rename deliver_exception() -> cyg_hal_deliver_exception() + QA improvements + + * include/hal_intr.h: + Reorganise vector/interrupt/exception names according to purpose + Rename exception_handler() -> cyg_hal_exception_handler() + QA improvements + + * src/hal_intr.c: + Rename exception_handler() -> cyg_hal_exception_handler() + Rename deliver_exception() -> cyg_hal_deliver_exception() + Rename CYG_ISR_COUNT -> CYGNUM_HAL_ISR_COUNT + QA improvements + + * src/vec_ivsr.S: + * src/vec_xvsr.S: + Rename CYG_ISR_COUNT -> CYGNUM_HAL_ISR_COUNT + QA improvements + + * tests/sparc_ex.c: + Rename CYG_EXCEPTION_* -> CYGNUM_HAL_EXCEPTION_* + Rename CYG_VECTOR_UNALIGNED -> CYGNUM_HAL_VECTOR_UNALIGNED + +1999-02-12 Hugo Tyson <hmt@cygnus.co.uk> + + * src/context.S (hal_thread_load_context, hal_setjmp): + Disable interrupts (but not traps) while doing the flush of all my + callers and their callers' callers register sets to the stack. + There is evidence that the inconsistency in the stack during this + is a bad thing, though I have to admit that I don't see exactly + how it goes wrong. Partly, it's impossible to debug, so if the + problem I saw (a SEGV in instrumentation of interrupt_end()) is + reproduced with this change, I'll have more to go on. This is a + conservative change in that sense. + + * include/hal_arch.h (HAL_FLUSH_REGISTERS_TO_STACK): + Disable interrupts but not traps while doing this. Ditto. + +1999-02-12 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/hal_sparclite.h (CYGNUM_HAL_MINIMUM_STACK_SIZE): + Define a minimal sensible stack size for apps to use. Note that + this file is included by hal_arch.h and so is available to all HAL + users, and in fact almost everyone by default. + +1999-02-12 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_intr.c (exception_handler): + Include <cyg/infra/cyg_ass.h> so that the CYG_FAIL() in some + configurations actually compiles (actually: links). + combo{22,18,10,6} were thus afflicted. + +1999-02-11 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/sparc_ex.c (do_test): Make the test run for much less time + when CYG_USE_TRACING and in any case bleat periodically about how + successful it is to prevent testing system timeouts. Also move + the test routines (those which provoke the exception) to the end + so that (ever helpful) -O3 cannot inline them and then "optimize" + the result and thus spoil the whole damned test too. + +1999-02-08 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_sparclite.h: Correct capitalization of + 'SPARClite'. + +1999-02-08 John Dallaway <jld@cygnus.co.uk> + + * src/sparclite.ld: New MLT-compatible linker script + * src/PKGconf.mak: Add build rules for sparclite.ld + +1999-02-04 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vec_ivsr.S (hal_default_interrupt_vsr): Preserve global + registers over interrupts, and implement support for + CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT ie. save a + minimal register set rather than a maximal. Create a saved + register set whose address is passed to the interrupt handler + (though it may well be mostly empty). + [also tidied up trailing tabs and long blank lines] + + * src/vec_xvsr.S (hal_default_exception_vsr): Preserve all + registers over interrupts; create a saved register set whose + address is passed to the exception handler so it can modify it. + [also tidied up trailing tabs and long blank lines] + + * src/context.S( hal_setjmp, hal_longjmp): + (hal_thread_switch_context,hal_thread_load_context): Implement + CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM support; ie. save a minimal + register set rather than a maximal. + + * include/hal_arch.h (HAL_FLUSH_REGISTERS_TO_STACK): New macro + useful for writing exception handlers, for example. + (HAL_GET_GDB_REGISTERS, HAL_SET_GDB_REGISTERS): provided initial + dummy versions of these. + + * tests/sparc_ex.c: A test of the exception mechanism: + deliberately cause unaligned accesses of various sizes and check + we get exactly one trap and correctly step over it by modifying + the saved register set whose address the exception ISR is handed. + This test should be regarded as documentation for the exception + handler API/ABI. + + * tests/PKGconf.mak (TESTS): Build sparc_ex. + +1999-02-01 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vectors.S (genuine_reset): + Include <cyg/hal/halboot.si> to set up RAM controllers, cache and + the like - this is rather platform dependant. + +1999-02-01 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_intr.h (HAL_TRANSLATE_VECTOR): + Include a definition of this important macro. Not. + It's used when interrupt chaining is selected, BUT we the HAL make + no distinction, it's up to the kernel to look after things. So + this macro is an assignment. + +1999-01-28 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_intr.h: + Get interrupt controller definitions from a board-specific file: + #include <cyg/hal/hal_xpic.h> + Get clock control definitions from a board-specific file: + #include <cyg/hal/hal_clock.h> + Delete the original definitions from this central file. + + * include/hal_cache.h: REMOVED to the simulator tree in the first + instance; more generally to various board-specific files. + + +1999-01-26 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_cache.h (HAL_DCACHE_ENABLE) (and its friends): + Define initial empty placeholder versions of these so that cache + tests build. Well it's a start. + +1999-01-21 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/hal_boot.c (cyg_hal_invoke_constructors): + Add code to deal with CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + Tidy up and update description header + Shorten needlessly long lines + Remove all traces of non-CYG_KERNEL_USE_INIT_PRIORITY code + +1999-01-21 Hugo Tyson <hmt@cygnus.co.uk> + + * src/vectors.S (genuine_reset): Set the RAM size to 4MB in the + erc32 simulator. + + * include/hal_io.h: New file; macros to access IO space, really a + place holder at present. + + * include/hal_intr.h: Do not define WATCHDOG() macro. + + * src/hal_intr.c (hal_default_isr): Do not mess with the watchdog + in the the default interrupt handler. + + * src/hal_boot.c (hal_zero_bss): use an efficient 8-byte zero. + (hal_copy_data): use an efficient 8-byte copy. + (cyg_hal_start): turn off the ERC32 watchdog timer before we start + anything very time consuming. + + NB: the 8-byte copy changes require alignment in the linker + script: see the Changelog in hal/sparclite/sim/... for details. + +1999-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + Modified files in arch: + * include/hal_arch.h + * include/hal_intr.h + * src/PKGconf.mak + * src/context.S + * src/hal_intr.c + * src/vec_ivsr.S + * src/vec_xvsr.S + * src/vectors.S + + New files in arch: + * src/hal_boot.c (bss initialization, constructors &c) + * include/hal_cache.h (empty but required header) + + Modified files in sim: + * include/hal_diag.h + + Lots more progress; essentially, everything now works. + + Simulator's treatment of stdio is poor though, it doesn't work + under pkgtest. This has been slowing me up. + +1999-01-14 Hugo Tyson <hmt@cygnus.co.uk> + + * ecc/ecc/hal/sparclite/...: + + Initial checkin of SPARClite HAL; it doesn't work yet, except the + most trivial of tests - timer and interrupt manipulation stuff is + entirely absent. + + Here's some documentation of the initial checkin tree; this will + change, as platform dependent stuff moves correctly into the sim + or <board> directories. + + arch/current/include: + basetype.h nothing much here. + vectors.h definitions of symbols shared between the + various vector code assembler files, can be + included in both C and assembler. + hal_intr.h various macros for clock and interrupt + control plus the eCos vector numbering scheme; we + map thus: + what SPARC trap type eCos vector numbers + ----------------------------------------------- + (not used) --- 0 + interrupts (17-31) 1-15 + user traps (128-255) 16 + exceptions (1-9,36==4) 17-25 + others (10,?) 26 + ----------------------------------------------- + Trap types 5 and 6 which would be eCos vectors 21 + and 22 are handled in the trampoline code in + file src/vectors.S + hal_arch.h definition of a thread context, plus + macros for thread switching and the like. Some + ancillary bit twiddling macros and cache barriers + too. + + arch/current/include/pkgconf: + hal_sparclite.h pkgconf config/header file. + + arch/current/src: + vectors.S boot-up stuff, trampoline code that hangs + on the interrupt/trap vector, handlers for window + under/overflow. Saves some state in registers + then jumps to the interrupt or exception VSR + respectively. + Also instantiates the VSR table. + vec_ivsr.S the default interrupt VSR; it establishes + a C calling environment (ie. anticipates a window + overflow) then locks the scheduler, calls the ISR + with appropriate arguments, and then interrupt_end() + before undoing that environment, anticipating + window underflow and returning to the interrupted + instruction. + vec_xvsr.S the default exception AKA trap VSR; does + the same as the interrupt one but without the + scheduler lock or interrupt end. + hal_intr.c instantiates the ISR table used by the + code above. + context.S context switch code, saves and loads up a + whole register state, coroutine or longjump-like. + icontext.c initializes a context to "jump" to in + context.S at the birth of a new thread. + + sim/current/include: + hal_diag.h macros to deal with debugging output via a + fake serial device of some kind; initially empty, + but definitely board/sim dependent. + + sim/current/include/pkgconf: + hal_sparclite_sim.h pkgconf config/header file. + + sim/current/src: + sim.ld linker script bits for "sim" target. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== + +//EOF ChangeLog diff --git a/ecos/packages/hal/sparclite/arch/current/cdl/hal_sparclite.cdl b/ecos/packages/hal/sparclite/arch/current/cdl/hal_sparclite.cdl new file mode 100644 index 0000000..d6368ae --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/cdl/hal_sparclite.cdl @@ -0,0 +1,130 @@ +# ==================================================================== +# +# hal_sparclite.cdl +# +# SPARClite architectural HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: hmt +# Contributors: +# Date: 1999-11-01 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_SPARCLITE { + display "SPARClite architecture" + parent CYGPKG_HAL + hardware + include_dir cyg/hal + define_header hal_sparclite.h + description " + The SPARClite architecture HAL package provides generic support + for this processor architecture. It is also necessary to select + a specific target platform HAL package." + + compile vectors.S vec_ivsr.S vec_xvsr.S context.S icontext.c + compile hal_intr.c hal_boot.c + + make { + <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S + $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 vectors.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm vectors.tmp + } + + make { + <PREFIX>/lib/target.ld: <PACKAGE>/src/sparclite.ld + $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 target.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm target.tmp + } + + cdl_component CYGPKG_HAL_SPARCLITE_OPTIONS { + display "SPARClite build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_HAL_SPARCLITE_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the SPARClite HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_SPARCLITE_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the SPARClite HAL. These flags are removed from + the set of global flags if present." + } + + cdl_option CYGPKG_HAL_SPARCLITE_TESTS { + display "SPARClite tests" + flavor data + no_define + calculated { "tests/sparc_ex" } + description " + This option specifies the set of tests for the SPARClite HAL." + } + } + + cdl_option CYGBLD_LINKER_SCRIPT { + display "Linker script" + flavor data + no_define + calculated { "src/sparclite.ld" } + } +} diff --git a/ecos/packages/hal/sparclite/arch/current/include/basetype.h b/ecos/packages/hal/sparclite/arch/current/include/basetype.h new file mode 100644 index 0000000..facfb28 --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/include/basetype.h @@ -0,0 +1,73 @@ +#ifndef CYGONCE_HAL_BASETYPE_H +#define CYGONCE_HAL_BASETYPE_H + +//============================================================================= +// +// basetype.h +// +// Standard types for this architecture. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1998-12-10 +// Purpose: Define architecture base types. +// Usage: Included by "cyg_type.h", do not use directly + +// +//####DESCRIPTIONEND#### +// + +//----------------------------------------------------------------------------- +// Characterize the architecture + +#define CYG_BYTEORDER CYG_MSBFIRST // Big endian + +//----------------------------------------------------------------------------- +// SPARC does not usually use labels with underscores. + +//#define CYG_LABEL_NAME(_name_) _name_ + +//----------------------------------------------------------------------------- +// Define the standard variable sizes + +// The SPARClite architecture uses the default definitions of the base +// types, so we do not need to define any here. + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_BASETYPE_H +// End of basetype.h diff --git a/ecos/packages/hal/sparclite/arch/current/include/hal_arch.h b/ecos/packages/hal/sparclite/arch/current/include/hal_arch.h new file mode 100644 index 0000000..7b8880f --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/include/hal_arch.h @@ -0,0 +1,364 @@ +#ifndef CYGONCE_HAL_ARCH_H +#define CYGONCE_HAL_ARCH_H + +//========================================================================== +// +// hal_arch.h +// +// Architecture specific abstractions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1999-02-20 +// Purpose: Define architecture abstractions +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_intr.h> // HAL_DISABLE_INTERRUPTS + +//-------------------------------------------------------------------------- +// Processor saved states: +// +// All these structures must be doubleword (64 bit) aligned. +// The code that creates them on the stack will ensure this is so. + +#define HAL_THREAD_CONTEXT_GLOBAL_BASE 0 +#define HAL_THREAD_CONTEXT_OUT_BASE 8 +#define HAL_THREAD_CONTEXT_LOCAL_BASE 16 +#define HAL_THREAD_CONTEXT_IN_BASE 24 + +typedef struct +{ + // this is the save structure found at *(stack_ptr) always, note that + // i[6] is the frame pointer is the previous stack pointer, and + // o[6] is the stack pointer is the next frame pointer, + // so they form a linked list back up the call stack. + cyg_uint32 l[8]; /* Locals r16-r23 */ + cyg_uint32 i[8]; /* Ins r24-r31 */ +} HAL_SavedWindow; + +typedef struct +{ + // Window save at stack pointer + HAL_SavedWindow li; +//16 + // This is the rest of the save state: + // NOTE: g[0] is used for the CWP, for %g0 == 0. Also note that the + // assembler routines must load/store it in the right order. + cyg_uint32 g[8] ; /* Globals r0- r7 */ + cyg_uint32 o[8] ; /* Outs r8-r15 */ +//32 words in size + +// There is no need to save any other state; for example, condition codes, +// the PC and NextPC, and Y, are preserved in local registers in the trap +// handling window and so preserved in the caller stack frame as viewed +// from an ISR. Note that the VSR is jumped to with those locals being set +// up (and Y in situ), and it must preserve them itself before calling any +// subsequent handlers (ISRs). + +} HAL_SavedRegisters; + + +typedef struct +{ + // Window save at stack pointer + HAL_SavedWindow li; + cyg_uint32 composite_return_ptr; /* structure returns */ + cyg_uint32 spill_args[6]; /* for callee to store */ + cyg_uint32 spare; /* keep this 64-bits */ +} HAL_FrameStructure; + + +//-------------------------------------------------------------------------- +// Exception handling function. +// This function is defined by the kernel according to this prototype. It is +// invoked from the HAL to deal with any CPU exceptions that the HAL does +// not want to deal with itself. It usually invokes the kernel's exception +// delivery mechanism. + +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); + +//-------------------------------------------------------------------------- +// Bit manipulation macros + +#define HAL_LSBIT_INDEX(index, mask) \ + CYG_MACRO_START \ + asm volatile ( \ + "scan %1, 0, %%l7;" \ + "mov 31, %0;" \ + "sub %0, %%l7, %0" \ + : "=r"(index) \ + : "r"(mask & ~(mask-1)) \ + : "l7" \ + ); \ +CYG_MACRO_END + +#define HAL_MSBIT_INDEX(index, mask) \ + CYG_MACRO_START \ + asm volatile ( \ + "scan %1, 0, %%l7;" \ + "mov 31, %0;" \ + "sub %0, %%l7, %0" \ + : "=r"(index) \ + : "r"(mask) \ + : "l7" \ + ); \ +CYG_MACRO_END + + +//-------------------------------------------------------------------------- +// Context Initialization +// Initialize the context of a thread. +// Arguments: +// _sparg_ name of variable containing current sp, will be written with new sp +// _thread_ thread object address, passed as argument to entry point +// _entry_ entry point address. +// _id_ bit pattern used in initializing registers, for debugging. + +externC CYG_ADDRESS +hal_thread_init_context( CYG_WORD sparg, + CYG_WORD thread, + CYG_WORD entry, + CYG_WORD id ); + +#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ +CYG_MACRO_START \ + _sparg_ = hal_thread_init_context( (CYG_WORD)(_sparg_), \ + (CYG_WORD)(_thread_), \ + (CYG_WORD)(_entry_), \ + (CYG_WORD)(_id_) ); \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +// Context switch macros. +// The arguments are pointers to locations where the stack pointer +// of the current thread is to be stored, and from where the sp of the +// next thread is to be fetched. + +externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); +externC void hal_thread_load_context( CYG_ADDRESS to ) + __attribute__ ((noreturn)); + +#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ + hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \ + (CYG_ADDRESS)_fspptr_); + +#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ + hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); + + +//--------------------------------------------------------------------------- +// Execution reorder barrier. +// When optimizing the compiler can reorder code. In multithreaded systems +// where the order of actions is vital, this can sometimes cause problems. +// This macro may be inserted into places where reordering should not happen. + +#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) + +//--------------------------------------------------------------------------- +// Breakpoint support +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen +// if executed. +// HAL_BREAKINST is the value of the breakpoint instruction and +// HAL_BREAKINST_SIZE is its size in bytes. + +#define HAL_BREAKPOINT(_label_) \ +asm volatile (" .globl " #_label_ ";" \ + #_label_":" \ + "ta 1" \ + ); + +#define HAL_BREAKINST {0x91,0xd0,0x20,0x01} +#define HAL_BREAKINST_SIZE 4 + +//--------------------------------------------------------------------------- +// Thread register state manipulation for GDB support. + +// Translate a stack pointer as saved by the thread context macros above into +// a pointer to a HAL_SavedRegisters structure. +#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ + (_regs_) = (HAL_SavedRegisters *)(_sp_) + +// Routines in icontext.c used here because they're quite large for +// the SPARClite (note param order): +externC void +cyg_hal_sparc_get_gdb_regs( void *gdb_regset, + HAL_SavedRegisters *eCos_regset ); + +externC void +cyg_hal_sparc_set_gdb_regs( HAL_SavedRegisters *eCos_regset, + void *gdb_regset ); + + +// Copy a set of registers from a HAL_SavedRegisters structure into a GDB +// ordered array. +#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ + CYG_MACRO_START \ + cyg_hal_sparc_get_gdb_regs( (_aregval_), (_regs_) ); \ +CYG_MACRO_END + +// Copy a GDB ordered array into a HAL_SavedRegisters structure. +#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ + CYG_MACRO_START \ + cyg_hal_sparc_set_gdb_regs( (_regs_), (_aregval_) ); \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +// HAL setjmp + +#define CYGARC_JMP_BUF_SIZE 32 // (words) + +// this too must be doubleword aligned (64 bit) + +typedef cyg_uint64 hal_jmp_buf[ CYGARC_JMP_BUF_SIZE / 2 ]; + +externC int hal_setjmp(hal_jmp_buf env); +externC void hal_longjmp(hal_jmp_buf env, int val); + +//--------------------------------------------------------------------------- +// Flush Register Windows +// +// This is implemented as trap 3 in some SPARC systems. +// This macro is only for use from normal, foreground code. +// (including exception handlers and the like) + +#define HAL_FLUSH_REGISTERS_TO_STACK() \ + CYG_MACRO_START \ + cyg_uint32 _saveintr_; \ + HAL_DISABLE_INTERRUPTS( _saveintr_ ); /* leave traps on */ \ + asm volatile ( \ + /* force out all our callers register sets onto the stack */ \ + /* if necessary: the system will handily take care of this for */ \ + /* us as follows: */ \ + "save %%sp, -16 * 4, %%sp;" /* need all these to preserve */ \ + "save %%sp, -16 * 4, %%sp;" /* the linked list property... */ \ + "save %%sp, -16 * 4, %%sp;" \ + "save %%sp, -16 * 4, %%sp;" \ + "save %%sp, -16 * 4, %%sp;" \ + "save %%sp, -16 * 4, %%sp;" \ + "restore;" \ + "restore;" \ + "restore;" \ + "restore;" \ + "restore;" \ + "restore" \ + /* six of these is correct; a seventh would force out the */ \ + /* current set that we are using right now. Note that minimal */ \ + /* space is allowed on stack for locals and ins in case this */ \ + /* sequence itself gets interrupted and recurses too deep. */ \ + : \ + : \ + : "memory" \ + ); \ + HAL_RESTORE_INTERRUPTS( _saveintr_ ); \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +// Idle thread code. +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. + +//externC void hal_idle_thread_action(cyg_uint32 loop_count); + +#ifndef HAL_IDLE_THREAD_ACTION +#define HAL_IDLE_THREAD_ACTION(_count_) \ + /* Cyg_Clock::real_time_clock->tick() */ +#endif + +//--------------------------------------------------------------------------- + +// Minimal and sensible stack sizes: the intention is that applications +// will use these to provide a stack size in the first instance prior to +// proper analysis. Idle thread stack should be this big. + +// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. +// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. +// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! + +// We define quite large stack needs for SPARClite, for it requires 576 +// bytes (144 words) to process an interrupt and thread-switch, and +// momentarily, but needed in case of recursive interrupts, it needs 208 +// words - if a sequence of saves to push out other regsets is interrupted. + +// This is not a config option because it should not be adjusted except +// under "enough rope" sort of disclaimers. + +// A minimal, optimized stack frame is 24 words, but even -O2 code seems to +// place a few locals in the locals area: round this up to provide a +// sensible overestimate: +#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 32) + +// Stack needed for a context switch: this is implicit in the estimate for +// interrupts so not explicitly used below: +#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 32) + +// Interrupt + call to ISR, interrupt_end() and the DSR +#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ + ((208 * 4) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) + +// And we have lots of registers so no particular amount is added in for +// typical local variable usage. + +// Typically we have 4 nestable interrupt sources, clock, serialin, +// serialout, (and NMI button, but you want it to not destroy context): + +#define CYGNUM_HAL_STACK_SIZE_MINIMUM \ + (4 * CYGNUM_HAL_STACK_INTERRUPT_SIZE + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) + +#define CYGNUM_HAL_STACK_SIZE_TYPICAL \ + (CYGNUM_HAL_STACK_SIZE_MINIMUM + 8 * CYGNUM_HAL_STACK_FRAME_SIZE) + +//-------------------------------------------------------------------------- +// Macros for switching context between two eCos instances (jump from +// code in ROM to code in RAM or vice versa). +#define CYGARC_HAL_SAVE_GP() +#define CYGARC_HAL_RESTORE_GP() + +//----------------------------------------------------------------------------- + +#endif // CYGONCE_HAL_ARCH_H +// End of hal_arch.h diff --git a/ecos/packages/hal/sparclite/arch/current/include/hal_intr.h b/ecos/packages/hal/sparclite/arch/current/include/hal_intr.h new file mode 100644 index 0000000..d195b78 --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/include/hal_intr.h @@ -0,0 +1,406 @@ +#ifndef CYGONCE_HAL_INTR_H +#define CYGONCE_HAL_INTR_H + +//=========================================================================== +// +// hal_intr.h +// +// HAL Interrupt and clock support +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt, +// jlarmour +// Date: 1999-02-20 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock. +// +// Usage: +// #include <cyg/hal/hal_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> + +#include <cyg/infra/cyg_type.h> + +//--------------------------------------------------------------------------- +// SPARClite exception vectors. +// +// A note on nomenclature: +// +// SPARClite has traps: interrupts are traps, and so are exceptions. +// There are 255 of them in the hardware: this HAL's trampoline code decodes +// them into the 27 listed below as CYGNUM_HAL_VECTOR_xxx. +// They are handled uniformly in the trampoline code in the sense that +// each vector has a VSR which is called in the same way. +// Interrupts (vectors 1-15) have one VSR by default, exceptions (vectors +// 16-26) another. +// The interrupt VSR sets up a C stack and calls the corresponding ISR with +// the required arguments; this ABI is mandated by the kernel. +// The exception VSR sets up a C stack and calls the corresponding XSR +// (just an entry in the ISR[sic] table) with similar arguments, such that +// it (by default) can call the kernel's cyg_hal_deliver_exception(). +// +// So: +// CYGNUM_HAL_VSR_MAX/MIN/COUNT describe the number of VSR entries *and* +// the number of ISR (and associated data) entries (including those which +// are XSRs, just a special case of ISRs). +// CYGNUM_HAL_ISR_MAX/MIN/COUNT describe the number of interrupt sources +// and is used for bounds checking in kernel interrupt objects. +// CYGNUM_HAL_EXCEPTION_MAX/MIN/COUNT describe vector numbers which have +// by default the exception VSR and default XSR installed. + + +// These correspond to VSRs and the values are the ones to use for +// HAL_VSR_GET/SET + +#define CYGNUM_HAL_VECTOR_RESERVED_0 0 +#define CYGNUM_HAL_VECTOR_INTERRUPT_1 1 // NB: least important +#define CYGNUM_HAL_VECTOR_INTERRUPT_2 2 // (lowest priority) +#define CYGNUM_HAL_VECTOR_INTERRUPT_3 3 +#define CYGNUM_HAL_VECTOR_INTERRUPT_4 4 +#define CYGNUM_HAL_VECTOR_INTERRUPT_5 5 +#define CYGNUM_HAL_VECTOR_INTERRUPT_6 6 +#define CYGNUM_HAL_VECTOR_INTERRUPT_7 7 +#define CYGNUM_HAL_VECTOR_INTERRUPT_8 8 +#define CYGNUM_HAL_VECTOR_INTERRUPT_9 9 +#define CYGNUM_HAL_VECTOR_INTERRUPT_10 10 +#define CYGNUM_HAL_VECTOR_INTERRUPT_11 11 +#define CYGNUM_HAL_VECTOR_INTERRUPT_12 12 +#define CYGNUM_HAL_VECTOR_INTERRUPT_13 13 +#define CYGNUM_HAL_VECTOR_INTERRUPT_14 14 // (highest priority) +#define CYGNUM_HAL_VECTOR_INTERRUPT_15 15 // NB: most important (NMI) + +#define CYG_VECTOR_IS_INTERRUPT(v) (15 >= (v)) + +#define CYGNUM_HAL_VECTOR_USER_TRAP 16 // Ticc instructions +#define CYGNUM_HAL_VECTOR_FETCH_ABORT 17 // trap type 1 +#define CYGNUM_HAL_VECTOR_ILLEGAL_OP 18 // trap type 2 +#define CYGNUM_HAL_VECTOR_PRIV_OP 19 // tt 3: privileged op +#define CYGNUM_HAL_VECTOR_NOFPCP 20 // tt 4,36: FP or coproc +#define CYGNUM_HAL_VECTOR_RESERVED_1 21 // (not used) +#define CYGNUM_HAL_VECTOR_RESERVED_2 22 // (not used) +#define CYGNUM_HAL_VECTOR_UNALIGNED 23 // tt 7: unaligned memory access +#define CYGNUM_HAL_VECTOR_TT_EIGHT 24 // tt 8: not defined +#define CYGNUM_HAL_VECTOR_DATA_ABORT 25 // tt 9: read/write failed + +#define CYGNUM_HAL_VECTOR_OTHERS 26 // any others + +#define CYGNUM_HAL_VSR_MIN 0 +#define CYGNUM_HAL_VSR_MAX 26 +#define CYGNUM_HAL_VSR_COUNT 27 + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + +// Interrupt vectors. These are the values used with HAL_INTERRUPT_ATTACH() +// et al + +#define CYGNUM_HAL_INTERRUPT_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0 +#define CYGNUM_HAL_INTERRUPT_1 CYGNUM_HAL_VECTOR_INTERRUPT_1 +#define CYGNUM_HAL_INTERRUPT_2 CYGNUM_HAL_VECTOR_INTERRUPT_2 +#define CYGNUM_HAL_INTERRUPT_3 CYGNUM_HAL_VECTOR_INTERRUPT_3 +#define CYGNUM_HAL_INTERRUPT_4 CYGNUM_HAL_VECTOR_INTERRUPT_4 +#define CYGNUM_HAL_INTERRUPT_5 CYGNUM_HAL_VECTOR_INTERRUPT_5 +#define CYGNUM_HAL_INTERRUPT_6 CYGNUM_HAL_VECTOR_INTERRUPT_6 +#define CYGNUM_HAL_INTERRUPT_7 CYGNUM_HAL_VECTOR_INTERRUPT_7 +#define CYGNUM_HAL_INTERRUPT_8 CYGNUM_HAL_VECTOR_INTERRUPT_8 +#define CYGNUM_HAL_INTERRUPT_9 CYGNUM_HAL_VECTOR_INTERRUPT_9 +#define CYGNUM_HAL_INTERRUPT_10 CYGNUM_HAL_VECTOR_INTERRUPT_10 +#define CYGNUM_HAL_INTERRUPT_11 CYGNUM_HAL_VECTOR_INTERRUPT_11 +#define CYGNUM_HAL_INTERRUPT_12 CYGNUM_HAL_VECTOR_INTERRUPT_12 +#define CYGNUM_HAL_INTERRUPT_13 CYGNUM_HAL_VECTOR_INTERRUPT_13 +#define CYGNUM_HAL_INTERRUPT_14 CYGNUM_HAL_VECTOR_INTERRUPT_14 +#define CYGNUM_HAL_INTERRUPT_15 CYGNUM_HAL_VECTOR_INTERRUPT_15 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 15 +#define CYGNUM_HAL_ISR_COUNT 16 + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + +// Exception vectors. These are the values used when passed out to an +// external exception handler using cyg_hal_deliver_exception() +// They can also be used with HAL_INTERRUPT_ATTACH() et al to install +// different XSRs. + +#define CYGNUM_HAL_EXCEPTION_TRAP CYGNUM_HAL_VECTOR_USER_TRAP +#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_FETCH_ABORT +#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \ + CYGNUM_HAL_VECTOR_ILLEGAL_OP +#define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION \ + CYGNUM_HAL_VECTOR_PRIV_OP +#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_NOFPCP +#define CYGNUM_HAL_EXCEPTION_RESERVED1 CYGNUM_HAL_VECTOR_RESERVED1 +#define CYGNUM_HAL_EXCEPTION_RESERVED2 CYGNUM_HAL_VECTOR_RESERVED2 +#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ + CYGNUM_HAL_VECTOR_UNALIGNED +#define CYGNUM_HAL_EXCEPTION_TT_EIGHT CYGNUM_HAL_VECTOR_TT_EIGHT +#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DATA_ABORT +#define CYGNUM_HAL_EXCEPTION_OTHERS CYGNUM_HAL_VECTOR_OTHERS + + +#define CYGNUM_HAL_EXCEPTION_MIN 16 +#define CYGNUM_HAL_EXCEPTION_MAX (16 + 10) +#define CYGNUM_HAL_EXCEPTION_COUNT (1 + CYGNUM_HAL_EXCEPTION_MAX - \ + CYGNUM_HAL_EXCEPTION_MIN) + +//--------------------------------------------------------------------------- +// (Null) Translation from a wider space of interrupt sources: + +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_) + +//--------------------------------------------------------------------------- +// Routine to execute DSRs using separate interrupt stack + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + +externC void hal_interrupt_stack_call_pending_DSRs(void); +#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ + hal_interrupt_stack_call_pending_DSRs() + +// these are offered solely for stack usage testing +// if they are not defined, then there is no interrupt stack. +#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base +#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack +// use them to declare these extern however you want: +// extern char HAL_INTERRUPT_STACK_BASE[]; +// extern char HAL_INTERRUPT_STACK_TOP[]; +// is recommended +#endif + +//--------------------------------------------------------------------------- +// Static data used by HAL + +// VSR table +externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; + +// ISR + XSR tables - so VSR count. +externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_VSR_COUNT]; +externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_VSR_COUNT]; +externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_VSR_COUNT]; +// (interrupt_objects only used in the interrupt case _but_ the interrupt +// attach &co macros write it, so keep it full-sized) + +//--------------------------------------------------------------------------- +// Default ISRs for exception/interrupt handing. + +// note that these have the same ABI apart from the extra SP parameter +// for exceptions. + +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); +// return code from ISR is passed to interrupt_end() in the kernel. + +externC void cyg_hal_exception_handler(CYG_ADDRWORD vector, + CYG_ADDRWORD data, + CYG_ADDRWORD stackpointer); + +//--------------------------------------------------------------------------- +// Default VSRs for exception/interrupt handing. + +// note that these do not have a C ABI as such; they are *vector* service +// routines and are written in assembler. + +externC void hal_default_exception_vsr( void ); +externC void hal_default_interrupt_vsr( void ); + +//--------------------------------------------------------------------------- +// Interrupt state storage + +typedef cyg_uint32 CYG_INTERRUPT_STATE; + +//--------------------------------------------------------------------------- +// Interrupt control macros + +// THIS ONE IS NOT A STANDARD HAL ENTRY (HAL_DISABLE_TRAPS) +// (so should be unused externally) +#define HAL_DISABLE_TRAPS(_old_) \ + asm volatile ( \ + "rd %%psr, %0;" \ + "andn %0, 0x20, %%l7;" \ + "wr %%l7, %%psr;" \ + "nop; nop; nop" \ + : "=r"(_old_) \ + : \ + : "l7" \ + ); + +// THIS ONE IS NOT A STANDARD HAL ENTRY (HAL_QUERY_TRAPS) +// (so should be unused externally) +#define HAL_QUERY_TRAPS(_old_) \ + asm volatile ( \ + "rd %%psr, %%l7;" \ + "and %%l7, 0x020, %0" \ + : "=r"(_old_) \ + : \ + : "l7" \ + ); + +#define HAL_DISABLE_INTERRUPTS(_old_) \ + asm volatile ( \ + "rd %%psr, %0;" \ + "or %0, 0xf00, %%l7;" \ + "wr %%l7, %%psr;" \ + "nop; nop; nop" \ + : "=r"(_old_) \ + : \ + : "l7" \ + ); + +#define HAL_ENABLE_INTERRUPTS() \ + asm volatile ( \ + "rd %%psr, %%l7;" \ + "andn %%l7, 0xf00, %%l7;" \ + "or %%l7, 0x020, %%l7;" \ + "wr %%l7, %%psr;" \ + "nop; nop; nop" \ + : \ + : \ + : "l7" \ + ); + +#define HAL_RESTORE_INTERRUPTS(_old_) \ + asm volatile ( \ + "rd %%psr, %%l7;" \ + "andn %%l7, 0xf20, %%l7;" \ + "and %0 , 0xf20, %%l6;" \ + "wr %%l6, %%l7, %%psr;" \ + "nop; nop; nop" \ + : \ + : "r"(_old_) \ + : "l6","l7" \ + ); + +#define HAL_QUERY_INTERRUPTS(_old_) \ + asm volatile ( \ + "rd %%psr, %%l7;" \ + "and %%l7, 0xf00, %%l7;" \ + "xor %%l7, 0xf00, %0" \ + : "=r"(_old_) \ + : \ + : "l7" \ + ); + + +//--------------------------------------------------------------------------- +// Interrupt and VSR attachment macros + +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if( (CYG_ADDRESS)hal_default_isr == hal_interrupt_handlers[_vector_] || \ + (CYG_ADDRESS)cyg_hal_exception_handler == \ + hal_interrupt_handlers[_vector_] ) { \ + (_state_) = 0; \ + } else { \ + (_state_) = 1; \ + } \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ + CYG_MACRO_START \ + if( (CYG_ADDRESS)hal_default_isr == hal_interrupt_handlers[_vector_] ||\ + (CYG_ADDRESS)cyg_hal_exception_handler == \ + hal_interrupt_handlers[_vector_] ) \ + { \ + hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \ + hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \ + hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \ + } \ +CYG_MACRO_END + +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) CYG_MACRO_START \ + if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \ + { \ + hal_interrupt_handlers[_vector_] = \ + (CYG_VECTOR_IS_INTERRUPT( _vector_ ) \ + ? (CYG_ADDRESS)hal_default_isr \ + : (CYG_ADDRESS)cyg_hal_exception_handler); \ + hal_interrupt_data[_vector_] = 0; \ + hal_interrupt_objects[_vector_] = 0; \ + } \ +CYG_MACRO_END + +#define HAL_VSR_GET( _vector_, _pvsr_ ) \ + *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_]; + + +#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \ + if( _poldvsr_ != NULL ) \ + *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \ + hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ +CYG_MACRO_END + +// This is an ugly name, but what it means is: grab the VSR back to eCos +// internal handling, or if you like, the default handler. But if +// cooperating with GDB and CygMon, the default behaviour is to pass most +// exceptions to CygMon. This macro undoes that so that eCos handles the +// exception. So use it with care. + +#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \ + if( _poldvsr_ != NULL ) \ + *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \ + hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \ + ? (CYG_ADDRESS)hal_default_interrupt_vsr \ + : (CYG_ADDRESS)hal_default_exception_vsr ); \ +CYG_MACRO_END + + + +//--------------------------------------------------------------------------- + +// Which PIC (if any) is available is dependent on the board. +// This sets up that stuff: + +#include <cyg/hal/hal_xpic.h> + +// Ditto the clock(s) +// This defines all the clock macros the kernel requires: + +#include <cyg/hal/hal_clock.h> + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_INTR_H +// End of hal_intr.h diff --git a/ecos/packages/hal/sparclite/arch/current/include/hal_io.h b/ecos/packages/hal/sparclite/arch/current/include/hal_io.h new file mode 100644 index 0000000..20e806a --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/include/hal_io.h @@ -0,0 +1,186 @@ +#ifndef CYGONCE_HAL_IO_H +#define CYGONCE_HAL_IO_H + +//============================================================================= +// +// hal_io.h +// +// HAL device IO register support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, hmt +// Contributors: nickg, hmt +// Date: 1998-02-17 +// Purpose: Define IO register support +// Description: The macros defined here provide the HAL APIs for handling +// device IO control registers. +// +// Usage: +// #include <cyg/hal/hal_io.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Enforce in-order IO for all HAL reads/writes using this macro. +#define HAL_IO_BARRIER() \ + asm volatile ( "" : : : "memory" ) + +//----------------------------------------------------------------------------- +// IO Register address. +// This type is for recording the address of an IO register. + +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; + +//----------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + +#define HAL_READ_UINT8( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_BYTE *)(_register_))); \ + HAL_IO_BARRIER (); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \ + HAL_IO_BARRIER (); \ + CYG_MACRO_END + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ + HAL_IO_BARRIER (); \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ + HAL_IO_BARRIER (); \ + } \ + CYG_MACRO_END + + +//----------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + +#define HAL_READ_UINT16( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_WORD16 *)(_register_))); \ + HAL_IO_BARRIER (); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \ + HAL_IO_BARRIER (); \ + CYG_MACRO_END + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ + HAL_IO_BARRIER (); \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ + HAL_IO_BARRIER (); \ + } \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_WORD32 *)(_register_))); \ + HAL_IO_BARRIER (); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \ + HAL_IO_BARRIER (); \ + CYG_MACRO_END + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ + HAL_IO_BARRIER (); \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ + HAL_IO_BARRIER (); \ + } \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- + +#ifndef CYGPKG_HAL_SPARCLITE_SIM +#include <cyg/hal/hal_hwio.h> +#endif // Not the SPARClite simulator + +#endif // ifndef CYGONCE_HAL_IO_H +// End of hal_io.h diff --git a/ecos/packages/hal/sparclite/arch/current/include/vectors.h b/ecos/packages/hal/sparclite/arch/current/include/vectors.h new file mode 100644 index 0000000..5e339bb --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/include/vectors.h @@ -0,0 +1,117 @@ +#ifndef CYGONCE_HAL_VECTORS_H +#define CYGONCE_HAL_VECTORS_H + +//============================================================================= +// +// vectors.h +// +// SPARClite Architecture specific vector numbers &c +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt +// Date: 1998-12-10 +// Purpose: Define architecture abstractions and some shared info; +// this file is included by assembler files as well as C/C++. +// Usage: #include <cyg/hal/vectors.h> + +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#define __WINSIZE 8 + +#if __WINSIZE <= 8 +# define __WINBITS 7 +#else +# error __WINSIZE window size probably not supported +#endif + +// These should be generic to all SPARCs: + +#define __WINBITS_MAXIMAL 0x1f + +#define __WIN_INIT (__WINSIZE - 1) +#define __WIM_INIT (1 << __WIN_INIT) + +// ------------------------------------------------------------------------ + +#define TRAP_WUNDER 6 // Window Underflow trap number +#define TRAP_WOVER 5 // Window Overflow trap number + +#define TRAP_INTR_MIN 17 // smallest interrupt trap number +#define TRAP_INTR_MAX 31 // largest interrupt trap number + +#define TT_MASK 0xff0 // trap type mask from tbr +#define TT_SHL 4 // shift to get a tbr value + +// Alternatively, detect an interrupt by testing tbr for being in the range +// 16-31 by masking &c: +#define TT_IS_INTR_MASK 0xf00 +#define TT_IS_INTR_VALUE 0x100 + +#if TT_IS_INTR_VALUE != ((TRAP_INTR_MIN << TT_SHL) & TT_IS_INTR_MASK) +#error "Bad *_INTR_* symbol definition (1)" +#endif + +#if TT_IS_INTR_VALUE != ((TRAP_INTR_MAX << TT_SHL) & TT_IS_INTR_MASK) +#error "Bad *_INTR_* symbol definition (2)" +#endif + +#if TT_IS_INTR_VALUE != (((TRAP_INTR_MIN+1) << TT_SHL) & TT_IS_INTR_MASK) +#error "Bad *_INTR_* symbol definition (3)" +#endif + +#if TT_IS_INTR_VALUE != (((TRAP_INTR_MAX-1) << TT_SHL) & TT_IS_INTR_MASK) +#error "Bad *_INTR_* symbol definition (4)" +#endif + + + +//#define SCHED_LOCK_MANGLED_NAME _18Cyg_Scheduler_Base.sched_lock +#define SCHED_LOCK_MANGLED_NAME cyg_scheduler_sched_lock + + + +#define SAVE_REGS_SIZE (4 * 32) // 32 words of 4 bytes each + + + + +#endif // CYGONCE_HAL_VECTORS_H +// EOF vectors.h diff --git a/ecos/packages/hal/sparclite/arch/current/src/context.S b/ecos/packages/hal/sparclite/arch/current/src/context.S new file mode 100644 index 0000000..d5a7cc1 --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/src/context.S @@ -0,0 +1,400 @@ +/*============================================================================= +// +// context.S +// +// SPARClite context switch code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1998-12-15 +// Purpose: SPARClite context switch code +// Description: This file contains implementations of the thread context +// switch routines. It also contains the longjmp() and setjmp() +// routines. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/hal/vectors.h> + +#define DELAYS_AFTER_WRPSR_SAME_WINDOW +#define DELAYS_AFTER_WRWIM + + .text + +! ------------------------------------------------------------------------------ +! hal_thread_switch_context +! Switch thread contexts +! %o0 = address of sp of next thread to execute +! %o1 = address of sp save location of current thread + + .global hal_thread_switch_context +hal_thread_switch_context: + + ! First take the stack down to make room for the saved register + ! state, including a window save area at the base. Leave the + ! current window save area undisturbed. It is unused within the + ! save but will become current again when we continue in this + ! context. This lets us do this whole piece of work without + ! diabling interrupts for too long, since, for example, we can + ! lower the stack atomically with one instruction: + sub %sp, SAVE_REGS_SIZE, %sp + st %sp, [ %o1 ] ! return SP for this thread + + std %l0, [%sp + 0 * 4] ! save L & I registers + std %l2, [%sp + 2 * 4] + std %l4, [%sp + 4 * 4] + std %l6, [%sp + 6 * 4] + + std %i0, [%sp + 8 * 4] + std %i2, [%sp + 10 * 4] + std %i4, [%sp + 12 * 4] + std %i6, [%sp + 14 * 4] + +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + st %o7, [%sp + 31 * 4] ! save only the return address + ! and no need to preserve %o0 even though it is restored +#else // save a maximal context + st %g1, [%sp + 17 * 4] ! save G & O registers + std %g2, [%sp + 18 * 4] + std %g4, [%sp + 20 * 4] + std %g6, [%sp + 22 * 4] + + std %o0, [%sp + 24 * 4] + std %o2, [%sp + 26 * 4] + std %o4, [%sp + 28 * 4] + std %o6, [%sp + 30 * 4] +#endif // !CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + ! and save the CWP in %g0 save place + rd %psr, %g7 + st %g7, [%sp + 16 * 4] + + ! Now load the destination thread by dropping through + ! to hal_thread_load_context + +! ------------------------------------------------------------------------------ +! hal_thread_load_context +! Load thread context +! %o0 = address of sp of next thread to execute +! Note that this function is also the second half of hal_thread_switch_context +! and is simply dropped into from it. + + .global hal_thread_load_context +hal_thread_load_context: + + ! Here, we are a leaf routine but with slightly odd properties. + ! The stack is still the callers at this point but the register + ! set is up for grabs. So we can use globals: + + ld [ %o0 ], %g7 ! Get the next saved SP + + ! DISABLE INTERRUPTS *ONLY* NOT TRAPS + rd %psr, %g6 + or %g6, 0xfe0, %g5 ! PIL up to 15 leave traps enabled + wr %g5, %psr + + ! force out all our callers register sets onto the stack + ! if necessary: the system will handily take care of this for + ! us as follows: + save %sp, -16 * 4, %sp ! need all these to preserve + save %sp, -16 * 4, %sp ! the linked list property... + save %sp, -16 * 4, %sp + save %sp, -16 * 4, %sp +#if 6 < __WINSIZE + save %sp, -16 * 4, %sp +#if 7 < __WINSIZE + save %sp, -16 * 4, %sp +#endif +#endif + ! Fewer saves if fewer register windows. For 8 register windows, + ! six of these is correct; a seventh would force out the current + ! set that was already saved manually above. Note that minimal + ! space is allowed on stack for locals and ins in case this + ! sequence itself gets interrupted and recurses too deep. + + ! now select the new window with traps disabled... + + ! get the new PSR and CWP that we will ultimately restore + ! from the %g0 save place... + ld [%g7 + 16 * 4], %g6 ! %g7 holds the new stack pointer + andn %g6, 0x20, %g5 ! clear ET into %g5 + and %g6, __WINBITS, %g4 ! CWP bits only in %g4 + + ! calculate a new WIM... + add %g4, 1, %g3 ! required invalid window number +#if 8 == __WINSIZE + and %g3, __WINBITS, %g3 ! modulo 8 +#else // expect 5 or 6 or 7 windows + cmp %g3, __WINSIZE + bge,a 567f ! taken: do delay slot, handle overflow + mov 0, %g3 ! only if .ge. above +567: +#endif + mov 1, %g2 + sll %g2, %g3, %g2 ! converted to a mask for the WIM + + ! DISABLE INTERRUPTS (TRAPS) + wr %g5, %psr ! set CWP to new window, disable traps + wr %g2, %wim ! and WIM to new value + nop + nop + nop + + ! Must do this atomically so that the registers match the stack. + ! After locals and ins are loaded, we are conformant to the PCS + ! so can re-enable interrupts. + mov %g7, %sp ! target sp in situ (%sp = %o6) + + ldd [%sp + 0 * 4], %l0 ! restore L & I registers + ldd [%sp + 2 * 4], %l2 + ldd [%sp + 4 * 4], %l4 + ldd [%sp + 6 * 4], %l6 + + ldd [%sp + 8 * 4], %i0 + ldd [%sp + 10 * 4], %i2 + ldd [%sp + 12 * 4], %i4 + ldd [%sp + 14 * 4], %i6 + + ! RESTORE INTERRUPTS to saved state + wr %g6, %psr ! set new CWP and old ET and PIL + nop + nop + nop + + ! now load the rest of the context; we can be interrupted here + ! (if the saved context was a voluntary yield or threadstart) + ! but that is OK, other state will be preserved in that case... + +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + ld [%sp + 24 * 4], %o0 ! must load the initial argument +#else // restore a maximal context + ld [%sp + 17 * 4], %g1 + ldd [%sp + 18 * 4], %g2 + ldd [%sp + 20 * 4], %g4 + ldd [%sp + 22 * 4], %g6 + + ldd [%sp + 24 * 4], %o0 + ldd [%sp + 26 * 4], %o2 + ldd [%sp + 28 * 4], %o4 +#endif // !CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + ! %o6 = %sp, already set up + ld [%sp + 31 * 4], %o7 ! "return" address + + retl + add %sp, SAVE_REGS_SIZE, %sp ! and set the stack back + ! to its entrant value + +! ------------------------------------------------------------------------------ +! HAL longjmp, setjmp implementations + +!FUNC_START(hal_setjmp) + .global hal_setjmp +hal_setjmp: + ! Treat this as a leaf routine, may as well. + ! %o0 is the address of the buffer. + + std %l0, [%o0 + 0 * 4] ! save L & I registers + std %l2, [%o0 + 2 * 4] + std %l4, [%o0 + 4 * 4] + std %l6, [%o0 + 6 * 4] + + std %i0, [%o0 + 8 * 4] + std %i2, [%o0 + 10 * 4] + std %i4, [%o0 + 12 * 4] + std %i6, [%o0 + 14 * 4] + +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + std %o6, [%o0 + 30 * 4] ! just save %sp and return address +#else // save a maximal context + st %g1, [%o0 + 17 * 4] ! save G & O registers + std %g2, [%o0 + 18 * 4] + std %g4, [%o0 + 20 * 4] + std %g6, [%o0 + 22 * 4] + + std %o0, [%o0 + 24 * 4] + std %o2, [%o0 + 26 * 4] + std %o4, [%o0 + 28 * 4] + std %o6, [%o0 + 30 * 4] +#endif // !CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + + ! and save the CWP in %g0 save place + rd %psr, %g7 + st %g7, [%o0 + 16 * 4] + + ! DISABLE INTERRUPTS *ONLY* NOT TRAPS + or %g7, 0xfe0, %g6 ! PIL up to 15 leave traps enabled + wr %g6, %psr + + ! force out all our callers register sets onto the stack + ! if necessary: the system will handily take care of this for + ! us as follows: + save %sp, -16 * 4, %sp ! need all these to preserve + save %sp, -16 * 4, %sp ! the linked list property... + save %sp, -16 * 4, %sp + save %sp, -16 * 4, %sp +#if 6 < __WINSIZE + save %sp, -16 * 4, %sp +#if 7 < __WINSIZE + save %sp, -16 * 4, %sp +#endif +#endif + ! Fewer saves if fewer register windows. For 8 register windows, + ! six of these is correct; a seventh would force out the current + ! set that was already saved manually above. Note that minimal + ! space is allowed on stack for locals and ins in case this + ! sequence itself gets interrupted and recurses too deep. + + ! (after all, we are about to call deeper not shallower, otherwise + ! using setjmp is inappropriate) + + ! ENABLE INTERRUPTS + wr %g7, %psr ! set CWP back to as-was + nop + nop + nop + +#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + ldd [%o0 + 22 * 4], %g6 ! preserve %g7 and %g6 +#endif + + retl ! ret and return zero to indicate + mov 0, %o0 ! not longjumped-to + +! hal_longjmp loads state from arg0 and returns arg1 +!FUNC_START(hal_longjmp) + .global hal_longjmp +hal_longjmp: + ! This is kind of a leaf routine, it returns elsewhere + ! %o0 is the address of the buffer. + ! %o1 is the value to return in %o0 (since we are a leaf) + + mov %o0, %g7 ! keep the pointer handy + mov %o1, %g1 ! and the return value + ! now select the new window with traps disabled... + rd %psr, %g6 + ! preserve ET, clear CWP + andn %g6, __WINBITS_MAXIMAL, %g6 + andn %g6, 0x20, %g5 ! clear ET also into %g5 + + ! get new CWP from %g0 save place... + ld [%g7 + 16 * 4], %g4 ! %g7 holds the new stack pointer + and %g4, __WINBITS, %g4 ! preserve CWP bits + + ! calculate a new WIM... + add %g4, 1, %g3 ! required invalid window number +#if 8 == __WINSIZE + and %g3, __WINBITS, %g3 ! modulo 8 +#else // expect 5 or 6 or 7 windows + cmp %g3, __WINSIZE + bge,a 567f ! taken: do delay slot, handle overflow + mov 0, %g3 ! only if .ge. above +567: +#endif + mov 1, %g2 + sll %g2, %g3, %g2 ! converted to a mask for the WIM + + ! DISABLE INTERRUPTS + wr %g5, %g4, %psr ! set CWP to new window, disable traps + wr %g2, %wim ! and WIM to new value + nop + nop + nop + + ! Must do this atomically so that the registers match the stack. + ! After locals and ins are loaded, we are conformant to the PCS + ! so can re-enable interrupts. + + ldd [%g7 + 0 * 4], %l0 ! restore L & I registers + ldd [%g7 + 2 * 4], %l2 + ldd [%g7 + 4 * 4], %l4 + ldd [%g7 + 6 * 4], %l6 + + ldd [%g7 + 8 * 4], %i0 + ldd [%g7 + 10 * 4], %i2 + ldd [%g7 + 12 * 4], %i4 + ldd [%g7 + 14 * 4], %i6 + + ld [%g7 + 30 * 4], %sp ! %o6 = %sp, set up now so as to conform + ! to PCS and so be interruptible + ! ENABLE INTERRUPTS + wr %g6, %g4, %psr ! set new CWP and old ET + nop + nop + nop + + ! now load the rest of the context; we can be interrupted here, but + ! that is OK, other state will be preserved in that case... +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + ! we are not preserving globals... + ! %o6 = %sp, already set up + ld [%g7 + 31 * 4], %o7 ! "return" address + retl ! %g1 still holds the return value + mov %g1, %o0 + +#else // load a maximal context + mov %g7, %o0 ! original pointer was in %o0 anyway + + ldd [%o0 + 18 * 4], %g2 + ldd [%o0 + 20 * 4], %g4 + ldd [%o0 + 22 * 4], %g6 + + ld [%o0 + 25 * 4], %o1 ! %o0 = original pointer + ldd [%o0 + 26 * 4], %o2 + ldd [%o0 + 28 * 4], %o4 + ! %o6 = %sp, already set up + ld [%o0 + 31 * 4], %o7 ! "return" address + + ! %g1 still holds the return value; want to get this into %o0 + ! and restore %g1 from the saved state; %o0 is the state pointer: + ! g1 = R, o0 = P + xor %o0, %g1, %g1 ! g1 = R^P, o0 = P + xor %o0, %g1, %o0 ! g1 = R^P, o0 = R + xor %o0, %g1, %g1 ! g1 = P, o0 = R all done + + retl + ld [%g1 + 17 * 4], %g1 ! and finally restore %g1 +#endif // !CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + +! ------------------------------------------------------------------------------ +! end of context.S + + + diff --git a/ecos/packages/hal/sparclite/arch/current/src/hal_boot.c b/ecos/packages/hal/sparclite/arch/current/src/hal_boot.c new file mode 100644 index 0000000..5873afe --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/src/hal_boot.c @@ -0,0 +1,173 @@ +//========================================================================== +// +// hal_boot.c +// +// SPARClite Architecture specific interrupt dispatch tables +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1998-12-10 +// Purpose: Interrupt handler tables for SPARClite. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +/*------------------------------------------------------------------------*/ +/* calling this is our raison d'etre: */ +extern void cyg_start( void ); + +/*------------------------------------------------------------------------*/ +/* data copy and bss zero functions */ + +typedef void (CYG_ROM_ADDRESS)(void); + +#ifdef CYG_HAL_STARTUP_ROM +void hal_copy_data(void) +{ + extern char __ram_data_start; + extern char __ram_data_end; + extern CYG_ROM_ADDRESS __rom_data_start; + long *p = (long *)&__ram_data_start; + long *q = (long *)&__rom_data_start; + + while( p <= (long *)&__ram_data_end ) + *p++ = *q++; +} +#endif + +void hal_zero_bss(void) +{ + extern CYG_ROM_ADDRESS __bss_start; + extern CYG_ROM_ADDRESS __bss_end; + + register long long zero = 0; + register long long *end = (long long *)&__bss_end; + register long long *p = (long long *)&__bss_start; + + while( p <= end ) + *p++ = zero; +} + +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG +cyg_bool cyg_hal_stop_constructors; +#endif + +void +cyg_hal_invoke_constructors (void) +{ + typedef void (*pfunc) (void); + extern pfunc __CTOR_LIST__[]; + extern pfunc __CTOR_END__[]; + +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + static pfunc *p = &__CTOR_END__[-1]; + + cyg_hal_stop_constructors = 0; + for (; p >= __CTOR_LIST__; p--) { + (*p) (); + if (cyg_hal_stop_constructors) { + p--; + break; + } + } +#else + pfunc *p; + + for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) + (*p) (); +#endif +} + +// Override any __gccmain the compiler might generate. We don't want +// constructors to be called twice. +void __gccmain(void) {} + +/*------------------------------------------------------------------------*/ +/* CYG_HAL_START - pre-main-entrypoint */ + +#ifdef CYGPKG_HAL_SPARCLITE_SLEB +#define SLEB_LED (*(volatile char *)(0x02000003)) +#define LED( _x_ ) SLEB_LED = (char)(0xff & ~(_x_)) +#else +#define LED( _x_ ) CYG_EMPTY_STATEMENT +#endif + +extern void hal_board_prestart( void ); +extern void hal_board_poststart( void ); + +// This is called with traps enabled, but interrupts masked out: +// Be sure to enable them in hal_board_poststart() at the latest. + +void cyg_hal_start( void ) +{ + /* Board specific prestart that's best done in C */ + hal_board_prestart(); + + LED( 0xd0 ); + +#ifdef CYG_HAL_STARTUP_ROM + /* Copy data from ROM to RAM */ + hal_copy_data(); +#endif + + LED( 0xd4 ); + + /* Zero BSS */ + hal_zero_bss(); + + LED( 0xd8 ); + + /* Call constructors */ + cyg_hal_invoke_constructors(); + + LED( 0xdc ); + + /* Board specific late startup that's best done in C */ + hal_board_poststart(); + + LED( 0xf8 ); + + /* Call cyg_start */ + cyg_start(); /* does not return */ +} + +// EOF hal_boot.c diff --git a/ecos/packages/hal/sparclite/arch/current/src/hal_intr.c b/ecos/packages/hal/sparclite/arch/current/src/hal_intr.c new file mode 100644 index 0000000..16c4883 --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/src/hal_intr.c @@ -0,0 +1,161 @@ +//========================================================================== +// +// hal_intr.c +// +// SPARClite Architecture specific interrupt dispatch tables +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-02-20 +// Purpose: Interrupt handler tables for SPARClite. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arch.h> + +#include <cyg/infra/cyg_ass.h> // for CYG_FAIL() below + +// ------------------------------------------------------------------------ +// First level C default interrupt handler. + +//static int count = 0; + +cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + return 0; // 0x1def0000 + vector + (count += 0x0100); +} + +// ------------------------------------------------------------------------ +// First level C exception handler. + +externC void __handle_exception (void); + +externC HAL_SavedRegisters *_hal_registers; + +void cyg_hal_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data, + CYG_ADDRWORD stackpointer ) +{ +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + // Set the pointer to the registers of the current exception + // context. At entry the GDB stub will expand the + // HAL_SavedRegisters structure into a (bigger) register array. + _hal_registers = (HAL_SavedRegisters *)stackpointer; + + __handle_exception(); + +#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + defined(CYGPKG_HAL_EXCEPTIONS) + // We should decode the vector and pass a more appropriate + // value as the second argument. For now we simply pass a + // pointer to the saved registers. We should also divert + // breakpoint and other debug vectors into the debug stubs. + + cyg_hal_deliver_exception( vector, stackpointer ); + +#else + CYG_FAIL("Exception!!!"); +#endif + return; +} + +// ISR tables +volatile +CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_VSR_COUNT] = { + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, + (CYG_ADDRESS)hal_default_isr, /* 16 of these */ + + (CYG_ADDRESS)cyg_hal_exception_handler, + (CYG_ADDRESS)cyg_hal_exception_handler, + (CYG_ADDRESS)cyg_hal_exception_handler, + (CYG_ADDRESS)cyg_hal_exception_handler, + (CYG_ADDRESS)cyg_hal_exception_handler, + + (CYG_ADDRESS)cyg_hal_exception_handler, + (CYG_ADDRESS)cyg_hal_exception_handler, + (CYG_ADDRESS)cyg_hal_exception_handler, + (CYG_ADDRESS)cyg_hal_exception_handler, + (CYG_ADDRESS)cyg_hal_exception_handler, + + (CYG_ADDRESS)cyg_hal_exception_handler, /* 11 of these */ +}; + +volatile +CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_VSR_COUNT] = { + 0x11da1a00, 0x11da1a01, 0x11da1a02, 0x11da1a03, + 0x11da1a04, 0x11da1a05, 0x11da1a06, 0x11da1a07, + 0x11da1a08, 0x11da1a09, 0x11da1a0a, 0x11da1a0b, + 0x11da1a0c, 0x11da1a0d, 0x11da1a0e, 0x11da1a0f, + 0xeeda1a00, 0xeeda1a01, 0xeeda1a02, 0xeeda1a03, 0xeeda1a04, + 0xeeda1a05, 0xeeda1a06, 0xeeda1a07, 0xeeda1a08, 0xeeda1a09, + 0xeeda1a0A +}; + +volatile +CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_VSR_COUNT] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, +}; + +// EOF hal_intr.c diff --git a/ecos/packages/hal/sparclite/arch/current/src/icontext.c b/ecos/packages/hal/sparclite/arch/current/src/icontext.c new file mode 100644 index 0000000..76cba75 --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/src/icontext.c @@ -0,0 +1,497 @@ +/*============================================================================= +// +// icontext.c +// +// SPARClite HAL context init function +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1998-12-14 +// Purpose: HAL context initialization function +// Description: Initialize a HAL context for SPARClite; this is in C and out +// of line because there is too much of it for a simple macro. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_arch.h> // HAL header + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/vectors.h> // SAVE_REGS_SIZE, __WINSIZE, ... + +/*---------------------------------------------------------------------------*/ + +/* We lay out the stack in the manner that the PCS demands: + * frame pointer -----> [top of stack] + * Argument spill area (6 words) + * Return Arg pointer + * Initial saved register window (i[8], l[8]) + * for use by program when it starts + * [rest of] saved register object (various) + * stack pointer -----> saved register window (i[8], l[8]) + * to allow us to be interrupted. + * + * ie. frame pointer -> + * struct HAL_FrameStructure + * stack pointer -> struct HAL_SavedRegisters + * + * and when the context "resumes" sp is incremented by 40 * 4, the size of + * a _struct HAL_SavedRegisters_ which points it at the extant but unused + * _struct HAL_FrameStructure_ as the PCS requires. The frame pointer is + * left pointing off the top of stack. + * + * + * Thus the stack is the same if created from an already executing context: + * + * frame pointer -----> + * [temporaries and locals] + * [more arguments] + * Argument spill area (6 words) + * Return Arg pointer + * [sp at entry]------> Previous saved register window (i[8], l[8]) + * for use by program when it starts + * [rest of] saved register object (various) + * stack pointer -----> saved register window (i[8], l[8]) + * to allow us to be interrupted. + */ + +CYG_ADDRESS +hal_thread_init_context( CYG_WORD sparg, + CYG_WORD thread, + CYG_WORD entry, + CYG_WORD id ) +{ + register CYG_WORD fp = sparg; + register CYG_WORD sp = 0; + register HAL_SavedRegisters *regs; + register HAL_FrameStructure *frame; + int i; + + if ( 0 == (id & 0xffff0000) ) + id <<= 16; + + fp &= ~15; // round down to double alignment + + frame = (HAL_FrameStructure *)( + fp - sizeof( HAL_FrameStructure ) ); + + regs = (HAL_SavedRegisters *)( + ((CYG_WORD)frame) - sizeof(HAL_SavedRegisters) ); + + sp = (CYG_WORD)regs; + + for ( i = 0; i < 6; i++ ) { + frame->spill_args[i] = id | 0xa0 | i; + } + frame->composite_return_ptr = 0; + + for ( i = 0; i < 8; i++ ) { + frame->li.i[i] = id | ( 56 + i ); + frame->li.l[i] = id | ( 48 + i ); + regs ->li.i[i] = id | ( 24 + i ); + regs ->li.l[i] = id | ( 16 + i ); + regs ->o[i] = id | ( 8 + i ); + regs ->g[i] = id | ( i ); + } + + // first terminate the linked list on the stack in the initial + // (already saved) register window: + frame->li.i[6] = regs->li.i[6] = (cyg_uint32)fp; // frame pointer + frame->li.i[7] = regs->li.i[7] = (cyg_uint32)0; // no ret addr here + + // and set up other saved regs as if called from just before + // the entry point: + regs->o[7] = (entry - 8); + regs->o[6] = sp; + + // this is the argument that the entry point is called with + regs->o[0] = thread; + + // this is the initial CWP and interrupt state; CWP is quite arbitrary + // really, the WIM is set up accordingly in hal_thread_load_context(). + + regs->g[0] = 0x0e0 + __WIN_INIT; // PIL zero, ET, S, PS and CWP set. + + return (CYG_ADDRESS)sp; +} + +// --------------------------------------------------------------------------- + +//#define THREAD_DEBUG_SERIAL_VERBOSE + +#ifdef THREAD_DEBUG_SERIAL_VERBOSE // NOT INCLUDED + +// This is unpleasant to try to debug, because these routines are called +// WHEN THE PROGRAM IS NOT RUNNING from the CygMon's GDB stubs - so you +// can't use any normal output: these little routines use the serial +// line directly, so are best used when debugging via Ethernet, so you +// just have a separate output stream to read. Nasty... + +#include <cyg/hal/hal_diag.h> + +#undef HAL_DIAG_WRITE_CHAR +#define HAL_DIAG_WRITE_CHAR(_c_) CYG_MACRO_START \ + SLEB_LED = (_c_); \ + HAL_DIAG_WRITE_CHAR_DIRECT( _c_ ); \ +CYG_MACRO_END + +static void swritec( char c ) +{ + HAL_DIAG_WRITE_CHAR( c ); +} + +static void swrites( char *s ) +{ + char c; + while ( 0 != (c = *s++) ) + HAL_DIAG_WRITE_CHAR( c ); +} + +static void swritex( cyg_uint32 x ) +{ + int i; + swrites( "0x" ); + for ( i = 28; i >= 0; i-= 4 ) { + char c = "0123456789abcdef"[ 0xf & (x >> i) ]; + HAL_DIAG_WRITE_CHAR( c ); + } +} + +#define newline() swrites( "\n\r" ) + +static void x8( char *s, unsigned long *xp ) +{ + int i; + for ( i = 0; i < 8; i++ ) { + swrites( s ); + swritec( '0' + i ); + swrites( " = " ); + swritex( xp[i] ); + if ( 3 == (i & 3) ) + newline(); + else + swrites( " " ); + } +} + +#endif // THREAD_DEBUG_SERIAL_VERBOSE ... NOT INCLUDED + +// --------------------------------------------------------------------------- +// Routines in icontext.c used here because they're quite large for +// the SPARClite (note param order); these are used in talking to GDB. + +enum regnames {G0 = 0, G1, G2, G3, G4, G5, G6, G7, + O0, O1, O2, O3, O4, O5, SP, O7, + L0, L1, L2, L3, L4, L5, L6, L7, + I0, I1, I2, I3, I4, I5, FP, I7, + + F0, F1, F2, F3, F4, F5, F6, F7, + F8, F9, F10, F11, F12, F13, F14, F15, + F16, F17, F18, F19, F20, F21, F22, F23, + F24, F25, F26, F27, F28, F29, F30, F31, + Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR}; + +typedef unsigned long target_register_t; + +void +cyg_hal_sparc_get_gdb_regs( void *gdb_regset, + HAL_SavedRegisters *eCos_regset ) +{ + target_register_t *gdb = (target_register_t *)gdb_regset; + int reg; + cyg_uint32 scratch = 0; + cyg_uint32 *sptrap; + HAL_SavedWindow *trapli, *ctxli; + + if ( 0 == eCos_regset->g[0] || + 0xc0 == (0xe0 & eCos_regset->g[0]) ) { + // Then it's an interrupt stack saved state: + // (either minimal, or a saved PSR with traps disabled) + // The saved register set is pretty minimal, so we have to grub + // around in the stack to find out some truth... + sptrap = (cyg_uint32 *)eCos_regset; // point to the IL save area for + sptrap -= 24; // the trap handler, for PC, NPC + trapli = (HAL_SavedWindow *)sptrap; // Get at those regs + + ctxli = (HAL_SavedWindow *)(trapli->i[6]); // (the frame pointer) + // and get at the interruptee's regs + + // Pick up interruptee's registers from all over the stack: + for ( reg = 0; reg < 8 ; reg++ ) { + gdb[ G0 + reg ] = eCos_regset->g[reg]; + gdb[ O0 + reg ] = trapli->i[reg]; + gdb[ L0 + reg ] = ctxli->l[reg]; + gdb[ I0 + reg ] = ctxli->i[reg]; + } + + // Clear out G0 which is always 0 (but abused in eCos_regset) + // and the FP regs which we do not have: + gdb[ G0 ] = 0; + for ( reg = F0; reg <= F31; reg++ ) + gdb[ reg ] = 0; + + // In the save context _of the trap handler_ registers are as follows: + // %l0 = psr (with this CWP/window-level in it) + // %l1 = pc + // %l2 = npc + // %l3 = vector number (1-15 for interrupts) + // %l4 = Y register preserved + gdb[ Y ] = trapli->l[4]; + + scratch = trapli->l[0]; // the PSR in the trap handler +#if 8 == __WINSIZE + scratch++; // back to interupted thread's window + scratch &=~ 0x38; // clear ET and any __WINSIZE overflow + gdb[ PSR ] = scratch; + gdb[ WIM ] = 1 << ((__WINBITS & (1 + scratch))); +#else // 6 or 7 windows only + reg = (int)(scratch & __WINBITS); + scratch &=~ (__WINBITS_MAXIMAL | 0x20); // clear ET and CWP + if ( __WINSIZE <= ++reg ) reg = 0; // back to intr'd window + gdb[ PSR ] = scratch | reg; + if ( __WINSIZE <= ++reg ) reg = 0; // good index for WIM + gdb[ WIM ] = 1 << reg; +#endif // __WINSIZE + + // Read _a_ TBR value and ignore the current trap details: + asm volatile ( "rd %%tbr, %0" : "=r"(scratch) : ); + gdb[ TBR ] = (scratch &~ 0xfff); + + gdb[ PC ] = trapli->l[1]; + gdb[ NPC ] = trapli->l[2]; + + gdb[ FPSR ] = 0; + gdb[ CPSR ] = 0; + +#ifdef THREAD_DEBUG_SERIAL_VERBOSE + newline(); + swrites( "-----------------------------------------------------" ); newline(); + swrites( "-------------- INTERRUPT STACK GET ------------------" ); newline(); + swrites( "eCos regset at " ); swritex( eCos_regset ); newline(); + swrites( " trapli " ); swritex( trapli ); newline(); + swrites( " ctxli " ); swritex( ctxli ); newline(); + x8( "global ", &(gdb[G0]) ); + x8( " in ", &(gdb[I0]) ); + x8( " local ", &(gdb[L0]) ); + x8( " out ", &(gdb[O0]) ); + swrites( "gdb PC = " ); swritex( gdb[ PC ] ); newline(); + swrites( "gdb NPC = " ); swritex( gdb[ NPC ] ); newline(); + swrites( "gdb PSR = " ); swritex( gdb[ PSR ] ); newline(); +#endif + + } + else { + // It's a synchronous context switch that led to this object. + // Pick up interruptee's registers from the saved context: + for ( reg = 0; reg < 8 ; reg++ ) { +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + gdb[ G0 + reg ] = 0; + gdb[ O0 + reg ] = 0; +#else + gdb[ G0 + reg ] = eCos_regset->g[reg]; + gdb[ O0 + reg ] = eCos_regset->o[reg]; +#endif + gdb[ L0 + reg ] = eCos_regset->li.l[reg]; + gdb[ I0 + reg ] = eCos_regset->li.i[reg]; + } + +#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + // Set up the stack pointer by arithmetic and the return address + gdb[ SP ] = ((cyg_uint32)(eCos_regset)); + gdb[ O7 ] = eCos_regset->o[ 7 ]; +#else + // Clear out G0 which is always 0 (but abused in eCos_regset) + gdb[ G0 ] = 0; +#endif + // and clear the FP regs which we do not have: + for ( reg = F0; reg <= F31; reg++ ) + gdb[ reg ] = 0; + + gdb[ Y ] = 0; // it's not preserved. + + scratch = eCos_regset->g[ 0 ]; // the PSR in the saved context + gdb[ PSR ] = scratch; // return it verbatim. +#if 8 == __WINSIZE + gdb[ WIM ] = 1 << ((__WINBITS & (1 + scratch))); +#else // 6 or 7 windows only + reg = (int)(scratch & __WINBITS); + if ( __WINSIZE <= ++reg ) reg = 0; // good index for WIM + gdb[ WIM ] = 1 << reg; +#endif // __WINSIZE + + // Read _a_ TBR value and ignore the current trap details: + asm volatile ( "rd %%tbr, %0" : "=r"(scratch) : ); + gdb[ TBR ] = (scratch &~ 0xfff); + + gdb[ PC ] = eCos_regset->o[ 7 ]; // the return address + gdb[ NPC ] = 4 + gdb[ PC ]; + + gdb[ FPSR ] = 0; + gdb[ CPSR ] = 0; + +#ifdef THREAD_DEBUG_SERIAL_VERBOSE + newline(); + swrites( "-----------------------------------------------------" ); newline(); + swrites( "-------------- SYNCHRONOUS SWITCH GET----------------" ); newline(); + swrites( "eCos regset at " ); swritex( eCos_regset ); newline(); + x8( "global ", &(gdb[G0]) ); + x8( " in ", &(gdb[I0]) ); + x8( " local ", &(gdb[L0]) ); + x8( " out ", &(gdb[O0]) ); + swrites( "gdb PC = " ); swritex( gdb[ PC ] ); newline(); + swrites( "gdb NPC = " ); swritex( gdb[ NPC ] ); newline(); + swrites( "gdb PSR = " ); swritex( gdb[ PSR ] ); newline(); +#endif + } + +} + +// --------------------------------------------------------------------------- + +void +cyg_hal_sparc_set_gdb_regs( HAL_SavedRegisters *eCos_regset, + void *gdb_regset ) +{ + target_register_t *gdb = (target_register_t *)gdb_regset; + int reg; + cyg_uint32 scratch = 0; + cyg_uint32 *sptrap; + HAL_SavedWindow *trapli, *ctxli; + + // Guess where the eCos register set really is: + if ( 0 == eCos_regset->g[0] || + 0xc0 == (0xe0 & eCos_regset->g[0]) ) { + // Then it's an interrupt stack saved state: + // (either minimal, or a saved PSR with traps disabled) + // The saved register set is pretty minimal, so we have to grub + // around in the stack to find out some truth... + sptrap = (cyg_uint32 *)eCos_regset; // point to the IL save area for + sptrap -= 24; // the trap handler, for PC, NPC + trapli = (HAL_SavedWindow *)sptrap; // Get at those regs + + ctxli = (HAL_SavedWindow *)(trapli->i[6]); // (the frame pointer) + // and get at the interruptee's regs + + scratch = eCos_regset->g[0]; + + // Put back interruptee's registers all over the stack: + for ( reg = 0; reg < 8 ; reg++ ) { + eCos_regset->g[reg] = gdb[ G0 + reg ] ; + trapli->i[reg] = gdb[ O0 + reg ] ; + ctxli->l[reg] = gdb[ L0 + reg ] ; + ctxli->i[reg] = gdb[ I0 + reg ] ; + } + + // Put back the eCos G0 which is always 0 (but abused in eCos_regset) + eCos_regset->g[0] = scratch; + + // In the save context _of the trap handler_ registers are as follows: + // %l0 = psr (with this CWP/window-level in it) + // %l1 = pc + // %l2 = npc + // %l3 = vector number (1-15 for interrupts) + // %l4 = Y register preserved + trapli->l[4] = gdb[ Y ]; + + // I am *not* interfering with the saved PSR, nor the TBR nor WIM. + + // put back return PC and NPC + trapli->l[1] = gdb[ PC ] ; + trapli->l[2] = gdb[ NPC ]; + +#ifdef THREAD_DEBUG_SERIAL_VERBOSE + newline(); + swrites( "-----------------------------------------------------" ); newline(); + swrites( "-------------- INTERRUPT STACK SET ------------------" ); newline(); + swrites( "eCos regset at " ); swritex( eCos_regset ); newline(); + swrites( " trapli " ); swritex( trapli ); newline(); + swrites( " ctxli " ); swritex( ctxli ); newline(); + x8( "global ", &(gdb[G0]) ); + x8( " in ", &(gdb[I0]) ); + x8( " local ", &(gdb[L0]) ); + x8( " out ", &(gdb[O0]) ); + swrites( "gdb PC = " ); swritex( gdb[ PC ] ); newline(); + swrites( "gdb NPC = " ); swritex( gdb[ NPC ] ); newline(); + swrites( "gdb PSR = " ); swritex( gdb[ PSR ] ); newline(); +#endif + + } + else { + // It's a synchronous context switch that led to this object. + // Pick up interruptee's registers from the saved context: + + scratch = eCos_regset->g[0]; + + for ( reg = 0; reg < 8 ; reg++ ) { + eCos_regset->g[reg] = gdb[ G0 + reg ]; + eCos_regset->o[reg] = gdb[ O0 + reg ]; + eCos_regset->li.l[reg] = gdb[ L0 + reg ]; + eCos_regset->li.i[reg] = gdb[ I0 + reg ]; + } + + // Put back the eCos G0 which is always 0 (but abused in eCos_regset) + eCos_regset->g[0] = scratch; + + // I am *not* interfering with the saved PSR, nor the TBR nor WIM. + + // The PC is in o7, altering it via GDB's PC is not on. + // Setting the NPC in a voluntary context is meaningless. + +#ifdef THREAD_DEBUG_SERIAL_VERBOSE + newline(); + swrites( "-----------------------------------------------------" ); newline(); + swrites( "-------------- SYNCHRONOUS SWITCH SET ---------------" ); newline(); + swrites( "eCos regset at " ); swritex( eCos_regset ); newline(); + x8( "global ", &(gdb[G0]) ); + x8( " in ", &(gdb[I0]) ); + x8( " local ", &(gdb[L0]) ); + x8( " out ", &(gdb[O0]) ); + swrites( "gdb PC = " ); swritex( gdb[ PC ] ); newline(); + swrites( "gdb NPC = " ); swritex( gdb[ NPC ] ); newline(); + swrites( "gdb PSR = " ); swritex( gdb[ PSR ] ); newline(); +#endif + } + +} + +/*---------------------------------------------------------------------------*/ +// EOF icontext.c diff --git a/ecos/packages/hal/sparclite/arch/current/src/sparclite.ld b/ecos/packages/hal/sparclite/arch/current/src/sparclite.ld new file mode 100644 index 0000000..707a175 --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/src/sparclite.ld @@ -0,0 +1,151 @@ +//=========================================================================== +// +// MLT linker script for SPARClite +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== + +STARTUP(vectors.o) +ENTRY(reset_vector) +#ifdef EXTRAS +INPUT(extras.o) +#endif +#if (__GNUC__ >= 3) +GROUP(libtarget.a libgcc.a libsupc++.a) +#else +GROUP(libtarget.a libgcc.a) +#endif + +#define ALIGN_LMA 8 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#define SECTIONS_BEGIN + +#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ + .rom_vectors _vma_ : _lma_ \ + { FORCE_OUTPUT; KEEP (*(.vectors)) } \ + > _region_ + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { _stext = ABSOLUTE(.); \ + *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \ + > _region_ \ + _etext = .; PROVIDE (etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fini) } \ + > _region_ + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata*) } \ + > _region_ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata1) } \ + > _region_ + +#define SECTION_fixup(_region_, _vma_, _lma_) \ + .fixup _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fixup) } \ + > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.gcc_except_table) } \ + > _region_ + +#define SECTION_ram_vectors(_region_, _vma_, _lma_) \ + .ram_vectors _vma_ : _lma_ \ + { __ram_vectors_start = ABSOLUTE(.); \ + KEEP (*(.ram_vectors)) \ + __ram_vectors_end = ABSOLUTE(.); } \ + > _region_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { __ram_data_start = ABSOLUTE (.); \ + *(.data*) *(.data1) \ + _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ + _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ + . = ALIGN (4); \ + KEEP(*( SORT (.ecos.table.*))) ; \ + __CTOR_LIST__ = ABSOLUTE (.); \ + KEEP(*(SORT(.ctors*))) \ + __CTOR_END__ = ABSOLUTE (.); \ + __DTOR_LIST__ = ABSOLUTE (.); \ + KEEP(*(SORT(.dtors*))) \ + __DTOR_END__ = ABSOLUTE (.); \ + _GOT_START = ABSOLUTE (.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE (.) + 32768; \ + _SDA_BASE_ = ABSOLUTE (.); \ + *(.got.plt) *(.got) _GOT_END_ = ABSOLUTE (.); \ + *(.dynamic) *(.sdata*) *(.sbss*) *(.eh_frame) } \ + > _region_ \ + __rom_data_start = LOADADDR (.data); \ + . = ALIGN (8); \ + __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { __bss_start = ABSOLUTE (.); \ + *(.scommon) *(.dynbss) *(.bss) *(COMMON) \ + __bss_end = ABSOLUTE (.); } \ + > _region_ + +#define SECTIONS_END . = ALIGN(8); _end = .; PROVIDE (end = .); \ + .debug 0 : { *(.debug) } \ + .line 0 : { *(.line) } \ + .debug_srcinfo 0 : { *(.debug_srcinfo) } \ + .debug_sfnames 0 : { *(.debug_sfnames) } \ + .debug_aranges 0 : { *(.debug_aranges) } \ + .debug_pubnames 0 : { *(.debug_pubnames) } \ + .debug_info 0 : { *(.debug_info) } \ + .debug_abbrev 0 : { *(.debug_abbrev) } \ + .debug_line 0 : { *(.debug_line) } \ + .debug_frame 0 : { *(.debug_frame) } \ + .debug_str 0 : { *(.debug_str) } \ + .debug_loc 0 : { *(.debug_loc) } \ + .debug_macinfo 0 : { *(.debug_macinfo) } \ + .debug_weaknames 0 : { *(.debug_weaknames) } \ + .debug_funcnames 0 : { *(.debug_funcnames) } \ + .debug_typenames 0 : { *(.debug_typenames) } \ + .debug_varnames 0 : { *(.debug_varnames) } + +#include <pkgconf/system.h> +#include CYGHWR_MEMORY_LAYOUT_LDI diff --git a/ecos/packages/hal/sparclite/arch/current/src/vec_ivsr.S b/ecos/packages/hal/sparclite/arch/current/src/vec_ivsr.S new file mode 100644 index 0000000..9ef325d --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/src/vec_ivsr.S @@ -0,0 +1,442 @@ +/*=========================================================================== +// +// vec_ivsr.S +// +// SPARClite vectors: interrupt vector service routine +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-02-20 +// Purpose: SPARClite vector code +// Description: see vectors.S; this is the default vector service routine +// for interrupts. +// +//####DESCRIPTIONEND#### +// +//=========================================================================*/ + +!---------------------------------------------------------------------------- + +// .file "vec_ivsr.S" + +!---------------------------------------------------------------------------- + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#else +# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT +#endif + +!------------------------------------------------------------------------ + +#include <cyg/hal/vectors.h> + +#define DELAYS_AFTER_WRPSR_SAME_WINDOW +#define DELAYS_AFTER_WRWIM + +! Macro to mark the stack as we descend, for debugging, because it is likely +! that actually running the ISR won~t touch the stack, but the memory needs +! to be there. Normally blank. +//#define MARKSTACKUSED st %sp, [ %sp ] +#define MARKSTACKUSED + +!------------------------------------------------------------------------ + + .text + +!--------------------------------------------------------------------------- +! default interrupt VSR, which calls the appropriate ISR after scheduler +! lock and interrupt masking, then interrupt_end(). interrupt_end() must be +! called with interrupts enabled, on the original thread stack (no separate +! interrupt stack) or with interrupts masked, on the original stack (when +! separate interrupt stack is supported). + + .global hal_default_interrupt_vsr +hal_default_interrupt_vsr: + ! here,locals have been set up as follows: + ! %l0 = psr (with this CWP/window-level in it) + ! %l1 = pc + ! %l2 = npc + ! %l3 = vector number (1-15 for interrupts) + ! and we are in our own register window, though it is likely that + ! the next one will need to be saved before we can use it: + ! ie. this one is the invalid register window. + + ! must establish a safe stack before re-enabling interrupts + traps + and %l0, __WINBITS, %l7 ! CWP extracted + ! no inc/dec here, so no need for special measures for not-8-windows + mov 1, %l6 + sll %l6, %l7, %l6 ! 1 << CWP + rd %wim, %l5 + cmp %l5, %l6 ! are they the same? + bne 1f ! No, so the stack is OK as is. + + ! now do by hand an overflow trap, effectively + mov %g1, %l7 ! (DELAY SLOT) + srl %l5, 1, %l5 + sll %l6, __WINSIZE-1, %l6 + or %l6, %l5, %g1 ! new WIM in %g1 so we can get it + ! within the save: + save ! Slip into next window + mov %g1, %wim ! Install the new wim + ! (invalidates current window!) +#ifdef DELAYS_AFTER_WRWIM + nop + nop + nop +#endif + + std %l0, [%sp + 0 * 4] ! save L & I registers + std %l2, [%sp + 2 * 4] + std %l4, [%sp + 4 * 4] + std %l6, [%sp + 6 * 4] + + std %i0, [%sp + 8 * 4] + std %i2, [%sp + 10 * 4] + std %i4, [%sp + 12 * 4] + std %i6, [%sp + 14 * 4] + + restore ! Go back to trap window. + mov %l7, %g1 ! Restore %g1 + +1: ! now save away the regs we must preserve + sub %fp, 32 * 4, %sp +#ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + std %g0, [%sp + 16 * 4] ! save G registers + std %g2, [%sp + 18 * 4] ! (set %g0 place to 0 to flag special context) + std %g4, [%sp + 20 * 4] + std %g6, [%sp + 22 * 4] +#else // not CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + std %l0, [%sp + 0 * 4] ! save L & I registers + std %l2, [%sp + 2 * 4] + std %l4, [%sp + 4 * 4] + std %l6, [%sp + 6 * 4] + + std %i0, [%sp + 8 * 4] + std %i2, [%sp + 10 * 4] + std %i4, [%sp + 12 * 4] + std %i6, [%sp + 14 * 4] + + st %g1, [%sp + 17 * 4] ! save G registers + std %g2, [%sp + 18 * 4] + std %g4, [%sp + 20 * 4] + std %g6, [%sp + 22 * 4] + + ! no point whatsoever in saving O registers + + ! and save the CWP in %g0 save place + st %l0, [%sp + 16 * 4] +#endif // ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + + sub %sp, 24 * 4, %sp ! fresh frame including + ! arg spill area for callees + MARKSTACKUSED ! kilroy was here + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + ! we will switch to the interrupt stack unless already running on it + + .extern cyg_interrupt_stack + .extern cyg_interrupt_stack_base + set cyg_interrupt_stack, %g1 + set cyg_interrupt_stack_base, %g2 + + cmp %sp, %g2 ! below base? + blu 1f ! if so, switch. + cmp %sp, %g1 ! below top? (DELAY SLOT) + blu 2f ! if so, DON~T switch. + nop ! (DELAY SLOT) +1: ! switch to the interrupt stack + st %sp, [ %g1 ] ! there is spare above stack + sub %g1, 24 * 4, %sp ! fresh frame including + ! arg spill area for callees + MARKSTACKUSED ! kilroy was here +2: + ! continue as before, already in the interrupt stack. +#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + ! Lock the scheduler + .extern SCHED_LOCK_MANGLED_NAME + sethi %hi(SCHED_LOCK_MANGLED_NAME), %l7 + ld [ %l7 + %lo(SCHED_LOCK_MANGLED_NAME) ], %l6 + add %l6, 1, %l6 + st %l6, [ %l7 + %lo(SCHED_LOCK_MANGLED_NAME) ] +#endif + + ! HELP_GDB_WITH_BACKTRACE + mov %i7, %l5 ! preserve it in l5 + mov %l1, %i7 ! bogus return link here + + ! and we must preserve the Y register (multiply/divide auxiliary) + ! over these calls; we will keep it in %l4 which is otherwise unused. + rd %y, %l4 + + ! Now we can reenable traps and mask off only lower prio interrupts: + andn %l0, 0xf00, %l7 ! clear PIL field + or %l7, 0x0e0, %l7 ! and ET (+S,PS) + sll %l3, 8, %l6 ! trap number (1-15) into PIL bitfield + wr %l7, %l6, %psr ! and enable! +#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW + nop + nop + nop +#endif + ! now call the ISR and so on with the appropriate args: + ! ie. + ! isr_retcode = (*(hal_interrupt_handlers[ vector ])) + ! ( vector, hal_interrupt_data[ vector ] ); + + ! from hal_arch.h + !// ISR tables + !CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; + !CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; + !CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + + mov %l3, %o0 + sll %l3, 2, %l3 ! %l3 to a word offset + sethi %hi(hal_interrupt_data), %l7 + or %l7, %lo(hal_interrupt_data), %l7 + ld [ %l7 + %l3 ], %o1 + + sethi %hi(hal_interrupt_handlers), %l7 + or %l7, %lo(hal_interrupt_handlers), %l7 + ld [ %l7 + %l3 ], %l6 + call %l6 + nop + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + ! We only need to call _interrupt_end() when there is a kernel + ! present to do any tidying up. + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + ! now we switch back to the user stack (if we~re at the top + ! of the interrupt stack). + + or %l0, 0xfe0, %l7 + wr %l7, %psr ! Interrupts all masked, ET +#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW + nop + nop + nop +#endif + + .extern cyg_interrupt_stack + set cyg_interrupt_stack - (24 * 4), %g1 + + cmp %sp, %g1 ! is SP less? + blu 1f ! if so, do not change back + nop + ! switch to the thread stack + ld [ %g1 + (24 * 4) ], %sp ! there is spare above stack +1: + +#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + ! First restore the processor interrupt level to that interrupted + ! (otherwise a task-switch runs at the current PIL) on the assumption + ! that the ISR dealt with the interrupt source per se, so it is safe + ! to unmask it, effectively: + or %l0, 0x0e0, %l7 ! original PSR and ET (+S,PS) + wr %l7, %psr ! and enable! +#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW + nop + nop + nop +#endif +#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + + ! then call interrupt_end( isr_retcode, &intr_object, ®save ) + ! to unlock the scheduler and do any rescheduling that~s needed. + ! argument 0 (isr_retcode) is already in place in %o0 + sethi %hi(hal_interrupt_objects), %l7 + or %l7, %lo(hal_interrupt_objects), %l7 + ld [ %l7 + %l3 ], %o1 + add %sp, 24 * 4, %o2 ! saved regset (maybe tiny) + + .extern interrupt_end + call interrupt_end + nop +#endif + + ! restore the Y register having done our callouts to C + wr %l4, %y + + ! We can reinstall the original CWP here; even if interrupt_end() + ! performed a reschedule (ie. yield/resume pair) we will be in the + ! same window. The window is preserved by reschedule precisely + ! because it is impossible atomically to disable traps here without + ! involving a CWP living in a register for a time when other + ! interrupts may occur. + + ! disable traps (using the saved psr is fastest way) + wr %l0, %psr ! restores flags, disables traps, and old PIL +#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW + nop + nop + nop +#endif + + ! HELP_GDB_WITH_BACKTRACE + mov %l5, %i7 ! restore (unused) return link + + ! and restore other saved regs + ! (see CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT) + add %sp, 24 * 4, %sp ! undo fresh frame + + ld [%sp + 17 * 4], %g1 ! restore G registers + ldd [%sp + 18 * 4], %g2 + ldd [%sp + 20 * 4], %g4 + ldd [%sp + 22 * 4], %g6 + + ! and do NOT restore any other registers L, I or O + + ! Now test for window underflow here and fix up if needs be. + ! + ! Why? interrupt_end() might have yielded us, when only + ! its own frame was restored; its own return to us caused a + ! window underflow trap, as would our return to interruptee + ! unless we deal with it now. + + add %l0, 1, %l7 ! interruptee~s CWP plus noise + and %l7, __WINBITS, %l7 ! CWP only +#if 8 == __WINSIZE + ! it is in range already +#else // expect 5 or 6 or 7 windows + cmp %l7, __WINSIZE + bge,a 567f ! taken: do delay slot, handle overflow + mov 0, %l7 ! only if .ge. above +567: +#endif + mov 1, %l6 + sll %l6, %l7, %l6 ! 1 << CWP + rd %wim, %l5 + cmp %l5, %l6 ! are they the same? + bne 2f ! No, so the stack is OK as is. + + ! now do by hand an underflow trap, effectively + sll %l5, 1, %l5 ! Rotate wim left + srl %l6, __WINSIZE-1, %l6 + wr %l5, %l6, %wim +#ifdef DELAYS_AFTER_WRWIM + nop ! are these delays needed? + nop ! (following restore uses wim) + nop +#endif + restore ! Interruptee~s window + ldd [%sp + 0 * 4], %l0 ! restore L & I registers + ldd [%sp + 2 * 4], %l2 + ldd [%sp + 4 * 4], %l4 + ldd [%sp + 6 * 4], %l6 + + ldd [%sp + 8 * 4], %i0 + ldd [%sp + 10 * 4], %i2 + ldd [%sp + 12 * 4], %i4 + ldd [%sp + 14 * 4], %i6 + save ! Back to trap window + +2: ! restore the condition codes, PSR and PIL and return from trap. + wr %l0, %psr ! restores flags, disables traps, and old PIL +#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW + nop + nop + nop +#endif + jmpl %l1, %g0 + rett %l2 + +!---------------------------------------------------------------------------- + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + +! This routine can only be called from a thread stack, maybe +! with interrupts (but not traps) disabled. +! It switches to the interrupt stack then calls back to the +! kernel to execute DSRs. + + .global hal_interrupt_stack_call_pending_DSRs +hal_interrupt_stack_call_pending_DSRs: + save %sp, -24 * 4, %sp + + MARKSTACKUSED ! kilroy was here + + ! be atomic + rd %psr, %l0 + andn %l0, 0x20, %l1 ! clear ET to disable traps + wr %l1, %psr ! into the PSR + nop + nop + nop + + mov %sp, %l7 ! save calling stack location + + ! now switch stack to the interrupt stack, plus some headroom + ! for saving a register set if we are interrupted + .extern cyg_interrupt_stack + set cyg_interrupt_stack - 4 * 24, %sp + + MARKSTACKUSED ! kilroy was here + + ! and enable interrupts unconditionally to call the DSRs + or %l0, 0x0e0, %l2 ! set ET, S, PS + andn %l2, 0xf00, %l2 ! PIL to zero + wr %l2, %psr ! into the PSR + nop + nop + nop + + .extern cyg_interrupt_call_pending_DSRs + call cyg_interrupt_call_pending_DSRs + nop + + mov %l7, %sp ! restore calling stack + + wr %l0, %psr ! restore interrupt status + nop + nop + nop + + ret + restore +#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + +!---------------------------------------------------------------------------- + +! end of vec_ivsr.S diff --git a/ecos/packages/hal/sparclite/arch/current/src/vec_xvsr.S b/ecos/packages/hal/sparclite/arch/current/src/vec_xvsr.S new file mode 100644 index 0000000..0294bbf --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/src/vec_xvsr.S @@ -0,0 +1,296 @@ +/*=========================================================================== +// +// vec_xvsr.S +// +// SPARClite vectors: exception vector service routine +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-02-20 +// Purpose: SPARClite vector code +// Description: see vectors.S; this is the default vector service routine +// for exceptions. +// +//####DESCRIPTIONEND#### +// +//=========================================================================*/ + +!----------------------------------------------------------------------------- + +// .file "vec_xvsr.S" + +!---------------------------------------------------------------------------- + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#endif + +!------------------------------------------------------------------------ + +#include <cyg/hal/vectors.h> + +#define DELAYS_AFTER_WRPSR_SAME_WINDOW +#define DELAYS_AFTER_WRWIM + +!------------------------------------------------------------------------ + + .text + +!--------------------------------------------------------------------------- +! default exception handler VSR, which calls the appropriate ISR after +! interrupt masking - much the same as the interrupt VSR but does not lock +! scheduler or call interrupt_end(). + + .global hal_default_exception_vsr +hal_default_exception_vsr: + ! here,locals have been set up as follows: + ! %l0 = psr (with this CWP/window-level in it) + ! %l1 = pc + ! %l2 = npc + ! %l3 = vector number (16-25 for traps) + ! and we are in our own register window, though it is likely that + ! the next one will need to be saved before we can use it: + ! ie. this one is the invalid register window. + + ! must establish a safe stack before re-enabling interrupts + traps + and %l0, __WINBITS, %l7 ! CWP extracted + ! no inc/dec here, so no need for special measures for not-8-windows + mov 1, %l6 + sll %l6, %l7, %l6 ! 1 << CWP + rd %wim, %l5 + cmp %l5, %l6 ! are they the same? + bne 1f ! No, so the stack is OK as is. + + ! now do by hand an overflow trap, effectively + mov %g1, %l7 ! (DELAY SLOT) + srl %l5, 1, %l5 + sll %l6, __WINSIZE-1, %l6 + or %l6, %l5, %g1 ! new WIM in %g1 so we can get it + ! within the save: + save ! Slip into next window + mov %g1, %wim ! Install the new wim + ! (invalidates current window!) +#ifdef DELAYS_AFTER_WRWIM + nop + nop + nop +#endif + + std %l0, [%sp + 0 * 4] ! save L & I registers + std %l2, [%sp + 2 * 4] + std %l4, [%sp + 4 * 4] + std %l6, [%sp + 6 * 4] + + std %i0, [%sp + 8 * 4] + std %i2, [%sp + 10 * 4] + std %i4, [%sp + 12 * 4] + std %i6, [%sp + 14 * 4] + + restore ! Go back to trap window. + mov %l7, %g1 ! Restore %g1 + +1: ! now save away the regs we must preserve + sub %fp, 32 * 4, %sp + ! save a maximal context regardless: see also + ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + std %l0, [%sp + 0 * 4] ! save L & I registers + std %l2, [%sp + 2 * 4] + std %l4, [%sp + 4 * 4] + std %l6, [%sp + 6 * 4] + + std %i0, [%sp + 8 * 4] + std %i2, [%sp + 10 * 4] + std %i4, [%sp + 12 * 4] + std %i6, [%sp + 14 * 4] + + st %g1, [%sp + 17 * 4] ! save G registers + std %g2, [%sp + 18 * 4] + std %g4, [%sp + 20 * 4] + std %g6, [%sp + 22 * 4] + + ! no point whatsoever in saving O registers + + ! and save the CWP in %g0 save place + st %l0, [%sp + 16 * 4] + + sub %sp, 24 * 4, %sp ! fresh frame including + ! arg spill area for callees + + ! do not lock the scheduler + + ! HELP_GDB_WITH_BACKTRACE + mov %i7, %l5 ! preserve it JIC + mov %l1, %i7 ! bogus return link here + + ! and we must preserve the Y register (multiply/divide auxiliary) + ! over these calls; we will keep it in %l4 which is otherwise unused. + rd %y, %l4 + + ! Now we can reenable traps (preserving interrupt level) + or %l0, 0x0e0, %l7 ! set ET (+S,PS), preserve PIL + wr %l7, %psr ! and enable! +#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW + nop + nop + nop +#endif + ! now call the XSR and so on with the appropriate args: + ! ie. + ! isr_retcode = (*(hal_interrupt_handlers[ vector ])) + ! ( vector, hal_interrupt_data[ vector ], stackp ); + + ! from hal_arch.h + !// ISR tables + !CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; + !CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; + !CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + + mov %l3, %o0 + sll %l3, 2, %l3 ! %l3 to a word offset + sethi %hi(hal_interrupt_data), %l7 + or %l7, %lo(hal_interrupt_data), %l7 + ld [ %l7 + %l3 ], %o1 ! data + add %sp, 24 * 4, %o2 ! stackpointer of saved regset + + sethi %hi(hal_interrupt_handlers), %l7 + or %l7, %lo(hal_interrupt_handlers), %l7 + ld [ %l7 + %l3 ], %l6 + call %l6 + nop + + ! do not call _interrupt_end() + + ! restore the Y register having done our callouts to C + wr %l4, %y + + ! We can reinstall the original CWP here; even if interrupt_end() + ! performed a reschedule (ie. yield/resume pair) we will be in the + ! same window. The window is preserved by reschedule precisely + ! because it is impossible atomically to disable traps here without + ! involving a CWP living in a register for a time when other + ! interrupts may occur. + + ! disable traps (using the saved psr is fastest way) + wr %l0, %psr ! restores flags, disables traps, same PIL. +#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW + nop + nop + nop +#endif + ! HELP_GDB_WITH_BACKTRACE + mov %l5, %i7 ! restore (unused) return link + + ! and restore other saved regs + add %sp, 24 * 4, %sp ! undo fresh frame + ! restore a maximal context regardless: see also + ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + ldd [%sp + 0 * 4], %l0 ! restore L & I registers + ldd [%sp + 2 * 4], %l2 ! to support the handler + ldd [%sp + 4 * 4], %l4 ! having messed with them. + ldd [%sp + 6 * 4], %l6 + + ldd [%sp + 8 * 4], %i0 + ldd [%sp + 10 * 4], %i2 + ldd [%sp + 12 * 4], %i4 + ldd [%sp + 14 * 4], %i6 + + ld [%sp + 17 * 4], %g1 ! and G registers + ldd [%sp + 18 * 4], %g2 + ldd [%sp + 20 * 4], %g4 + ldd [%sp + 22 * 4], %g6 + ! no point whatsoever in loading back O registers. + + ! Now test for window underflow here and fix up if needs be. + ! + ! Why? interrupt_end() might have yielded us, when only + ! its own frame was restored; its own return to us caused a + ! window underflow trap, as would our return to interruptee + ! unless we deal with it now. + + add %l0, 1, %l7 ! interruptee~s CWP plus noise + and %l7, __WINBITS, %l7 ! CWP only +#if 8 == __WINSIZE + ! it is in range already +#else // expect 5 or 6 or 7 windows + cmp %l7, __WINSIZE + bge,a 567f ! taken: do delay slot, handle overflow + mov 0, %l7 ! only if .ge. above +567: +#endif + mov 1, %l6 + sll %l6, %l7, %l6 ! 1 << CWP + rd %wim, %l5 + cmp %l5, %l6 ! are they the same? + bne 2f ! No, so the stack is OK as is. + + ! now do by hand an underflow trap, effectively + sll %l5, 1, %l5 ! Rotate wim left + srl %l6, __WINSIZE-1, %l6 + wr %l5, %l6, %wim +#ifdef DELAYS_AFTER_WRWIM + nop ! are these delays needed? + nop ! (following restore uses wim) + nop +#endif + restore ! Interruptee~s window + ldd [%sp + 0 * 4], %l0 ! restore L & I registers + ldd [%sp + 2 * 4], %l2 + ldd [%sp + 4 * 4], %l4 + ldd [%sp + 6 * 4], %l6 + + ldd [%sp + 8 * 4], %i0 + ldd [%sp + 10 * 4], %i2 + ldd [%sp + 12 * 4], %i4 + ldd [%sp + 14 * 4], %i6 + save ! Back to trap window + +2: ! restore the condition codes, PSR and PIL and return from trap. + wr %l0, %psr ! restores flags, disables traps, and old PIL +#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW + nop + nop + nop +#endif + jmpl %l1, %g0 + rett %l2 + + +! end of vec_xvsr.S diff --git a/ecos/packages/hal/sparclite/arch/current/src/vectors.S b/ecos/packages/hal/sparclite/arch/current/src/vectors.S new file mode 100644 index 0000000..fcfc980 --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/src/vectors.S @@ -0,0 +1,550 @@ +/*============================================================================= +// +// vectors.S +// +// SPARClite vectors and bootup code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt +// Date: 1998-12-15 +// Purpose: SPARClite vector code +// Description: This file contains the code which hangs off SPARClite vectors +// including reset; it handles register under/overflow as well +// as bootup, anything else is deferred to the default interrupt +// or exception vsrs respectively. See vec_[ix]vsr.S ... +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +!----------------------------------------------------------------------------- + +// .file "vectors.S" + +!----------------------------------------------------------------------------- + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#include <pkgconf/hal_sparclite.h> +#include CYGBLD_HAL_PLATFORM_H // Platform config file + +#ifdef CYGPKG_KERNEL +# include <pkgconf/kernel.h> +#else +# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT +#endif + +#if defined( CYGPKG_HAL_SPARCLITE_SIM ) || \ + defined( CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK ) +#define BOOTUPSTACK_IS_INTERRUPTSTACK +#endif + +//#define CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING + +#ifndef CYGHWR_HAL_SPARCLITE_HAS_ASR17 +#ifndef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +#error Single Vector Trapping (SVT) demands ASR17 +#endif +#endif + +#ifdef CYG_HAL_STARTUP_ROM +# ifndef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING + +! ROM startup and Single Vector Trapping demands a copy to RAM. +! Otherwise it may be configured in, but it is not required. + +# ifndef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM +# define CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM +# endif + +# endif +#endif + +!------------------------------------------------------------------------ + +#include <cyg/hal/vectors.h> + +#define DELAYS_AFTER_WRPSR_SAME_WINDOW +#define DELAYS_AFTER_WRWIM + +!------------------------------------------------------------------------ + +#ifdef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING + + .macro VECTOR_EXCEPTION + .p2align 4 + rd %tbr, %l3 + rd %psr, %l0 + ba __entry_exception + and %l3, TT_MASK, %l4 + .endm + + .macro VECTOR_INTERRUPT level + .p2align 4 + rd %psr, %l0 + mov \level << 2, %l5 + ba __entry_interrupt + mov \level << 4, %l4 + .endm + + .macro VECTOR_CODE_WIM name + .p2align 4 + ba __entry_\name + rd %wim, %l0 + .endm + +#endif // CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING + +!------------------------------------------------------------------------ +! The start of the code; this is the entry point: + + .section ".vectors","ax" + + .global rom_vectors +rom_vectors: + .global reset_vector +reset_vector: + ! this code goes to the real reset handler, it will be + ! overwritten by the start of vectoring handler... + b genuine_reset + nop + ! usually drop through to: +#ifdef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING + ba __entry_exception ! reset becomes an exception + and %l3, TT_MASK, %l4 ! once we are running + + VECTOR_EXCEPTION ! 1 + VECTOR_EXCEPTION ! 2 + VECTOR_EXCEPTION ! 3 + VECTOR_EXCEPTION ! 4 + + VECTOR_CODE_WIM wover ! 5 window overflow + VECTOR_CODE_WIM wunder ! 6 window underflow + VECTOR_EXCEPTION ! 7 + VECTOR_EXCEPTION ! 8 + VECTOR_EXCEPTION ! 9 + + VECTOR_EXCEPTION ! 10 + VECTOR_EXCEPTION ! 11 + VECTOR_EXCEPTION ! 12 + VECTOR_EXCEPTION ! 13 + VECTOR_EXCEPTION ! 14 + + VECTOR_EXCEPTION ! 15 + VECTOR_EXCEPTION ! 16 + VECTOR_INTERRUPT 1 ! 17 interrupt_level_1 + VECTOR_INTERRUPT 2 ! 18 interrupt_level_2 + VECTOR_INTERRUPT 3 ! 19 interrupt_level_3 + + VECTOR_INTERRUPT 4 ! 20 interrupt_level_4 + VECTOR_INTERRUPT 5 ! 21 interrupt_level_5 + VECTOR_INTERRUPT 6 ! 22 interrupt_level_6 + VECTOR_INTERRUPT 7 ! 23 interrupt_level_7 + VECTOR_INTERRUPT 8 ! 24 interrupt_level_8 + + VECTOR_INTERRUPT 9 ! 25 interrupt_level_9 + VECTOR_INTERRUPT 10 ! 26 interrupt_level_10 + VECTOR_INTERRUPT 11 ! 27 interrupt_level_11 + VECTOR_INTERRUPT 12 ! 28 interrupt_level_12 + VECTOR_INTERRUPT 13 ! 29 interrupt_level_13 + + VECTOR_INTERRUPT 14 ! 30 interrupt_level_14 + VECTOR_INTERRUPT 15 ! 31 interrupt_level_15 + VECTOR_EXCEPTION ! 32 + VECTOR_EXCEPTION ! 33 + VECTOR_EXCEPTION ! 34 + + VECTOR_EXCEPTION ! 35 + VECTOR_EXCEPTION ! 36 + VECTOR_EXCEPTION ! 37 + VECTOR_EXCEPTION ! 38 + VECTOR_EXCEPTION ! 39 + + .rept 216 ! 40-255 is 216 of them + VECTOR_EXCEPTION ! whichever + .endr +#endif // CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING + +#ifndef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +real_vector: + ! here,locals have been set up as follows: + ! %l0 = psr + ! %l1 = pc + ! %l2 = npc + ! %l3 = tbr + and %l3, TT_IS_INTR_MASK, %l4 + cmp %l4, TT_IS_INTR_VALUE + bne not_an_interrupt ! delay slot does not matter + ! here be the pre-vector interrupt handler +interrupt: + and %l3, 0x0f0, %l4 ! get an interrupt number out + srl %l4, 2, %l5 ! to a word address offset +#endif // !CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +__entry_interrupt: + sethi %hi(hal_vsr_table), %l6 + or %l6, %lo(hal_vsr_table), %l6 + ld [ %l6 + %l5 ], %l6 ! get vector in %l6 + jmp %l6 ! and go there + srl %l4, 4, %l3 ! vector number into %l3: so that + ! interrupts and exceptions/traps + ! have the same API to VSRs + +#ifndef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +not_an_interrupt: + and %l3, TT_MASK, %l4 + cmp %l4, (TRAP_WUNDER << TT_SHL) + + bne,a not_window_underflow + cmp %l4, (TRAP_WOVER << TT_SHL) ! (if taken) + + ! here be the window underflow handler: +window_underflow: + ! CWP is trap handler + ! CWP + 1 is trapped RESTORE instruction + ! CWP + 2 is invalid context which must be restored + ! CWP + 3 is next invalid context + + wr %l0, %psr ! restore the condition flags + ! (CWP is unchanged) + ! the following instructions delay enough; no need for NOPs + rd %wim, %l0 ! get the wim +#endif // !CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +__entry_wunder: + sll %l0, 1, %l3 ! Rotate wim left + srl %l0, __WINSIZE-1, %l0 + wr %l0, %l3, %wim ! Install the new wim + +#ifdef DELAYS_AFTER_WRWIM + nop ! are these delays needed? + nop ! (following restore uses wim) + nop +#endif + restore ! Users window + restore ! Her callers window (now valid) + + ldd [%sp + 0 * 4], %l0 ! restore L & I registers + ldd [%sp + 2 * 4], %l2 + ldd [%sp + 4 * 4], %l4 + ldd [%sp + 6 * 4], %l6 + + ldd [%sp + 8 * 4], %i0 + ldd [%sp + 10 * 4], %i2 + ldd [%sp + 12 * 4], %i4 + ldd [%sp + 14 * 4], %i6 + + save ! Back to trap window + save + + jmp %l1 + rett %l2 + +#ifndef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +not_window_underflow: + bne,a not_window_overflow + srl %l4, 4, %l4 ! (if taken) + + ! here be the window overflow handler: +window_overflow: + ! CWP + 1 is caller whose SAVE bounced + ! CWP is trap handler = invalid window + ! CWP - 1 is next invalid window which needs to be saved + + wr %l0, %psr ! restore the condition flags + ! (CWP is unchanged) + ! the following instructions delay enough; no need for NOPs + rd %wim, %l0 +#endif // !CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +__entry_wover: + mov %g1, %l3 ! Save g1, we use it to hold the wim + srl %l0, 1, %g1 ! Rotate wim right + sll %l0, __WINSIZE-1, %l0 + or %l0, %g1, %g1 + + save ! Slip into next window + mov %g1, %wim ! Install the new wim + ! (invalidates current window!) + + std %l0, [%sp + 0 * 4] ! save L & I registers + std %l2, [%sp + 2 * 4] + std %l4, [%sp + 4 * 4] + std %l6, [%sp + 6 * 4] + + std %i0, [%sp + 8 * 4] + std %i2, [%sp + 10 * 4] + std %i4, [%sp + 12 * 4] + std %i6, [%sp + 14 * 4] + + restore ! Go back to trap window. + mov %l3, %g1 ! Restore %g1 + + jmpl %l1, %g0 + rett %l2 + +#ifdef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING + // ADDITIONAL code to provide an entry point: +__entry_exception: + srl %l4, 4, %l4 +#endif // CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +not_window_overflow: + ! from here on in, %l4 is the trap number in clear + cmp %l4, 128 + bge 1f + mov 0, %l5 ! offset 0 for user traps + + cmp %l4, 36 ! coprocessor special case + beq 1f + mov 4, %l5 ! ...treated as FP, code 4 + + cmp %l4, 10 + bge 1f + mov 10, %l5 ! offset 10 for "others" + + ! if we are here, the trap number is 1-9 inclusive + ! so put it in %l5 and drop through... + mov %l4, %l5 +1: + or %l5, 16, %l5 ! offset into table is 16... for traps. + sll %l5, 2, %l5 ! to a word address offset + sethi %hi(hal_vsr_table), %l6 + or %l6, %lo(hal_vsr_table), %l6 + ld [ %l6 + %l5 ], %l6 ! get vector in %l6 + jmp %l6 ! and go there + srl %l5, 2, %l3 ! vector number into %l3: so that + ! interrupts and exceptions/traps + ! have the same API to VSRs + ! NB that~s eCos vector number not TRAP number above. + + ! and that is the end of the pre-vector trap handler + + .global rom_vectors_end +rom_vectors_end: + + ! these instructions are copied into the reset vector + ! after startup to _not_ branch to the genuine_reset code below +real_vector_instructions: + rd %tbr, %l3 + rd %psr, %l0 + + + + ! genuine reset code called from time zero: +genuine_reset: ! set psr, mask interrupts & traps + wr %g0, 0xfc0 + __WIN_INIT, %psr + nop ! mode = prevMode = S, CWP=7 + nop + nop + wr %g0, 0, %wim ! No invalid windows (yet) + nop + nop + nop + + sethi %hi(reset_vector), %g1 + andn %g1, 0xfff, %g1 ! should not be needed + wr %g1, %tbr ! Traps are at reset_vector + nop + nop + nop +#ifdef CYGHWR_HAL_SPARCLITE_HAS_ASR17 +#ifdef CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING + wr %g0, 0, %asr17 ! Multiple vector trapping +#else + wr %g0, 1, %asr17 ! Single vector trapping +#endif // !CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING +#endif // CYGHWR_HAL_SPARCLITE_HAS_ASR17 + nop + nop + nop + +// INCLUDE PLATFORM BOOT + +// This should set up RAM and caches, and calm down any external interrupt +// sources. Also copy two instructions from real_vector_instructions +// into reset_vector, then invalidate the instruction cache. + +#include <cyg/hal/halboot.si> + +// halboot.si returns with %sp all set, in sleb versions. +// (though we override if there is an interrupt stack) + + led 0x80 + + ! now set up a stack and initial frame linkage + ! so as to be able to make C function calls: + ! current window is 7, the highest, so we store a + ! saved frame thingy that refers to itself in the stack, + ! then another which is valid and drop into main from there. + +#ifdef BOOTUPSTACK_IS_INTERRUPTSTACK + sethi %hi(cyg_interrupt_stack), %i6 + or %i6, %lo(cyg_interrupt_stack), %i6 +#endif + andn %i6, 7, %i6 ! round fp down to double alignment + mov 0, %i7 ! null return address + sethi %hi(0xb51ac000), %i0 ! "BStac" pattern + or %i0, 24, %i0 + or %i0, 1, %i1 + or %i0, 2, %i2 + or %i0, 3, %i3 + or %i0, 4, %i4 + or %i0, 5, %i5 + + sethi %hi(0xb51ac000), %l0 ! "BStac" pattern + or %l0, 16, %l0 + or %l0, 1, %l1 + or %l0, 2, %l2 + or %l0, 3, %l3 + or %l0, 4, %l4 + or %l0, 5, %l5 + or %l0, 6, %l6 + or %l0, 7, %l7 + + sub %fp, 16 * 4, %sp ! Stack pointer + + led 0x90 + + std %l0, [%sp + 0 * 4] ! save L & I registers + std %l2, [%sp + 2 * 4] ! into new stack frame + std %l4, [%sp + 4 * 4] + std %l6, [%sp + 6 * 4] + + led 0x91 + + std %i0, [%sp + 8 * 4] + std %i2, [%sp + 10 * 4] + std %i4, [%sp + 12 * 4] + std %i6, [%sp + 14 * 4] + + led 0x92 + + sethi %hi(0xb0010000), %o0 ! "Boot" pattern + or %o0, 8, %o0 + or %o0, 1, %o1 + or %o0, 2, %o2 + or %o0, 3, %o3 + or %o0, 4, %o4 + or %o0, 5, %o5 + + led 0x98 + + wr %g0, __WIM_INIT, %wim ! Window 7 (current) is invalid + nop + nop + nop + + led 0x99 + + sethi %hi(0xb0010000), %g1 ! "Boot" pattern + or %g1, 2, %g2 + or %g1, 3, %g3 + or %g1, 4, %g4 + or %g1, 5, %g5 + or %g1, 6, %g6 + or %g1, 7, %g7 + or %g1, 1, %g1 + + led 0xa0 + + wr %g0, 0xfe0 + __WIN_INIT, %psr + nop ! Enable traps: + nop ! set psr, _do_ mask interrupts + nop ! mode = prevMode = S, CWP=7 + + led 0xb0 + + ! now we can start calling out and running C code! + .extern cyg_hal_start + call cyg_hal_start ! puts return address in %o7 + or %g1, 1, %g1 + +loop_forever: + ta 1 + b loop_forever ! if it returns + nop + + +!--------------------------------------------------------------------------- +! hal_vsr_table... + + .section ".data" + .balign 4 + .global hal_vsr_table +hal_vsr_table: + .rept 16 + .word hal_default_interrupt_vsr + .endr + .rept 11 + .word hal_default_exception_vsr + .endr + +!--------------------------------------------------------------------------- +! Bootup stack (only needed explicitly in sim) + +#ifdef BOOTUPSTACK_IS_INTERRUPTSTACK + .section ".bss" + +#ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 +#endif + .balign 16 + .global cyg_interrupt_stack_base +cyg_interrupt_stack_base: + .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + .byte 0 + .endr + .balign 16 + .global cyg_interrupt_stack +cyg_interrupt_stack: + .long 0,0,0,0,0,0,0,0 ! here be secret state stored +#endif + +!------------------------------------------------------------------------ +! Define a section that reserves space at the start of RAM for the +! vectors to be copied into, for ROM start only. + + .section ".ram_vectors","awx",@nobits +#ifdef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM + ! need a space at base of RAM for copied vector/trampoline code + .align 0x1000 + .space 8 ! for fencepost errors + .space (rom_vectors_end - rom_vectors) +#endif // CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM + +!------------------------------------------------------------------------ +! end of vectors.S diff --git a/ecos/packages/hal/sparclite/arch/current/tests/sparc_ex.c b/ecos/packages/hal/sparclite/arch/current/tests/sparc_ex.c new file mode 100644 index 0000000..19519ea --- /dev/null +++ b/ecos/packages/hal/sparclite/arch/current/tests/sparc_ex.c @@ -0,0 +1,436 @@ +/*================================================================= +// +// sparc_ex.c +// +// SPARClite HAL exception and register manipulation test +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dsm +// Contributors: dsm, nickg +// Date: 1998-06-18 +//####DESCRIPTIONEND#### +*/ + +#include <pkgconf/system.h> + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/infra/testcase.h> + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> + +#include <pkgconf/infra.h> + +#ifdef CYGDBG_USE_TRACING +#define OUTER_REPEATS 1 +#define SIM_REPEATS 10 +#define HW_REPEATS 1000 +#else +#define OUTER_REPEATS 10 +#define SIM_REPEATS 100 +#define HW_REPEATS 10000 +#endif // using tracing to slow everything down + +// ------------------------------------------------------------------------- +// These routines are used to cause an alignment trap; the compiler is too +// darned clever by half, if you try to inline this stuff as macros it uses +// different instruction sequences and register pairs. This makes for a +// less thorough test, but there's no option other than writing a LOT of +// assembler code. + +// Further, with -O3, the compiler inlines these anyway and so makes +// non-trapping code. So they are now at the end, to prevent this. + +extern cyg_uint64 get_ll( cyg_uint64 *p ); + +extern cyg_uint64 get_llplus( cyg_uint64 *p ); + +extern cyg_uint32 get_i( cyg_uint32 *p ); + +extern cyg_uint32 get_iplus( cyg_uint32 *p ); + +extern cyg_uint16 get_s( cyg_uint16 *p ); + +extern cyg_uint16 get_splus( cyg_uint16 *p ); + +// ------------------------------------------------------------------------- +// Some memory to read in more-or-less aligned manners. + +#define L1 (0x123456789abcdef0l) +#define L2 (0xfedcba9876543210l) +static cyg_uint64 a[ 2 ] = { + L1, + L2 +}; + +#define M32 (0x00000000ffffffffl) +#define M16 (0x000000000000ffffl) +#define M8 (0x00000000000000ffl) + +volatile cyg_uint32 trap = 0; +volatile cyg_uint32 same = 0; +volatile cyg_uint32 tcount = 0; + +// ------------------------------------------------------------------------- +// This macro invokes a routine then checks that a suitable trap occurred. +// It expects the instruction simply to be skipped, rather than the trap +// _handled_ or the unaligned access to be _emulated_ in any way. This +// test is just a proof that we could write such a handler. + +#define TRAPPROC( _var_, _type_, _align_, _proc_ ) \ +CYG_MACRO_START \ + otrap = trap; \ + otcount = tcount; \ + _var_ = _proc_( (_type_ *)(cp + (_align_)) ); \ + CYG_TEST_CHECK( trap != otrap || same > 0, \ + "No trap [" #_type_ ":" #_align_ "," #_proc_ "]" ); \ + CYG_TEST_CHECK( same < 20, \ + "Undetected trap loop[" #_type_ ":" #_align_ "," #_proc_ "]" ); \ + CYG_TEST_CHECK( tcount > otcount, \ + "No trap counted [" #_type_ ":" #_align_ "," #_proc_ "]" ); \ + CYG_TEST_CHECK( (tcount - 1) <= otcount, \ + "Tcount overinc [" #_type_ ":" #_align_ "," #_proc_ "]" ); \ +CYG_MACRO_END + +// and this one expects no trap to occur: +#define SAFEPROC( _var_, _type_, _align_, _proc_ ) \ +CYG_MACRO_START \ + trap = 0; \ + otcount = tcount; \ + _var_ = _proc_( (_type_ *)(cp + (_align_)) ); \ + CYG_TEST_CHECK( 0 == trap, \ + "Trap [" #_type_ ":" #_align_ "," #_proc_ "]" ); \ + CYG_TEST_CHECK( tcount == otcount, \ + "Trap counted [" #_type_ ":" #_align_ "," #_proc_ "]" ); \ +CYG_MACRO_END + +static void do_test( void ) +{ + cyg_uint32 *ip = (cyg_uint32 *)a; + cyg_uint16 *sp = (cyg_uint16 *)a; + cyg_uint8 *cp = (cyg_uint8 *)a; + + cyg_uint64 l; + cyg_uint32 i; + cyg_uint16 s; + cyg_uint8 c; + + cyg_int32 z, repeats; + + cyg_uint32 otrap; + cyg_uint32 otcount; + + otrap = trap = 0; + otcount = tcount; + + // First test interestingly aligned accesses that are legal. + + l = a[0]; CYG_TEST_CHECK( L1 == l, "a[0] read bad" ); + l = a[1]; CYG_TEST_CHECK( L2 == l, "a[1] read bad" ); + + i = ip[0]; CYG_TEST_CHECK( ((L1 >> 32) & M32) == i, "ip[0]" ); + i = ip[1]; CYG_TEST_CHECK( ((L1 ) & M32) == i, "ip[1]" ); + i = ip[2]; CYG_TEST_CHECK( ((L2 >> 32) & M32) == i, "ip[2]" ); + i = ip[3]; CYG_TEST_CHECK( ((L2 ) & M32) == i, "ip[3]" ); + + s = sp[0]; CYG_TEST_CHECK( ((L1 >> 48) & M16) == s, "sp[0]" ); + s = sp[1]; CYG_TEST_CHECK( ((L1 >> 32) & M16) == s, "sp[1]" ); + s = sp[2]; CYG_TEST_CHECK( ((L1 >> 16) & M16) == s, "sp[2]" ); + s = sp[3]; CYG_TEST_CHECK( ((L1 ) & M16) == s, "sp[3]" ); + s = sp[4]; CYG_TEST_CHECK( ((L2 >> 48) & M16) == s, "sp[4]" ); + s = sp[5]; CYG_TEST_CHECK( ((L2 >> 32) & M16) == s, "sp[5]" ); + s = sp[6]; CYG_TEST_CHECK( ((L2 >> 16) & M16) == s, "sp[6]" ); + s = sp[7]; CYG_TEST_CHECK( ((L2 ) & M16) == s, "sp[7]" ); + + c = cp[0]; CYG_TEST_CHECK( ((L1 >> 56) & M8) == c, "cp[0]" ); + c = cp[1]; CYG_TEST_CHECK( ((L1 >> 48) & M8) == c, "cp[1]" ); + c = cp[2]; CYG_TEST_CHECK( ((L1 >> 40) & M8) == c, "cp[2]" ); + c = cp[3]; CYG_TEST_CHECK( ((L1 >> 32) & M8) == c, "cp[3]" ); + c = cp[4]; CYG_TEST_CHECK( ((L1 >> 24) & M8) == c, "cp[4]" ); + c = cp[5]; CYG_TEST_CHECK( ((L1 >> 16) & M8) == c, "cp[5]" ); + c = cp[6]; CYG_TEST_CHECK( ((L1 >> 8) & M8) == c, "cp[6]" ); + c = cp[7]; CYG_TEST_CHECK( ((L1 ) & M8) == c, "cp[7]" ); + c = cp[8]; CYG_TEST_CHECK( ((L2 >> 56) & M8) == c, "cp[8]" ); + c = cp[9]; CYG_TEST_CHECK( ((L2 >> 48) & M8) == c, "cp[9]" ); + c = cp[10]; CYG_TEST_CHECK( ((L2 >> 40) & M8) == c, "cp[10]" ); + c = cp[11]; CYG_TEST_CHECK( ((L2 >> 32) & M8) == c, "cp[11]" ); + c = cp[12]; CYG_TEST_CHECK( ((L2 >> 24) & M8) == c, "cp[12]" ); + c = cp[13]; CYG_TEST_CHECK( ((L2 >> 16) & M8) == c, "cp[13]" ); + c = cp[14]; CYG_TEST_CHECK( ((L2 >> 8) & M8) == c, "cp[14]" ); + c = cp[15]; CYG_TEST_CHECK( ((L2 ) & M8) == c, "cp[15]" ); + + CYG_TEST_CHECK( 0 == trap, "Traps occurred (legal accesses)" ); + CYG_TEST_CHECK( tcount == otcount, "Traps counted (legal accesses)" ); + + CYG_TEST_PASS( "Aligned accesses OK" ); + + for ( z = OUTER_REPEATS; z > 0; z-- ) { + + for ( repeats = (cyg_test_is_simulator ? SIM_REPEATS : HW_REPEATS) ; + repeats > 0 ; repeats-- ) { + + TRAPPROC( l, cyg_uint64, 4, get_llplus ); + TRAPPROC( l, cyg_uint64, 5, get_llplus ); + TRAPPROC( l, cyg_uint64, 6, get_llplus ); + TRAPPROC( l, cyg_uint64, 7, get_llplus ); + + TRAPPROC( l, cyg_uint64, 4, get_ll ); + TRAPPROC( l, cyg_uint64, 1, get_ll ); + TRAPPROC( l, cyg_uint64, 2, get_ll ); + TRAPPROC( l, cyg_uint64, 3, get_ll ); + + TRAPPROC( i, cyg_uint32, 1, get_iplus ); + TRAPPROC( i, cyg_uint32, 2, get_iplus ); + TRAPPROC( i, cyg_uint32, 3, get_iplus ); + + TRAPPROC( i, cyg_uint32, 5, get_i ); + TRAPPROC( i, cyg_uint32, 6, get_i ); + TRAPPROC( i, cyg_uint32, 7, get_i ); + + TRAPPROC( s, cyg_uint16, 1, get_splus ); + TRAPPROC( s, cyg_uint16, 3, get_splus ); + + TRAPPROC( s, cyg_uint16, 5, get_s ); + TRAPPROC( s, cyg_uint16, 7, get_s ); + } + + CYG_TEST_PASS( "Unaligned accesses OK" ); + + // Now test some legal and illegal accesses intermingled. + + for ( repeats = (cyg_test_is_simulator ? SIM_REPEATS : HW_REPEATS) ; + repeats > 0 ; repeats-- ) { + + SAFEPROC( l, cyg_uint64, 0, get_llplus ); + TRAPPROC( l, cyg_uint64, 5, get_llplus ); + TRAPPROC( l, cyg_uint64, 6, get_llplus ); + SAFEPROC( l, cyg_uint64, 8, get_llplus ); + + TRAPPROC( i, cyg_uint32, 1, get_iplus ); + SAFEPROC( i, cyg_uint32, 4, get_iplus ); + TRAPPROC( i, cyg_uint32, 2, get_iplus ); + SAFEPROC( i, cyg_uint32, 8, get_iplus ); + SAFEPROC( i, cyg_uint32, 12, get_iplus ); + SAFEPROC( i, cyg_uint32, 16, get_iplus ); + TRAPPROC( i, cyg_uint32, 3, get_iplus ); + + TRAPPROC( s, cyg_uint16, 5, get_s ); + SAFEPROC( s, cyg_uint16, 6, get_s ); + TRAPPROC( s, cyg_uint16, 7, get_s ); + SAFEPROC( s, cyg_uint16, 8, get_s ); + + TRAPPROC( i, cyg_uint32, 5, get_i ); + SAFEPROC( i, cyg_uint32, 4, get_i ); + TRAPPROC( i, cyg_uint32, 6, get_i ); + TRAPPROC( i, cyg_uint32, 7, get_i ); + SAFEPROC( i, cyg_uint32, 0, get_i ); + + TRAPPROC( l, cyg_uint64, 4, get_ll ); + SAFEPROC( l, cyg_uint64, 0, get_ll ); + TRAPPROC( l, cyg_uint64, 1, get_ll ); + SAFEPROC( l, cyg_uint64, 8, get_ll ); + + TRAPPROC( s, cyg_uint16, 1, get_splus ); + SAFEPROC( s, cyg_uint16, 2, get_splus ); + TRAPPROC( s, cyg_uint16, 3, get_splus ); + SAFEPROC( s, cyg_uint16, 4, get_splus ); + } + + CYG_TEST_PASS( "Mixture of accesses OK" ); + } +} + +// ------------------------------------------------------------------------- + +externC void +skip_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data, + CYG_ADDRWORD stackpointer); + +externC void +fail_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data, + CYG_ADDRWORD stackpointer); + +// ------------------------------------------------------------------------- + +void sparc_ex_main( void ) +{ + int i; + + CYG_TEST_INIT(); + + for ( i = CYGNUM_HAL_EXCEPTION_MIN; i <= CYGNUM_HAL_EXCEPTION_MAX; i++ ){ + int j; + HAL_TRANSLATE_VECTOR( i, j ); + HAL_INTERRUPT_ATTACH( j, &fail_exception_handler, j, 0 ); + // we must also ensure that eCos handles the exception; + // do not drop into CygMon or equivalent. + // Leave USER_TRAP undisturbed so that breakpoints work. + if ( CYGNUM_HAL_VECTOR_USER_TRAP != i ) { + extern void hal_default_exception_vsr( void ); + HAL_VSR_SET( i, (CYG_ADDRESS)hal_default_exception_vsr, NULL ); + } + } + + HAL_TRANSLATE_VECTOR( CYGNUM_HAL_VECTOR_UNALIGNED, i ); + HAL_INTERRUPT_DETACH( i, &fail_exception_handler ); + HAL_INTERRUPT_ATTACH( i, &skip_exception_handler, i, 0 ); + + CYG_TEST_INFO( "Vectors attached OK; calling do_test" ); + + do_test(); + + CYG_TEST_EXIT( "Done" ); +} + +// ------------------------------------------------------------------------- +externC void +skip_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data, + CYG_ADDRWORD stackpointer) +{ + HAL_SavedRegisters *save; + HAL_FrameStructure *frame; + + HAL_FLUSH_REGISTERS_TO_STACK(); + + save = (HAL_SavedRegisters *) stackpointer; + frame = (HAL_FrameStructure *) (save + 1); // immediately after + + // now, this is the invokation environment when this saved regset + // was created (copied from hal_xvsr.S): + // ! here,locals have been set up as follows: + // ! %l0 = psr (with this CWP/window-level in it) + // ! %l1 = pc + // ! %l2 = npc + // ! %l3 = vector number (16-25 for traps) + // ! and we are in our own register window, though it is likely that + // ! the next one will need to be saved before we can use it: + // ! ie. this one is the invalid register window. + // and the intention is that we can mess therewith: + + // Check we're not in a trap loop + if ( trap == save->li.l[1] ) { + same++; + if ( 10 < same ) + CYG_TEST_FAIL_EXIT( "Repeated trap" ); + } + else // restart the count + same = 0; + + // and record it + trap = save->li.l[1]; + tcount++; + + // now step on so that we return to the instruction after: + save->li.l[1] = save->li.l[2]; // PC := NPC + save->li.l[2] += 4; // NPC += 4 + + // that's all. +} + +externC void +fail_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data, + CYG_ADDRWORD stackpointer) +{ + HAL_FLUSH_REGISTERS_TO_STACK(); + CYG_TEST_FAIL_EXIT( "Other exception handler called" ); +} + +// ------------------------------------------------------------------------- + +externC void +#ifdef CYGPKG_KERNEL +cyg_user_start( void ) +#else +cyg_start( void ) +#endif +{ + sparc_ex_main(); +} + +// ------------------------------------------------------------------------- + +cyg_uint64 get_ll( cyg_uint64 *p ) +{ + return *p; +} + +cyg_uint64 get_llplus( cyg_uint64 *p ) +{ + cyg_uint64 ll = 0l, v; + ll = (cyg_uint32)p; + ll++; + v = *p; + v^= ll; + return v; +} + +cyg_uint32 get_i( cyg_uint32 *p ) +{ + return *p; +} + +cyg_uint32 get_iplus( cyg_uint32 *p ) +{ + cyg_uint32 i = 0, v; + i = (cyg_uint32)p; + i++; + v = *p; + v^= i; + return v; +} + +cyg_uint16 get_s( cyg_uint16 *p ) +{ + return *p; +} + +cyg_uint16 get_splus( cyg_uint16 *p ) +{ + cyg_uint16 s = 0, v; + s = (cyg_uint16)(0xffff & (cyg_uint32)p); + s++; + v = *p; + v^= s; + return v; +} + +// ------------------------------------------------------------------------- + +/* EOF sparc_ex.c */ diff --git a/ecos/packages/hal/sparclite/sim/current/ChangeLog b/ecos/packages/hal/sparclite/sim/current/ChangeLog new file mode 100644 index 0000000..1748446 --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/ChangeLog @@ -0,0 +1,273 @@ +2009-01-31 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_sparclite_sim.cdl: update compiler flags for gcc 4.x + +2003-07-18 Nick Garnett <nickg@balti.calivar.com> + + * cdl/hal_sparclite_sim.cdl: + Changed values for CYGNUM_HAL_RTC_NUMERATOR, + CYGNUM_HAL_RTC_DENOMINATOR and CYGNUM_HAL_RTC_PERIOD to + "default_value" from "calculated". This makes it easier + to change these values globally. + +2000-10-20 Jonathan Larmour <jlarmour@redhat.com> + + * include/pkgconf/mlt_sparclite_sim_ram.mlt: + Add heap1 section + + * include/pkgconf/mlt_sparclite_sim_ram.h: + * include/pkgconf/mlt_sparclite_sim_ram.ldi: + Regenerated + +2000-02-10 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sparclite_sim.cdl: Added. + +1999-11-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/mlt_sparclite_sim_ram.h: New file. + +1999-10-13 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/hal_sparclite_sim.h: Add define of + CYGHWR_HAL_SPARCLITE_HAS_ASR17 for arch HAL to DTRT with SVT + (anticipating cores with no SVT at all, so no %asr17) + +1999-04-08 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/*.ldi: Revised SECTION_* macro arguments to + avoid padded output sections (PR 19787) + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_priv.c: Remove bogus FIX ME; it wasn't true. + +1999-03-16 Hugo Tyson <hmt@cygnus.co.uk> + + * include/halboot.si: Add a dummy LED macro for debug in the + vectors.S; correct a scary line length. + +1999-03-04 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/hal_sparclite_sim.h: Take out DEVICES dependencies. + +1999-03-04 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/*.ldi: give all LDI files unique names so + that they can co-exist in an eCos build tree (PR 19184) + * include/pkgconf/*.mlt: give all MLT files unique names so + that they can co-exist in an eCos build tree (PR 19184) + +1999-02-25 Hugo Tyson <hmt@cygnus.co.uk> + + These log entries from 1999-02-22 to 1999-02-24 were executed in + a branch; this change is a merge of that branch into the trunk. + + (1999-02-23 John Dallaway <jld@cygnus.co.uk>) + + * include/pkgconf/hal_sparclite_sim.h: New rules + CYGPKG_HAL_SPARCLITE_SIM precludes CYGPKG_DEVICES_GDB + CYGPKG_HAL_SPARCLITE_SIM precludes CYGPKG_DEVICES_SERIAL_RS232_COMMON + + (1999-02-22 Hugo Tyson <hmt@cygnus.co.uk>) + + * src/hal_priv.c (hal_board_prestart, hal_board_poststart): + Shut down the erc32 watchdog in and enable interrupts in these two + new routines. + + * include/halboot.si: + Remove N/A code that I was just storing here, and install the real + vector instructions in this fragment; there be cache-wangling to + do in hardware cases either side of the vector installation. + +1999-02-20 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/hal_xpic.h: + Rename CYG_VECTOR_* -> CYGNUM_HAL_INTERRUPT_* + + * src/hal_priv.c: + Add a FIX ME + +1999-02-08 John Dallaway <jld@cygnus.co.uk> + + * src/sim.ld: Remove platform-specific linker script for + MLT compliance. + + * src/PKGconf.mak: Remove build rules for sim.ld. + + * include/pkgconf/ram.*: Add MLT save file and and linker + script fragment for RAM startup. + +1999-02-01 Hugo Tyson <hmt@cygnus.co.uk> + + * include/halboot.si: + New file: performs platform-oriented setup of RAM and cache + controllers, and quietens any interrupt sources. + + * include/pkgconf/hal_sparclite_sim.h: + Correct comments/CDL description of sim invocation. + +1999-01-28 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_cache.h: NEW FILE to this directory; moved here from + the sparclite/arch tree; cache control is very much board-specific + + * include/hal_clock.h: NEW FILE to this directory; it was a part + of hal_intr.h, but is now here because the clock is target determined. + + * include/hal_xpic.h: NEW FILE to this directory; it was a part of + hal_intr.h, but is now here because the detail of interrupot + control is target determined. + + * src/hal_priv.c: NEW FILE to this directory; it was a part + of hal_intr.h, but is now here because the clock is target + determined, and it's the clock that needs a local variable. + + * src/PKGconf.mak (COMPILE): compile it. + + +1999-01-26 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sim.ld: + Add copyright notice. (Though these files will later be generated + by a tool and so not copyright, these default setups are.) + +1999-01-22 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sim.ld: + Remove some bogus comments. + +1999-01-21 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * src/sim.ld: + Remove all traces of non-CYG_KERNEL_USE_INIT_PRIORITY code + +1999-01-21 Hugo Tyson <hmt@cygnus.co.uk> + + * src/sim.ld: + Align bss and rom/ram_data starts and ends by 8 bytes to permit + fast copy routines. + +1999-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + Modified files in arch: + * include/hal_arch.h + * include/hal_intr.h + * src/PKGconf.mak + * src/context.S + * src/hal_intr.c + * src/vec_ivsr.S + * src/vec_xvsr.S + * src/vectors.S + + New files in arch: + * src/hal_boot.c (bss initialization, constructors &c) + * include/hal_cache.h (empty but required header) + + Modified files in sim: + * include/hal_diag.h + + Lots more progress; essentially, everything now works. + + Simulator's treatment of stdio is poor though, it doesn't work + under pkgtest. This has been slowing me up. + +1999-01-14 Hugo Tyson <hmt@cygnus.co.uk> + + * ecc/ecc/hal/sparclite/...: + + Initial checkin of SPARClite HAL; it doesn't work yet, except the + most trivial of tests - timer and interrupt manipulation stuff is + entirely absent. + + Here's some documentation of the initial checkin tree; this will + change, as platform dependent stuff moves correctly into the sim + or <board> directories. + + arch/current/include: + basetype.h nothing much here. + vectors.h definitions of symbols shared between the + various vector code assembler files, can be + included in both C and assembler. + hal_intr.h various macros for clock and interrupt + control plus the eCos vector numbering scheme; we + map thus: + what SPARC trap type eCos vector numbers + ----------------------------------------------- + (not used) --- 0 + interrupts (17-31) 1-15 + user traps (128-255) 16 + exceptions (1-9,36==4) 17-25 + others (10,?) 26 + ----------------------------------------------- + Trap types 5 and 6 which would be eCos vectors 21 + and 22 are handled in the trampoline code in + file src/vectors.S + hal_arch.h definition of a thread context, plus + macros for thread switching and the like. Some + ancillary bit twiddling macros and cache barriers + too. + + arch/current/include/pkgconf: + hal_sparclite.h pkgconf config/header file. + + arch/current/src: + vectors.S boot-up stuff, trampoline code that hangs + on the interrupt/trap vector, handlers for window + under/overflow. Saves some state in registers + then jumps to the interrupt or exception VSR + respectively. + Also instantiates the VSR table. + vec_ivsr.S the default interrupt VSR; it establishes + a C calling environment (ie. anticipates a window + overflow) then locks the scheduler, calls the ISR + with appropriate arguments, and then interrupt_end() + before undoing that environment, anticipating + window underflow and returning to the interrupted + instruction. + vec_xvsr.S the default exception AKA trap VSR; does + the same as the interrupt one but without the + scheduler lock or interrupt end. + hal_intr.c instantiates the ISR table used by the + code above. + context.S context switch code, saves and loads up a + whole register state, coroutine or longjump-like. + icontext.c initializes a context to "jump" to in + context.S at the birth of a new thread. + + sim/current/include: + hal_diag.h macros to deal with debugging output via a + fake serial device of some kind; initially empty, + but definitely board/sim dependent. + + sim/current/include/pkgconf: + hal_sparclite_sim.h pkgconf config/header file. + + sim/current/src: + sim.ld linker script bits for "sim" target. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== + +//EOF ChangeLog diff --git a/ecos/packages/hal/sparclite/sim/current/cdl/hal_sparclite_sim.cdl b/ecos/packages/hal/sparclite/sim/current/cdl/hal_sparclite_sim.cdl new file mode 100644 index 0000000..2da2364 --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/cdl/hal_sparclite_sim.cdl @@ -0,0 +1,204 @@ +# ==================================================================== +# +# hal_sparclite_sim.cdl +# +# SPARClite/SIM target HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: hmt +# Contributors: +# Date: 2000-02-10 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_SPARCLITE_SIM { + display "SPARClite minimal simulator" + parent CYGPKG_HAL_SPARCLITE + define_header hal_sparclite_sim.h + include_dir cyg/hal + description " + The minimal simulator HAL package is provided for when only a + simple simulation of the processor architecture is desired, as + opposed to detailed simulation of any specific board. To use + this minimal simulator the command `target sim -nfp -sparclite + -dumbio' should be used from inside gdb. It is not possible to + use any of the eCos device drivers when the simulator is running + in this mode" + + compile hal_priv.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sparclite.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sparclite_sim.h>" + puts $::cdl_header "#define CYGHWR_HAL_SPARCLITE_HAS_ASR17 /* true for SIM */" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the SPARClite simulator only the RAM startup type + is usable." + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 9999 + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "sparclite-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-msoft-float -mcpu=sparclite -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions " } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-msoft-float -mcpu=sparclite -g -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGPKG_HAL_SPARCLITE_SIM_OPTIONS { + display "SPARClite simulator build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_HAL_SPARCLITE_SIM_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the SPARClite simulator HAL. These flags are + used in addition to the set of global flags." + } + + cdl_option CYGPKG_HAL_SPARCLITE_SIM_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the SPARClite simulator HAL. These flags are + removed from the set of global flags if present." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { "sparclite_sim_ram" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_sparclite_sim_ram.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_sparclite_sim_ram.h>" } + } + } +} diff --git a/ecos/packages/hal/sparclite/sim/current/include/hal_cache.h b/ecos/packages/hal/sparclite/sim/current/include/hal_cache.h new file mode 100644 index 0000000..aefa2af --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/include/hal_cache.h @@ -0,0 +1,181 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL Cache control support (such as it is in the simulator) +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1999-01-28 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// the caches. +// +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// SPARClite cache macros + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +#define HAL_DCACHE_SIZE 0x800 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line +#define HAL_DCACHE_WAYS 4 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 0x800 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line +#define HAL_ICACHE_WAYS 4 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() +// Disable the data cache +#define HAL_DCACHE_DISABLE() +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache - use Data cache controls since they +// are not separatable. + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC(); HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h diff --git a/ecos/packages/hal/sparclite/sim/current/include/hal_clock.h b/ecos/packages/hal/sparclite/sim/current/include/hal_clock.h new file mode 100644 index 0000000..36ade9c --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/include/hal_clock.h @@ -0,0 +1,133 @@ +#ifndef CYGONCE_HAL_CLOCK_H +#define CYGONCE_HAL_CLOCK_H + +//============================================================================= +// +// hal_clock.h +// +// HAL clock support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1999-01-28 +// Purpose: Define clock support +// Description: The macros defined here provide the HAL APIs for handling +// the clock. +// +// Usage: +// #include <cyg/hal/hal_intr.h> // which includes this file +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/hal/hal_io.h> + +//----------------------------------------------------------------------------- +// Clock control + +// in erc32 simulator: +// 4 = UART A +// 5 = UART B +// 7 = UART error +// 12 = GPT (general purpose timer) +// 13 = RTC (realtime clock) +// 15 = watchdog + +// in erc32 simulator: + +// The vector used by the Real time clock is defined in hal_xpic.h + +// We could place conditional code here to choose one clock or the other +// depending on the selected interrupt vector... but pro tem: (pun intended) + +#define SPARC_MEC_RTC_CLOCK_SCALE (5) + +/* These must be accessed word-wide to work! */ + +#define SPARC_MEC_RTC (0x01f80080) + +#define SPARC_MEC_RTC_COUNTER (SPARC_MEC_RTC + 0) +#define SPARC_MEC_RTC_SCALER (SPARC_MEC_RTC + 4) + +#define SPARC_MEC_GPT_COUNTER (SPARC_MEC_RTC + 8) +#define SPARC_MEC_GPT_SCALER (SPARC_MEC_RTC + 0x0c) + +/* MEC timer control register bits */ +#define SPARC_MEC_TCR_GACR 1 /* Continuous Running */ +#define SPARC_MEC_TCR_GACL 2 /* Counter Load */ +#define SPARC_MEC_TCR_GASE 4 /* System Enable */ +#define SPARC_MEC_TCR_GASL 8 /* not used */ +#define SPARC_MEC_TCR_TCRCR 0x100 /* Continuous Running */ +#define SPARC_MEC_TCR_TCRCL 0x200 /* Counter Load */ +#define SPARC_MEC_TCR_TCRSE 0x400 /* System Enable */ +#define SPARC_MEC_TCR_TCRSL 0x800 /* not used */ + +#define SPARC_MEC_RTC_CONTROL (SPARC_MEC_RTC + 0x18) + +externC cyg_int32 cyg_hal_sparclite_clock_period; + +#define HAL_CLOCK_INITIALIZE( _period_ ) CYG_MACRO_START \ + HAL_WRITE_UINT32( SPARC_MEC_RTC_SCALER, SPARC_MEC_RTC_CLOCK_SCALE );\ + cyg_hal_sparclite_clock_period = (_period_); \ + HAL_WRITE_UINT32( SPARC_MEC_RTC_COUNTER, (_period_) ); \ + HAL_WRITE_UINT32( SPARC_MEC_RTC_CONTROL, \ + (SPARC_MEC_TCR_TCRCR | \ + SPARC_MEC_TCR_TCRCL | \ + SPARC_MEC_TCR_TCRSE) ); \ +CYG_MACRO_END + +#define HAL_CLOCK_RESET( _vector_, _period_ ) /* nowt, it is freerunning */ + +#define HAL_CLOCK_READ( _pvalue_ ) CYG_MACRO_START \ + cyg_uint32 _read_; \ + HAL_READ_UINT32( SPARC_MEC_RTC_COUNTER, _read_ ); \ + *((cyg_uint32 *)(_pvalue_)) = \ + (cyg_hal_sparclite_clock_period - _read_ ); \ +CYG_MACRO_END + + +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY +#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( _pvalue_ ) +#endif + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CLOCK_H +// End of hal_clock.h diff --git a/ecos/packages/hal/sparclite/sim/current/include/hal_diag.h b/ecos/packages/hal/sparclite/sim/current/include/hal_diag.h new file mode 100644 index 0000000..d0e14cc --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/include/hal_diag.h @@ -0,0 +1,135 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-01-11 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +/*---------------------------------------------------------------------------*/ + +#define CYG_DIAG_USE_ERC32 + +/*---------------------------------------------------------------------------*/ + +#ifdef CYG_DIAG_USE_ERC32 + +/*---------------------------------------------------------------------------*/ +/* Register addresses */ + +#define SPARC_MEC_UART (0x01f800e0) + +/* These must be accessed word-wide to work! */ +#define SPARC_MEC_UART_IO( x ) ((cyg_uint32)(x)) + +#define SPARC_MEC_UART_A_RX ((volatile cyg_uint32 *)(SPARC_MEC_UART + 0)) +#define SPARC_MEC_UART_A_TX ((volatile cyg_uint32 *)(SPARC_MEC_UART + 0)) +#define SPARC_MEC_UART_B_RX ((volatile cyg_uint32 *)(SPARC_MEC_UART + 4)) +#define SPARC_MEC_UART_B_TX ((volatile cyg_uint32 *)(SPARC_MEC_UART + 4)) +#define SPARC_MEC_UART_STATUS ((volatile cyg_uint32 *)(SPARC_MEC_UART + 8)) +#define SPARC_MEC_UART_RXAMASK (0x00006) +#define SPARC_MEC_UART_RXBMASK (0x60000) +#define SPARC_MEC_UART_TXAMASK (0x00001) +#define SPARC_MEC_UART_TXBMASK (0x10000) + + +/*---------------------------------------------------------------------------*/ + +#define HAL_DIAG_INIT() + +#define HAL_DIAG_WRITE_CHAR(_c_) \ +{ \ + if( 1 || _c_ != '\r' ) \ + { \ + while( (SPARC_MEC_UART_RXAMASK & *SPARC_MEC_UART_STATUS) == 0 ) \ + continue; \ + *SPARC_MEC_UART_A_TX = SPARC_MEC_UART_IO(_c_); \ + } \ +} + +#define HAL_DIAG_READ_CHAR(_c_) \ +{ \ + while( (SPARC_MEC_UART_TXAMASK & *SPARC_MEC_UART_STATUS) == 0 ) \ + continue; \ + _c_ = (char)*SPARC_MEC_UART_A_TX; \ +} + +#define XHAL_DIAG_WRITE_CHAR(_c_) \ +{ \ + if( _c_ != '\r' ) \ + { \ + *SPARC_MEC_UART_A_TX = SPARC_MEC_UART_IO(_c_); \ + } \ +} + +#define XHAL_DIAG_READ_CHAR(_c_) \ +{ \ + _c_ = (char)*SPARC_MEC_UART_A_TX; \ +} + +#else +/*---------------------------------------------------------------------------*/ +/* There is no diagnostic output on SPARCLITE simulator */ + +#define HAL_DIAG_INIT() + +#define HAL_DIAG_WRITE_CHAR(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) (_c_) = 0 + +#endif + +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */ +#endif /* CYGONCE_HAL_HAL_DIAG_H */ diff --git a/ecos/packages/hal/sparclite/sim/current/include/hal_xpic.h b/ecos/packages/hal/sparclite/sim/current/include/hal_xpic.h new file mode 100644 index 0000000..13ebc20 --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/include/hal_xpic.h @@ -0,0 +1,119 @@ +#ifndef CYGONCE_HAL_XPIC_H +#define CYGONCE_HAL_XPIC_H + +//============================================================================= +// +// hal_xpic.h +// +// HAL eXternal Programmable Interrupt Controller support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1999-01-28 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// an external interrupt controller, and which interrupt is +// used for what. +// +// Usage: +// #include <cyg/hal/hal_intr.h> // which includes this file +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/hal/hal_io.h> + +//----------------------------------------------------------------------------- +// Interrupt controller access + +// in erc32 simulator: +// 4 = UART A +// 5 = UART B +// 7 = UART error +// 12 = GPT (general purpose timer) +// 13 = RTC (realtime clock) +// 15 = watchdog + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_13 + + +/* These must be accessed word-wide to work! */ +#define SPARC_MEC_INTCON (0x01f80000) + +#define SPARC_MEC_INTCON_PENDING (SPARC_MEC_INTCON + 0x48) +#define SPARC_MEC_INTCON_MASK (SPARC_MEC_INTCON + 0x4c) +#define SPARC_MEC_INTCON_CLEAR (SPARC_MEC_INTCON + 0x50) +#define SPARC_MEC_INTCON_FORCE (SPARC_MEC_INTCON + 0x54) + + +#define HAL_INTERRUPT_MASK( _vector_ ) CYG_MACRO_START \ + cyg_uint32 _traps_, _mask_; \ + HAL_DISABLE_TRAPS( _traps_ ); \ + HAL_READ_UINT32( SPARC_MEC_INTCON_MASK, _mask_ ); \ + _mask_ |= ( 1 << (_vector_) ); \ + HAL_WRITE_UINT32(SPARC_MEC_INTCON_MASK, _mask_ ); \ + HAL_RESTORE_INTERRUPTS( _traps_ ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK( _vector_ ) CYG_MACRO_START \ + cyg_uint32 _traps_, _mask_; \ + HAL_DISABLE_TRAPS( _traps_ ); \ + HAL_READ_UINT32( SPARC_MEC_INTCON_MASK, _mask_ ); \ + _mask_ &=~ ( 1 << (_vector_) ); \ + HAL_WRITE_UINT32( SPARC_MEC_INTCON_MASK, _mask_ ); \ + HAL_RESTORE_INTERRUPTS( _traps_ ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) CYG_MACRO_START \ + cyg_uint32 _traps_; \ + HAL_DISABLE_TRAPS( _traps_ ); \ + HAL_WRITE_UINT32( SPARC_MEC_INTCON_CLEAR, ( 1 << (_vector_) ) ); \ + HAL_RESTORE_INTERRUPTS( _traps_ ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) /* nothing */ + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) /* nothing */ + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_XPIC_H +// End of hal_xpic.h diff --git a/ecos/packages/hal/sparclite/sim/current/include/halboot.si b/ecos/packages/hal/sparclite/sim/current/include/halboot.si new file mode 100644 index 0000000..2bcb2ba --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/include/halboot.si @@ -0,0 +1,94 @@ +#ifndef CYGONCE_HAL_HALBOOT_SI /* -*-asm-*- */ +#define CYGONCE_HAL_HALBOOT_SI +// ==================================================================== +// +// <platform>/halboot.si +// +// HAL bootup platform-oriented code (assembler) +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-02-01 +// Purpose: Bootup code, platform oriented. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// External Platform Initial Setup +// +// This should set up RAM and caches, and calm down any external +// interrupt sources. +// +// It is just plain included in vectors.S +// +// RAM has not yet been touched at all; in fact all you have is a +// register window selected. + + + ! Empty macro for debugging vectors.S + .macro led val + .endm + + ! First of all - before setting up the stack - set + ! the available memory to the full 4Mb; +#define MEC_MEMCFG (0x01f80010) + sethi %hi( MEC_MEMCFG ), %g1 + ld [ %g1 + %lo(MEC_MEMCFG) ], %g2 + mov 7, %g3 + sll %g3, 10, %g3 ! Bits 10,11,12 are of interest + andn %g2, %g3, %g2 + mov 4, %g3 + sll %g3, 10, %g3 ! Bits 10,11,12 are of interest + or %g2, %g3, %g2 ! Shift 256k left 4 times to + st %g2, [ %g1 + %lo(MEC_MEMCFG) ] + ! ...give memsize of 4Mb + + ! then copy the branch instructions into the vector + rd %tbr, %g1 + andn %g1, 0xfff, %g1 ! clear non-address bits + sethi %hi(real_vector_instructions), %l0 + or %l0, %lo(real_vector_instructions), %l0 + ld [ %l0 ], %l1 + st %l1, [ %g1 ] ! into the vector + ld [ %l0 + 4 ], %l1 + st %l1, [ %g1 + 4 ] ! into the vector + +#endif /* CYGONCE_HAL_HALBOOT_SI */ +/* EOF halboot.si */ diff --git a/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.h b/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.h new file mode 100644 index 0000000..d1be417 --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Fri Oct 20 08:18:20 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x2000000) +#define CYGMEM_REGION_ram_SIZE (0x80000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x2080000 - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.ldi b/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.ldi new file mode 100644 index 0000000..85f4cc9 --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.ldi @@ -0,0 +1,26 @@ +// eCos memory layout - Fri Oct 20 08:18:20 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x2000000, LENGTH = 0x80000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x2000000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.mlt b/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.mlt new file mode 100644 index 0000000..72ef7a3 --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/include/pkgconf/mlt_sparclite_sim_ram.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 2000000 80000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 2000000 2000000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 1 0 1 0 1 0 1 bss bss ! +section bss 0 8 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! diff --git a/ecos/packages/hal/sparclite/sim/current/src/hal_priv.c b/ecos/packages/hal/sparclite/sim/current/src/hal_priv.c new file mode 100644 index 0000000..cbbdfb5 --- /dev/null +++ b/ecos/packages/hal/sparclite/sim/current/src/hal_priv.c @@ -0,0 +1,78 @@ +//=========================================================================== +// +// hal_priv.c +// +// SPARClite Architecture sim-specific private variables +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-02-20 +// Purpose: private vars for SPARClite sim. +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arch.h> + +// ------------------------------------------------------------------------ +// Clock static to keep period recorded. +cyg_int32 cyg_hal_sparclite_clock_period = 0; + +// ------------------------------------------------------------------------ +// Board specific startups. + +extern void hal_board_prestart( void ); +extern void hal_board_poststart( void ); + +#define WATCHDOG() *((int *)0x01f80064) = (int)0x00000000 // watchdog off + +void hal_board_prestart( void ) +{ + WATCHDOG(); // Turn off the ERC32 watchdog. +} + +void hal_board_poststart( void ) +{ + HAL_ENABLE_INTERRUPTS(); + // OK to do this post constructors, and good for testing. +} + +// EOF hal_priv.c diff --git a/ecos/packages/hal/sparclite/sleb/current/ChangeLog b/ecos/packages/hal/sparclite/sleb/current/ChangeLog new file mode 100644 index 0000000..b35de60 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/ChangeLog @@ -0,0 +1,504 @@ +2009-01-31 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_sparclite_sleb.cdl: update compiler flags for gcc 4.x + +2003-07-18 Nick Garnett <nickg@balti.calivar.com> + + * cdl/hal_sparclite_sleb.cdl: + Changed values for CYGNUM_HAL_RTC_NUMERATOR, + CYGNUM_HAL_RTC_DENOMINATOR and CYGNUM_HAL_RTC_PERIOD to + "default_value" from "calculated". This makes it easier + to change these values globally. + +2002-04-29 Jonathan Larmour <jlarmour@redhat.com> + + * src/hal_cygm.S: + Don't use .file as it can confuse debugging since the .file + doesn't contain the path and therefore the debugger will never + know where it lives! This conflicts with using -Wa,--gstabs. + +2000-10-20 Jonathan Larmour <jlarmour@redhat.com> + + * tests/slebtime.cxx: Ensure default priority constructors + are called. + +2000-10-20 Jonathan Larmour <jlarmour@redhat.com> + + * include/pkgconf/mlt_sparclite_sleb_ram.mlt: + * include/pkgconf/mlt_sparclite_sleb_rom.mlt: + Add heap1 section + + * include/pkgconf/mlt_sparclite_sleb_ram.h: + * include/pkgconf/mlt_sparclite_sleb_rom.h: + * include/pkgconf/mlt_sparclite_sleb_ram.ldi: + * include/pkgconf/mlt_sparclite_sleb_rom.ldi: + Regenerated + +2000-02-16 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sparclite_sleb.cdl: removed fix me + +2000-02-07 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sparclite_sleb.cdl: use cpu options when linking. + +2000-02-04 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/hal_sparclite_sleb.cdl (define_proc): Add output of a + #define for CYGHWR_HAL_SPARCLITE_HAS_ASR17 - because a Fujitsu + SPARClite does. + +2000-01-24 John Dallaway <jld@cygnus.co.uk> + + * cdl/*.cdl: + + Remove obsolete option CYGTST_TESTING_IDENTIFIER. + +2000-01-19 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/*.cdl: Add descriptions to a number of options &c which were + lacking same, also tidied up other typos as noticed en passant. + +1999-12-20 Gary Thomas <gthomas@cygnus.co.uk> + + * cdl/hal_sparclite_sleb.cdl: Add -Wl for linker options. + +1999-11-25 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/mlt_sparclite_sleb_rom.h: + * include/pkgconf/mlt_sparclite_sleb_ram.h: New file(s). + +1999-11-03 John Dallaway <jld@cygnus.co.uk> + + * cdl/hal_sparclite_sleb.cdl: Define build options. + +1999-11-01 Jesper Skov <jskov@cygnus.co.uk> + + * cdl/hal_sparclite_sleb.cdl: Added. + Use define_proc for const header defs. + +1999-10-14 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/mlt_sparclite_sleb_ram.mlt, + include/pkgconf/mlt_sparclite_sleb_rom.mlt: + + Fix .mlt files to match the latest .ldi files. ROM startup + requires latest config tool which contains fix for PR 19799. + +1999-10-13 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/hal_sparclite_sleb.h: Add CDL and + [un]definitions for handling optional Multiple Vector Trapping and + optional copy of vectors into RAM - when it is optional. Also + define CYGHWR_HAL_SPARCLITE_HAS_ASR17 so that the arch HAL + self-configures correctly. + + * include/halboot.si: Copy trampoline code into section + .ram_vectors at __ram_vectors_start if so configured. + + * include/pkgconf/mlt_sparclite_sleb_ram.ldi: + * include/pkgconf/mlt_sparclite_sleb_ram.mlt: + * include/pkgconf/mlt_sparclite_sleb_rom.ldi: + * include/pkgconf/mlt_sparclite_sleb_rom.mlt: + Link in new variable size, sometimes 0 size, ram_vectors section; + this does away with the need to fib about the size of RAM, it was + previously defined to start at 0x4000200 to reserve a bit for + trampoline code. + (comment from the example .ldi files...) + The ram_vectors section is to allow some free space to copy + vectors into from the ROM. This is required to be variable size + to accomodate SVT or MVT; 80 bytes vs 4kB. Copying is not + necessary with MVT, but it is optional because it may offer + performance gains. Copying is required for SVT because the + (aligned) start of ROM contains initialization instructions. RAM + copy is used rather than leave a big gap in the ROM to get an + aligned address for the trampoline code. For RAM startup, + ram_vectors will usually be of size zero, unless MVT and copying + are enabled for memory estimation reasons. + +1999-06-14 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/slebtime.cxx (entry2): Fix a dumb fencepost prob in some + string poking code for output without printf... + +1999-04-23 Jesper Skov <jskov@cygnus.co.uk> + + * src/hal_diag.c (hal_bsp_console_write): Added a workaround for PR + 19926. + +1999-04-09 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_cache.h (HAL_[DI]CACHE_IS_ENABLED): + Implement these macros. + +1999-04-09 Hugo Tyson <hmt@cygnus.co.uk> + + * include/halboot.si: Use 10 wait states for access to the 86940 + on CS1; it seems to make the Reliability Difference(tm). + +1999-04-08 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/slebtime.cxx: Add CYG_INIT_PRIORITY( APPLICATION ) to the + two static thread objects so that the test works even when libc + steals away the default constructors. Unfortunately this also + means switching to an assignment constructor instead of a call. + +1999-04-08 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/*.ldi: Revised SECTION_* macro arguments to + avoid padded output sections (PR 19787) + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_hwio.h: New file: define accessors for 86940 via + alternate address space 4, register names and all that... just a + paste out of previous hal_diag.h - it was the wrong place, but + that's how it evolved. + + * include/hal_diag.h: Include hal_hwio.h to get accessors for + 86940 et al. Do not define them here, it was the wrong place. + + * include/hal_clock.h: + * include/hal_xpic.h: + Include hal_hwio.h instead of hal_diag.h + +1999-04-07 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/slebintr.c (checkallbut): This is a more informative + version of the test when it fails: this is still under + investigation somewhat, and running the more verbose version + nightly will be useful. + +1999-03-30 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/slebintr.c (start): After some thought, the timing code in + here could cause the test to take arbitrarily long; so some safety + features added. Normally the test loop is very fast, but with + cache effects and instrumentation and -O0 it could take ages; this + could explain the occasional timeouts we have seen for this test. + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_cache.h: + Implement the cache control macros: at least + for x in ( D I ) + HAL_xCACHE_ENABLE/DISABLE + HAL_xCACHE_INVALIDATE_ALL, HAL_xCACHE_SYNC + in the first instance. kcache1 reports sensible numbers too! + +1999-03-26 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/slebintr.c (HAL_CLOCK_READ): If there is no kernel, the + clock is not initialized, so looking at it is useless for a clue. + So provide a dummy so we perform a "few" loops when there's no + kernel. If there is no kernel, cyg_user_start() is never called, + main gets in and steals the CPU. So we hang. So if there is no + kernel, define cyg_start() instead to wrest control. Also very + much weaken the looping count check; kernel instrumentation, for + example, is more than enough to slow the world down too much. + + * tests/slebstak.c (cyg_[user_]start): + If there is no kernel, cyg_user_start() is never called, main gets + in and steals the CPU. So we hang. So if there is no kernel, + define cyg_start() instead to wrest control. + + * tests/slebtime.cxx: + Make this build when no kernel present; include of testcase &c + was the wrong side of the ifdef. Doh! + +1999-03-25 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_priv.c (hal_clock_initialize): Oh dear, the clock was + only running half the speed it should have; this will make the + tm_basic figures look bad, maybe. It _appeared_ right because of + spurious interrupts, making two ISRs per tick, which covered the + error beautifully. So, the initialization is now corrected, now + that the interrupt management is better dealt with. + + * include/hal_xpic.h (HAL_INTERRUPT_ACKNOWLEDGE): Loop until + either the interrupt has stopped being asserted by the + prioritization latch (CLIRL) or the source has actually re-flagged + the interrupt, so that repeated, fast interrupts will re-interrupt + rather than causing a loop here. This is to prevent spurious + double interrupts caused by HAL_INTERRUPT_ACKNOWLEDGE() not taking + effect before the CPU re-enabled interrupts; this had been + covering the clock bug as well as confusing the serial system. + + Also placed a HAL_INTERRUPT_ACKNOWLEDGE() in + HAL_INTERRUPT_CONFIGURE() since the doc implies it is necessary + when changing that stuff; a spurious interrupt may be latched. + +1999-03-24 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_xpic.h (HAL_INTERRUPT_CONFIGURE): + Implement this functionality, since Gary wanted to experiment with + it. Also add HAL_INTERRUPT_QUERY_INFO (platform specific) to read + back the settings of a particular interrupt source. + + * tests/slebintr.c: NEW FILE: test case for the above new macros. + * tests/slebstak.c: NEW FILE: tests the register save/restore code + by carrying out lots of factorial calculations. + * tests/slebtime.c: NEW FILE: tests HAL clocks for sanity; prints + useful diagnostics. Most useful when a human observes, if + it goes wrong this test is more likely to report a timeout + than a failure. + + * tests/sleb.c: FILE DELETED - moved to slebstak.c + + * tests/PKGconf.mak (TESTS): Reflect above changes. + +1999-03-23 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_sparclite_sleb.h: Modify display string + for consistency. + +1999-03-23 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_diag.c (hal_diag_write_char): Precisely undo the + previous change: we disable interrupts to prevent the clock + advancing during the time taken to output to GDB. + +1999-03-18 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_diag.c (hal_diag_write_char_serial): Do not disable + interrupts while calling the CygMon write-line routine; CygMon is + better now and can cope with interrupts there. + +1999-03-17 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/mlt_sparclite_sleb_rom.mlt: Regenerate using + the eCos configuration tool to resolve errors. + +1999-03-17 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/mlt_sparclite_sleb_rom.mlt: + * include/pkgconf/mlt_sparclite_sleb_rom.ldi: + Move the start of RAM up 512 bytes; it is now at 0x04000200. This + is to leave space for the trampoline code ie. RAM trap vector + handler to live in RAM as is required. NB the vector must be on a + 4k boundary; its location is determined by rounding down the start + of "normal" RAM ie. the symbol ".data". So if the start of RAM + isn't on a 4k boundary, or the trampoline code gets > 4k, there + will be trouble. + + * include/halboot.si: Copy trampoline code into RAM base during + startup, and deal with associated caching issues. + + * src/hal_priv.c (LED): Add this tidier macro and some extra LED + debug during start for help with ROM start. + + * include/pkgconf/hal_sparclite_sleb.h + (CYGHWR_HAL_SPARCLITE_SLEB_STARTUP): Add this define and its + associated notCDL for the GUI Config tool. + +1999-03-16 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/mlt_sparclite_sleb_rom.ldi: + * include/pkgconf/mlt_sparclite_sleb_rom.mlt: + New files, linker script fragment and MLT doc for ROM startup. + + * include/halboot.si: Only copy real instructions into the vector + if RAM startup. Delete lots of obsolete debugging "printout". + Size RAM dynamically. Set up chip selects, wait states, refresh + timing, system services, caches, buffers, burst mode access, ... + In other words complete hardware initialization. + + * include/hal_cpu.h: new file, taken directly from CygMon sources, + which defines various MB8683x internal registers which are used in + the initialization in halboot.si. + + * include/hal_diag.h (HAL_SPARC_86940_PRS_ODIV2): Add lots more + definition of the MB86940 companion I/O chip, editted from CygMon + sources. This should move into a proper IO file later. + Also, in the non-CYG_KERNEL_DIAG_GDB case where we write output to + the serial line in clear, do perform initialization. + + * src/hal_diag.c (hal_diag_init): Properly initialize the serial + line when not using GDB encoding (if GDB coding is in use, then we + have CygMon). + + * include/hal_clock.h (HAL_CLOCK_INITIALIZE): Initialize the clock + more cleanly and correctly, as CygMon does: so ticks are actually + centiSeconds, pretty much. Actual init routine is in hal_priv.c. + + * src/hal_priv.c (hal_clock_initialize): Properly initialize the + system clock to centiSeconds. + +1999-03-11 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_priv.c (hal_board_prestart): + Link in the multi-thread aware debugging routine if + CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT. + +1999-03-09 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_priv.c (hal_board_prestart): If playing nice with + CygMon, unmask and pass through interrupt 14 (Ethernet + controller). Install and unmask interrupt 15 (NMI button) + likewise. + + * src/hal_cygm.S (hal_nmi_handler): Add new handler for the NMI + interrupt (like a PIN number) INT15, the button near the serial + connector on the board. The handler must wait for the interrupt + to go away, then acknowledge it to prevent CygMon getting in a + loop. + + * include/halboot.si: Set IRC channel 14 (Ethernet controller) + interrupt to active low so that we can pass such events on to + CygMon. Tidy up comments and ifdefs. + + * include/hal_cygm.h (BSP_NOTVEC_BSP_COMM_PROCS): Define the + CygMon vector table entry that isn't a vector, but is a pointer to + struct tree with IO functions therein. + + * src/hal_diag.c (hal_diag_write_char et al): Add variants of + these routines to use IO functions provided by CygMon if thus + configured. Also tidied up direct GDB-ized serial output, which + is selected by CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT within + CYG_KERNEL_DIAG_GDB now. + + * include/pkgconf/hal_sparclite_sleb.h: Add definition for + CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT, disabled by default. More + comments too. + +1999-03-04 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/*.ldi: give all LDI files unique names so + that they can co-exist in an eCos build tree (PR 19184) + * include/pkgconf/*.mlt: give all MLT files unique names so + that they can co-exist in an eCos build tree (PR 19184) + +1999-02-25 Hugo Tyson <hmt@cygnus.co.uk> + + These log entries from 1999-02-22 to 1999-02-24 were executed in + a branch; this change is a merge of that branch into the trunk. + +1999-02-25 Hugo Tyson <hmt@masala.cygnus.co.uk> + + * src/hal_diag.c (hal_diag_write_char): + Wait for the GDB protocol ack character '+' after sending a line + of output as a $O packet; this prevents mismatches of the GDB + protocol when a breakpoint is hit temporally near such output. + This has the side effect that we must deal with seeing a ^C + character instead of the '+', whence we must bounce into CygMon's + BREAK vector using a trap. Hence the next change... + + * src/hal_cygm.S (hal_user_trap_to_cygmon_vsr): + Add additional "bounce to cygmon" capability such that user trap + 2, "ta 2" trap type 130, does the same as "ta 1" ie. a breakpoint, + but first it advances the PC and NPC so that you can continue at + the instruction after. This is so that a voluntary inline + breakpoint can be implemented as "ta 2; nop; nop; nop" (nops just + for paranoia). + +1999-02-24 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/hal_diag.h: + Make hal_diag_init() and hal_diag_write_char() prototypes be extern "C" + for C++ files so they don't get name mangled + +1999-02-24 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_sparclite_sleb.h: Add MB8683x board + designation to description field. + +1999-02-24 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/hal_sparclite_sleb.h: + Non-CDLoptions, but #defines nontheless, + CYG_HAL_USE_ROM_MONITOR_CYGMON and CYG_KERNEL_DIAG_GDB are defined + here to control whether we cooperate with CygMon, and if so, do we + encapsulate out output in GDB $O packets, respectively. + + * include/hal_cygm.h: + New file to describe the CygMon vectors we call to cooperate with + CygMon and GDB. When cooperating, we install VSRs in some slots + that demux into CygMon's vector table, and in most slots we just + patch in the appropriate value from CygMon's vector table so that + CygMon is called directly. + + * include/hal_xpic.h: + Document the interrupt sources on the SLEB. + + * include/hal_diag.h (HAL_DIAG_WRITE_CHAR): + Call routines in hal_diag.c to perform encapsulation, or not, + depending on CYG_KERNEL_DIAG_GDB. + + * src/hal_cygm.S: New file, demuxer trampolines for user trap and + no-fp/no-cp VSRs to bounce into CygMon. + + * src/hal_diag.c: New file, routines to perform encapsulation of + output in GDB $O packets if required by CYG_KERNEL_DIAG. + + * src/hal_priv.c (hal_board_prestart): + If CYG_HAL_USE_ROM_MONITOR_CYGMON, install either CygMon's vectors + or demuxer trampolines into our VSRs during startup. + + * src/PKGconf.mak (COMPILE): Add new files hal_cygm.S hal_diag.c + +1999-02-23 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_sparclite_sleb.h: Revise capitalization + of CDL strings. + +1999-02-23 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_sparclite_sleb.h: Specify correct platform + for cdl_package CYGPKG_HAL_SPARCLITE_SLEB. + +1999-02-22 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/ram.mlt: + * include/pkgconf/ram.ldi: + All a lot more constraints on alignment: sections must be + word-aligned at least for the network loader to accept them. + I hope I have correctly modified the .mlt file; it's not exactly + self documenting. + +1999-02-22 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_cache.h: New file + * include/hal_clock.h: New file + * include/hal_diag.h: New file + * include/hal_xpic.h: New file + * include/halboot.si: New file + * include/pkgconf/hal_sparclite_sleb.h: New file + * include/pkgconf/ram.ldi: New file + * include/pkgconf/ram.mlt: New file + * src/PKGconf.mak: New file + * src/hal_priv.c: New file + * tests/PKGconf.mak: New file + * tests/sleb.c: New file + + Initial checkin of the hardware platform port for SPARClite: + platform is sleb: SPARClite Evaluation Board. + + The structure here mirrors that in the sim directory, and in fact + was cloned from it after the change of 1999-02-08 for MLT + compliance. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== + +//EOF ChangeLog diff --git a/ecos/packages/hal/sparclite/sleb/current/cdl/hal_sparclite_sleb.cdl b/ecos/packages/hal/sparclite/sleb/current/cdl/hal_sparclite_sleb.cdl new file mode 100644 index 0000000..2770694 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/cdl/hal_sparclite_sleb.cdl @@ -0,0 +1,292 @@ +# ==================================================================== +# +# hal_sparclite_sleb.cdl +# +# SPARClite/SLEB target HAL package configuration data +# +# ==================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): jskov +# Original data: hmt +# Contributors: +# Date: 1999-11-01 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_SPARCLITE_SLEB { + display "SPARClite MB8683x evaluation board" + parent CYGPKG_HAL_SPARCLITE + define_header hal_sparclite_sleb.h + include_dir cyg/hal + description " + The SPARClite evaluation board HAL package is provided for use + with the Fujitsu MB8683x boards." + + compile hal_priv.c hal_cygm.S hal_diag.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sparclite.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sparclite_sleb.h>" + puts $::cdl_header "#define CYGHWR_HAL_SPARCLITE_HAS_ASR17 /* true for SLEBs */" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the SPARClite Evaluation Board it is possible to + build the system for either RAM bootstrap or ROM bootstrap. The + former generally requires that the board is equipped with ROMs + containing the Cygmon ROM monitor or equivalent software that + allows gdb to download the eCos application on to the board. The + latter typically requires that the eCos application be blown + into EPROMs or equivalent technology." + } + + cdl_option CYGHWR_HAL_SPARCLITE_MULTIPLE_VECTOR_TRAPPING { + display "Multiple vector trapping (MVT)" + default_value 0 + description " + Use Multiple Vector Trapping (MVT) rather than Single Vector + Trapping (SVT); SVT is a feature of SPARClite CPUs which saves + code RAM at a cost of perhaps slower interrupt and trap dispatch + time, depending on cache behavior. This includes speed of + handling register window underflow and overflow, a feature of + deep function call stacks on SPARC. MVT requires 4kB of code + space for trap vectors; in contrast SVT uses fewer than 20 + instructions for trap decoding." + } + + cdl_option CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM { + display "Copy vectors to RAM" + default_value 0 + description " + Copy the vectors and trap code out of the executable image + to separate RAM. With ROM startup, performance might be gained + by copying the vectors into RAM; this includes the code for + handling register window under/overflow. Enable this with + RAM startup to simulate the code and data sizes of an eventual + ROM image. Note: if MVT is not selected with ROM start, the + trap code (including register window handling) is copied + to RAM regardless; that code is small." + } + + + cdl_component CYG_HAL_USE_ROM_MONITOR_CYGMON { + display "Use ROM monitor CygMon" + default_value 1 + active_if { CYG_HAL_STARTUP == "RAM" } + description " + This is defined by default to allow interworking with + CygMon and thus GDB so that Breakpoints and ^C interrupts + and the like work. Disable it if building to run with the + native Fujitsu boot proms (NOT CYGMON) ie. a + load-and-go type startup by means of + (gdb) target sparclite udp sleb0 + or + (gdb) target sparclite serial /dev/ttyS0 + as opposed to the CygMon way: + (gdb) set remotebaud 19200 + (gdb) target remote /dev/ttyS0 + Such builds will load-and-go when using CygMon, but + load-and-go is all the interaction you get." + + cdl_option CYG_KERNEL_DIAG_GDB { + display "Output diag strings as \$O packets" + default_value 1 + description " + If using CygMon it's generally helpful to wrap output + characters in the GDB protocol as \$O packets; This + option enables this by means of calling into CygMon + through the vectors provided; this therefore also + works with eg. ethernet debugging. + + Disable this option and output goes direct, in clear, + to serial port 0 (CON1)." + } + + cdl_option CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT { + display "Output diag strings as \$O packets on serial" + active_if CYG_KERNEL_DIAG_GDB + default_value 0 + description " + However, you might want to force GDB-encoded output to + the serial port NOT using CygMon to perform the + formatting; this is really only here as a debugging + option, in case GDB is behaving oddly. Enable this + option to make GDB \$O packets come out the serial port + (CON1)" + } + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 9999 + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "sparclite-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-msoft-float -mcpu=sparclite -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions " } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-msoft-float -mcpu=sparclite -g -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGPKG_HAL_SPARCLITE_SLEB_OPTIONS { + display "SPARClite MB8683x build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + + cdl_option CYGPKG_HAL_SPARCLITE_SLEB_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the SPARClite MB8683x HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_SPARCLITE_SLEB_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the SPARClite MB8683x HAL. These flags are removed from + the set of global flags if present." + } + + cdl_option CYGPKG_HAL_SPARCLITE_SLEB_TESTS { + display "SPARClite MB8683x tests" + flavor data + no_define + calculated { "tests/slebstak tests/slebintr tests/slebtime" } + description " + This option specifies the set of tests for the SPARClite MB8683x HAL." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "sparclite_sleb_ram" : \ + "sparclite_sleb_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sparclite_sleb_ram.ldi>" : \ + "<pkgconf/mlt_sparclite_sleb_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sparclite_sleb_ram.h>" : \ + "<pkgconf/mlt_sparclite_sleb_rom.h>" } + } + } +} diff --git a/ecos/packages/hal/sparclite/sleb/current/include/hal_cache.h b/ecos/packages/hal/sparclite/sleb/current/include/hal_cache.h new file mode 100644 index 0000000..17ffbcf --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/hal_cache.h @@ -0,0 +1,289 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL Cache control support (such as it is in the simulator) +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1999-01-28 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// the caches. +// +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// SPARClite cache macros + +// The MB6863x Control Registers are in Address Space 1: +#define HAL_SPARC_ASI_1_READ( addr, res ) \ + asm volatile( \ + "lda [ %1 ] 1, %0" \ + : "=r"(res) \ + : "r"(addr) \ + ); + +#define HAL_SPARC_ASI_1_WRITE( addr, val ) \ + asm volatile( \ + "sta %0, [ %1 ] 1" \ + : \ + : "r"(val),"r"(addr) \ + ); + +#define HAL_SPARC_MMCR_CBIR 0x00 // Cache/BusInterfaceUnit Control +#define HAL_SPARC_MMCR_LCR 0x04 // Lock Control Register +#define HAL_SPARC_MMCR_LCSR 0x08 // Lock Control Save Reg +#define HAL_SPARC_MMCR_CSR 0x0c // Cache Status Reg +#define HAL_SPARC_MMCR_RLCR 0x10 // Restore Lock Control Register + +#define HAL_SPARC_MMCR_CBIR_ICE 0x01 // Instruction Cache Enable +#define HAL_SPARC_MMCR_CBIR_GICL 0x02 // Global IC Lock +#define HAL_SPARC_MMCR_CBIR_DCE 0x04 // Data CE +#define HAL_SPARC_MMCR_CBIR_GDCL 0x08 // G Data CE +#define HAL_SPARC_MMCR_CBIR_PBE 0x10 // Prefetch Buffer Enable +#define HAL_SPARC_MMCR_CBIR_WBE 0x20 // Write BE + + +//----------------------------------------------------------------------------- +// Cache dimensions + +// These definitions are suitable for any MB8683x processor: +// The largest possible cachesize and "ways", +// the smallest possible line size. +// This gives values that can correctly manipulate the cache by +// jumping on memory. + +// Data cache +#define HAL_DCACHE_SIZE 0x2000 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 0x2000 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() CYG_MACRO_START \ + int _v_; \ + HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ + _v_ |= HAL_SPARC_MMCR_CBIR_DCE; \ + HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ + asm volatile ( "nop; nop; nop; nop;" ); \ +CYG_MACRO_END + +// Disable the data cache +#define HAL_DCACHE_DISABLE() CYG_MACRO_START \ + int _v_; \ + HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ + _v_ &=~ HAL_SPARC_MMCR_CBIR_DCE; \ + HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ + asm volatile ( "nop; nop; nop; nop;" ); \ +CYG_MACRO_END + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() CYG_MACRO_START \ + asm volatile ( \ + "set 3, %%l0;" \ + "set 0x00001000, %%l1;" \ + "set 0x80001000, %%l2;" \ + "sta %%l0, [ %%l1 ] 0x0e;" \ + "sta %%l0, [ %%l2 ] 0x0e;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop" : : : "l0","l1","l2" ); \ +CYG_MACRO_END + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() CYG_MACRO_START \ + /* read 8k from the ROM; that should do it... */ \ + volatile cyg_uint32 *_p_ = (cyg_uint32 *)0; \ + volatile cyg_uint32 *_q_ = (cyg_uint32 *)HAL_DCACHE_SIZE; \ + volatile cyg_uint32 _tmp_; \ + for ( ; _p_ < _q_; _p_ ++ ) _tmp_ = *_q_; \ +CYG_MACRO_END + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) CYG_MACRO_START \ + int _v_; \ + HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ + (_state_) = (0 != (_v_ & HAL_SPARC_MMCR_CBIR_DCE)); \ +CYG_MACRO_END + + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache - use Data cache controls since they +// are not separatable. + +// Enable the data cache +#define HAL_ICACHE_ENABLE() CYG_MACRO_START \ + int _v_; \ + HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ + _v_ |= HAL_SPARC_MMCR_CBIR_ICE; \ + HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ + asm volatile ( "nop; nop; nop; nop;" ); \ +CYG_MACRO_END + +// Disable the data cache +#define HAL_ICACHE_DISABLE() CYG_MACRO_START \ + int _v_; \ + HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ + _v_ &=~ HAL_SPARC_MMCR_CBIR_ICE; \ + HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ + asm volatile ( "nop; nop; nop; nop;" ); \ +CYG_MACRO_END + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() CYG_MACRO_START \ + asm volatile ( \ + "set 3, %%l0;" \ + "set 0x00001000, %%l1;" \ + "set 0x80001000, %%l2;" \ + "sta %%l0, [ %%l1 ] 0x0c;" \ + "sta %%l0, [ %%l2 ] 0x0c;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "nop" : : : "l0","l1","l2" ); \ +CYG_MACRO_END + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() CYG_MACRO_START \ + HAL_DCACHE_SYNC(); /* Ensure data is in memory */ \ + HAL_ICACHE_INVALIDATE_ALL(); /* Pick up new memory contents */ \ +CYG_MACRO_END + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) CYG_MACRO_START \ + int _v_; \ + HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ + (_state_) = (0 != (_v_ & HAL_SPARC_MMCR_CBIR_ICE)); \ +CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h diff --git a/ecos/packages/hal/sparclite/sleb/current/include/hal_clock.h b/ecos/packages/hal/sparclite/sleb/current/include/hal_clock.h new file mode 100644 index 0000000..bda9a73 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/hal_clock.h @@ -0,0 +1,130 @@ +#ifndef CYGONCE_HAL_CLOCK_H +#define CYGONCE_HAL_CLOCK_H + +//============================================================================= +// +// hal_clock.h +// +// HAL clock support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1999-01-28 +// Purpose: Define clock support +// Description: The macros defined here provide the HAL APIs for handling +// the clock. +// +// Usage: +// #include <cyg/hal/hal_intr.h> // which includes this file +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// #include <cyg/hal/hal_io.h> + +#include <cyg/hal/hal_hwio.h> // HAL_SPARC_86940_READ/WRITE + +//----------------------------------------------------------------------------- +// Clock control + + +// The vector used by the Real time clock is defined in hal_xpic.h + +extern cyg_int32 cyg_hal_sparclite_clock_period; + +//----------------------------------------------------------------------------- + +#define HAL_SPARC_86940_REG_TIMER1_PRESCALER ( 0x14 * 4 ) +#define HAL_SPARC_86940_REG_TIMER1_CONTROL ( 0x15 * 4 ) +#define HAL_SPARC_86940_REG_TIMER1_RELOAD ( 0x16 * 4 ) +#define HAL_SPARC_86940_REG_TIMER1_COUNT ( 0x17 * 4 ) + + + +#define HAL_SPARC_86940_TIMER1_PRESCALER_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TIMER1_PRESCALER, v ) + +#define HAL_SPARC_86940_TIMER1_PRESCALER_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TIMER1_PRESCALER, r ) + +#define HAL_SPARC_86940_TIMER1_CONTROL_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TIMER1_CONTROL, v ) + +#define HAL_SPARC_86940_TIMER1_CONTROL_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TIMER1_CONTROL, r ) + +#define HAL_SPARC_86940_TIMER1_RELOAD_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TIMER1_RELOAD, v ) + +#define HAL_SPARC_86940_TIMER1_RELOAD_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TIMER1_RELOAD, r ) + +#define HAL_SPARC_86940_TIMER1_COUNT_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TIMER1_COUNT, r ) + +//----------------------------------------------------------------------------- + +// Initialize the clock to 1MHz whatever the system clock speed. This +// requires calculation... + +externC void hal_clock_initialize( cyg_uint32 p ); +#define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ ) + +// This is the easiest way to clear the interrupt. +#define HAL_CLOCK_RESET( _vector_, _period_ ) CYG_MACRO_START \ + cyg_uint32 _scratch_; \ + HAL_SPARC_86940_TIMER1_COUNT_READ( _scratch_ ); \ +CYG_MACRO_END + +#define HAL_CLOCK_READ( _pvalue_ ) CYG_MACRO_START \ + cyg_uint32 _read_; \ + HAL_SPARC_86940_TIMER1_COUNT_READ( _read_ ); \ + *((cyg_uint32 *)(_pvalue_)) = cyg_hal_sparclite_clock_period - _read_; \ +CYG_MACRO_END + +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY +#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( _pvalue_ ) +#endif + +//----------------------------------------------------------------------------- + +#endif // ifndef CYGONCE_HAL_CLOCK_H +// End of hal_clock.h diff --git a/ecos/packages/hal/sparclite/sleb/current/include/hal_cpu.h b/ecos/packages/hal/sparclite/sleb/current/include/hal_cpu.h new file mode 100644 index 0000000..415cea2 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/hal_cpu.h @@ -0,0 +1,542 @@ +#ifndef CYGONCE_HAL_SPARCLITE_HAL_CPU_H +#define CYGONCE_HAL_SPARCLITE_HAL_CPU_H +// ==================================================================== +// +// hal_cpu.h +// +// HAL CPU architecture file for MB8683x +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Red Hat +// Contributors: Red Hat, hmt +// Date: 1999-03-01 +// Purpose: MB8683x SPARClite CPU symbols +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + + +// NOTE: THIS FILE HAS NOT BEEN "CLEANED UP" WRT NAMESPACE USE +// +// it is only used internally to the SLEB HAL +// +// it should not be exported by inclusion in API header files +// + +#ifndef __ASSEMBLER__ +/* + * Register numbers. These are assumed to match the + * register numbers used by GDB. + */ +enum __regnames { + REG_G0, REG_G1, REG_G2, REG_G3, + REG_G4, REG_G5, REG_G6, REG_G7, + REG_O0, REG_O1, REG_O2, REG_O3, + REG_O4, REG_O5, REG_SP, REG_O7, + REG_L0, REG_L1, REG_L2, REG_L3, + REG_L4, REG_L5, REG_L6, REG_L7, + REG_I0, REG_I1, REG_I2, REG_I3, + REG_I4, REG_I5, REG_FP, REG_I7, + + REG_F0, REG_F1, REG_F2, REG_F3, + REG_F4, REG_F5, REG_F6, REG_F7, + REG_F8, REG_F9, REG_F10, REG_F11, + REG_F12, REG_F13, REG_F14, REG_F15, + REG_F16, REG_F17, REG_F18, REG_F19, + REG_F20, REG_F21, REG_F22, REG_F23, + REG_F24, REG_F25, REG_F26, REG_F27, + REG_F28, REG_F29, REG_F30, REG_F31, + + REG_Y, REG_PSR, REG_WIM, REG_TBR, + REG_PC, REG_NPC, REG_FPSR, REG_CPSR, + REG_DIA1, REG_DIA2, REG_DDA1, REG_DDA2, + REG_DDV1, REG_DDV2, REG_DCR, REG_DSR, + + REG_LAST +}; +#endif + +#ifdef __ASSEMBLER__ +/* + * Macros to glue together two tokens. + */ +#ifdef __STDC__ +#define XGLUE(a,b) a##b +#else +#define XGLUE(a,b) a/**/b +#endif + +#define GLUE(a,b) XGLUE(a,b) + +#ifdef NEED_UNDERSCORE +#define SYM_NAME(name) GLUE(_,name) + + .macro FUNC_START name + .align 4 + .globl _\name + .type _\name,#function + .proc 04 + _\name: + .endm + + .macro FUNC_END name + .LL_\name: + .size _\name,.LL_\name - _\name + .endm + +#else +#define SYM_NAME(name) name + + .macro FUNC_START name + .align 4 + .globl \name + .type \name,#function + .proc 04 + \name: + .endm + + .macro FUNC_END name + .LL\name: + .size \name,.LL\name - \name + .endm + +#endif + +#endif /* __ASSEMBLER__ */ + +/* + * breakpoint opcode. + */ +#define BREAKPOINT_OPCODE 0x91d02001 + +/* + * inline asm statement to cause breakpoint. + */ +#define BREAKPOINT() asm volatile ("ta 1\n") + +/* + * Core Exception vectors. + */ +#define BSP_EXC_IACCESS 0 +#define BSP_EXC_ILL 1 +#define BSP_EXC_IPRIV 2 +#define BSP_EXC_FPDIS 3 +#define BSP_EXC_WINOVF 4 +#define BSP_EXC_WINUND 5 +#define BSP_EXC_ALIGN 6 +#define BSP_EXC_DACCESS 7 +#define BSP_EXC_TAGOVF 8 +#define BSP_EXC_INT1 9 +#define BSP_EXC_INT2 10 +#define BSP_EXC_INT3 11 +#define BSP_EXC_INT4 12 +#define BSP_EXC_INT5 13 +#define BSP_EXC_INT6 14 +#define BSP_EXC_INT7 15 +#define BSP_EXC_INT8 16 +#define BSP_EXC_INT9 17 +#define BSP_EXC_INT10 18 +#define BSP_EXC_INT11 19 +#define BSP_EXC_INT12 20 +#define BSP_EXC_INT13 21 +#define BSP_EXC_INT14 22 +#define BSP_EXC_INT15 23 +#define BSP_EXC_CPDIS 24 +#define BSP_EXC_BREAK 25 +#define BSP_EXC_WINFLUSH 26 +#define BSP_EXC_SYSCALL 27 +#define BSP_EXC_DEBUG 28 +#define BSP_EXC_TRAP 29 + +#define BSP_MAX_EXCEPTIONS 30 + +#define BSP_VEC_MT_DEBUG 30 +#define BSP_VEC_STUB_ENTRY 31 +#define BSP_VEC_BSPDATA 32 + +#define NUM_VTAB_ENTRIES 33 + +#define CPU_WINSIZE 8 + +/* + * Exception frame offsets. + */ +#define GPR_SIZE 4 +#define FPR_SIZE 4 +#define PTR_BYTES 4 + +/* Leave room for locals + hidden arg + arg spill + dword align */ +#define FR_BIAS ((16+1+6+1)*GPR_SIZE) + +#define FR_G0 FR_BIAS +#define FR_G1 (FR_G0 + GPR_SIZE) +#define FR_G2 (FR_G1 + GPR_SIZE) +#define FR_G3 (FR_G2 + GPR_SIZE) +#define FR_G4 (FR_G3 + GPR_SIZE) +#define FR_G5 (FR_G4 + GPR_SIZE) +#define FR_G6 (FR_G5 + GPR_SIZE) +#define FR_G7 (FR_G6 + GPR_SIZE) +#define FR_O0 (FR_G7 + GPR_SIZE) +#define FR_O1 (FR_O0 + GPR_SIZE) +#define FR_O2 (FR_O1 + GPR_SIZE) +#define FR_O3 (FR_O2 + GPR_SIZE) +#define FR_O4 (FR_O3 + GPR_SIZE) +#define FR_O5 (FR_O4 + GPR_SIZE) +#define FR_O6 (FR_O5 + GPR_SIZE) +#define FR_SP FR_O6 +#define FR_O7 (FR_SP + GPR_SIZE) +#define FR_L0 (FR_O7 + GPR_SIZE) +#define FR_L1 (FR_L0 + GPR_SIZE) +#define FR_L2 (FR_L1 + GPR_SIZE) +#define FR_L3 (FR_L2 + GPR_SIZE) +#define FR_L4 (FR_L3 + GPR_SIZE) +#define FR_L5 (FR_L4 + GPR_SIZE) +#define FR_L6 (FR_L5 + GPR_SIZE) +#define FR_L7 (FR_L6 + GPR_SIZE) +#define FR_I0 (FR_L7 + GPR_SIZE) +#define FR_I1 (FR_I0 + GPR_SIZE) +#define FR_I2 (FR_I1 + GPR_SIZE) +#define FR_I3 (FR_I2 + GPR_SIZE) +#define FR_I4 (FR_I3 + GPR_SIZE) +#define FR_I5 (FR_I4 + GPR_SIZE) +#define FR_I6 (FR_I5 + GPR_SIZE) +#define FR_FP FR_I6 +#define FR_I7 (FR_FP + GPR_SIZE) + +#define FR_FREG0 (FR_I7 + GPR_SIZE) +#define FR_FREG1 (FR_FREG0 + FPR_SIZE) +#define FR_FREG2 (FR_FREG1 + FPR_SIZE) +#define FR_FREG3 (FR_FREG2 + FPR_SIZE) +#define FR_FREG4 (FR_FREG3 + FPR_SIZE) +#define FR_FREG5 (FR_FREG4 + FPR_SIZE) +#define FR_FREG6 (FR_FREG5 + FPR_SIZE) +#define FR_FREG7 (FR_FREG6 + FPR_SIZE) +#define FR_FREG8 (FR_FREG7 + FPR_SIZE) +#define FR_FREG9 (FR_FREG8 + FPR_SIZE) +#define FR_FREG10 (FR_FREG9 + FPR_SIZE) +#define FR_FREG11 (FR_FREG10 + FPR_SIZE) +#define FR_FREG12 (FR_FREG11 + FPR_SIZE) +#define FR_FREG13 (FR_FREG12 + FPR_SIZE) +#define FR_FREG14 (FR_FREG13 + FPR_SIZE) +#define FR_FREG15 (FR_FREG14 + FPR_SIZE) +#define FR_FREG16 (FR_FREG15 + FPR_SIZE) +#define FR_FREG17 (FR_FREG16 + FPR_SIZE) +#define FR_FREG18 (FR_FREG17 + FPR_SIZE) +#define FR_FREG19 (FR_FREG18 + FPR_SIZE) +#define FR_FREG20 (FR_FREG19 + FPR_SIZE) +#define FR_FREG21 (FR_FREG20 + FPR_SIZE) +#define FR_FREG22 (FR_FREG21 + FPR_SIZE) +#define FR_FREG23 (FR_FREG22 + FPR_SIZE) +#define FR_FREG24 (FR_FREG23 + FPR_SIZE) +#define FR_FREG25 (FR_FREG24 + FPR_SIZE) +#define FR_FREG26 (FR_FREG25 + FPR_SIZE) +#define FR_FREG27 (FR_FREG26 + FPR_SIZE) +#define FR_FREG28 (FR_FREG27 + FPR_SIZE) +#define FR_FREG29 (FR_FREG28 + FPR_SIZE) +#define FR_FREG30 (FR_FREG29 + FPR_SIZE) +#define FR_FREG31 (FR_FREG30 + FPR_SIZE) + +#define FR_Y (FR_FREG31 + FPR_SIZE) +#define FR_PSR (FR_Y + GPR_SIZE) +#define FR_WIM (FR_PSR + GPR_SIZE) +#define FR_TBR (FR_WIM + GPR_SIZE) +#define FR_PC (FR_TBR + GPR_SIZE) +#define FR_NPC (FR_PC + GPR_SIZE) +#define FR_FPSR (FR_NPC + GPR_SIZE) +#define FR_CPSR (FR_FPSR + GPR_SIZE) +#define FR_DIA1 (FR_CPSR + GPR_SIZE) +#define FR_DIA2 (FR_DIA1 + GPR_SIZE) +#define FR_DDA1 (FR_DIA2 + GPR_SIZE) +#define FR_DDA2 (FR_DDA1 + GPR_SIZE) +#define FR_DDV1 (FR_DDA2 + GPR_SIZE) +#define FR_DDV2 (FR_DDV1 + GPR_SIZE) +#define FR_DCR (FR_DDV2 + GPR_SIZE) +#define FR_DSR (FR_DCR + GPR_SIZE) +#define FR_ASR17 (FR_DSR + GPR_SIZE) + +#define EX_STACK_SIZE (FR_ASR17 + GPR_SIZE) + +#ifndef __ASSEMBLER__ +/* + * How registers are stored for exceptions. + */ +typedef struct +{ + unsigned long _g0; + unsigned long _g1; + unsigned long _g2; + unsigned long _g3; + unsigned long _g4; + unsigned long _g5; + unsigned long _g6; + unsigned long _g7; + unsigned long _o0; + unsigned long _o1; + unsigned long _o2; + unsigned long _o3; + unsigned long _o4; + unsigned long _o5; + unsigned long _sp; + unsigned long _o7; + unsigned long _l0; + unsigned long _l1; + unsigned long _l2; + unsigned long _l3; + unsigned long _l4; + unsigned long _l5; + unsigned long _l6; + unsigned long _l7; + unsigned long _i0; + unsigned long _i1; + unsigned long _i2; + unsigned long _i3; + unsigned long _i4; + unsigned long _i5; + unsigned long _fp; + unsigned long _i7; + + unsigned long _fpr[32]; + + unsigned long _y; + unsigned long _psr; + unsigned long _wim; + unsigned long _tbr; + + unsigned long _pc; + unsigned long _npc; + unsigned long _fpsr; + unsigned long _cpsr; + unsigned long _dia1; + unsigned long _dia2; + unsigned long _dda1; + unsigned long _dda2; + unsigned long _ddv1; + unsigned long _ddv2; + unsigned long _dcr; + unsigned long _dsr; + + unsigned long _asr17; + +} ex_regs_t; + +/* + * How gdb expects registers to be stored. + */ +typedef struct +{ + unsigned long _g0; + unsigned long _g1; + unsigned long _g2; + unsigned long _g3; + unsigned long _g4; + unsigned long _g5; + unsigned long _g6; + unsigned long _g7; + unsigned long _o0; + unsigned long _o1; + unsigned long _o2; + unsigned long _o3; + unsigned long _o4; + unsigned long _o5; + unsigned long _sp; + unsigned long _o7; + unsigned long _l0; + unsigned long _l1; + unsigned long _l2; + unsigned long _l3; + unsigned long _l4; + unsigned long _l5; + unsigned long _l6; + unsigned long _l7; + unsigned long _i0; + unsigned long _i1; + unsigned long _i2; + unsigned long _i3; + unsigned long _i4; + unsigned long _i5; + unsigned long _fp; + unsigned long _i7; + unsigned long _fpr[32]; + unsigned long _y; + unsigned long _psr; + unsigned long _wim; + unsigned long _tbr; + unsigned long _pc; + unsigned long _npc; + unsigned long _fpsr; + unsigned long _cpsr; + unsigned long _dia1; + unsigned long _dia2; + unsigned long _dda1; + unsigned long _dda2; + unsigned long _ddv1; + unsigned long _ddv2; + unsigned long _dcr; + unsigned long _dsr; +} gdb_regs_t; + + +extern void __dcache_flush(void *addr, int nbytes); +extern void __icache_flush(void *addr, int nbytes); +extern int __dcache_disable(void); +extern void __dcache_enable(void); +extern void __icache_disable(void); +extern void __icache_enable(void); + + +#endif /* !__ASSEMBLER__ */ + + +#define PSR_INIT 0xfa7 + + +/* + * Memory-mapped (ASI=1) registers for MB8683x series. + */ +#define CBIR 0x00000000 +#define LCR 0x00000004 +#define LCSR 0x00000008 +#define CSR 0x0000000C +#define RLCR 0x00000010 +#define BCR 0x00000020 +#define SSCR 0x00000080 + +#define SPGMR 0x00000120 +#define ARSR1 0x00000124 +#define ARSR2 0x00000128 +#define ARSR3 0x0000012C +#define ARSR4 0x00000130 +#define ARSR5 0x00000134 +#define AMR0 0x00000140 +#define AMR1 0x00000144 +#define AMR2 0x00000148 +#define AMR3 0x0000014C +#define AMR4 0x00000150 +#define AMR5 0x00000154 +#define WSSR0 0x00000160 +#define WSSR1 0x00000164 +#define WSSR2 0x00000168 +#define BWCR 0x0000016C +#define REFTMR 0x00000174 +#define DRLD 0x00000178 +#define VER2 0x00020000 +#define SLPMD 0x00020004 + +/* CBIR bit fields */ +#define CBIR_ICEN 0x01 /* Icache enable */ +#define CBIR_ICLOCK 0x02 /* Icache lock */ +#define CBIR_DCEN 0x04 /* Dcache enable */ +#define CBIR_DCLOCK 0x08 /* Dcache lock */ +#define CBIR_PBEN 0x10 /* Prefetch Buffer enable */ +#define CBIR_WBEN 0x20 /* Write Buffer enable */ + +/* LCR bit fields */ +#define LCR_ILOCK 0x01 /* Icache Auto-lock enable */ +#define LCR_DLOCK 0x02 /* Dcache Auto-lock enable */ + +/* WSSRn bit fields */ +#define WSSR_OVERRIDE 1 +#define WSSR_SINGLE 2 +#define WSSR_WAITEN 4 + +#define WSSR_CNT1_SHIFT 8 +#define WSSR_CNT2_SHIFT 3 +#define WSSR_CS0_SHIFT 6 +#define WSSR_CS1_SHIFT 19 + +#define WSSR_SUBVAL(c1,c2,flags) (((c1)<<8)|((c2)<<3)|(flags)) +#define WSSR_VAL(c1b,c2b,flagsb,c1a,c2a,flagsa) \ + ((WSSR_SUBVAL(c1b,c2b,flagsb)<<19)|(WSSR_SUBVAL(c1a,c2a,flagsa)<<6)) + +#define SPGMR_VAL(asi,addr) (((asi)<<23)|(((addr)>>9)&0x007ffffe)) +#define ARSR_VAL(asi,base) ((((asi)&0xff)<<23)|(((base)>>9)&0x007ffffe)) +#define AMR_VAL(asi,base) (((~(asi))<<23)|(((~(base))>>9)&0x007fffff)) + +/* SSCR bit fields */ +#define SSCR_TIMER 0x04 +#define SSCR_WAIT 0x08 +#define SSCR_CS 0x10 +#define SSCR_SAMEPG 0x20 +#define SSCR_DRAM 0x40 +#define SSCR_BURST 0x80 + +/* BCR bit fields */ +#define BCR_IBE 1 +#define BCR_DBE 2 + + +/* DRAM Controller registers as offsets into CS3 space */ +#define DBANKR 0x20 +#define DTIMR 0x24 + +/* DBANKR bit fields */ +#define DBANKR_512K 0 +#define DBANKR_1M 1 +#define DBANKR_2M 2 +#define DBANKR_4M 3 +#define DBANKR_8M 4 +#define DBANKR_16M 5 +#define DBANKR_32M 6 +#define DBANKR_64M 7 +#define DBANKR_CA9 (2<<4) +#define DBANKR_CA10 (3<<4) +#define DBANKR_CA11 (4<<4) +#define DBANKR_CA12 (5<<4) +#define DBANKR_4C1W (0<<7) /* 4CAS/1WE */ +#define DBANKR_1C4W (1<<7) /* 1CAS/4WE */ +#define DBANKR_EDO (1<<8) +#define DBANKR_SA01 (1<<9) +#define DBANKR_SA02 (2<<9) +#define DBANKR_SA04 (3<<9) + +/* DTIMR bit fields */ +#define DTIMR_RP1 0 +#define DTIMR_RP2 1 +#define DTIMR_CAS1 (0<<1) +#define DTIMR_CAS2 (1<<1) +#define DTIMR_CBR1 (0<<2) +#define DTIMR_CBR2 (1<<2) +#define DTIMR_CBR3 (2<<2) +#define DTIMR_RPS2 (0<<4) +#define DTIMR_RPS4 (1<<4) + + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_HAL_SPARCLITE_HAL_CPU_H */ +/* EOF hal_cpu.h */ diff --git a/ecos/packages/hal/sparclite/sleb/current/include/hal_cygm.h b/ecos/packages/hal/sparclite/sleb/current/include/hal_cygm.h new file mode 100644 index 0000000..3ee4bad --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/hal_cygm.h @@ -0,0 +1,126 @@ +#ifndef CYGONCE_HAL_CYGM_H +#define CYGONCE_HAL_CYGM_H + +//============================================================================= +// +// hal_cygm.h +// +// HAL CygMon vector definitions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-02-24 +// Purpose: Define Interrupt vectors in CygMon +// Description: +// +// Usage: +// #include <cyg/hal/hal_cygm.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> +#include <pkgconf/hal_sparclite_sleb.h> + +// *** THIS FILE IS ALSO USED IN ASSEMBLY SOURCE *** +// so it does not include eg. cyg_type.h ... + +#ifdef CYG_HAL_USE_ROM_MONITOR_CYGMON + +//----------------------------------------------------------------------------- +// SPARClite CygMon vector numbers and address + +#define CYGMON_VECTOR_TABLE_BASE (0x04000000) + +#define CYGMON_VECTOR_TABLE ((CYG_ADDRESS *)CYGMON_VECTOR_TABLE_BASE) + +// The ROM vector table is located at 0x04000000 and has the +// following layout: + +#define BSP_EXC_IACCESS 0 /* insn access */ +#define BSP_EXC_ILL 1 /* illegal insn */ +#define BSP_EXC_IPRIV 2 /* privileged insn */ +#define BSP_EXC_FPDIS 3 /* FPU disabled */ +#define BSP_EXC_WINOVF 4 /* window overflow */ +#define BSP_EXC_WINUND 5 /* window underflow */ +#define BSP_EXC_ALIGN 6 /* alignment */ +#define BSP_EXC_DACCESS 7 /* data access */ +#define BSP_EXC_TAGOVF 8 /* tag overflow */ +#define BSP_EXC_INT1 9 +#define BSP_EXC_INT2 10 +#define BSP_EXC_INT3 11 +#define BSP_EXC_INT4 12 +#define BSP_EXC_INT5 13 +#define BSP_EXC_INT6 14 +#define BSP_EXC_INT7 15 /* serial Ch0 rxrdy */ +#define BSP_EXC_INT8 16 +#define BSP_EXC_INT9 17 +#define BSP_EXC_INT10 18 /* serial Ch0 rxrdy */ +#define BSP_EXC_INT11 19 +#define BSP_EXC_INT12 20 +#define BSP_EXC_INT13 21 +#define BSP_EXC_INT14 22 /* ethernet interrupt */ +#define BSP_EXC_INT15 23 +#define BSP_EXC_CPDIS 24 /* CP disabled */ +#define BSP_EXC_BREAK 25 /* breakpoint "ta 1" */ +#define BSP_EXC_WINFLUSH 26 /* window flush "ta 3" */ +#define BSP_EXC_SYSCALL 27 /* syscall "ta 8" */ +#define BSP_EXC_DEBUG 28 /* DSU exception */ +#define BSP_EXC_TRAP 29 /* all other traps */ +#define BSP_VEC_MT_DEBUG 30 /* Multi-Threaded debugging */ +#define BSP_VEC_STUB_ENTRY 31 /* low level stub entry, eg. ^C rx */ + +// These vectors should be called with: +// +// %l0 - PSR +// %l1 - PC +// %l2 - NPC +// [%l3 - TBR ; STUB_ENTRY only, TBR from original exception ] + +#define BSP_NOTVEC_BSP_COMM_PROCS 32 /* pointer to structure for comms */ + +#endif // CYG_HAL_USE_ROM_MONITOR_CYGMON + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CYGM_H +// End of hal_cygm.h diff --git a/ecos/packages/hal/sparclite/sleb/current/include/hal_diag.h b/ecos/packages/hal/sparclite/sleb/current/include/hal_diag.h new file mode 100644 index 0000000..a996191 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/hal_diag.h @@ -0,0 +1,141 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-01-11 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> +#include <pkgconf/hal_sparclite_sleb.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_hwio.h> + +/*---------------------------------------------------------------------------*/ +/* SPARClite Evaluation Board - SLEB - 86940 SDTR output (+ the LEDs) */ + +#define SLEB_LED (*(volatile char *)(0x02000003)) + +#define SLEB_86940_SDTR0_OUT +#ifdef SLEB_86940_SDTR0_OUT + + +#define HAL_SPARC_86940_FLAG_TXRDY (0x01) +#define HAL_SPARC_86940_FLAG_RXRDY (0x02) + +#define HAL_DIAG_WRITE_CHAR_DIRECT(_c_) CYG_MACRO_START \ + cyg_uint32 status = 0; \ + while ( 0 == (HAL_SPARC_86940_FLAG_TXRDY & status) ) { \ + HAL_SPARC_86940_SDTR0_STAT_READ( status ); \ + } \ + HAL_SPARC_86940_SDTR0_TXDATA_WRITE( _c_ ); \ +CYG_MACRO_END + +#define HAL_DIAG_WRITE_CHAR_WAIT_FOR_EMPTY() CYG_MACRO_START \ + cyg_uint32 status = HAL_SPARC_86940_FLAG_TXRDY; \ + while ( 0 != (HAL_SPARC_86940_FLAG_TXRDY & status) ) { \ + HAL_SPARC_86940_SDTR0_STAT_READ( status ); \ + } \ +CYG_MACRO_END + + + +#ifdef CYG_KERNEL_DIAG_GDB +// then use routines from hal_diag.c: + +externC void hal_diag_init(void); +externC void hal_diag_write_char(char c); +#define HAL_DIAG_INIT() hal_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) CYG_MACRO_START \ + SLEB_LED = (_c_); /* immediately */ \ + hal_diag_write_char(_c_); \ +CYG_MACRO_END + + +#else // CYG_KERNEL_DIAG_GDB +// else go to the serial line directly (after initialization): + +externC void hal_diag_init(void); +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) CYG_MACRO_START \ + SLEB_LED = (_c_); \ + HAL_DIAG_WRITE_CHAR_DIRECT( _c_ ); \ +CYG_MACRO_END + +#endif // CYG_KERNEL_DIAG_GDB + + + +#define HAL_DIAG_READ_CHAR(_c_) (_c_) = 0 + + +#else +/*---------------------------------------------------------------------------*/ +/* SPARClite Evaluation Board - SLEB - Just use the LEDs on board */ + +#define HAL_DIAG_INIT() + +#define HAL_DIAG_WRITE_CHAR(_c_) CYG_MACRO_START \ + SLEB_LED = (_c_); \ +CYG_MACRO_END + +#define HAL_DIAG_READ_CHAR(_c_) (_c_) = 0 + + +#endif // SLEB_86940_SDTR0_OUT + +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */ +#endif /* CYGONCE_HAL_HAL_DIAG_H */ diff --git a/ecos/packages/hal/sparclite/sleb/current/include/hal_hwio.h b/ecos/packages/hal/sparclite/sleb/current/include/hal_hwio.h new file mode 100644 index 0000000..cec5b0f --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/hal_hwio.h @@ -0,0 +1,312 @@ +#ifndef CYGONCE_HAL_HAL_HWIO_H +#define CYGONCE_HAL_HAL_HWIO_H + +/*============================================================================= +// +// hal_hwio.h +// +// HAL Support for IO to platform-specific devices +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-01-11 +// Purpose: HAL Support for IO to platform-specific devices +// Description: Macros to access the 86940 SPARClite companion chip +// Usage: #include <cyg/hal/hal_hwio.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> +#include <pkgconf/hal_sparclite_sleb.h> + +#include <cyg/infra/cyg_type.h> + +/*---------------------------------------------------------------------------*/ +/* MB86940 flags and the like */ + +/* Interrupt trigger modes. */ +#define HAL_SPARC_86940_TRIG_LEVEL_H 0 /* trigger on high level */ +#define HAL_SPARC_86940_TRIG_LEVEL_L 1 /* trigger on low level */ +#define HAL_SPARC_86940_TRIG_EDGE_H 2 /* trigger on rising edge */ +#define HAL_SPARC_86940_TRIG_EDGE_L 3 /* trigger on falling edge */ + +/* Timer prescaler register values */ +#define HAL_SPARC_86940_PRS_EXTCLK 0x8000 +#define HAL_SPARC_86940_PRS_ODIV1 (0<<8) +#define HAL_SPARC_86940_PRS_ODIV2 (1<<8) +#define HAL_SPARC_86940_PRS_ODIV4 (2<<8) +#define HAL_SPARC_86940_PRS_ODIV8 (3<<8) +#define HAL_SPARC_86940_PRS_ODIV16 (4<<8) +#define HAL_SPARC_86940_PRS_ODIV32 (5<<8) +#define HAL_SPARC_86940_PRS_ODIV64 (6<<8) +#define HAL_SPARC_86940_PRS_ODIV128 (7<<8) + +/* Timer control register values */ +#define HAL_SPARC_86940_TCR_CE (1<<11) +#define HAL_SPARC_86940_TCR_CLKINT (0<<9) +#define HAL_SPARC_86940_TCR_CLKEXT (1<<9) +#define HAL_SPARC_86940_TCR_CLKPRS (2<<9) +#define HAL_SPARC_86940_TCR_CLKRSVD (3<<9) +#define HAL_SPARC_86940_TCR_OUTSAME (0<<7) +#define HAL_SPARC_86940_TCR_OUTHIGH (1<<7) +#define HAL_SPARC_86940_TCR_OUTLOW (2<<7) +#define HAL_SPARC_86940_TCR_OUTC3 (3<<7) +#define HAL_SPARC_86940_TCR_INV (1<<6) +#define HAL_SPARC_86940_TCR_PER_INT (0<<3) +#define HAL_SPARC_86940_TCR_TO_INT (1<<3) +#define HAL_SPARC_86940_TCR_SQWAVE (2<<3) +#define HAL_SPARC_86940_TCR_SW_WATCH (3<<3) +#define HAL_SPARC_86940_TCR_HW_WATCH (4<<3) +#define HAL_SPARC_86940_TCR_LEVEL_L 0 +#define HAL_SPARC_86940_TCR_LEVEL_H 1 +#define HAL_SPARC_86940_TCR_EDGE_H 2 +#define HAL_SPARC_86940_TCR_EDGE_L 3 +#define HAL_SPARC_86940_TCR_EDGE 4 + +/* serial mode register values */ +#define HAL_SPARC_86940_SER_STOP0 (0<<6) +#define HAL_SPARC_86940_SER_STOP1 (1<<6) +#define HAL_SPARC_86940_SER_STOP1_5 (2<<6) +#define HAL_SPARC_86940_SER_STOP2 (3<<6) +#define HAL_SPARC_86940_SER_NO_PARITY (0<<4) +#define HAL_SPARC_86940_SER_ODD_PARITY (1<<4) +#define HAL_SPARC_86940_SER_EVEN_PARITY (3<<4) +#define HAL_SPARC_86940_SER_5BITS (0<<2) +#define HAL_SPARC_86940_SER_6BITS (1<<2) +#define HAL_SPARC_86940_SER_7BITS (2<<2) +#define HAL_SPARC_86940_SER_8BITS (3<<2) +#define HAL_SPARC_86940_SER_MODE_SYNCH 0 +#define HAL_SPARC_86940_SER_DIV1_CLK 1 +#define HAL_SPARC_86940_SER_DIV16_CLK 2 +#define HAL_SPARC_86940_SER_DIV64_CLK 3 + +/* serial command register (asynch) */ +#define HAL_SPARC_86940_SER_CMD_EHM (1<<7) +#define HAL_SPARC_86940_SER_CMD_IRST (1<<6) +#define HAL_SPARC_86940_SER_CMD_RTS (1<<5) +#define HAL_SPARC_86940_SER_CMD_EFR (1<<4) +#define HAL_SPARC_86940_SER_CMD_BREAK (1<<3) +#define HAL_SPARC_86940_SER_CMD_RXEN (1<<2) +#define HAL_SPARC_86940_SER_CMD_DTR (1<<1) +#define HAL_SPARC_86940_SER_CMD_TXEN (1<<0) + +/* serial status register */ +#define HAL_SPARC_86940_SER_STAT_DSR (1<<7) +#define HAL_SPARC_86940_SER_STAT_BREAK (1<<6) +#define HAL_SPARC_86940_SER_STAT_FERR (1<<5) +#define HAL_SPARC_86940_SER_STAT_OERR (1<<4) +#define HAL_SPARC_86940_SER_STAT_PERR (1<<3) +#define HAL_SPARC_86940_SER_STAT_TXEMP (1<<2) +#define HAL_SPARC_86940_SER_STAT_RXRDY (1<<1) +#define HAL_SPARC_86940_SER_STAT_TXRDY (1<<0) + +#define HAL_SPARC_86940_CHIP_ASI 4 +#define HAL_SPARC_86940_CHIP_BASE 0x10000000 +#define HAL_SPARC_86940_REGADDR_SHIFT 2 +#define HAL_SPARC_86940_REGVAL_SHIFT 16 + +/*---------------------------------------------------------------------------*/ +/* Register addresses */ + +// The "interesting" IO parts are in Address Space Four: +#define HAL_SPARC_ASI_4_READ( addr, res ) \ + asm volatile( \ + "lda [ %1 ] 4, %0" \ + : "=r"(res) \ + : "r"(addr) \ + ); + +#define HAL_SPARC_ASI_4_WRITE( addr, val ) \ + asm volatile( \ + "sta %0, [ %1 ] 4" \ + : \ + : "r"(val),"r"(addr) \ + ); + +#define HAL_SPARC_86940_BASE (0x10000000) // in ASI 4 + +// The 86940 is connected to the upper 16 bits! +#define HAL_SPARC_86940_READ( reg, result ) CYG_MACRO_START \ + cyg_uint32 hires; \ + HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires ); \ + hires >>= 16; \ + result = hires; \ +CYG_MACRO_END + +// THIS IS ONLY HERE FOR DEBUGGING: +// The 86940 is connected to the upper 16 bits! +// And seems to be an unreliable deprecated thing... +// so read it 3 times and believe the majority. +#define HAL_SPARC_86940_READ3( reg, result ) CYG_MACRO_START \ + cyg_uint32 hires1; \ + cyg_uint32 hires2; \ + cyg_uint32 hires3; \ + HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires1 ); \ + HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires2 ); \ + HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires3 ); \ + result = ((hires1&hires2)|(hires1&hires3)|(hires2&hires3)) >> 16; \ +CYG_MACRO_END + +#define HAL_SPARC_86940_WRITE( reg, value ) CYG_MACRO_START \ + cyg_uint32 hival = (value) << 16; \ + HAL_SPARC_ASI_4_WRITE( reg + HAL_SPARC_86940_BASE, hival ); \ +CYG_MACRO_END + +// Registers are at word offsets +#define HAL_SPARC_86940_REG_SDTR0_TXDATA ( 0x08 * 4 ) +#define HAL_SPARC_86940_REG_SDTR0_RXDATA ( 0x08 * 4 ) +#define HAL_SPARC_86940_REG_SDTR0_STAT ( 0x09 * 4 ) +#define HAL_SPARC_86940_REG_SDTR0_CTRL ( 0x09 * 4 ) +#define HAL_SPARC_86940_REG_SDTR1_TXDATA ( 0x0c * 4 ) +#define HAL_SPARC_86940_REG_SDTR1_RXDATA ( 0x0c * 4 ) +#define HAL_SPARC_86940_REG_SDTR1_STAT ( 0x0d * 4 ) +#define HAL_SPARC_86940_REG_SDTR1_CTRL ( 0x0d * 4 ) + +#define HAL_SPARC_86940_REG_PRS0 ( 0x10 * 4 ) +#define HAL_SPARC_86940_REG_TCR0 ( 0x11 * 4 ) +#define HAL_SPARC_86940_REG_RELOAD0 ( 0x12 * 4 ) +#define HAL_SPARC_86940_REG_CNT0 ( 0x13 * 4 ) +#define HAL_SPARC_86940_REG_PRS1 ( 0x14 * 4 ) +#define HAL_SPARC_86940_REG_TCR1 ( 0x15 * 4 ) +#define HAL_SPARC_86940_REG_RELOAD1 ( 0x16 * 4 ) +#define HAL_SPARC_86940_REG_CNT1 ( 0x17 * 4 ) +#define HAL_SPARC_86940_REG_TCR2 ( 0x19 * 4 ) +#define HAL_SPARC_86940_REG_RELOAD2 ( 0x1A * 4 ) +#define HAL_SPARC_86940_REG_CNT2 ( 0x1B * 4 ) +#define HAL_SPARC_86940_REG_TCR3 ( 0x1D * 4 ) +#define HAL_SPARC_86940_REG_RELOAD3 ( 0x1E * 4 ) +#define HAL_SPARC_86940_REG_CNT3 ( 0x1F * 4 ) + +// Glue together to access them neatly +#define HAL_SPARC_86940_SDTR0_TXDATA_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR0_TXDATA, v ) +#define HAL_SPARC_86940_SDTR0_RXDATA_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR0_RXDATA, r ) + +#define HAL_SPARC_86940_SDTR0_STAT_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR0_STAT, r ) +#define HAL_SPARC_86940_SDTR0_CTRL_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR0_CTRL, v ) + +#define HAL_SPARC_86940_SDTR1_TXDATA_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR1_TXDATA, v ) +#define HAL_SPARC_86940_SDTR1_RXDATA_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR1_RXDATA, r ) + +#define HAL_SPARC_86940_SDTR1_STAT_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR1_STAT, r ) +#define HAL_SPARC_86940_SDTR1_CTRL_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR1_CTRL, v ) + +#define HAL_SPARC_86940_PRS0_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_PRS0, r ) +#define HAL_SPARC_86940_PRS0_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_PRS0, v ) + +#define HAL_SPARC_86940_TCR0_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR0, r ) +#define HAL_SPARC_86940_TCR0_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR0, v ) + +#define HAL_SPARC_86940_RELOAD0_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD0, r ) +#define HAL_SPARC_86940_RELOAD0_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD0, v ) + +#define HAL_SPARC_86940_CNT0_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT0, r ) +#define HAL_SPARC_86940_CNT0_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT0, v ) + +#define HAL_SPARC_86940_PRS1_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_PRS1, r ) +#define HAL_SPARC_86940_PRS1_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_PRS1, v ) + +#define HAL_SPARC_86940_TCR1_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR1, r ) +#define HAL_SPARC_86940_TCR1_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR1, v ) + +#define HAL_SPARC_86940_RELOAD1_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD1, r ) +#define HAL_SPARC_86940_RELOAD1_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD1, v ) + +#define HAL_SPARC_86940_CNT1_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT1, r ) +#define HAL_SPARC_86940_CNT1_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT1, v ) + +#define HAL_SPARC_86940_TCR2_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR2, r ) +#define HAL_SPARC_86940_TCR2_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR2, v ) + +#define HAL_SPARC_86940_RELOAD2_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD2, r ) +#define HAL_SPARC_86940_RELOAD2_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD2, v ) + +#define HAL_SPARC_86940_CNT2_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT2, r ) +#define HAL_SPARC_86940_CNT2_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT2, v ) + +#define HAL_SPARC_86940_TCR3_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR3, r ) +#define HAL_SPARC_86940_TCR3_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR3, v ) + +#define HAL_SPARC_86940_RELOAD3_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD3, r ) +#define HAL_SPARC_86940_RELOAD3_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD3, v ) + +#define HAL_SPARC_86940_CNT3_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT3, r ) +#define HAL_SPARC_86940_CNT3_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT3, v ) + +/*---------------------------------------------------------------------------*/ +/* end of hal_hwio.h */ +#endif /* CYGONCE_HAL_HAL_HWIO_H */ diff --git a/ecos/packages/hal/sparclite/sleb/current/include/hal_xpic.h b/ecos/packages/hal/sparclite/sleb/current/include/hal_xpic.h new file mode 100644 index 0000000..736b903 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/hal_xpic.h @@ -0,0 +1,210 @@ +#ifndef CYGONCE_HAL_XPIC_H +#define CYGONCE_HAL_XPIC_H + +//============================================================================= +// +// hal_xpic.h +// +// HAL eXternal Programmable Interrupt Controller support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas, hmt +// Contributors: nickg, gthomas, hmt +// Date: 1999-01-28 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// an external interrupt controller, and which interrupt is +// used for what. +// +// Usage: +// #include <cyg/hal/hal_intr.h> // which includes this file +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/hal/hal_hwio.h> // HAL_SPARC_86940_READ/WRITE + +//----------------------------------------------------------------------------- +// Interrupt controller access +// +// In the Fuitsu SPARClite Evaluation Boards, when the external IRC (86940) +// is used (set Switch 1, position 8 (SW1#8)), interrupts are as follows: +// +// 15 : NMI Push Switch (SW7) +// 14 : N_INT# Ethernet LAN Controller (MB86964) +// 13 : EX_IRQ13 from expansion board, active HIGH +// 12 : EX_IRQ12 from expansion board, active LOW +// 11 : EX_IRQ11 from expansion board, active LOW +// 10 : RRDY0 Serial CH0 receive ready signal +// 9 : TRDY0 Serial CH0 transmit ready signal +// 8 : TIMER1 Timer 1 output counter +// 7 : RRDY1 Serial CH1 receive ready signal +// 6 : TRDY1 Serial CH1 transmit ready signal +// 5 : EX_IRQ5 from expansion board, active LOW +// 4 : EX_IRQ4 from expansion board, active LOW +// 3 : EX_IRQ3 from expansion board, active HIGH +// 2 : EX_IRQ2 from expansion board, active LOW +// 1 : TIMER2 Timer 2 output counter + +// The vector used by the Real time clock + +//#define CYG_VECTOR_RTC CYG_VECTOR_INTERRUPT_8 +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_VECTOR_INTERRUPT_8 + +#define HAL_SPARC_86940_REG_IRC_TRGM0 ( 0 * 4 ) +#define HAL_SPARC_86940_REG_IRC_TRGM1 ( 1 * 4 ) +#define HAL_SPARC_86940_REG_IRC_RQSNS ( 2 * 4 ) +#define HAL_SPARC_86940_REG_IRC_RQCLR ( 3 * 4 ) +#define HAL_SPARC_86940_REG_IRC_IMASK ( 4 * 4 ) +#define HAL_SPARC_86940_REG_IRC_CLIRL ( 5 * 4 ) + +#define HAL_SPARC_86940_FLAG_CLIRL_CL (0x10) + +#define HAL_SPARC_86940_IRC_IMASK_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_IRC_IMASK, r ) + +#define HAL_SPARC_86940_IRC_IMASK_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_IRC_IMASK, v ) + +#define HAL_SPARC_86940_IRC_RQSNS_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_IRC_RQSNS, r ) + +#define HAL_SPARC_86940_IRC_RQCLR_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_IRC_RQCLR, v ) + +#define HAL_SPARC_86940_IRC_CLIRL_READ( r ) \ + HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_IRC_CLIRL, r ) + +#define HAL_SPARC_86940_IRC_CLIRL_WRITE( v ) \ + HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_IRC_CLIRL, v ) + +//----------------------------------------------------------------------------- + +#define HAL_INTERRUPT_MASK( _vector_ ) CYG_MACRO_START \ + cyg_uint32 _traps_, _mask_; \ + HAL_DISABLE_TRAPS( _traps_ ); \ + HAL_SPARC_86940_IRC_IMASK_READ( _mask_ ); \ + _mask_ |= (1 << (_vector_) ); \ + HAL_SPARC_86940_IRC_IMASK_WRITE( _mask_ ); \ + HAL_SPARC_86940_IRC_RQCLR_WRITE( (1 << (_vector_) ) ); \ + HAL_SPARC_86940_IRC_CLIRL_WRITE( HAL_SPARC_86940_FLAG_CLIRL_CL ); \ + HAL_RESTORE_INTERRUPTS( _traps_ ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK( _vector_ ) CYG_MACRO_START \ + cyg_uint32 _traps_, _mask_; \ + HAL_DISABLE_TRAPS( _traps_ ); \ + HAL_SPARC_86940_IRC_IMASK_READ( _mask_ ); \ + _mask_ &=~ (1 << (_vector_) ); \ + HAL_SPARC_86940_IRC_IMASK_WRITE( _mask_ ); \ + HAL_RESTORE_INTERRUPTS( _traps_ ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) CYG_MACRO_START \ + cyg_uint32 _traps_; \ + cyg_uint32 _req_, _irl_; \ + HAL_DISABLE_TRAPS( _traps_ ); \ + HAL_SPARC_86940_IRC_RQCLR_WRITE( (1 << (_vector_) ) ); \ + do { \ + HAL_SPARC_86940_IRC_CLIRL_WRITE( HAL_SPARC_86940_FLAG_CLIRL_CL ); \ + HAL_SPARC_86940_IRC_RQSNS_READ( _req_ ); \ + HAL_SPARC_86940_IRC_CLIRL_READ( _irl_ ); \ + _req_ &= (1 << (_vector_)); /* if there really is a new intr */ \ + _irl_ &= 0x0f; /* then get out - else poll until */ \ + } while ( (!_req_) && (_irl_ == (_vector_)) ); /* no intr here */ \ + HAL_RESTORE_INTERRUPTS( _traps_ ); \ +CYG_MACRO_END + +// Set an interrupt source's sensitivity: +// _level_ != 0 ? level-sensitive : edge-sensitive +// _up_ != 0 ? high/up : low/down +// SPARClite's 86940 has values as follows: +// 0 : high level +// 1 : low level +// 2 : rising edge +// 3 : falling edge +// TRGM0 controls sources 15-8, TRGM1 sources 7-1. + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) CYG_MACRO_START \ + int _reg_ = (8 > (_vector_)) ? HAL_SPARC_86940_REG_IRC_TRGM1 \ + : HAL_SPARC_86940_REG_IRC_TRGM0; \ + int _val_, _myvect_ = (_vector_); \ + cyg_uint32 _traps_; \ + HAL_DISABLE_TRAPS( _traps_ ); \ + (_myvect_) &= 7; \ + (_myvect_) <<= 1; \ + HAL_SPARC_86940_READ( _reg_, _val_ ); \ + _val_ &=~ (3 << (_myvect_)); \ + _val_ |= ( ((_level_) ? 0 : 2) + ((_up_) ? 0 : 1) ) << (_myvect_); \ + HAL_SPARC_86940_WRITE( _reg_, _val_ ); \ + HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ); \ + HAL_RESTORE_INTERRUPTS( _traps_ ); \ +CYG_MACRO_END + +// This is not a standard macro - platform dependent for debugging only: +// o level, up tell you how this source was configured as above. +// o hipri returns the number of the highest prio requesting interrupt +// o mask tells you whether this source is masked off +// o req tells you whether this source is requesting right now. +#define HAL_INTERRUPT_QUERY_INFO( _vector_, _level_, _up_, \ + _hipri_, _mask_, _req_ ) CYG_MACRO_START \ + int _reg_ = (8 > (_vector_)) ? HAL_SPARC_86940_REG_IRC_TRGM1 \ + : HAL_SPARC_86940_REG_IRC_TRGM0; \ + int _val_, _myvect_ = (_vector_); \ + HAL_SPARC_86940_IRC_IMASK_READ( _val_ ); \ + _mask_ = (0 != ((1 << (_vector_)) & _val_ )); \ + HAL_SPARC_86940_IRC_RQSNS_READ( _val_ ); \ + _req_ = (0 != ((1 << (_vector_)) & _val_ )); \ + HAL_SPARC_86940_IRC_CLIRL_READ( _hipri_ ); \ + (_myvect_) &= 7; \ + (_myvect_) <<= 1; \ + HAL_SPARC_86940_READ( _reg_, _val_ ); \ + _val_ >>= (_myvect_); \ + (_level_) = !(_val_ & 2); \ + (_up_) = !(_val_ & 1); \ +CYG_MACRO_END + +// This may set the priority of a vector to a particular level: +// SPARClite does not support this. +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) /* nothing */ + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_XPIC_H +// End of hal_xpic.h diff --git a/ecos/packages/hal/sparclite/sleb/current/include/halboot.si b/ecos/packages/hal/sparclite/sleb/current/include/halboot.si new file mode 100644 index 0000000..8e17c57 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/halboot.si @@ -0,0 +1,515 @@ +#ifndef CYGONCE_HAL_HALBOOT_SI /* -*-asm-*- */ +#define CYGONCE_HAL_HALBOOT_SI +// ==================================================================== +// +// <platform>/halboot.si +// +// HAL bootup platform-oriented code (assembler) +// +// ==================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-02-01 +// Purpose: Bootup code, platform oriented. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// External Platform Initial Setup +// +// This should set up RAM and caches, and calm down any external +// interrupt sources. +// +// It is just plain included in vectors.S +// +// RAM has not yet been touched at all; in fact all you have is a +// register window selected. + + +#ifdef CYG_HAL_STARTUP_RAM + ! Hit the entry point instructions in situ +#ifndef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM + ! *unless* we are going to copy into a different RAM area anyway: + ! copy the real instructions into the vector: + rd %tbr, %g1 + andn %g1, 0xfff, %g1 ! clear non-address bits + set real_vector_instructions, %l0 + ld [ %l0 ], %l1 + st %l1, [ %g1 ] ! into the vector + ld [ %l0 + 4 ], %l1 + st %l1, [ %g1 + 4 ] ! into the vector + ! then invalidate the instruction cache: + set 3, %l0 + set 0x00001000, %l1 + set 0x80001000, %l2 + sta %l0, [ %l1 ] 0x0c + sta %l0, [ %l2 ] 0x0c + ! and the data cache + sta %l0, [ %l1 ] 0x0e + sta %l0, [ %l2 ] 0x0e + nop + nop + nop + nop ! should be enough +#endif // !CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM +#endif // CYG_HAL_STARTUP_RAM + + +#include <cyg/hal/hal_cpu.h> // a copy of CygMon~s cpu.h + + +/* Address of clock switch */ +#define CLKSW_ADDR 0x01000003 + +/* Address of SW1 */ +#define SW1_ADDR 0x02000003 + +/* Address of LED bank */ +#define LED_ADDR 0x02000003 + +#define SRAM_BASE 0x30000000 +#define SRAM_END 0x30080000 + + +#define DRAM_BASE 0x04000000 /* base of system DRAM */ +#define CS3_BASE 0x00000000 /* base of internal resource regs */ +#define CS3_ASI 7 /* ASI of internal resource regs */ + +// DRAM_BASE2 is defined so that we run the same RAM-sizing code in both +// RAM and ROM startup versions; but the RAM startup one starts RAM sizing +// at 0x043ff000 ie. 4k down from the top of the 4M available. + +#ifdef CYG_HAL_STARTUP_RAM +#define DRAM_BASE2 DRAM_BASE + 0x00400000 - 0x1000 +#else +#define DRAM_BASE2 DRAM_BASE +#endif + + .macro led val + sethi %hi(LED_ADDR),%l7 + set \val,%l6 + not %l6, %l6 + stb %l6,[%l7 + %lo(LED_ADDR)] + .endm + + /* + * First, setup chip selects. + * + * NB: The AMR_VAL macro actually inverts the mask bits. For me, it is + * more natural to write a 1 bit where I want the address compared. + * The sparc registers use 0 bits, instead. + */ + + /* -CS0 ADDR_MASK:0xfc000000 ASI_MASK:0xfc */ + set AMR_VAL(0xfc,0xfc000000),%l0 + mov AMR0,%l1 + sta %l0,[%l1] 1 + + /* -CS1 BASE:0x10000000 ASI:4 */ + set ARSR_VAL(4,0x10000000),%l0 + mov ARSR1,%l1 + sta %l0,[%l1] 1 + /* -CS1 ADDR MASK:0xf0000000 ASI MASK:0x7 */ + set AMR_VAL(7,0xf0000000),%l0 + mov AMR1,%l1 + sta %l0,[%l1] 1 + + /* -CS2 BASE:0x20000000 ASI:4 */ + set ARSR_VAL(4,0x20000000), %l0 + mov ARSR2,%l1 + sta %l0,[%l1] 1 + /* -CS2 ADDR MASK:0xf0000000 ASI MASK:0x7 */ + set AMR_VAL(7,0xf0000000),%l0 + mov AMR2,%l1 + sta %l0,[%l1] 1 + + /* -CS3 BASE:CS3_BASE ASI:CS3_ASI */ + set ARSR_VAL(CS3_ASI,CS3_BASE),%l0 + mov ARSR3,%l1 + sta %l0,[%l1] 1 + /* -CS3 ADDR MASK:0xffff0000 ASI MASK:0x7 */ + set AMR_VAL(7,0xffff0000),%l0 + mov AMR3,%l1 + sta %l0,[%l1] 1 + + /* -CS4 BASE: DRAM_BASE ASI:0xb */ + set ARSR_VAL(0xb,DRAM_BASE),%l0 + mov ARSR4,%l1 + sta %l0,[%l1] 1 + /* -CS4 ADDR MASK:0xfc000000 ASI MASK:0xfc */ + set AMR_VAL(0xfc,0xfc000000),%l0 + mov AMR4,%l1 + sta %l0,[%l1] 1 + + /* -CS5 BASE:0x30000000 ASI:0xb */ + set ARSR_VAL(0xb,0x30000000),%l0 + mov ARSR5,%l1 + sta %l0,[%l1] 1 + /* -CS5 ADDR MASK:0xfff80000 ASI MASK:0xfc */ + set AMR_VAL(0xfc,0xfff80000),%l0 + mov AMR5,%l1 + sta %l0,[%l1] 1 + + + /* + * Setup wait states. Each wait state register sets the wait states for + * a pair of chip selects. The lower bits hold the wait state info for + * the lower numbered chip select. + */ + + /* -CS0: 5 wait states, -CS1: 7 wait states */ +// set WSSR_VAL(7,7,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 +// set WSSR_VAL(4,4,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 // FOUR -> CS1 + set WSSR_VAL(10,10,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 // TEN -> CS1 + mov WSSR0,%l1 + sta %l0,[%l1] 1 + + /* -CS2: wait states disabled, -CS3: wait states disabled */ + set WSSR_VAL(0,0,0,0,0,0),%l0 + mov WSSR1,%l1 + sta %l0,[%l1] 1 + + /* -CS4: wait states disabled, -CS5: 0 wait states */ + set WSSR_VAL(0,0,WSSR_WAITEN|WSSR_OVERRIDE,0,0,0),%l0 + mov WSSR2,%l1 + sta %l0,[%l1] 1 + + led 0x10 + + /* clear cache/BIU control register */ + mov CBIR,%l1 + sta %g0,[%l1] 1 + + /* Read clock switch to determine the value of the refresh timer */ + sethi %hi(CLKSW_ADDR),%l1 + ldub [%l1 + %lo(CLKSW_ADDR)],%l0 + btst 0x80,%l0 + bne,a 1f + mov 10,%l0 /* force to 10MHz if CLKSW-8 is ON */ + 1: + umul %l0,15,%l0 + mov DRLD,%l1 + sta %l0,[%l1] 1 + mov REFTMR,%l1 + sta %l0,[%l1] 1 + + /* read SW1 to get DRAM page size */ + sethi %hi(SW1_ADDR),%l1 + ldub [%l1 + %lo(SW1_ADDR)],%l0 + btst 0x10,%l0 + be,a 1f + mov 0x0e,%l0 /* 1K page if branch taken (SW1-5 is OFF) */ + mov 0x06,%l0 /* 2K page (SW1-5 is OFF) */ + 1: + mov SPGMR,%l1 + sta %l0,[%l1] 1 + + led 0x20 + +#ifdef CYG_HAL_STARTUP_ROM + /* Turn on all system services */ + mov SSCR_TIMER|SSCR_WAIT|SSCR_CS|SSCR_SAMEPG,%l0 + mov SSCR,%l1 + sta %l0,[%l1] 1 + nop + nop + nop + nop + +#endif + + led 0x30 + + /* + * Initialize caches. + */ + sethi %hi(0x1000),%l0 /* bank 1 invalidate */ + sethi %hi(0x80000000),%l1 /* bank 2 invalidate */ + mov 3,%l2 /* clear lock, lru, and valid bits */ + sta %l2,[%l0] 0xc /* do it - icache bank 1 */ + sta %l2,[%l0] 0xe /* do it - dcache bank 1 */ + sta %l2,[%l0 + %l1] 0xc /* do it - icache bank 2 */ + sta %l2,[%l0 + %l1] 0xe /* do it - dcache bank 2 */ + + /* now, enable caches and buffers */ + mov CBIR_ICEN|CBIR_DCEN|CBIR_PBEN|CBIR_WBEN,%l0 + mov CBIR,%l1 + sta %l0,[%l1] 1 + nop + nop + nop + nop + + /* enable data and insn bursts */ + mov BCR_IBE|BCR_DBE,%l0 + mov BCR,%l1 + sta %l0,[%l1] 1 + nop + nop + nop + nop + + /* + * DRAM setup/test. + */ + led 0x40 + + /* + * Test SW1-7 to determine normal or EDO mode. + * SW1-7 ON = EDO + * SW1-7 OFF = Normal. + */ + sethi %hi(SW1_ADDR),%l1 + ldub [%l1 + %lo(SW1_ADDR)],%l7 + mov DBANKR_SA04,%l0 /* DRAM starts at 0x04000000 */ + btst 0x40,%l7 + bne 1f /* branch if SW1-7 is OFF */ + mov SSCR_DRAM,%l1 + /* EDO DRAM, enable burst in SSCR and EDO in DBANKR */ + or %l1,SSCR_BURST,%l1 + or %l0,DBANKR_EDO,%l0 + 1: + /* + * Now, test SW1 to get DRAM page and bank size. + * SW1-5 ON = 2k page, 16MB bank. (up to 64MB total) + * SW1-5 OFF = 1k page, 4MB bank. (up to 16MB total) + */ + btst 0x10,%l7 + bne,a 1f /* branch if OFF */ + or %l0,DBANKR_4M|DBANKR_CA10,%l0 /* 1K page */ + or %l0,DBANKR_16M|DBANKR_CA11,%l0 /* 2K page */ + 1: + mov CS3_BASE+DBANKR,%l2 + sta %l0,[%l2] CS3_ASI + + mov DTIMR_RPS2|DTIMR_CBR3|DTIMR_CAS2|DTIMR_RP2,%l0 + mov CS3_BASE+DTIMR,%l2 + sta %l0,[%l2] CS3_ASI + + mov SSCR,%l2 + lda [%l2] 1, %l0 + or %l0,%l1,%l0 + sta %l0,[%l2] 1 + + /* + * Test SW1 to get potential DRAM limit. + * SW1-5 ON = 2k page, up to 64MB total + * SW1-5 OFF = 1k page, up to 16MB total + */ + btst 0x10,%l7 + bne,a 1f /* branch if OFF */ + sethi %hi(DRAM_BASE + 16*1024*1024),%l0 + sethi %hi(DRAM_BASE + 64*1024*1024),%l0 + 1: + + /* subtract 4 to get last valid DRAM address */ + add %l0,-4,%l0 + + /* Assume maximim memory and fill with pattern */ + set DRAM_BASE2,%l2 + set 0xaaaaaaaa,%l3 + 1: + st %l3,[%l2] + cmp %l2,%l0 + blt 1b + add %l2,4,%l2 + + /* + * Go back, read data and compare with written data. + * Fill in with zero as we go along. + */ + set DRAM_BASE2,%l2 + 1: + ld [%l2],%l4 + cmp %l4,%l3 + bne 2f + st %g0,[%l2] + cmp %l2,%l0 + blt,a 1b + add %l2,4,%l2 + 2: + led 0x50 + + sub %l2,64,%i6 + sethi %hi(DRAM_BASE),%l1 + sub %l2,%l1,%l0 + st %l0,[%i6] + +// NOTE that here, the frame pointer is set up to the top of RAM minus a +// little bit with the size of RAM at %fp (%i6) +#ifdef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM + + led 0x58 + + ! copy the trampoline code into the base of RAM (__ram_vectors_start) + ! including the two ~rogue~ instructions... + + .extern __ram_vectors_start + ! Using the true address here for the copy makes a badly-aligned + ! __ram_vectors less likely to hide as an obscure failure: + set __ram_vectors_start, %l0 ! get the start of RAM + set rom_vectors, %l1 ! get the start of the trampoline + set rom_vectors_end, %l2 ! ...and its end. +33: + ldd [ %l1 ], %l4 ! also uses %l5 + std %l4, [ %l0 ] + inc 8, %l1 + inc 8, %l0 + cmp %l1, %l2 + bl 33b + nop + + led 0x59 + + sethi %hi(__ram_vectors_start), %g1 ! get the start of RAM + andn %g1, 0xfff, %g1 + set real_vector_instructions, %l0 + ld [ %l0 ], %l1 + st %l1, [ %g1 ] ! into the vector + ld [ %l0 + 4 ], %l1 + st %l1, [ %g1 + 4 ] ! into the vector + + led 0x5a + + ! then invalidate the instruction cache: + set 3, %l0 + set 0x00001000, %l1 + set 0x80001000, %l2 + sta %l0, [ %l1 ] 0x0c + sta %l0, [ %l2 ] 0x0c + + led 0x5b + + ! and the data cache + sta %l0, [ %l1 ] 0x0e + sta %l0, [ %l2 ] 0x0e + nop + nop + nop + nop ! should be enough + + led 0x5c + + ! and (re)set the tbr, finally. + sethi %hi(__ram_vectors_start), %g1 + andn %g1, 0xfff, %g1 + wr %g1, %tbr ! Traps are at RAM start + nop ! (__ram_vectors_start) + nop + nop + + led 0x5d + +#else + + led 0x5f + +#endif // CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM (was CYG_HAL_STARTUP_ROM) + + ! turn on caches - copied from the book +#define set_size 64 +#define ini_tag 0 +#define adr1 0x00000000 +#define adr2 0x80000000 +#define step 16 +#define CTL_BITS 0x35 + + set set_size, %l7 + set adr1, %o1 + set adr2, %o2 + set ini_tag, %l0 +10: + sta %l0, [ %o1 ] 0x0c + sta %l0, [ %o1 ] 0x0e + sta %l0, [ %o2 ] 0x0c + sta %l0, [ %o2 ] 0x0e + add %o1, step, %o1 + subcc %l7, 1, %l7 + bne 10b + add %o2, step, %o2 + + set 0, %l1 + set CTL_BITS, %l2 + sta %l2, [ %l1 ] 0x01 + nop + nop + nop + nop ! delay to let caches stabilize + + led 0x60 + + // Now set up the 86940 + +#define TRGM0 0 +#define TRGM1 4 +#define REQSNS 8 +#define REQCLR 12 +#define IMASK 16 +#define IRLAT 20 +#define IMODE 24 + + sethi %hi( 0x10000000 ), %l1 ! base address of the 86940 companion + + set 0xfffe0000, %l4 ! mask all intrs + add %l1, IMASK, %l3 + sta %l4, [ %l3 ] 4 + + set 0x11400000, %l6 ! Channels 14,12,11 into Active Low + add %l1, TRGM0, %l3 + sta %l6, [ %l3 ] 4 + + set 0x05100000, %l6 ! Channels 5,4,2 into Active Low + add %l1, TRGM1, %l3 + sta %l6, [ %l3 ] 4 + + add %l1, REQCLR, %l3 ! clear all pending intrs + sta %l4, [ %l3 ] 4 + + set 0x00100000, %l6 ! clear the latch + add %l1, IRLAT, %l3 + sta %l6, [ %l3 ] 4 + + nop + nop + nop + + led 0x70 + +#endif /* CYGONCE_HAL_HALBOOT_SI */ +/* EOF halboot.si */ diff --git a/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.h b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.h new file mode 100644 index 0000000..671cf17 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Fri Oct 20 09:29:47 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x4010000) +#define CYGMEM_REGION_ram_SIZE (0x3f0000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x4400000 - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.ldi b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.ldi new file mode 100644 index 0000000..58c9364 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Fri Oct 20 09:29:47 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x4010000, LENGTH = 0x3f0000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_ram_vectors (ram, 0x4010000, LMA_EQ_VMA) + SECTION_rom_vectors (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.mlt b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.mlt new file mode 100644 index 0000000..b59fc2a --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_ram.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 4010000 3f0000 0 ! +section ram_vectors 0 1 0 1 1 1 1 1 4010000 4010000 rom_vectors rom_vectors !The ram_vectors section is to allow some free space to copy vectors into from the ROM. This is required to be variable size to accomodate SVT or MVT; 80 bytes vs 4kB. Copying is not necessary with MVT, but it is optional because it may offer performance gains. Copying is required for SVT because the (aligned) start of ROM contains initialization instructions. RAM copy is used rather than leave a big gap in the ROM to get an aligned address for the trampoline code. For RAM startup, ram_vectors will usually be of size zero, unless MVT and copying are enabled for memory estimation reasons. +section rom_vectors 0 8 0 1 0 1 0 1 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 8 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 8 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 bss bss ! +section bss 0 8 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! diff --git a/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.h b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.h new file mode 100644 index 0000000..10051ee --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Fri Oct 20 09:30:14 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_rom (0) +#define CYGMEM_REGION_rom_SIZE (0x20000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#define CYGMEM_REGION_ram (0x4000000) +#define CYGMEM_REGION_ram_SIZE (0x400000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x4400000 - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.ldi b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.ldi new file mode 100644 index 0000000..1edd5e0 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.ldi @@ -0,0 +1,28 @@ +// eCos memory layout - Fri Oct 20 09:30:14 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + rom : ORIGIN = 0, LENGTH = 0x20000 + ram : ORIGIN = 0x4000000, LENGTH = 0x400000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_ram_vectors (ram, 0x4000000, LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.mlt b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.mlt new file mode 100644 index 0000000..a59b574 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/include/pkgconf/mlt_sparclite_sleb_rom.mlt @@ -0,0 +1,14 @@ +version 0 +region rom 0 20000 1 ! +region ram 4000000 400000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 0 0 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 8 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 8 0 1 0 0 0 1 data ! +section ram_vectors 0 1 0 1 1 1 1 0 4000000 4000000 data !The ram_vectors section is to allow some free space to copy vectors into from the ROM. This is required to be variable size to accomodate SVT or MVT; 80 bytes vs 4kB. Copying is not necessary with MVT, but it is optional because it may offer performance gains. Copying is required for SVT because the (aligned) start of ROM contains initialization instructions. RAM copy is used rather than leave a big gap in the ROM to get an aligned address for the trampoline code. For RAM startup, ram_vectors will usually be of size zero, unless MVT and copying are enabled for memory estimation reasons. +section data 0 8 1 1 0 1 0 0 bss ! +section bss 0 8 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! diff --git a/ecos/packages/hal/sparclite/sleb/current/src/hal_cygm.S b/ecos/packages/hal/sparclite/sleb/current/src/hal_cygm.S new file mode 100644 index 0000000..8ad381c --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/src/hal_cygm.S @@ -0,0 +1,227 @@ +/*============================================================================= +// +// hal_cygm.S +// +// SPARClite and CygMon play nice: vector service routines +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt +// Date: 1998-02-24 +// Purpose: SPARClite vectors for interworking with CygMon +// Description: see vectors.S and hal_priv.c; these VSRs are installed to +// interwork with CygMon. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +!----------------------------------------------------------------------------- + +// .file "hal_cygm.S" + +!----------------------------------------------------------------------------- + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> +#include <pkgconf/hal_sparclite_sleb.h> + +!------------------------------------------------------------------------ + +#include <cyg/hal/vectors.h> // eCos vector number et al +#include <cyg/hal/hal_cygm.h> // CygMon vector number et al + +#define DELAYS_AFTER_WRPSR_SAME_WINDOW +#define DELAYS_AFTER_WRWIM + +!------------------------------------------------------------------------ + + .text + +!--------------------------------------------------------------------------- + +#ifdef CYG_HAL_USE_ROM_MONITOR_CYGMON + + .global hal_user_trap_to_cygmon_vsr +hal_user_trap_to_cygmon_vsr: + ! here,locals have been set up as follows: + ! %l0 = psr (with this CWP/window-level in it) + ! %l1 = pc + ! %l2 = npc + ! %l3 = vector number (1-15 for interrupts) + ! and we are in our own register window, though it is likely that + ! the next one will need to be saved before we can use it: + ! ie. this one is the invalid register window. + + rd %tbr, %l4 ! Get the trap type + srl %l4, 4, %l4 ! into the bottom byte + and %l4, 0xff, %l4 ! actual trap number + + ! we deal with traps 1,3,8(+128) and 255 here. + ! ta 1 => tt 129 : breakpoint + ! ta 3 => tt 131 : flush windows (unneccessary, JIC) + ! ta 8 => tt 136 : syscall (apparently) + ! ta 127 -OR- Debug Support Unit trap + ! => tt 255 : debug trap + ! others bounce through to eCos handler, of course. + + cmp %l4, 129 + beq bounce_to_cygmon + mov BSP_EXC_BREAK, %l5 + + ! ta 2 is a "skipped" breakpoint, we increment the PC, NPC + ! ourselves to permit continuation. + cmp %l4, 130 + bne 1f + nop + mov %l2, %l1 + add %l2, 4, %l2 + b bounce_to_cygmon + mov BSP_EXC_BREAK, %l5 + +1: + cmp %l4, 131 + beq bounce_to_cygmon + mov BSP_EXC_WINFLUSH, %l5 + + cmp %l4, 136 + beq bounce_to_cygmon + mov BSP_EXC_SYSCALL, %l5 + + cmp %l4, 255 + beq bounce_to_cygmon + mov BSP_EXC_DEBUG, %l5 + + ! if we are here, it~s not a recognized trap to feed to CygMon, so + ! call the eCos default trap VSR: + .extern hal_default_exception_vsr + ba hal_default_exception_vsr ! should be in range + nop ! does not return + + + .global hal_nofpcp_trap_to_cygmon_vsr +hal_nofpcp_trap_to_cygmon_vsr: + rd %tbr, %l4 ! Get the trap type + srl %l4, 4, %l4 ! into the bottom byte + and %l4, 0xff, %l4 ! actual trap number + ! we deal with trap types 4 and 36 here. + + cmp %l4, 4 + beq bounce_to_cygmon + mov BSP_EXC_FPDIS, %l5 + + cmp %l4, 36 + beq bounce_to_cygmon + mov BSP_EXC_CPDIS, %l5 + + ! we really should not be here otherwise, but for best debugging... + b bounce_to_cygmon + mov BSP_EXC_TRAP, %l5 + +bounce_to_cygmon: + ! here we have decided to jump over CygMon, the CygMon vector + ! number to use is in %l5. + set CYGMON_VECTOR_TABLE_BASE, %l6 + sll %l5, 2, %l5 ! to a word offset + ! our calling convention is the same, so... + ld [ %l6 + %l5 ], %l6 + jmp %l6 + nop + + +// Now a handler for INT15 (NMI) to assist in debugging; we have to ack and +// clear the interrupt, after waiting for the source to go away, I guess... + .global hal_nmi_handler +hal_nmi_handler: + ! here,locals have been set up as follows: + ! %l0 = psr (with this CWP/window-level in it) + ! %l1 = pc + ! %l2 = npc + ! %l3 = vector number (1-15 for interrupts) + ! and we are in our own register window, though it is likely that + ! the next one will need to be saved before we can use it: + ! ie. this one is the invalid register window. + +#define TRGM0 0 +#define TRGM1 4 +#define REQSNS 8 +#define REQCLR 12 +#define IMASK 16 +#define IRLAT 20 +#define IMODE 24 + +#define NMIBIT 0x80000000 + + sethi %hi( 0x10000000 ), %l4 ! base address of the 86940 companion + +10: + add %l4, REQCLR, %l5 ! Request clear register + set NMIBIT, %l6 + sta %l6, [ %l5 ] 4 ! Clear INT15 + + add %l4, REQSNS, %l5 ! Request sense register + lda [ %l5 ] 4, %l7 + andcc %l6, %l7, %g0 ! test the sense bit + + sethi %hi( 0x02000000 ), %l6 ! Pump it out to the LED + srl %l7, 24, %l7 + stb %l7, [ %l6 + 3 ] + + bne 10b ! poll until the request is gone + nop + nop + nop + + set 0x00100000, %l6 ! clear the latch + add %l4, IRLAT, %l5 + sta %l6, [ %l5 ] 4 + + nop + nop + nop + + b bounce_to_cygmon + mov BSP_EXC_INT15, %l5 + + + + + +#endif // CYG_HAL_USE_ROM_MONITOR_CYGMON + +! end of hal_cygm.S diff --git a/ecos/packages/hal/sparclite/sleb/current/src/hal_diag.c b/ecos/packages/hal/sparclite/sleb/current/src/hal_diag.c new file mode 100644 index 0000000..d826636 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/src/hal_diag.c @@ -0,0 +1,365 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: nickg +// Date: 1998-03-02 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> +#include <pkgconf/hal_sparclite_sleb.h> + +#include <cyg/infra/cyg_type.h> // base types + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> + +#include <cyg/hal/hal_cygm.h> + +/*---------------------------------------------------------------------------*/ + +#ifdef CYG_KERNEL_DIAG_GDB + +#ifdef CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT // then force $O packets to serial + +void hal_diag_init(void) +{ + // hal_diag_init_serial(); +} + +void hal_diag_write_char_serial( char c ) +{ + HAL_REORDER_BARRIER(); + HAL_DIAG_WRITE_CHAR_DIRECT( c ); + HAL_REORDER_BARRIER(); + HAL_DIAG_WRITE_CHAR_WAIT_FOR_EMPTY(); + HAL_REORDER_BARRIER(); +} + +void hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + + HAL_DISABLE_INTERRUPTS(old); + + while(1) + { + cyg_uint32 status, c1, tries; + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + + hal_diag_write_char_serial('$'); + hal_diag_write_char_serial('O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial(h); + hal_diag_write_char_serial(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial('#'); + hal_diag_write_char_serial(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial(hex[csum&0xF]); + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. This is the reason for this clause + // being a loop. + status = 0; + tries = 1000000000; + while ( 0 == (HAL_SPARC_86940_FLAG_RXRDY & status) ) { + if ( 0 == --tries ) + break; + HAL_SPARC_86940_SDTR0_STAT_READ( status ); + } + if ( 0 == tries ) // then we broke out after waiting + continue; // the outer loop, send the packet + + HAL_SPARC_86940_SDTR0_RXDATA_READ( c1 ); + + // We must ack the interrupt caused by that read to avoid + // confusing the GDB stub ROM. + HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_VECTOR_INTERRUPT_10 ); + + if( c1 == '+' ) + break; // a good acknowledge + + if( c1 == 3 ) { + // Ctrl-C: breakpoint. + asm volatile( "ta 2; nop; nop; nop" ); + break; + } + // otherwise, loop round again + } + + pos = 0; + + // And re-enable interrupts + HAL_RESTORE_INTERRUPTS(old); + + } +} +#else // CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT not defined; use CygMon + +// All this code provided by MSalter - ta. + +struct bsp_comm_procs { + void *ch_data; + void (*__write)(void *ch_data, const char *buf, int len); + int (*__read)(void *ch_data, char *buf, int len); + void (*__putc)(void *ch_data, char ch); + int (*__getc)(void *ch_data); + int (*__control)(void *ch_data, int func, ...); +}; + +// This is pointed to by entry BSP_NOTVEC_BSP_COMM_PROCS: +typedef struct { + int version; /* version number for future expansion */ + void *__ictrl_table; + void *__exc_table; + void *__dbg_vector; + void *__kill_vector; + struct bsp_comm_procs *__console_procs; + struct bsp_comm_procs *__debug_procs; + void *__flush_dcache; + void *__flush_icache; + void *__cpu_data; + void *__board_data; + void *__sysinfo; + int (*__set_debug_comm)(int __comm_id); + void *__set_console_comm; +} bsp_shared_t; + + +static int +hal_bsp_set_debug_comm(int arg) +{ + bsp_shared_t *shared; + + shared = (bsp_shared_t *) + (CYGMON_VECTOR_TABLE[ BSP_NOTVEC_BSP_COMM_PROCS ]); + + if (0 != shared->__set_debug_comm) { + return (*(shared->__set_debug_comm))(arg); + } + return 0; +} + +static int +hal_bsp_console_write(const char *p, int len) +{ + bsp_shared_t *shared; + struct bsp_comm_procs *com; + + shared = (bsp_shared_t *) + (CYGMON_VECTOR_TABLE[ BSP_NOTVEC_BSP_COMM_PROCS ]); + + com = shared->__console_procs; + + if (0 != com) { + com->__write(com->ch_data, p, len); + +#if 1 + // FIXME: This is a workaround for PR 19926; CygMon does not + // expect to be sharing the line with a serial driver (which + // can be excused :) and so doesn't acknowledge the interrupt. + // In normal circumstances CygMon would handle the resulting + // interrupt and do the right thing. However, when using the + // serial driver it is handling the interrupts and gets + // mightily confused by these spurious interrupts. + // + // As a workaround, ask CygMon which communication port is + // using for console output. If this is the serial port + // (comm 0), acknowledge the interrupt. + if ( 0 == hal_bsp_set_debug_comm( -1 ) ) + HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_VECTOR_INTERRUPT_10 ); +#endif + + return 1; + } + return 0; +} + +static void +hal_dumb_serial_write(const char *p, int len) +{ + int i; + for ( i = 0 ; i < len; i++ ) { + HAL_DIAG_WRITE_CHAR_DIRECT( p[ i ] ); + } +} + + +void hal_diag_init(void) +{ +} + +void hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + + HAL_DISABLE_INTERRUPTS(old); + + if ( ! hal_bsp_console_write( line, pos ) ) + // then there is no function registered, just spew it out serial + hal_dumb_serial_write( line, pos ); + + pos = 0; + + // And re-enable interrupts + HAL_RESTORE_INTERRUPTS(old); + + } +} + +#endif // CYG_KERNEL_DIAG_GDB_SERIAL_DIRECT not defined; use CygMon + +#else // CYG_KERNEL_DIAG_GDB not defined, so we are going to the serial line + // without GDB encoding - likely to be ROM startup. + +/* Address of clock switch */ +#define CLKSW_ADDR 0x01000003 + +/* Address of SW1 */ +#define SW1_ADDR 0x02000003 + +void hal_diag_init(void) +{ + cyg_uint32 clk, tval; + + // first set the baud rate + + clk = *(unsigned char *)CLKSW_ADDR; + if (clk & 0x80) + clk = 10; + + clk = (clk & 0x3f) * 1000000; /* in MHz */ + + tval = clk / 19200; + tval /= 32; + tval -= 1; + + HAL_SPARC_86940_TCR3_WRITE( + HAL_SPARC_86940_TCR_CE | + HAL_SPARC_86940_TCR_CLKINT | + HAL_SPARC_86940_TCR_OUTC3 | + HAL_SPARC_86940_TCR_SQWAVE ); + + HAL_SPARC_86940_RELOAD3_WRITE( tval); + +#define DELAY(x) \ + CYG_MACRO_START int i; for (i = 0; i < x; i++); CYG_MACRO_END + + HAL_SPARC_86940_SDTR0_CTRL_WRITE( 0 ); + DELAY(100); + HAL_SPARC_86940_SDTR0_CTRL_WRITE( 0 ); + DELAY(100); + HAL_SPARC_86940_SDTR0_CTRL_WRITE( 0 ); + DELAY(100); + + HAL_SPARC_86940_SDTR0_CTRL_WRITE( HAL_SPARC_86940_SER_CMD_IRST ); + DELAY(100); + + /* first write after reset is to mode register */ + HAL_SPARC_86940_SDTR0_CTRL_WRITE( HAL_SPARC_86940_SER_DIV16_CLK | + HAL_SPARC_86940_SER_8BITS | + HAL_SPARC_86940_SER_NO_PARITY | + HAL_SPARC_86940_SER_STOP1 ); + DELAY(100); + + /* subsequent writes are to command register */ + HAL_SPARC_86940_SDTR0_CTRL_WRITE( HAL_SPARC_86940_SER_CMD_RTS | + HAL_SPARC_86940_SER_CMD_DTR | + HAL_SPARC_86940_SER_CMD_EFR | + HAL_SPARC_86940_SER_CMD_RXEN | + HAL_SPARC_86940_SER_CMD_TXEN ); + DELAY(100); +} + + + + + +#endif // CYG_KERNEL_DIAG_GDB + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */ diff --git a/ecos/packages/hal/sparclite/sleb/current/src/hal_priv.c b/ecos/packages/hal/sparclite/sleb/current/src/hal_priv.c new file mode 100644 index 0000000..85e3f06 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/src/hal_priv.c @@ -0,0 +1,218 @@ +//============================================================================= +// +// hal_priv.c +// +// SPARClite Architecture sim-specific private variables +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt +// Date: 1998-12-10 +// Purpose: private vars for SPARClite sim. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_sparclite.h> +#include <pkgconf/hal_sparclite_sleb.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arch.h> + +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> // CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT +#endif + +#include <cyg/hal/hal_clock.h> + +// ------------------------------------------------------------------------ +// Clock static to keep period recorded. +cyg_int32 cyg_hal_sparclite_clock_period = 0; + +/* Address of clock switch */ +#define CLKSW_ADDR 0x01000003 + +#define HAL_SPARC_86940_TIMER1_CONTROL_INIT ( \ + 0 | \ + HAL_SPARC_86940_TCR_CLKPRS | \ + HAL_SPARC_86940_TCR_OUTLOW ) + // Disable, CLKSEL=prescale(2), periodic interrupts, gate 0 + // and lower the output: OUTCTL = 2 + +#define HAL_SPARC_86940_TIMER1_CONTROL_ENABLE ( \ + HAL_SPARC_86940_TCR_CE | \ + HAL_SPARC_86940_TCR_CLKPRS | \ + HAL_SPARC_86940_TCR_OUTSAME ) + // Enable + .... and no change to the output: OUTCTL = 0 + +void hal_clock_initialize( cyg_uint32 p ) +{ + cyg_uint32 ints; + cyg_uint32 clk; + HAL_DISABLE_INTERRUPTS( ints ); + + HAL_SPARC_86940_TIMER1_CONTROL_WRITE( + HAL_SPARC_86940_TIMER1_CONTROL_INIT ); // Make sure it's disabled + + // Clear any pending interrupts: + HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_RTC ); + + clk = *(unsigned char *)CLKSW_ADDR; + if (clk & 0x80) + clk = 10; + + /* could be 10 - 62 MHz */ + clk = (clk & 0x3f); /* in MHz */ + // BUT the 86940 is internally clocked at half that speed (page 20 RHS) + clk >>= 1; + // so the clock is now the number of system ticks we want per counter + // tick... + HAL_SPARC_86940_TIMER1_PRESCALER_WRITE( + 0 /* internal clock */ | + HAL_SPARC_86940_PRS_ODIV1 | + clk ); + // should give 1MHz on the externally visible counter... + HAL_SPARC_86940_TIMER1_CONTROL_WRITE( + HAL_SPARC_86940_TIMER1_CONTROL_INIT ); + HAL_SPARC_86940_TIMER1_RELOAD_WRITE( p ); + HAL_SPARC_86940_TIMER1_CONTROL_WRITE( + HAL_SPARC_86940_TIMER1_CONTROL_ENABLE ); + HAL_SPARC_86940_TIMER1_RELOAD_WRITE( p ); + cyg_hal_sparclite_clock_period = p; + HAL_RESTORE_INTERRUPTS( ints ); +} + +// ------------------------------------------------------------------------ + +#ifdef CYG_HAL_USE_ROM_MONITOR_CYGMON +#include <cyg/hal/hal_cygm.h> // CygMon vector table & layout + +static struct { int eCosV, CygMonV; } setup[] = { + { CYGNUM_HAL_VECTOR_OTHERS , BSP_EXC_TRAP }, + { CYGNUM_HAL_VECTOR_FETCH_ABORT , BSP_EXC_IACCESS }, + { CYGNUM_HAL_VECTOR_ILLEGAL_OP , BSP_EXC_ILL }, + { CYGNUM_HAL_VECTOR_PRIV_OP , BSP_EXC_IPRIV }, + { CYGNUM_HAL_VECTOR_UNALIGNED , BSP_EXC_ALIGN }, + { CYGNUM_HAL_VECTOR_DATA_ABORT , BSP_EXC_DACCESS }, +}; + +#endif // CYG_HAL_USE_ROM_MONITOR_CYGMON + +// ------------------------------------------------------------------------ +// Board specific startups. + +extern void hal_board_prestart( void ); +extern void hal_board_poststart( void ); + +#define SLEB_LED (*(volatile char *)(0x02000003)) + +#define LED( _x_ ) SLEB_LED = (char)(0xff & ~(_x_)) + +void hal_board_prestart( void ) +{ + + LED( 0xc0 ); + + // Disable default clocks &c + HAL_SPARC_86940_TIMER1_PRESCALER_WRITE( 1 ); // as if at reset + HAL_SPARC_86940_TIMER1_CONTROL_WRITE( 0 ); // as if at reset + +#ifdef CYG_HAL_USE_ROM_MONITOR_CYGMON + // then initialize our vectors to point to (or bounce to) + // CygMon's equivalent functionality. + { + extern void hal_user_trap_to_cygmon_vsr( void ); + extern void hal_nofpcp_trap_to_cygmon_vsr( void ); + extern void hal_nmi_handler( void ); + int i; + + HAL_VSR_SET( CYGNUM_HAL_VECTOR_USER_TRAP, + (CYG_ADDRESS)hal_user_trap_to_cygmon_vsr, NULL ); + + HAL_VSR_SET( CYGNUM_HAL_VECTOR_NOFPCP, + (CYG_ADDRESS)hal_nofpcp_trap_to_cygmon_vsr, NULL ); + + for ( i = 0; i < sizeof(setup)/sizeof(setup[0]); i++ ) + HAL_VSR_SET( setup[i].eCosV, + CYGMON_VECTOR_TABLE[ setup[i].CygMonV ], NULL ); + + // Just point this one straight though, and unmask it. + // That way CygMon looks after ^Cs itself. + HAL_VSR_SET( CYGNUM_HAL_VECTOR_INTERRUPT_10, + CYGMON_VECTOR_TABLE[ BSP_EXC_INT10 ], NULL ); + HAL_INTERRUPT_UNMASK( CYGNUM_HAL_VECTOR_INTERRUPT_10 ); + + // Just point this one straight though, and unmask it. + // That way CygMon looks after the Ethernet itself. + HAL_VSR_SET( CYGNUM_HAL_VECTOR_INTERRUPT_14, + CYGMON_VECTOR_TABLE[ BSP_EXC_INT14 ], NULL ); + HAL_INTERRUPT_UNMASK( CYGNUM_HAL_VECTOR_INTERRUPT_14 ); + + // Install handler for the NMI button on the board + HAL_VSR_SET( CYGNUM_HAL_VECTOR_INTERRUPT_15, + (CYG_ADDRESS)hal_nmi_handler, NULL ); + HAL_INTERRUPT_UNMASK( CYGNUM_HAL_VECTOR_INTERRUPT_15 ); + + LED( 0xc4 ); + +#ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT + { + extern void patch_dbg_syscalls(void * vector); + patch_dbg_syscalls( (void *)CYGMON_VECTOR_TABLE ); + } +#endif // CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT + + } +#endif // CYG_HAL_USE_ROM_MONITOR_CYGMON + + LED( 0xc8 ); +} + +void hal_board_poststart( void ) +{ + LED( 0xe0 ); + HAL_ENABLE_INTERRUPTS(); + LED( 0xf0 ); +} + + +// EOF hal_priv.c diff --git a/ecos/packages/hal/sparclite/sleb/current/tests/slebintr.c b/ecos/packages/hal/sparclite/sleb/current/tests/slebintr.c new file mode 100644 index 0000000..b8f85b1 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/tests/slebintr.c @@ -0,0 +1,306 @@ +/*================================================================= +// +// slebintr.c +// +// SPARClite HAL interrupt manipulation test +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dsm +// Contributors: dsm, nickg +// Date: 1998-06-18 +//####DESCRIPTIONEND#### +*/ + +#include <pkgconf/system.h> + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/infra/cyg_ass.h> + +#include <cyg/infra/testcase.h> + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_clock.h> + +#include <pkgconf/infra.h> + +#include <cyg/infra/diag.h> + +#define DELAY(x) \ + CYG_MACRO_START int i; for (i = 0; i < x; i++); CYG_MACRO_END + +#define DLA 100 + +static int l, u, m, j; + +int levels[ 16 ]; +int ups[ 16 ]; +int masks[ 16 ]; +int reqs[ 16 ]; + +#define XDIGIT( q ) (q + ((q < 10) ? '0' : ('A'-10) )) + +#define SETSTR( x, y, str ) CYG_MACRO_START \ + str[0] = XDIGIT( x ); \ + str[1] = XDIGIT( y ); \ +CYG_MACRO_END + +static char lstr[] = "xy Bad level"; +static char mstr[] = "xy Bad mask"; +static char ustr[] = "xy Bad up"; + + +static void checkallbut( int z ) +{ + int i; + for ( i = 1; i < 16; i++ ) { + int level, up, hipri, mask, req; + if ( z == i ) + continue; + + SETSTR( i, z, lstr ); + SETSTR( i, z, mstr ); + SETSTR( i, z, ustr ); + + HAL_INTERRUPT_QUERY_INFO( i, level, up, hipri, mask, req); + l = level; + u = up; + m = mask; + j = i; + +#if 0 // for manual testing really... + if ( level != levels[i] ) + CYG_TEST_INFO( lstr ); + if ( up != ups[i] ) + CYG_TEST_INFO( ustr ); + if ( mask != masks[i] ) + CYG_TEST_INFO( mstr ); + if ( (level != levels[i] ) + | ( up != ups[i] ) + | ( mask != masks[i] ) ) { + CYG_TEST_INFO( "Re-reading" ); + HAL_INTERRUPT_QUERY_INFO( i, level, up, hipri, mask, req); + } +#endif + CYG_TEST_CHECK( level == levels[i], lstr ); + CYG_TEST_CHECK( up == ups[i], ustr ); + CYG_TEST_CHECK( mask == masks[i], mstr ); + } +} + +// input is the active phase of the chosen interrupt. It is assumed that +// the source is normally level-sensititve rather than edge-sensitive. +static void interferewith( int which, int input ) +{ + int level, up, hipri, mask, req; + + // Interfere with interrupt 'which' + HAL_INTERRUPT_CONFIGURE( which, 1, input ); // should be no change + + checkallbut( 0 ); // so don't exclude any of them + + HAL_INTERRUPT_CONFIGURE( which, 1, !input ); // make it other-sensitive + DELAY( DLA ); + HAL_INTERRUPT_ACKNOWLEDGE( which ); + DELAY( DLA ); + HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req); + CYG_TEST_CHECK( 0 != level , "Int not level-sensitive (-ve level)" ); + if ( input ) + CYG_TEST_CHECK( 0 == up, "Int high level (-ve level)" ); + else + CYG_TEST_CHECK( 0 != up, "Int low level (-ve level)" ); + CYG_TEST_CHECK( 0 != mask , "Int unmasked (-ve level)" ); + CYG_TEST_CHECK( 0 != req , "Int not requesting (-ve level)" ); + checkallbut( which ); // don't check #which, we're messing with it + + HAL_INTERRUPT_CONFIGURE( which, 0, input ); // edge, default sense + DELAY( DLA ); + HAL_INTERRUPT_ACKNOWLEDGE( which ); + DELAY( DLA ); + HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req); + CYG_TEST_CHECK( 0 == level , "Int not edge-sensitive (+ve edge)" ); + if ( input ) + CYG_TEST_CHECK( 0 != up, "Int low edge (+ve edge)" ); + else + CYG_TEST_CHECK( 0 == up, "Int high edge (+ve edge)" ); + CYG_TEST_CHECK( 0 != mask , "Int unmasked (+ve edge)" ); + CYG_TEST_CHECK( 0 == req , "Int requesting (+ve edge)" ); + checkallbut( which ); // don't check #which, we're messing with it + + HAL_INTERRUPT_CONFIGURE( which, 0, !input ); // edge, opposite sense + DELAY( DLA ); + HAL_INTERRUPT_ACKNOWLEDGE( which ); + DELAY( DLA ); + HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req); + CYG_TEST_CHECK( 0 == level , "Int not edge-sensitive (-ve edge)" ); + if ( input ) + CYG_TEST_CHECK( 0 == up, "Int high edge (-ve edge)" ); + else + CYG_TEST_CHECK( 0 != up, "Int low edge (-ve edge)" ); + CYG_TEST_CHECK( 0 != mask , "Int unmasked (-ve edge)" ); + CYG_TEST_CHECK( 0 == req , "Int requesting (-ve edge)" ); + checkallbut( which ); // don't check #which, we're messing with it + + HAL_INTERRUPT_CONFIGURE( which, 1, input ); // back to original value + DELAY( DLA ); + HAL_INTERRUPT_ACKNOWLEDGE( which ); + DELAY( DLA ); + checkallbut( 0 ); // so don't exclude any of them +} + +// ------------------------------------------------------------------------ + +#ifndef CYGPKG_KERNEL +// then the clock is not initialized! +#undef HAL_CLOCK_READ +// so provide a dumb counter, so we do the test a number of times anyway. +static int pseudotime = 0; +#define HAL_CLOCK_READ( _pval_ ) *(_pval_) = \ + ((pseudotime > 10) ? (pseudotime = 0) : ++pseudotime) +#endif + +static int start( void ) +{ + // We'll mess about with these interrupt sources: + // 13 : EX_IRQ13 from expansion board, active HIGH + // 12 : EX_IRQ12 from expansion board, active LOW + // 4 : EX_IRQ4 from expansion board, active LOW + // 3 : EX_IRQ3 from expansion board, active HIGH + + int i, hipri; + for ( i = 1; i < 16; i++ ) { + HAL_INTERRUPT_QUERY_INFO( i, levels[i], ups[i], + hipri, masks[i], reqs[i]); + } + CYG_TEST_CHECK( 0 != masks[13], "Int 13 unmasked initially" ); + CYG_TEST_CHECK( 0 != masks[12], "Int 12 unmasked initially" ); + CYG_TEST_CHECK( 0 != masks[ 4], "Int 4 unmasked initially" ); + CYG_TEST_CHECK( 0 != masks[ 3], "Int 3 unmasked initially" ); + CYG_TEST_CHECK( 0 == reqs[13], "Int 13 requests initially" ); + CYG_TEST_CHECK( 0 == reqs[12], "Int 12 requests initially" ); + CYG_TEST_CHECK( 0 == reqs[ 4], "Int 4 requests initially" ); + CYG_TEST_CHECK( 0 == reqs[ 3], "Int 3 requests initially" ); + CYG_TEST_CHECK( 0 != levels[13], "Int 13 edgetrig initially" ); + CYG_TEST_CHECK( 0 != levels[12], "Int 12 edgetrig initially" ); + CYG_TEST_CHECK( 0 != levels[ 4], "Int 4 edgetrig initially" ); + CYG_TEST_CHECK( 0 != levels[ 3], "Int 3 edgetrig initially" ); + CYG_TEST_CHECK( 0 != ups[13], "Int 13 not up initially" ); + CYG_TEST_CHECK( 0 == ups[12], "Int 12 is up initially" ); + CYG_TEST_CHECK( 0 == ups[ 4], "Int 4 is up initially" ); + CYG_TEST_CHECK( 0 != ups[ 3], "Int 3 not up initially" ); + + checkallbut( 0 ); // don't exclude any of them + + // I want to run this loop for 100 centiSeconds, so that 100 clock + // interrupts have occurred whilst interfering with the other interrupt + // state, to provoke possible problems with interactions there. On a + // 100MHz 86832 with default configuration, this usually gives 1200 + // loops in total, 12 per centiSecond. But with config variance and + // caching behaviour, it's quite possible for this loop to take much + // longer, if it takes over 1/2 a centiSecond, aliasing effects could + // cause the timing to fail completely, causing test timeouts. Hence + // the additional loop limit of 20 times round the inner loop, aiming + // for a maximum elapsed time of 20 S maximum, plus extra chances to + // break out part way through the loop if a tick has passed. + + hipri = 0; + CYG_TEST_INFO( "About to configure interrupts" ); + for ( i = 0; i < 100; i++ ) { + int t1, t2, j; + HAL_CLOCK_READ( &t1 ); + // Do this while/until there is a clock tick + // ie. some interrupt activity: + for ( j = 0; j < 20; j++ ) { + t2 = t1; + hipri++; + interferewith( 13, 1 ); + interferewith( 3, 1 ); + interferewith( 4, 0 ); + HAL_CLOCK_READ( &t1 ); + if ( t1 < t2 ) + break; // clock has wrapped + t2 = t1; + interferewith( 12, 0 ); + interferewith( 3, 1 ); + interferewith( 3, 1 ); + HAL_CLOCK_READ( &t1 ); + if ( t1 < t2 ) + break; // clock has wrapped + t2 = t1; + interferewith( 4, 0 ); + interferewith( 13, 1 ); + interferewith( 12, 0 ); + interferewith( 12, 0 ); + HAL_CLOCK_READ( &t1 ); + if ( t1 < t2 ) + break; // clock has wrapped + } + } + CYG_TEST_PASS( "Configured interrupts 3,4,12 & 13 a great deal" ); + return hipri; +} + +// ------------------------------------------------------------------------- + +externC void +#ifdef CYGPKG_KERNEL +cyg_user_start( void ) +#else +cyg_start( void ) +#endif +{ + int loops; + CYG_TEST_INIT(); + CYG_TEST_INFO( "cyg_user_start()" ); + HAL_ENABLE_INTERRUPTS(); + loops = start(); + // Typically about 1200 loops execute on the 33MHz 86832; + // I hoped to put in a check that we hadn't wasted time in + // spurious interrupts, but kernel instrumentation, for example, + // is more than enough to slow the world down... so keep this + // very weak test in, as a placeholder. + CYG_TEST_CHECK( 100 <= loops, "Not enough tests executed" ); + CYG_TEST_EXIT( "All done" ); +} + +// ------------------------------------------------------------------------- + +/* EOF slebintr.c */ diff --git a/ecos/packages/hal/sparclite/sleb/current/tests/slebstak.c b/ecos/packages/hal/sparclite/sleb/current/tests/slebstak.c new file mode 100644 index 0000000..e4ca658 --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/tests/slebstak.c @@ -0,0 +1,166 @@ +/*================================================================= +// +// slebstak.c +// +// SPARClite HAL exception and register manipulation test +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dsm +// Contributors: dsm, nickg +// Date: 1998-06-18 +//####DESCRIPTIONEND#### +*/ + +#include <pkgconf/system.h> + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/infra/cyg_ass.h> + +#include <cyg/infra/testcase.h> + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_clock.h> + +#include <pkgconf/infra.h> + +#include <cyg/infra/diag.h> + +// ------------------------------------------------------------------------- + +cyg_uint32 fact( cyg_uint32 arg ) +{ + cyg_uint32 ret = (arg < 2) ? 1 : (arg * fact( arg - 1 )); + return ret; +} + + +// ------------------------------------------------------------------------- + +int i, j=0, bit; +int level[8]; +#define led (*(volatile char *)(0x02000003)) +int lval = 0; + +int sequence[] = { 0, 0, 1, 1, 2, 3, 4, 5, 6, 6, 7, 7, 7, 7, 6, 6, 5, 4, 3, 2, 1, 1, 0, 0, + }; + +int nseq=(sizeof(sequence)/sizeof(sequence[0])-1); + +void set_leds( void ) // and decay them too +{ + int i, j; + for (j=0; j<50; j++) + { + for (i=0; i<256; i++) + { + lval = 0; + for (bit=0; bit<8; bit++) + if (i >= level[bit]) + lval |= 1<<bit; + led = lval; + } +#define N 1 + for (i=0; i<8; i++) + if (level[i] != 256) + { + if (level[i] > 0) + level[i] -= N; + else + level[i] = 0; + } + } +} + +void start( void ) +{ + int op = 0; + int bright = 255; + cyg_uint32 f0; + +#if 0 + while ( 1 ) { +#else + int z; + for ( z = 0; z < 100; z++ ) { +#endif + f0 = 1; + for (op=0; op<nseq; op++) { + HAL_DIAG_WRITE_CHAR( 'A' + op ); + level[sequence[op]] = bright; + set_leds(); + if ( op ) { + int f1 = fact( op ); + f0 *= op; + if ( f0 != f1 ) { + while ( 1 ) { + led = op; + CYG_TEST_FAIL_EXIT( "Factorial wrong" ); + } + } + } + } + HAL_DIAG_WRITE_CHAR( '\n' ); + HAL_DIAG_WRITE_CHAR( '\r' ); + + CYG_TEST_PASS( "Stack thrashed OK" ); + } +} + +// ------------------------------------------------------------------------- + +externC void +#ifdef CYGPKG_KERNEL +cyg_user_start( void ) +#else +cyg_start( void ) +#endif +{ + CYG_TEST_INIT(); + CYG_TEST_INFO( "cyg_user_start()" ); + HAL_ENABLE_INTERRUPTS(); + start(); + CYG_TEST_EXIT( "LED bibbling and stack thrashing test" ); +} + +// ------------------------------------------------------------------------- + +/* EOF slebstak.c */ diff --git a/ecos/packages/hal/sparclite/sleb/current/tests/slebtime.cxx b/ecos/packages/hal/sparclite/sleb/current/tests/slebtime.cxx new file mode 100644 index 0000000..b0fc41c --- /dev/null +++ b/ecos/packages/hal/sparclite/sleb/current/tests/slebtime.cxx @@ -0,0 +1,192 @@ +/*================================================================= +// +// slebtime.cxx +// +// SPARClite HAL timing tests +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): dsm +// Contributors: dsm, nickg +// Date: 1998-06-18 +//####DESCRIPTIONEND#### +*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/infra/testcase.h> + +#ifdef CYGPKG_KERNEL + +#include <pkgconf/kernel.h> + +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_clock.h> + +#include <pkgconf/infra.h> + +#include <cyg/infra/diag.h> + +#include <cyg/kernel/thread.hxx> +#include <cyg/kernel/thread.inl> +#include <cyg/kernel/sched.hxx> +#include <cyg/kernel/sched.inl> + +// ------------------------------------------------------------------------- + +static void entry1( CYG_ADDRWORD arg ) +{ + int i; + char *s = "tick 00"; + extern Cyg_Thread thread2; + CYG_TEST_INFO( "Starting measured seconds..." ); + for ( i = 0; i < 20 ; i++ ) { + Cyg_Thread::self()->delay( 100 ); // units should be centiSeconds + if ( '9' == s[ 6 ]++ ) { + s[ 6 ] = '0'; + s[ 5 ] ++; + } + CYG_TEST_INFO( s ); + } + CYG_TEST_PASS( "Done measured seconds..." ); + thread2.resume(); +} + +static void entry2( CYG_ADDRWORD arg ) +{ +#define LOOPS 30 + int i, t1, t2, a; + int loops[ LOOPS ] = { 0,0,0,0,0 , 0,0,0,0,0 , + 0,0,0,0,0 , 0,0,0,0,0 , + 0,0,0,0,0 , 0,0,0,0,0 }; + + char s[] = "0 count 00 loops 00000"; + + for ( a = 0; a < 10; a++, (*s)++ ) { + CYG_TEST_INFO( "------------------------------------------" ); + HAL_CLOCK_READ( &t1 ); + do { + t2 = t1; + HAL_CLOCK_READ( &t1 ); + } while ( t1 >= t2 ); + + for ( i = 0; i < LOOPS; i++ ) { + register int z = 0; + while ( t1 <= i ) { + z++; + HAL_CLOCK_READ( &t1 ); + } + loops[ i ] = z; + } + + s[9] = '0'; + s[8] = '0'; + for ( i = 0; i < LOOPS; i++ ) { + s[ sizeof( s ) - 2 ] = '0' + loops[ i ] / 1 % 10; + s[ sizeof( s ) - 3 ] = '0' + loops[ i ] / 10 % 10; + s[ sizeof( s ) - 4 ] = '0' + loops[ i ] / 100 % 10; + s[ sizeof( s ) - 5 ] = '0' + loops[ i ] / 1000 % 10; + s[ sizeof( s ) - 6 ] = '0' + loops[ i ] / 10000 % 10; + CYG_TEST_INFO( s ); + if ( '9' == s[9]++ ) { + s[9] = '0'; + s[8]++; + } + } + } + CYG_TEST_PASS( "Counted loops per timer tick" ); + CYG_TEST_EXIT( "All done" ); +} + +// ------------------------------------------------------------------------- + +static char stack1[ CYGNUM_HAL_STACK_SIZE_TYPICAL ]; +static char stack2[ CYGNUM_HAL_STACK_SIZE_TYPICAL ]; + +static Cyg_Thread thread1 CYG_INIT_PRIORITY( APPLICATION ) + = Cyg_Thread( 2u, entry1, 0u, "timed minute thread", + (CYG_ADDRWORD)stack1, + (CYG_ADDRWORD)CYGNUM_HAL_STACK_SIZE_TYPICAL ); + +static Cyg_Thread thread2 CYG_INIT_PRIORITY( APPLICATION ) + = Cyg_Thread( 4u, entry2, 0u, "uS clock loops timing thread", + (CYG_ADDRWORD)stack2, + (CYG_ADDRWORD)CYGNUM_HAL_STACK_SIZE_TYPICAL ); + +// ------------------------------------------------------------------------- + +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG +externC void +cyg_hal_invoke_constructors(); +#endif + +externC void +cyg_user_start( void ) +{ +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + cyg_hal_invoke_constructors(); +#endif + CYG_TEST_INIT(); + CYG_TEST_INFO( "cyg_user_start()" ); + thread1.resume(); +} + +// ------------------------------------------------------------------------- + +#else // ! CYGVAR_KERNEL_COUNTERS_CLOCK +#define N_A_MSG "no kernel clock" +#endif // CYGVAR_KERNEL_COUNTERS_CLOCK +#else // ! CYGPKG_KERNEL +#define N_A_MSG "no kernel" +#endif // CYGPKG_KERNEL + +#ifdef N_A_MSG +externC void +cyg_start( void ) +{ + CYG_TEST_INIT(); + CYG_TEST_NA( N_A_MSG ); +} +#endif // N_A_MSG defined ie. we are N/A. + +/* EOF slebtime.cxx */ |