diff options
Diffstat (limited to 'ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c')
| -rw-r--r-- | ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c index 3aac8ed..d001f27 100644 --- a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c +++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c @@ -114,8 +114,8 @@ hal_get_cpu_clock(void) //PFDout = PLLput * (18 / PFD_FRAC) freq /= pfd; freq *= 18; + break; } - break; // Fall down as the pfd_sel == 0 selects PLL2 main clock case 3: // PLL2 main clock // check if PLL2 is bypassed @@ -133,7 +133,7 @@ hal_get_cpu_clock(void) mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M; // if CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT is set, then mfi is 22 mfi = (mfi ? 22 : 20); - // calculate the PLL! frequency + // calculate the PLL2 frequency freq = (24000000 * (mfi + (mfn / mfd))); break; case 4: // PLL1 PFD o/p clock defined by CCM_CCSR[PLL1_PFD_CLK_SEL] @@ -155,7 +155,6 @@ hal_get_cpu_clock(void) freq /= pfd; freq *= 18; } - //TODO: handle the PLL1 main clk break; case 5: // PLL3 main clock HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL, mfi); @@ -219,9 +218,14 @@ hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud) void hal_update_clock_var(void) { + cyghwr_hal_vybrid_ccm_t *ccm = CYGHWR_HAL_VYBRID_CCM_P; + cyg_uint32 ipg_clk_div; + + ipg_clk_div = (ccm->cacrr & CYGHWR_HAL_VYBRID_CCM_CACRR_IPG_CLK_DIV_M); + ipg_clk_div = (ipg_clk_div >> CYGHWR_HAL_VYBRID_CCM_CACRR_IPG_CLK_DIV_S); + hal_vybrid_sysclk = hal_get_cpu_clock(); - hal_vybrid_busclk = hal_vybrid_sysclk / - 2; //TODO: place option for selecting CCM_CACRR[IPG_CLK_DIV] from CDL + hal_vybrid_busclk = hal_vybrid_sysclk / (ipg_clk_div + 1); hal_cortexm_systick_clock = hal_vybrid_sysclk; } |