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author | Stefan Agner <stefan.agner@toradex.com> | 2019-08-16 16:40:08 +0200 |
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committer | Stefan Agner <stefan.agner@toradex.com> | 2019-08-16 16:40:08 +0200 |
commit | 3758b8bd81966b63dc93093a323e9bdd734545fd (patch) | |
tree | 229bda2abe1a31d59da4b48e71aeefde934fe1d0 /arch/riscv/mm/fault.c | |
parent | d15d0b7a9f89cf5a905ad6802eb23100c8063939 (diff) | |
parent | dd209b062b86dd951cf1da93f20aa497fe99d52d (diff) |
Merge tag 'v4.19.59-rt24' into toradex_4.19.y-rttoradex_4.19.y-rt
Linux 4.19.59-rt24
Diffstat (limited to 'arch/riscv/mm/fault.c')
-rw-r--r-- | arch/riscv/mm/fault.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 88401d5125bc..523dbfbac03d 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -29,6 +29,7 @@ #include <asm/pgalloc.h> #include <asm/ptrace.h> +#include <asm/tlbflush.h> /* * This routine handles page faults. It determines the address and the @@ -281,6 +282,18 @@ vmalloc_fault: pte_k = pte_offset_kernel(pmd_k, addr); if (!pte_present(*pte_k)) goto no_context; + + /* + * The kernel assumes that TLBs don't cache invalid + * entries, but in RISC-V, SFENCE.VMA specifies an + * ordering constraint, not a cache flush; it is + * necessary even after writing invalid entries. + * Relying on flush_tlb_fix_spurious_fault would + * suffice, but the extra traps reduce + * performance. So, eagerly SFENCE.VMA. + */ + local_flush_tlb_page(addr); + return; } } |