1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "imx8mp-evk.dts"
&i2c2 {
ov5640_0: ov5640_mipi@3c {
status = "disabled";
};
ov2775_0: ov2775_mipi@36 {
compatible = "ovti,ov2775";
reg = <0x36>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
csi_id = <0>;
pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
mclk = <24000000>;
mclk_source = <0>;
status = "okay";
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
ov5640_1: ov5640_mipi@3c {
status = "disabled";
};
ov2775_1: ov2775_mipi@36 {
compatible = "ovti,ov2775";
reg = <0x36>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <24000000>;
csi_id = <1>;
pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
mclk = <24000000>;
mclk_source = <0>;
status = "disabled";
};
};
&cameradev {
status = "okay";
};
&isi_0 {
status = "disabled";
};
&isi_1 {
status = "disabled";
};
&isp_0 {
status = "okay";
};
&mipi_csi_0 {
clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "axi_root", "apb_root";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <500000000>, <500000000>, <200000000>;
};
&mipi_csi_1 {
clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "axi_root", "apb_root";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <500000000>, <500000000>, <200000000>;
};
|
