diff options
| -rw-r--r-- | arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi | 724 |
1 files changed, 365 insertions, 359 deletions
diff --git a/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi b/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi index 31429e31d1..237e92d1d5 100644 --- a/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi +++ b/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi @@ -1,11 +1,16 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0 - * This file was generated on 05/23/2022 + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.20.0+3587 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.11.0 + * This file was generated on Fri May 17 2024 10:36:27 GMT+0200 (Central European Summer Time) */ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS2_PLL_FHS_CNT 5 +#define DDRSS3_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,6 +21,7 @@ #define MULTI_DDR_CFG_HYBRID_SELECT 24 #define MULTI_DDR_CFG_EMIFS_ACTIVE 15 + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -60,11 +66,11 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_44_DATA 0x040003C5 #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_46_DATA 0x1000922C #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 #define DDRSS0_CTL_50_DATA 0x2C040500 #define DDRSS0_CTL_51_DATA 0x08292C29 @@ -77,11 +83,11 @@ #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_61_DATA 0x00000063 #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 #define DDRSS0_CTL_68_DATA 0x00CB0012 @@ -118,27 +124,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x00003380 -#define DDRSS0_CTL_103_DATA 0x00003380 -#define DDRSS0_CTL_104_DATA 0x00003380 -#define DDRSS0_CTL_105_DATA 0x00003380 -#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000005A2 -#define DDRSS0_CTL_109_DATA 0x00081CC0 -#define DDRSS0_CTL_110_DATA 0x00081CC0 -#define DDRSS0_CTL_111_DATA 0x00081CC0 -#define DDRSS0_CTL_112_DATA 0x00081CC0 -#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x0000E325 -#define DDRSS0_CTL_116_DATA 0x00081CC0 -#define DDRSS0_CTL_117_DATA 0x00081CC0 -#define DDRSS0_CTL_118_DATA 0x00081CC0 -#define DDRSS0_CTL_119_DATA 0x00081CC0 -#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_122_DATA 0x00007173 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -192,15 +198,15 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_176_DATA 0xB3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000B3B3 #define DDRSS0_CTL_178_DATA 0x35000000 #define DDRSS0_CTL_179_DATA 0x27270035 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xB3B3B300 #define DDRSS0_CTL_185_DATA 0x00000000 #define DDRSS0_CTL_186_DATA 0x00353500 #define DDRSS0_CTL_187_DATA 0x00002727 @@ -307,7 +313,7 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00000101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 @@ -405,29 +411,29 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_389_DATA 0x000000C6 #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x000004D4 -#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_394_DATA 0x00000252 +#define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_397_DATA 0x0000206A #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000C2B2 -#define DDRSS0_CTL_403_DATA 0x000288FC +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 #define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000C2B2 -#define DDRSS0_CTL_411_DATA 0x000288FC +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 #define DDRSS0_CTL_412_DATA 0x02020E15 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 @@ -488,8 +494,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +543,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 #define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_67_DATA 0x0002020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -646,19 +652,19 @@ #define DDRSS0_PI_167_DATA 0x02000200 #define DDRSS0_PI_168_DATA 0x48120C04 #define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_170_DATA 0x00000063 #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 #define DDRSS0_PI_185_DATA 0x15040000 @@ -667,7 +673,7 @@ #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -693,24 +699,24 @@ #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 #define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 +#define DDRSS0_PI_217_DATA 0x09000001 #define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_223_DATA 0x6000838E #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_227_DATA 0x6000838E #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x00019C16 -#define DDRSS0_PI_230_DATA 0x00001018 -#define DDRSS0_PI_231_DATA 0x000040E6 -#define DDRSS0_PI_232_DATA 0x000288FC -#define DDRSS0_PI_233_DATA 0x000040E6 -#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -751,29 +757,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00B30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_277_DATA 0x35B33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_279_DATA 0x35B33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00B30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_283_DATA 0x35B33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_285_DATA 0x35B33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00B30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_289_DATA 0x35B33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_291_DATA 0x35B33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00B30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_295_DATA 0x35B33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_297_DATA 0x35B33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +795,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,7 +814,7 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_31_DATA 0x00000F08 #define DDRSS0_PHY_32_DATA 0x10400000 #define DDRSS0_PHY_33_DATA 0x0C002006 #define DDRSS0_PHY_34_DATA 0x00000000 @@ -877,7 +883,7 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 #define DDRSS0_PHY_102_DATA 0x0E0D0001 #define DDRSS0_PHY_103_DATA 0x10001000 @@ -1045,7 +1051,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,7 +1070,7 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_287_DATA 0x00000F08 #define DDRSS0_PHY_288_DATA 0x10400000 #define DDRSS0_PHY_289_DATA 0x0C002006 #define DDRSS0_PHY_290_DATA 0x00000000 @@ -1133,7 +1139,7 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 #define DDRSS0_PHY_358_DATA 0x0E0D0001 #define DDRSS0_PHY_359_DATA 0x10001000 @@ -1301,7 +1307,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,7 +1326,7 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_543_DATA 0x00000F08 #define DDRSS0_PHY_544_DATA 0x10400000 #define DDRSS0_PHY_545_DATA 0x0C002006 #define DDRSS0_PHY_546_DATA 0x00000000 @@ -1389,7 +1395,7 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 #define DDRSS0_PHY_614_DATA 0x0E0D0001 #define DDRSS0_PHY_615_DATA 0x10001000 @@ -1557,7 +1563,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,7 +1582,7 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_799_DATA 0x00000F08 #define DDRSS0_PHY_800_DATA 0x10400000 #define DDRSS0_PHY_801_DATA 0x0C002006 #define DDRSS0_PHY_802_DATA 0x00000000 @@ -1645,7 +1651,7 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 #define DDRSS0_PHY_870_DATA 0x0E0D0001 #define DDRSS0_PHY_871_DATA 0x10001000 @@ -2080,7 +2086,7 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 @@ -2174,7 +2180,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2245,11 +2251,11 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_44_DATA 0x040003C5 #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_46_DATA 0x1000922C #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 #define DDRSS1_CTL_50_DATA 0x2C040500 #define DDRSS1_CTL_51_DATA 0x08292C29 @@ -2262,11 +2268,11 @@ #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_61_DATA 0x00000063 #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 #define DDRSS1_CTL_68_DATA 0x00CB0012 @@ -2303,27 +2309,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x00003380 -#define DDRSS1_CTL_103_DATA 0x00003380 -#define DDRSS1_CTL_104_DATA 0x00003380 -#define DDRSS1_CTL_105_DATA 0x00003380 -#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000005A2 -#define DDRSS1_CTL_109_DATA 0x00081CC0 -#define DDRSS1_CTL_110_DATA 0x00081CC0 -#define DDRSS1_CTL_111_DATA 0x00081CC0 -#define DDRSS1_CTL_112_DATA 0x00081CC0 -#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x0000E325 -#define DDRSS1_CTL_116_DATA 0x00081CC0 -#define DDRSS1_CTL_117_DATA 0x00081CC0 -#define DDRSS1_CTL_118_DATA 0x00081CC0 -#define DDRSS1_CTL_119_DATA 0x00081CC0 -#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_122_DATA 0x00007173 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2377,15 +2383,15 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_176_DATA 0xB3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000B3B3 #define DDRSS1_CTL_178_DATA 0x35000000 #define DDRSS1_CTL_179_DATA 0x27270035 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xB3B3B300 #define DDRSS1_CTL_185_DATA 0x00000000 #define DDRSS1_CTL_186_DATA 0x00353500 #define DDRSS1_CTL_187_DATA 0x00002727 @@ -2492,7 +2498,7 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00000101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 @@ -2590,29 +2596,29 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_389_DATA 0x000000C6 #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x000004D4 -#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_394_DATA 0x00000252 +#define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_397_DATA 0x0000206A #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000C2B2 -#define DDRSS1_CTL_403_DATA 0x000288FC +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 #define DDRSS1_CTL_404_DATA 0x00000E15 -#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000C2B2 -#define DDRSS1_CTL_411_DATA 0x000288FC +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 #define DDRSS1_CTL_412_DATA 0x02020E15 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 @@ -2673,8 +2679,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2728,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2831,19 +2837,19 @@ #define DDRSS1_PI_167_DATA 0x02000200 #define DDRSS1_PI_168_DATA 0x48120C04 #define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_170_DATA 0x00000063 #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 #define DDRSS1_PI_185_DATA 0x15040000 @@ -2852,7 +2858,7 @@ #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2878,24 +2884,24 @@ #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 #define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 +#define DDRSS1_PI_217_DATA 0x09000001 #define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_223_DATA 0x6000838E #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_227_DATA 0x6000838E #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x00019C16 -#define DDRSS1_PI_230_DATA 0x00001018 -#define DDRSS1_PI_231_DATA 0x000040E6 -#define DDRSS1_PI_232_DATA 0x000288FC -#define DDRSS1_PI_233_DATA 0x000040E6 -#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2936,29 +2942,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00B30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_277_DATA 0x35B33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_279_DATA 0x35B33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00B30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_283_DATA 0x35B33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_285_DATA 0x35B33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00B30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_289_DATA 0x35B33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_291_DATA 0x35B33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00B30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_295_DATA 0x35B33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_297_DATA 0x35B33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +2980,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,7 +2999,7 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_31_DATA 0x00000F08 #define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 @@ -3062,7 +3068,7 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 #define DDRSS1_PHY_102_DATA 0x0E0D0001 #define DDRSS1_PHY_103_DATA 0x10001000 @@ -3230,7 +3236,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,7 +3255,7 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_287_DATA 0x00000F08 #define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 @@ -3318,7 +3324,7 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 #define DDRSS1_PHY_358_DATA 0x0E0D0001 #define DDRSS1_PHY_359_DATA 0x10001000 @@ -3486,7 +3492,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,7 +3511,7 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_543_DATA 0x00000F08 #define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 @@ -3574,7 +3580,7 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 #define DDRSS1_PHY_614_DATA 0x0E0D0001 #define DDRSS1_PHY_615_DATA 0x10001000 @@ -3742,7 +3748,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,7 +3767,7 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_799_DATA 0x00000F08 #define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 @@ -3830,7 +3836,7 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 #define DDRSS1_PHY_870_DATA 0x0E0D0001 #define DDRSS1_PHY_871_DATA 0x10001000 @@ -4265,7 +4271,7 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 @@ -4359,7 +4365,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4430,11 +4436,11 @@ #define DDRSS2_CTL_41_DATA 0x1760008B #define DDRSS2_CTL_42_DATA 0x2000422B #define DDRSS2_CTL_43_DATA 0x000A0A09 -#define DDRSS2_CTL_44_DATA 0x0400078A +#define DDRSS2_CTL_44_DATA 0x040003C5 #define DDRSS2_CTL_45_DATA 0x1E161104 -#define DDRSS2_CTL_46_DATA 0x10012458 +#define DDRSS2_CTL_46_DATA 0x1000922C #define DDRSS2_CTL_47_DATA 0x1E161110 -#define DDRSS2_CTL_48_DATA 0x10012458 +#define DDRSS2_CTL_48_DATA 0x1000922C #define DDRSS2_CTL_49_DATA 0x02030410 #define DDRSS2_CTL_50_DATA 0x2C040500 #define DDRSS2_CTL_51_DATA 0x08292C29 @@ -4447,11 +4453,11 @@ #define DDRSS2_CTL_58_DATA 0x00010100 #define DDRSS2_CTL_59_DATA 0x03010000 #define DDRSS2_CTL_60_DATA 0x00001508 -#define DDRSS2_CTL_61_DATA 0x000000CE +#define DDRSS2_CTL_61_DATA 0x00000063 #define DDRSS2_CTL_62_DATA 0x0000032B -#define DDRSS2_CTL_63_DATA 0x00002073 +#define DDRSS2_CTL_63_DATA 0x00001035 #define DDRSS2_CTL_64_DATA 0x0000032B -#define DDRSS2_CTL_65_DATA 0x00002073 +#define DDRSS2_CTL_65_DATA 0x00001035 #define DDRSS2_CTL_66_DATA 0x00000005 #define DDRSS2_CTL_67_DATA 0x00050000 #define DDRSS2_CTL_68_DATA 0x00CB0012 @@ -4488,27 +4494,27 @@ #define DDRSS2_CTL_99_DATA 0x00000000 #define DDRSS2_CTL_100_DATA 0x00040005 #define DDRSS2_CTL_101_DATA 0x00000000 -#define DDRSS2_CTL_102_DATA 0x00003380 -#define DDRSS2_CTL_103_DATA 0x00003380 -#define DDRSS2_CTL_104_DATA 0x00003380 -#define DDRSS2_CTL_105_DATA 0x00003380 -#define DDRSS2_CTL_106_DATA 0x00003380 +#define DDRSS2_CTL_102_DATA 0x000018C0 +#define DDRSS2_CTL_103_DATA 0x000018C0 +#define DDRSS2_CTL_104_DATA 0x000018C0 +#define DDRSS2_CTL_105_DATA 0x000018C0 +#define DDRSS2_CTL_106_DATA 0x000018C0 #define DDRSS2_CTL_107_DATA 0x00000000 -#define DDRSS2_CTL_108_DATA 0x000005A2 -#define DDRSS2_CTL_109_DATA 0x00081CC0 -#define DDRSS2_CTL_110_DATA 0x00081CC0 -#define DDRSS2_CTL_111_DATA 0x00081CC0 -#define DDRSS2_CTL_112_DATA 0x00081CC0 -#define DDRSS2_CTL_113_DATA 0x00081CC0 +#define DDRSS2_CTL_108_DATA 0x000002B5 +#define DDRSS2_CTL_109_DATA 0x00040D40 +#define DDRSS2_CTL_110_DATA 0x00040D40 +#define DDRSS2_CTL_111_DATA 0x00040D40 +#define DDRSS2_CTL_112_DATA 0x00040D40 +#define DDRSS2_CTL_113_DATA 0x00040D40 #define DDRSS2_CTL_114_DATA 0x00000000 -#define DDRSS2_CTL_115_DATA 0x0000E325 -#define DDRSS2_CTL_116_DATA 0x00081CC0 -#define DDRSS2_CTL_117_DATA 0x00081CC0 -#define DDRSS2_CTL_118_DATA 0x00081CC0 -#define DDRSS2_CTL_119_DATA 0x00081CC0 -#define DDRSS2_CTL_120_DATA 0x00081CC0 +#define DDRSS2_CTL_115_DATA 0x00007173 +#define DDRSS2_CTL_116_DATA 0x00040D40 +#define DDRSS2_CTL_117_DATA 0x00040D40 +#define DDRSS2_CTL_118_DATA 0x00040D40 +#define DDRSS2_CTL_119_DATA 0x00040D40 +#define DDRSS2_CTL_120_DATA 0x00040D40 #define DDRSS2_CTL_121_DATA 0x00000000 -#define DDRSS2_CTL_122_DATA 0x0000E325 +#define DDRSS2_CTL_122_DATA 0x00007173 #define DDRSS2_CTL_123_DATA 0x00000000 #define DDRSS2_CTL_124_DATA 0x00000000 #define DDRSS2_CTL_125_DATA 0x00000000 @@ -4562,15 +4568,15 @@ #define DDRSS2_CTL_173_DATA 0x00000000 #define DDRSS2_CTL_174_DATA 0x00000000 #define DDRSS2_CTL_175_DATA 0x3FF40084 -#define DDRSS2_CTL_176_DATA 0x33003FF4 -#define DDRSS2_CTL_177_DATA 0x00003333 +#define DDRSS2_CTL_176_DATA 0xB3003FF4 +#define DDRSS2_CTL_177_DATA 0x0000B3B3 #define DDRSS2_CTL_178_DATA 0x35000000 #define DDRSS2_CTL_179_DATA 0x27270035 #define DDRSS2_CTL_180_DATA 0x0F0F0000 #define DDRSS2_CTL_181_DATA 0x16000000 #define DDRSS2_CTL_182_DATA 0x00841616 #define DDRSS2_CTL_183_DATA 0x3FF43FF4 -#define DDRSS2_CTL_184_DATA 0x33333300 +#define DDRSS2_CTL_184_DATA 0xB3B3B300 #define DDRSS2_CTL_185_DATA 0x00000000 #define DDRSS2_CTL_186_DATA 0x00353500 #define DDRSS2_CTL_187_DATA 0x00002727 @@ -4677,7 +4683,7 @@ #define DDRSS2_CTL_288_DATA 0x00000000 #define DDRSS2_CTL_289_DATA 0x00000000 #define DDRSS2_CTL_290_DATA 0x03030300 -#define DDRSS2_CTL_291_DATA 0x00000001 +#define DDRSS2_CTL_291_DATA 0x00000101 #define DDRSS2_CTL_292_DATA 0x00000000 #define DDRSS2_CTL_293_DATA 0x00000000 #define DDRSS2_CTL_294_DATA 0x00000000 @@ -4775,29 +4781,29 @@ #define DDRSS2_CTL_386_DATA 0x00000000 #define DDRSS2_CTL_387_DATA 0x3A3A1B00 #define DDRSS2_CTL_388_DATA 0x000A0000 -#define DDRSS2_CTL_389_DATA 0x0000019C +#define DDRSS2_CTL_389_DATA 0x000000C6 #define DDRSS2_CTL_390_DATA 0x00000200 #define DDRSS2_CTL_391_DATA 0x00000200 #define DDRSS2_CTL_392_DATA 0x00000200 #define DDRSS2_CTL_393_DATA 0x00000200 -#define DDRSS2_CTL_394_DATA 0x000004D4 -#define DDRSS2_CTL_395_DATA 0x00001018 +#define DDRSS2_CTL_394_DATA 0x00000252 +#define DDRSS2_CTL_395_DATA 0x000007BC #define DDRSS2_CTL_396_DATA 0x00000204 -#define DDRSS2_CTL_397_DATA 0x000040E6 +#define DDRSS2_CTL_397_DATA 0x0000206A #define DDRSS2_CTL_398_DATA 0x00000200 #define DDRSS2_CTL_399_DATA 0x00000200 #define DDRSS2_CTL_400_DATA 0x00000200 #define DDRSS2_CTL_401_DATA 0x00000200 -#define DDRSS2_CTL_402_DATA 0x0000C2B2 -#define DDRSS2_CTL_403_DATA 0x000288FC +#define DDRSS2_CTL_402_DATA 0x0000613E +#define DDRSS2_CTL_403_DATA 0x00014424 #define DDRSS2_CTL_404_DATA 0x00000E15 -#define DDRSS2_CTL_405_DATA 0x000040E6 +#define DDRSS2_CTL_405_DATA 0x0000206A #define DDRSS2_CTL_406_DATA 0x00000200 #define DDRSS2_CTL_407_DATA 0x00000200 #define DDRSS2_CTL_408_DATA 0x00000200 #define DDRSS2_CTL_409_DATA 0x00000200 -#define DDRSS2_CTL_410_DATA 0x0000C2B2 -#define DDRSS2_CTL_411_DATA 0x000288FC +#define DDRSS2_CTL_410_DATA 0x0000613E +#define DDRSS2_CTL_411_DATA 0x00014424 #define DDRSS2_CTL_412_DATA 0x02020E15 #define DDRSS2_CTL_413_DATA 0x03030202 #define DDRSS2_CTL_414_DATA 0x00000022 @@ -4858,8 +4864,8 @@ #define DDRSS2_PI_09_DATA 0x00000000 #define DDRSS2_PI_10_DATA 0x00000000 #define DDRSS2_PI_11_DATA 0x00000000 -#define DDRSS2_PI_12_DATA 0x00000007 -#define DDRSS2_PI_13_DATA 0x00010002 +#define DDRSS2_PI_12_DATA 0x00000003 +#define DDRSS2_PI_13_DATA 0x00010001 #define DDRSS2_PI_14_DATA 0x0800000F #define DDRSS2_PI_15_DATA 0x00000103 #define DDRSS2_PI_16_DATA 0x00000005 @@ -4907,18 +4913,18 @@ #define DDRSS2_PI_58_DATA 0x00000000 #define DDRSS2_PI_59_DATA 0x00000000 #define DDRSS2_PI_60_DATA 0x0A0A140A -#define DDRSS2_PI_61_DATA 0x10020101 +#define DDRSS2_PI_61_DATA 0x10020201 #define DDRSS2_PI_62_DATA 0x00020805 #define DDRSS2_PI_63_DATA 0x01000404 #define DDRSS2_PI_64_DATA 0x00000000 #define DDRSS2_PI_65_DATA 0x00000000 #define DDRSS2_PI_66_DATA 0x00000100 -#define DDRSS2_PI_67_DATA 0x0001010F +#define DDRSS2_PI_67_DATA 0x0002020F #define DDRSS2_PI_68_DATA 0x00340000 #define DDRSS2_PI_69_DATA 0x00000000 #define DDRSS2_PI_70_DATA 0x00000000 #define DDRSS2_PI_71_DATA 0x0000FFFF -#define DDRSS2_PI_72_DATA 0x00000000 +#define DDRSS2_PI_72_DATA 0x01000000 #define DDRSS2_PI_73_DATA 0x00080000 #define DDRSS2_PI_74_DATA 0x02000200 #define DDRSS2_PI_75_DATA 0x01000100 @@ -5016,19 +5022,19 @@ #define DDRSS2_PI_167_DATA 0x02000200 #define DDRSS2_PI_168_DATA 0x48120C04 #define DDRSS2_PI_169_DATA 0x00154812 -#define DDRSS2_PI_170_DATA 0x000000CE +#define DDRSS2_PI_170_DATA 0x00000063 #define DDRSS2_PI_171_DATA 0x0000032B -#define DDRSS2_PI_172_DATA 0x00002073 +#define DDRSS2_PI_172_DATA 0x00001035 #define DDRSS2_PI_173_DATA 0x0000032B -#define DDRSS2_PI_174_DATA 0x04002073 +#define DDRSS2_PI_174_DATA 0x04001035 #define DDRSS2_PI_175_DATA 0x01010404 -#define DDRSS2_PI_176_DATA 0x00001501 +#define DDRSS2_PI_176_DATA 0x00001500 #define DDRSS2_PI_177_DATA 0x00150015 #define DDRSS2_PI_178_DATA 0x01000100 #define DDRSS2_PI_179_DATA 0x00000100 #define DDRSS2_PI_180_DATA 0x00000000 #define DDRSS2_PI_181_DATA 0x01010101 -#define DDRSS2_PI_182_DATA 0x00000101 +#define DDRSS2_PI_182_DATA 0x00000000 #define DDRSS2_PI_183_DATA 0x00000000 #define DDRSS2_PI_184_DATA 0x00000000 #define DDRSS2_PI_185_DATA 0x15040000 @@ -5037,7 +5043,7 @@ #define DDRSS2_PI_188_DATA 0x000D0035 #define DDRSS2_PI_189_DATA 0x00218049 #define DDRSS2_PI_190_DATA 0x00218049 -#define DDRSS2_PI_191_DATA 0x01010101 +#define DDRSS2_PI_191_DATA 0x01000101 #define DDRSS2_PI_192_DATA 0x0004000E #define DDRSS2_PI_193_DATA 0x00040216 #define DDRSS2_PI_194_DATA 0x01000216 @@ -5063,24 +5069,24 @@ #define DDRSS2_PI_214_DATA 0x03013212 #define DDRSS2_PI_215_DATA 0x00003600 #define DDRSS2_PI_216_DATA 0x3212005B -#define DDRSS2_PI_217_DATA 0x09000301 +#define DDRSS2_PI_217_DATA 0x09000001 #define DDRSS2_PI_218_DATA 0x04010504 -#define DDRSS2_PI_219_DATA 0x040006C9 +#define DDRSS2_PI_219_DATA 0x04000364 #define DDRSS2_PI_220_DATA 0x0A032001 #define DDRSS2_PI_221_DATA 0x2C31110A #define DDRSS2_PI_222_DATA 0x00002918 -#define DDRSS2_PI_223_DATA 0x6001071C +#define DDRSS2_PI_223_DATA 0x6000838E #define DDRSS2_PI_224_DATA 0x1E202008 #define DDRSS2_PI_225_DATA 0x2C311116 #define DDRSS2_PI_226_DATA 0x00002918 -#define DDRSS2_PI_227_DATA 0x6001071C +#define DDRSS2_PI_227_DATA 0x6000838E #define DDRSS2_PI_228_DATA 0x1E202008 -#define DDRSS2_PI_229_DATA 0x00019C16 -#define DDRSS2_PI_230_DATA 0x00001018 -#define DDRSS2_PI_231_DATA 0x000040E6 -#define DDRSS2_PI_232_DATA 0x000288FC -#define DDRSS2_PI_233_DATA 0x000040E6 -#define DDRSS2_PI_234_DATA 0x000288FC +#define DDRSS2_PI_229_DATA 0x0000C616 +#define DDRSS2_PI_230_DATA 0x000007BC +#define DDRSS2_PI_231_DATA 0x0000206A +#define DDRSS2_PI_232_DATA 0x00014424 +#define DDRSS2_PI_233_DATA 0x0000206A +#define DDRSS2_PI_234_DATA 0x00014424 #define DDRSS2_PI_235_DATA 0x033B0016 #define DDRSS2_PI_236_DATA 0x0303033B #define DDRSS2_PI_237_DATA 0x002AF803 @@ -5121,29 +5127,29 @@ #define DDRSS2_PI_272_DATA 0x00080804 #define DDRSS2_PI_273_DATA 0x00000000 #define DDRSS2_PI_274_DATA 0x00000000 -#define DDRSS2_PI_275_DATA 0x00330084 +#define DDRSS2_PI_275_DATA 0x00B30084 #define DDRSS2_PI_276_DATA 0x00160000 -#define DDRSS2_PI_277_DATA 0x35333FF4 +#define DDRSS2_PI_277_DATA 0x35B33FF4 #define DDRSS2_PI_278_DATA 0x00160F27 -#define DDRSS2_PI_279_DATA 0x35333FF4 +#define DDRSS2_PI_279_DATA 0x35B33FF4 #define DDRSS2_PI_280_DATA 0x00160F27 -#define DDRSS2_PI_281_DATA 0x00330084 +#define DDRSS2_PI_281_DATA 0x00B30084 #define DDRSS2_PI_282_DATA 0x00160000 -#define DDRSS2_PI_283_DATA 0x35333FF4 +#define DDRSS2_PI_283_DATA 0x35B33FF4 #define DDRSS2_PI_284_DATA 0x00160F27 -#define DDRSS2_PI_285_DATA 0x35333FF4 +#define DDRSS2_PI_285_DATA 0x35B33FF4 #define DDRSS2_PI_286_DATA 0x00160F27 -#define DDRSS2_PI_287_DATA 0x00330084 +#define DDRSS2_PI_287_DATA 0x00B30084 #define DDRSS2_PI_288_DATA 0x00160000 -#define DDRSS2_PI_289_DATA 0x35333FF4 +#define DDRSS2_PI_289_DATA 0x35B33FF4 #define DDRSS2_PI_290_DATA 0x00160F27 -#define DDRSS2_PI_291_DATA 0x35333FF4 +#define DDRSS2_PI_291_DATA 0x35B33FF4 #define DDRSS2_PI_292_DATA 0x00160F27 -#define DDRSS2_PI_293_DATA 0x00330084 +#define DDRSS2_PI_293_DATA 0x00B30084 #define DDRSS2_PI_294_DATA 0x00160000 -#define DDRSS2_PI_295_DATA 0x35333FF4 +#define DDRSS2_PI_295_DATA 0x35B33FF4 #define DDRSS2_PI_296_DATA 0x00160F27 -#define DDRSS2_PI_297_DATA 0x35333FF4 +#define DDRSS2_PI_297_DATA 0x35B33FF4 #define DDRSS2_PI_298_DATA 0x00160F27 #define DDRSS2_PI_299_DATA 0x00000000 @@ -5159,7 +5165,7 @@ #define DDRSS2_PHY_09_DATA 0x00000000 #define DDRSS2_PHY_10_DATA 0x00000000 #define DDRSS2_PHY_11_DATA 0x01000001 -#define DDRSS2_PHY_12_DATA 0x00000100 +#define DDRSS2_PHY_12_DATA 0x00000200 #define DDRSS2_PHY_13_DATA 0x000800C0 #define DDRSS2_PHY_14_DATA 0x060100CC #define DDRSS2_PHY_15_DATA 0x00030066 @@ -5178,7 +5184,7 @@ #define DDRSS2_PHY_28_DATA 0x2A000000 #define DDRSS2_PHY_29_DATA 0x00000808 #define DDRSS2_PHY_30_DATA 0x0F000000 -#define DDRSS2_PHY_31_DATA 0x00000F0F +#define DDRSS2_PHY_31_DATA 0x00000F08 #define DDRSS2_PHY_32_DATA 0x10400000 #define DDRSS2_PHY_33_DATA 0x0C002006 #define DDRSS2_PHY_34_DATA 0x00000000 @@ -5247,7 +5253,7 @@ #define DDRSS2_PHY_97_DATA 0x00050010 #define DDRSS2_PHY_98_DATA 0x51517041 #define DDRSS2_PHY_99_DATA 0x31C06001 -#define DDRSS2_PHY_100_DATA 0x07AB0340 +#define DDRSS2_PHY_100_DATA 0x07AB01AB #define DDRSS2_PHY_101_DATA 0x00C0C001 #define DDRSS2_PHY_102_DATA 0x0E0D0001 #define DDRSS2_PHY_103_DATA 0x10001000 @@ -5415,7 +5421,7 @@ #define DDRSS2_PHY_265_DATA 0x00000000 #define DDRSS2_PHY_266_DATA 0x00000000 #define DDRSS2_PHY_267_DATA 0x01000001 -#define DDRSS2_PHY_268_DATA 0x00000100 +#define DDRSS2_PHY_268_DATA 0x00000200 #define DDRSS2_PHY_269_DATA 0x000800C0 #define DDRSS2_PHY_270_DATA 0x060100CC #define DDRSS2_PHY_271_DATA 0x00030066 @@ -5434,7 +5440,7 @@ #define DDRSS2_PHY_284_DATA 0x2A000000 #define DDRSS2_PHY_285_DATA 0x00000808 #define DDRSS2_PHY_286_DATA 0x0F000000 -#define DDRSS2_PHY_287_DATA 0x00000F0F +#define DDRSS2_PHY_287_DATA 0x00000F08 #define DDRSS2_PHY_288_DATA 0x10400000 #define DDRSS2_PHY_289_DATA 0x0C002006 #define DDRSS2_PHY_290_DATA 0x00000000 @@ -5503,7 +5509,7 @@ #define DDRSS2_PHY_353_DATA 0x00050010 #define DDRSS2_PHY_354_DATA 0x51517041 #define DDRSS2_PHY_355_DATA 0x31C06001 -#define DDRSS2_PHY_356_DATA 0x07AB0340 +#define DDRSS2_PHY_356_DATA 0x07AB01AB #define DDRSS2_PHY_357_DATA 0x00C0C001 #define DDRSS2_PHY_358_DATA 0x0E0D0001 #define DDRSS2_PHY_359_DATA 0x10001000 @@ -5671,7 +5677,7 @@ #define DDRSS2_PHY_521_DATA 0x00000000 #define DDRSS2_PHY_522_DATA 0x00000000 #define DDRSS2_PHY_523_DATA 0x01000001 -#define DDRSS2_PHY_524_DATA 0x00000100 +#define DDRSS2_PHY_524_DATA 0x00000200 #define DDRSS2_PHY_525_DATA 0x000800C0 #define DDRSS2_PHY_526_DATA 0x060100CC #define DDRSS2_PHY_527_DATA 0x00030066 @@ -5690,7 +5696,7 @@ #define DDRSS2_PHY_540_DATA 0x2A000000 #define DDRSS2_PHY_541_DATA 0x00000808 #define DDRSS2_PHY_542_DATA 0x0F000000 -#define DDRSS2_PHY_543_DATA 0x00000F0F +#define DDRSS2_PHY_543_DATA 0x00000F08 #define DDRSS2_PHY_544_DATA 0x10400000 #define DDRSS2_PHY_545_DATA 0x0C002006 #define DDRSS2_PHY_546_DATA 0x00000000 @@ -5759,7 +5765,7 @@ #define DDRSS2_PHY_609_DATA 0x00050010 #define DDRSS2_PHY_610_DATA 0x51517041 #define DDRSS2_PHY_611_DATA 0x31C06001 -#define DDRSS2_PHY_612_DATA 0x07AB0340 +#define DDRSS2_PHY_612_DATA 0x07AB01AB #define DDRSS2_PHY_613_DATA 0x00C0C001 #define DDRSS2_PHY_614_DATA 0x0E0D0001 #define DDRSS2_PHY_615_DATA 0x10001000 @@ -5927,7 +5933,7 @@ #define DDRSS2_PHY_777_DATA 0x00000000 #define DDRSS2_PHY_778_DATA 0x00000000 #define DDRSS2_PHY_779_DATA 0x01000001 -#define DDRSS2_PHY_780_DATA 0x00000100 +#define DDRSS2_PHY_780_DATA 0x00000200 #define DDRSS2_PHY_781_DATA 0x000800C0 #define DDRSS2_PHY_782_DATA 0x060100CC #define DDRSS2_PHY_783_DATA 0x00030066 @@ -5946,7 +5952,7 @@ #define DDRSS2_PHY_796_DATA 0x2A000000 #define DDRSS2_PHY_797_DATA 0x00000808 #define DDRSS2_PHY_798_DATA 0x0F000000 -#define DDRSS2_PHY_799_DATA 0x00000F0F +#define DDRSS2_PHY_799_DATA 0x00000F08 #define DDRSS2_PHY_800_DATA 0x10400000 #define DDRSS2_PHY_801_DATA 0x0C002006 #define DDRSS2_PHY_802_DATA 0x00000000 @@ -6015,7 +6021,7 @@ #define DDRSS2_PHY_865_DATA 0x00050010 #define DDRSS2_PHY_866_DATA 0x51517041 #define DDRSS2_PHY_867_DATA 0x31C06001 -#define DDRSS2_PHY_868_DATA 0x07AB0340 +#define DDRSS2_PHY_868_DATA 0x07AB01AB #define DDRSS2_PHY_869_DATA 0x00C0C001 #define DDRSS2_PHY_870_DATA 0x0E0D0001 #define DDRSS2_PHY_871_DATA 0x10001000 @@ -6450,7 +6456,7 @@ #define DDRSS2_PHY_1300_DATA 0x00040101 #define DDRSS2_PHY_1301_DATA 0x0000010F #define DDRSS2_PHY_1302_DATA 0x00000000 -#define DDRSS2_PHY_1303_DATA 0x0000FFFF +#define DDRSS2_PHY_1303_DATA 0x00000064 #define DDRSS2_PHY_1304_DATA 0x00000000 #define DDRSS2_PHY_1305_DATA 0x01010000 #define DDRSS2_PHY_1306_DATA 0x01080402 @@ -6544,7 +6550,7 @@ #define DDRSS2_PHY_1394_DATA 0x00000003 #define DDRSS2_PHY_1395_DATA 0x00000000 #define DDRSS2_PHY_1396_DATA 0x00001142 -#define DDRSS2_PHY_1397_DATA 0x010207AB +#define DDRSS2_PHY_1397_DATA 0x040207AB #define DDRSS2_PHY_1398_DATA 0x01000080 #define DDRSS2_PHY_1399_DATA 0x03900390 #define DDRSS2_PHY_1400_DATA 0x03900390 @@ -6606,7 +6612,7 @@ #define DDRSS3_CTL_32_DATA 0x00000000 #define DDRSS3_CTL_33_DATA 0x00000000 #define DDRSS3_CTL_34_DATA 0x040C0000 -#define DDRSS3_CTL_35_DATA 0x12481248 +#define DDRSS3_CTL_35_DATA 0x12501250 #define DDRSS3_CTL_36_DATA 0x00050804 #define DDRSS3_CTL_37_DATA 0x09040008 #define DDRSS3_CTL_38_DATA 0x15000204 @@ -6615,11 +6621,11 @@ #define DDRSS3_CTL_41_DATA 0x1760008B #define DDRSS3_CTL_42_DATA 0x2000422B #define DDRSS3_CTL_43_DATA 0x000A0A09 -#define DDRSS3_CTL_44_DATA 0x0400078A +#define DDRSS3_CTL_44_DATA 0x040003C5 #define DDRSS3_CTL_45_DATA 0x1E161104 -#define DDRSS3_CTL_46_DATA 0x10012458 +#define DDRSS3_CTL_46_DATA 0x1000922C #define DDRSS3_CTL_47_DATA 0x1E161110 -#define DDRSS3_CTL_48_DATA 0x10012458 +#define DDRSS3_CTL_48_DATA 0x1000922C #define DDRSS3_CTL_49_DATA 0x02030410 #define DDRSS3_CTL_50_DATA 0x2C040500 #define DDRSS3_CTL_51_DATA 0x08292C29 @@ -6632,11 +6638,11 @@ #define DDRSS3_CTL_58_DATA 0x00010100 #define DDRSS3_CTL_59_DATA 0x03010000 #define DDRSS3_CTL_60_DATA 0x00001508 -#define DDRSS3_CTL_61_DATA 0x000000CE +#define DDRSS3_CTL_61_DATA 0x00000063 #define DDRSS3_CTL_62_DATA 0x0000032B -#define DDRSS3_CTL_63_DATA 0x00002073 +#define DDRSS3_CTL_63_DATA 0x00001035 #define DDRSS3_CTL_64_DATA 0x0000032B -#define DDRSS3_CTL_65_DATA 0x00002073 +#define DDRSS3_CTL_65_DATA 0x00001035 #define DDRSS3_CTL_66_DATA 0x00000005 #define DDRSS3_CTL_67_DATA 0x00050000 #define DDRSS3_CTL_68_DATA 0x00CB0012 @@ -6673,27 +6679,27 @@ #define DDRSS3_CTL_99_DATA 0x00000000 #define DDRSS3_CTL_100_DATA 0x00040005 #define DDRSS3_CTL_101_DATA 0x00000000 -#define DDRSS3_CTL_102_DATA 0x00003380 -#define DDRSS3_CTL_103_DATA 0x00003380 -#define DDRSS3_CTL_104_DATA 0x00003380 -#define DDRSS3_CTL_105_DATA 0x00003380 -#define DDRSS3_CTL_106_DATA 0x00003380 +#define DDRSS3_CTL_102_DATA 0x000018C0 +#define DDRSS3_CTL_103_DATA 0x000018C0 +#define DDRSS3_CTL_104_DATA 0x000018C0 +#define DDRSS3_CTL_105_DATA 0x000018C0 +#define DDRSS3_CTL_106_DATA 0x000018C0 #define DDRSS3_CTL_107_DATA 0x00000000 -#define DDRSS3_CTL_108_DATA 0x000005A2 -#define DDRSS3_CTL_109_DATA 0x00081CC0 -#define DDRSS3_CTL_110_DATA 0x00081CC0 -#define DDRSS3_CTL_111_DATA 0x00081CC0 -#define DDRSS3_CTL_112_DATA 0x00081CC0 -#define DDRSS3_CTL_113_DATA 0x00081CC0 +#define DDRSS3_CTL_108_DATA 0x000002B5 +#define DDRSS3_CTL_109_DATA 0x00040D40 +#define DDRSS3_CTL_110_DATA 0x00040D40 +#define DDRSS3_CTL_111_DATA 0x00040D40 +#define DDRSS3_CTL_112_DATA 0x00040D40 +#define DDRSS3_CTL_113_DATA 0x00040D40 #define DDRSS3_CTL_114_DATA 0x00000000 -#define DDRSS3_CTL_115_DATA 0x0000E325 -#define DDRSS3_CTL_116_DATA 0x00081CC0 -#define DDRSS3_CTL_117_DATA 0x00081CC0 -#define DDRSS3_CTL_118_DATA 0x00081CC0 -#define DDRSS3_CTL_119_DATA 0x00081CC0 -#define DDRSS3_CTL_120_DATA 0x00081CC0 +#define DDRSS3_CTL_115_DATA 0x00007173 +#define DDRSS3_CTL_116_DATA 0x00040D40 +#define DDRSS3_CTL_117_DATA 0x00040D40 +#define DDRSS3_CTL_118_DATA 0x00040D40 +#define DDRSS3_CTL_119_DATA 0x00040D40 +#define DDRSS3_CTL_120_DATA 0x00040D40 #define DDRSS3_CTL_121_DATA 0x00000000 -#define DDRSS3_CTL_122_DATA 0x0000E325 +#define DDRSS3_CTL_122_DATA 0x00007173 #define DDRSS3_CTL_123_DATA 0x00000000 #define DDRSS3_CTL_124_DATA 0x00000000 #define DDRSS3_CTL_125_DATA 0x00000000 @@ -6747,17 +6753,17 @@ #define DDRSS3_CTL_173_DATA 0x00000000 #define DDRSS3_CTL_174_DATA 0x00000000 #define DDRSS3_CTL_175_DATA 0x3FF40084 -#define DDRSS3_CTL_176_DATA 0x33003FF4 -#define DDRSS3_CTL_177_DATA 0x00003333 -#define DDRSS3_CTL_178_DATA 0x35000000 +#define DDRSS3_CTL_176_DATA 0xF3003FF4 +#define DDRSS3_CTL_177_DATA 0x0000F3F3 +#define DDRSS3_CTL_178_DATA 0x35350000 #define DDRSS3_CTL_179_DATA 0x27270035 #define DDRSS3_CTL_180_DATA 0x0F0F0000 #define DDRSS3_CTL_181_DATA 0x16000000 #define DDRSS3_CTL_182_DATA 0x00841616 #define DDRSS3_CTL_183_DATA 0x3FF43FF4 -#define DDRSS3_CTL_184_DATA 0x33333300 +#define DDRSS3_CTL_184_DATA 0xF3F3F300 #define DDRSS3_CTL_185_DATA 0x00000000 -#define DDRSS3_CTL_186_DATA 0x00353500 +#define DDRSS3_CTL_186_DATA 0x00353535 #define DDRSS3_CTL_187_DATA 0x00002727 #define DDRSS3_CTL_188_DATA 0x00000F0F #define DDRSS3_CTL_189_DATA 0x16161600 @@ -6862,7 +6868,7 @@ #define DDRSS3_CTL_288_DATA 0x00000000 #define DDRSS3_CTL_289_DATA 0x00000000 #define DDRSS3_CTL_290_DATA 0x03030300 -#define DDRSS3_CTL_291_DATA 0x00000001 +#define DDRSS3_CTL_291_DATA 0x00010101 #define DDRSS3_CTL_292_DATA 0x00000000 #define DDRSS3_CTL_293_DATA 0x00000000 #define DDRSS3_CTL_294_DATA 0x00000000 @@ -6890,7 +6896,7 @@ #define DDRSS3_CTL_316_DATA 0x01010001 #define DDRSS3_CTL_317_DATA 0x00010101 #define DDRSS3_CTL_318_DATA 0x050A0A03 -#define DDRSS3_CTL_319_DATA 0x10081F1F +#define DDRSS3_CTL_319_DATA 0x10082323 #define DDRSS3_CTL_320_DATA 0x00090310 #define DDRSS3_CTL_321_DATA 0x0B0C030F #define DDRSS3_CTL_322_DATA 0x0B0C0306 @@ -6960,30 +6966,30 @@ #define DDRSS3_CTL_386_DATA 0x00000000 #define DDRSS3_CTL_387_DATA 0x3A3A1B00 #define DDRSS3_CTL_388_DATA 0x000A0000 -#define DDRSS3_CTL_389_DATA 0x0000019C +#define DDRSS3_CTL_389_DATA 0x000000C6 #define DDRSS3_CTL_390_DATA 0x00000200 #define DDRSS3_CTL_391_DATA 0x00000200 #define DDRSS3_CTL_392_DATA 0x00000200 #define DDRSS3_CTL_393_DATA 0x00000200 -#define DDRSS3_CTL_394_DATA 0x000004D4 -#define DDRSS3_CTL_395_DATA 0x00001018 +#define DDRSS3_CTL_394_DATA 0x00000252 +#define DDRSS3_CTL_395_DATA 0x000007BC #define DDRSS3_CTL_396_DATA 0x00000204 -#define DDRSS3_CTL_397_DATA 0x000040E6 +#define DDRSS3_CTL_397_DATA 0x0000206A #define DDRSS3_CTL_398_DATA 0x00000200 #define DDRSS3_CTL_399_DATA 0x00000200 #define DDRSS3_CTL_400_DATA 0x00000200 #define DDRSS3_CTL_401_DATA 0x00000200 -#define DDRSS3_CTL_402_DATA 0x0000C2B2 -#define DDRSS3_CTL_403_DATA 0x000288FC -#define DDRSS3_CTL_404_DATA 0x00000E15 -#define DDRSS3_CTL_405_DATA 0x000040E6 +#define DDRSS3_CTL_402_DATA 0x0000613E +#define DDRSS3_CTL_403_DATA 0x00014424 +#define DDRSS3_CTL_404_DATA 0x00000E19 +#define DDRSS3_CTL_405_DATA 0x0000206A #define DDRSS3_CTL_406_DATA 0x00000200 #define DDRSS3_CTL_407_DATA 0x00000200 #define DDRSS3_CTL_408_DATA 0x00000200 #define DDRSS3_CTL_409_DATA 0x00000200 -#define DDRSS3_CTL_410_DATA 0x0000C2B2 -#define DDRSS3_CTL_411_DATA 0x000288FC -#define DDRSS3_CTL_412_DATA 0x02020E15 +#define DDRSS3_CTL_410_DATA 0x0000613E +#define DDRSS3_CTL_411_DATA 0x00014424 +#define DDRSS3_CTL_412_DATA 0x02020E19 #define DDRSS3_CTL_413_DATA 0x03030202 #define DDRSS3_CTL_414_DATA 0x00000022 #define DDRSS3_CTL_415_DATA 0x00000000 @@ -7000,7 +7006,7 @@ #define DDRSS3_CTL_426_DATA 0x00000000 #define DDRSS3_CTL_427_DATA 0x02000000 #define DDRSS3_CTL_428_DATA 0x01000404 -#define DDRSS3_CTL_429_DATA 0x0B1E0B1E +#define DDRSS3_CTL_429_DATA 0x0B220B22 #define DDRSS3_CTL_430_DATA 0x00000105 #define DDRSS3_CTL_431_DATA 0x00010101 #define DDRSS3_CTL_432_DATA 0x00010101 @@ -7043,8 +7049,8 @@ #define DDRSS3_PI_09_DATA 0x00000000 #define DDRSS3_PI_10_DATA 0x00000000 #define DDRSS3_PI_11_DATA 0x00000000 -#define DDRSS3_PI_12_DATA 0x00000007 -#define DDRSS3_PI_13_DATA 0x00010002 +#define DDRSS3_PI_12_DATA 0x00000003 +#define DDRSS3_PI_13_DATA 0x00010001 #define DDRSS3_PI_14_DATA 0x0800000F #define DDRSS3_PI_15_DATA 0x00000103 #define DDRSS3_PI_16_DATA 0x00000005 @@ -7092,18 +7098,18 @@ #define DDRSS3_PI_58_DATA 0x00000000 #define DDRSS3_PI_59_DATA 0x00000000 #define DDRSS3_PI_60_DATA 0x0A0A140A -#define DDRSS3_PI_61_DATA 0x10020101 +#define DDRSS3_PI_61_DATA 0x10020201 #define DDRSS3_PI_62_DATA 0x00020805 #define DDRSS3_PI_63_DATA 0x01000404 #define DDRSS3_PI_64_DATA 0x00000000 #define DDRSS3_PI_65_DATA 0x00000000 #define DDRSS3_PI_66_DATA 0x00000100 -#define DDRSS3_PI_67_DATA 0x0001010F +#define DDRSS3_PI_67_DATA 0x0002020F #define DDRSS3_PI_68_DATA 0x00340000 #define DDRSS3_PI_69_DATA 0x00000000 #define DDRSS3_PI_70_DATA 0x00000000 #define DDRSS3_PI_71_DATA 0x0000FFFF -#define DDRSS3_PI_72_DATA 0x00000000 +#define DDRSS3_PI_72_DATA 0x01000000 #define DDRSS3_PI_73_DATA 0x00080000 #define DDRSS3_PI_74_DATA 0x02000200 #define DDRSS3_PI_75_DATA 0x01000100 @@ -7196,33 +7202,33 @@ #define DDRSS3_PI_162_DATA 0x00000000 #define DDRSS3_PI_163_DATA 0x2B2B0200 #define DDRSS3_PI_164_DATA 0x00000034 -#define DDRSS3_PI_165_DATA 0x00000064 -#define DDRSS3_PI_166_DATA 0x00020064 +#define DDRSS3_PI_165_DATA 0x00000068 +#define DDRSS3_PI_166_DATA 0x00020068 #define DDRSS3_PI_167_DATA 0x02000200 -#define DDRSS3_PI_168_DATA 0x48120C04 -#define DDRSS3_PI_169_DATA 0x00154812 -#define DDRSS3_PI_170_DATA 0x000000CE +#define DDRSS3_PI_168_DATA 0x50120C04 +#define DDRSS3_PI_169_DATA 0x00155012 +#define DDRSS3_PI_170_DATA 0x00000063 #define DDRSS3_PI_171_DATA 0x0000032B -#define DDRSS3_PI_172_DATA 0x00002073 +#define DDRSS3_PI_172_DATA 0x00001035 #define DDRSS3_PI_173_DATA 0x0000032B -#define DDRSS3_PI_174_DATA 0x04002073 +#define DDRSS3_PI_174_DATA 0x04001035 #define DDRSS3_PI_175_DATA 0x01010404 -#define DDRSS3_PI_176_DATA 0x00001501 +#define DDRSS3_PI_176_DATA 0x00001500 #define DDRSS3_PI_177_DATA 0x00150015 #define DDRSS3_PI_178_DATA 0x01000100 #define DDRSS3_PI_179_DATA 0x00000100 #define DDRSS3_PI_180_DATA 0x00000000 #define DDRSS3_PI_181_DATA 0x01010101 -#define DDRSS3_PI_182_DATA 0x00000101 +#define DDRSS3_PI_182_DATA 0x00000000 #define DDRSS3_PI_183_DATA 0x00000000 #define DDRSS3_PI_184_DATA 0x00000000 -#define DDRSS3_PI_185_DATA 0x15040000 -#define DDRSS3_PI_186_DATA 0x0E0E0215 +#define DDRSS3_PI_185_DATA 0x19040000 +#define DDRSS3_PI_186_DATA 0x0E0E0219 #define DDRSS3_PI_187_DATA 0x00040402 #define DDRSS3_PI_188_DATA 0x000D0035 #define DDRSS3_PI_189_DATA 0x00218049 #define DDRSS3_PI_190_DATA 0x00218049 -#define DDRSS3_PI_191_DATA 0x01010101 +#define DDRSS3_PI_191_DATA 0x01000101 #define DDRSS3_PI_192_DATA 0x0004000E #define DDRSS3_PI_193_DATA 0x00040216 #define DDRSS3_PI_194_DATA 0x01000216 @@ -7244,28 +7250,28 @@ #define DDRSS3_PI_210_DATA 0x00110216 #define DDRSS3_PI_211_DATA 0x32000056 #define DDRSS3_PI_212_DATA 0x00000301 -#define DDRSS3_PI_213_DATA 0x005B0036 +#define DDRSS3_PI_213_DATA 0x005F0036 #define DDRSS3_PI_214_DATA 0x03013212 #define DDRSS3_PI_215_DATA 0x00003600 -#define DDRSS3_PI_216_DATA 0x3212005B -#define DDRSS3_PI_217_DATA 0x09000301 +#define DDRSS3_PI_216_DATA 0x3212005F +#define DDRSS3_PI_217_DATA 0x09000001 #define DDRSS3_PI_218_DATA 0x04010504 -#define DDRSS3_PI_219_DATA 0x040006C9 +#define DDRSS3_PI_219_DATA 0x04000364 #define DDRSS3_PI_220_DATA 0x0A032001 #define DDRSS3_PI_221_DATA 0x2C31110A #define DDRSS3_PI_222_DATA 0x00002918 -#define DDRSS3_PI_223_DATA 0x6001071C +#define DDRSS3_PI_223_DATA 0x6000838E #define DDRSS3_PI_224_DATA 0x1E202008 #define DDRSS3_PI_225_DATA 0x2C311116 #define DDRSS3_PI_226_DATA 0x00002918 -#define DDRSS3_PI_227_DATA 0x6001071C +#define DDRSS3_PI_227_DATA 0x6000838E #define DDRSS3_PI_228_DATA 0x1E202008 -#define DDRSS3_PI_229_DATA 0x00019C16 -#define DDRSS3_PI_230_DATA 0x00001018 -#define DDRSS3_PI_231_DATA 0x000040E6 -#define DDRSS3_PI_232_DATA 0x000288FC -#define DDRSS3_PI_233_DATA 0x000040E6 -#define DDRSS3_PI_234_DATA 0x000288FC +#define DDRSS3_PI_229_DATA 0x0000C616 +#define DDRSS3_PI_230_DATA 0x000007BC +#define DDRSS3_PI_231_DATA 0x0000206A +#define DDRSS3_PI_232_DATA 0x00014424 +#define DDRSS3_PI_233_DATA 0x0000206A +#define DDRSS3_PI_234_DATA 0x00014424 #define DDRSS3_PI_235_DATA 0x033B0016 #define DDRSS3_PI_236_DATA 0x0303033B #define DDRSS3_PI_237_DATA 0x002AF803 @@ -7306,29 +7312,29 @@ #define DDRSS3_PI_272_DATA 0x00080804 #define DDRSS3_PI_273_DATA 0x00000000 #define DDRSS3_PI_274_DATA 0x00000000 -#define DDRSS3_PI_275_DATA 0x00330084 +#define DDRSS3_PI_275_DATA 0x35F30084 #define DDRSS3_PI_276_DATA 0x00160000 -#define DDRSS3_PI_277_DATA 0x35333FF4 +#define DDRSS3_PI_277_DATA 0x35F33FF4 #define DDRSS3_PI_278_DATA 0x00160F27 -#define DDRSS3_PI_279_DATA 0x35333FF4 +#define DDRSS3_PI_279_DATA 0x35F33FF4 #define DDRSS3_PI_280_DATA 0x00160F27 -#define DDRSS3_PI_281_DATA 0x00330084 +#define DDRSS3_PI_281_DATA 0x35F30084 #define DDRSS3_PI_282_DATA 0x00160000 -#define DDRSS3_PI_283_DATA 0x35333FF4 +#define DDRSS3_PI_283_DATA 0x35F33FF4 #define DDRSS3_PI_284_DATA 0x00160F27 -#define DDRSS3_PI_285_DATA 0x35333FF4 +#define DDRSS3_PI_285_DATA 0x35F33FF4 #define DDRSS3_PI_286_DATA 0x00160F27 -#define DDRSS3_PI_287_DATA 0x00330084 +#define DDRSS3_PI_287_DATA 0x35F30084 #define DDRSS3_PI_288_DATA 0x00160000 -#define DDRSS3_PI_289_DATA 0x35333FF4 +#define DDRSS3_PI_289_DATA 0x35F33FF4 #define DDRSS3_PI_290_DATA 0x00160F27 -#define DDRSS3_PI_291_DATA 0x35333FF4 +#define DDRSS3_PI_291_DATA 0x35F33FF4 #define DDRSS3_PI_292_DATA 0x00160F27 -#define DDRSS3_PI_293_DATA 0x00330084 +#define DDRSS3_PI_293_DATA 0x35F30084 #define DDRSS3_PI_294_DATA 0x00160000 -#define DDRSS3_PI_295_DATA 0x35333FF4 +#define DDRSS3_PI_295_DATA 0x35F33FF4 #define DDRSS3_PI_296_DATA 0x00160F27 -#define DDRSS3_PI_297_DATA 0x35333FF4 +#define DDRSS3_PI_297_DATA 0x35F33FF4 #define DDRSS3_PI_298_DATA 0x00160F27 #define DDRSS3_PI_299_DATA 0x00000000 @@ -7344,7 +7350,7 @@ #define DDRSS3_PHY_09_DATA 0x00000000 #define DDRSS3_PHY_10_DATA 0x00000000 #define DDRSS3_PHY_11_DATA 0x01000001 -#define DDRSS3_PHY_12_DATA 0x00000100 +#define DDRSS3_PHY_12_DATA 0x00000200 #define DDRSS3_PHY_13_DATA 0x000800C0 #define DDRSS3_PHY_14_DATA 0x060100CC #define DDRSS3_PHY_15_DATA 0x00030066 @@ -7363,7 +7369,7 @@ #define DDRSS3_PHY_28_DATA 0x2A000000 #define DDRSS3_PHY_29_DATA 0x00000808 #define DDRSS3_PHY_30_DATA 0x0F000000 -#define DDRSS3_PHY_31_DATA 0x00000F0F +#define DDRSS3_PHY_31_DATA 0x00000F08 #define DDRSS3_PHY_32_DATA 0x10400000 #define DDRSS3_PHY_33_DATA 0x0C002006 #define DDRSS3_PHY_34_DATA 0x00000000 @@ -7432,9 +7438,9 @@ #define DDRSS3_PHY_97_DATA 0x00050010 #define DDRSS3_PHY_98_DATA 0x51517041 #define DDRSS3_PHY_99_DATA 0x31C06001 -#define DDRSS3_PHY_100_DATA 0x07AB0340 +#define DDRSS3_PHY_100_DATA 0x07AB01AB #define DDRSS3_PHY_101_DATA 0x00C0C001 -#define DDRSS3_PHY_102_DATA 0x0E0D0001 +#define DDRSS3_PHY_102_DATA 0x0E0D0101 #define DDRSS3_PHY_103_DATA 0x10001000 #define DDRSS3_PHY_104_DATA 0x0C083E42 #define DDRSS3_PHY_105_DATA 0x0F0C3701 @@ -7600,7 +7606,7 @@ #define DDRSS3_PHY_265_DATA 0x00000000 #define DDRSS3_PHY_266_DATA 0x00000000 #define DDRSS3_PHY_267_DATA 0x01000001 -#define DDRSS3_PHY_268_DATA 0x00000100 +#define DDRSS3_PHY_268_DATA 0x00000200 #define DDRSS3_PHY_269_DATA 0x000800C0 #define DDRSS3_PHY_270_DATA 0x060100CC #define DDRSS3_PHY_271_DATA 0x00030066 @@ -7619,7 +7625,7 @@ #define DDRSS3_PHY_284_DATA 0x2A000000 #define DDRSS3_PHY_285_DATA 0x00000808 #define DDRSS3_PHY_286_DATA 0x0F000000 -#define DDRSS3_PHY_287_DATA 0x00000F0F +#define DDRSS3_PHY_287_DATA 0x00000F08 #define DDRSS3_PHY_288_DATA 0x10400000 #define DDRSS3_PHY_289_DATA 0x0C002006 #define DDRSS3_PHY_290_DATA 0x00000000 @@ -7688,9 +7694,9 @@ #define DDRSS3_PHY_353_DATA 0x00050010 #define DDRSS3_PHY_354_DATA 0x51517041 #define DDRSS3_PHY_355_DATA 0x31C06001 -#define DDRSS3_PHY_356_DATA 0x07AB0340 +#define DDRSS3_PHY_356_DATA 0x07AB01AB #define DDRSS3_PHY_357_DATA 0x00C0C001 -#define DDRSS3_PHY_358_DATA 0x0E0D0001 +#define DDRSS3_PHY_358_DATA 0x0E0D0101 #define DDRSS3_PHY_359_DATA 0x10001000 #define DDRSS3_PHY_360_DATA 0x0C083E42 #define DDRSS3_PHY_361_DATA 0x0F0C3701 @@ -7856,7 +7862,7 @@ #define DDRSS3_PHY_521_DATA 0x00000000 #define DDRSS3_PHY_522_DATA 0x00000000 #define DDRSS3_PHY_523_DATA 0x01000001 -#define DDRSS3_PHY_524_DATA 0x00000100 +#define DDRSS3_PHY_524_DATA 0x00000200 #define DDRSS3_PHY_525_DATA 0x000800C0 #define DDRSS3_PHY_526_DATA 0x060100CC #define DDRSS3_PHY_527_DATA 0x00030066 @@ -7875,7 +7881,7 @@ #define DDRSS3_PHY_540_DATA 0x2A000000 #define DDRSS3_PHY_541_DATA 0x00000808 #define DDRSS3_PHY_542_DATA 0x0F000000 -#define DDRSS3_PHY_543_DATA 0x00000F0F +#define DDRSS3_PHY_543_DATA 0x00000F08 #define DDRSS3_PHY_544_DATA 0x10400000 #define DDRSS3_PHY_545_DATA 0x0C002006 #define DDRSS3_PHY_546_DATA 0x00000000 @@ -7944,9 +7950,9 @@ #define DDRSS3_PHY_609_DATA 0x00050010 #define DDRSS3_PHY_610_DATA 0x51517041 #define DDRSS3_PHY_611_DATA 0x31C06001 -#define DDRSS3_PHY_612_DATA 0x07AB0340 +#define DDRSS3_PHY_612_DATA 0x07AB01AB #define DDRSS3_PHY_613_DATA 0x00C0C001 -#define DDRSS3_PHY_614_DATA 0x0E0D0001 +#define DDRSS3_PHY_614_DATA 0x0E0D0101 #define DDRSS3_PHY_615_DATA 0x10001000 #define DDRSS3_PHY_616_DATA 0x0C083E42 #define DDRSS3_PHY_617_DATA 0x0F0C3701 @@ -8112,7 +8118,7 @@ #define DDRSS3_PHY_777_DATA 0x00000000 #define DDRSS3_PHY_778_DATA 0x00000000 #define DDRSS3_PHY_779_DATA 0x01000001 -#define DDRSS3_PHY_780_DATA 0x00000100 +#define DDRSS3_PHY_780_DATA 0x00000200 #define DDRSS3_PHY_781_DATA 0x000800C0 #define DDRSS3_PHY_782_DATA 0x060100CC #define DDRSS3_PHY_783_DATA 0x00030066 @@ -8131,7 +8137,7 @@ #define DDRSS3_PHY_796_DATA 0x2A000000 #define DDRSS3_PHY_797_DATA 0x00000808 #define DDRSS3_PHY_798_DATA 0x0F000000 -#define DDRSS3_PHY_799_DATA 0x00000F0F +#define DDRSS3_PHY_799_DATA 0x00000F08 #define DDRSS3_PHY_800_DATA 0x10400000 #define DDRSS3_PHY_801_DATA 0x0C002006 #define DDRSS3_PHY_802_DATA 0x00000000 @@ -8200,9 +8206,9 @@ #define DDRSS3_PHY_865_DATA 0x00050010 #define DDRSS3_PHY_866_DATA 0x51517041 #define DDRSS3_PHY_867_DATA 0x31C06001 -#define DDRSS3_PHY_868_DATA 0x07AB0340 +#define DDRSS3_PHY_868_DATA 0x07AB01AB #define DDRSS3_PHY_869_DATA 0x00C0C001 -#define DDRSS3_PHY_870_DATA 0x0E0D0001 +#define DDRSS3_PHY_870_DATA 0x0E0D0101 #define DDRSS3_PHY_871_DATA 0x10001000 #define DDRSS3_PHY_872_DATA 0x0C083E42 #define DDRSS3_PHY_873_DATA 0x0F0C3701 @@ -8635,7 +8641,7 @@ #define DDRSS3_PHY_1300_DATA 0x00040101 #define DDRSS3_PHY_1301_DATA 0x0000010F #define DDRSS3_PHY_1302_DATA 0x00000000 -#define DDRSS3_PHY_1303_DATA 0x0000FFFF +#define DDRSS3_PHY_1303_DATA 0x00000064 #define DDRSS3_PHY_1304_DATA 0x00000000 #define DDRSS3_PHY_1305_DATA 0x01010000 #define DDRSS3_PHY_1306_DATA 0x01080402 @@ -8729,7 +8735,7 @@ #define DDRSS3_PHY_1394_DATA 0x00000003 #define DDRSS3_PHY_1395_DATA 0x00000000 #define DDRSS3_PHY_1396_DATA 0x00001142 -#define DDRSS3_PHY_1397_DATA 0x010207AB +#define DDRSS3_PHY_1397_DATA 0x040207AB #define DDRSS3_PHY_1398_DATA 0x01000080 #define DDRSS3_PHY_1399_DATA 0x03900390 #define DDRSS3_PHY_1400_DATA 0x03900390 |