diff options
| author | Hiago De Franco <hiago.franco@toradex.com> | 2025-05-28 10:51:15 -0300 |
|---|---|---|
| committer | Hiago De Franco <hiago.franco@toradex.com> | 2025-05-28 11:07:46 -0300 |
| commit | 2a3bfb337d1dbee90c431a7e812fd14d574b4eaf (patch) | |
| tree | 97585ea4938e5d26a8b79521c84f75d2a2fe8b4d | |
| parent | 10f005979f4d9a5067ae6204ed7d86a232871391 (diff) | |
verdin-imx8mp: panel-cap-touch-10inch-lvds: update LDB clock configuration
Since commit ff06ea04e4cf ("clk: imx: clk-imx8mp: Allow media_disp pixel
clock reconfigure parent rate") from Linux kernel, it is possible to set
the clock rates inside &lvds_bridge node, instead of overwriting the
ones from &media_blk_ctrl.
When the overlay was first added, we did not realize this, therefore
update the overlay by dropping the unneeded assigned-clock-rates
in &media_blk_ctrl.
Fixes: 39e41f0e22f2 ("verdin-imx8mp: add panel-cap-touch-10inch-lvds overlay")
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
| -rw-r--r-- | overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts b/overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts index a9def83..28b8518 100644 --- a/overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts +++ b/overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts @@ -10,6 +10,7 @@ /dts-v1/; /plugin/; +#include <dt-bindings/clock/imx8mp-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> @@ -89,6 +90,14 @@ }; &lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + /* + * This display uses 71.1 MHz pixel clock, so IMX8MP_VIDEO_PLL1 needs + * to be 7 times 71.1MHz, or 497.7 MHz as the internal divider will + * always divide the output LVDS clock by 7. + */ + assigned-clock-rates = <0>, <497700000>; status = "okay"; ports { @@ -105,22 +114,6 @@ }; }; -&media_blk_ctrl { - /* - * Currently automatic display clock configuration is not possible, - * therefore is required to set them manually. The display being used - * uses 71.1 MHz pixel clock, so IMX8MP_VIDEO_PLL1 needs to be 7 times - * 71.1MHz, or 497.7 MHz as the internal divider will always divide the - * output LVDS clock by 7. - */ - assigned-clock-rates = <500000000>, /* IMX8MP_CLK_MEDIA_AXI */ - <200000000>, /* IMX8MP_CLK_MEDIA_APB */ - <0>, /* IMX8MP_CLK_MEDIA_DISP1_PIX */ - <0>, /* IMX8MP_CLK_MEDIA_DISP2_PIX */ - <500000000>, /* IMX8MP_CLK_MEDIA_ISP */ - <497700000>; /* IMX8MP_VIDEO_PLL1 */ -}; - /* Verdin PWM_2 */ &pwm2 { status = "okay"; |