diff options
Diffstat (limited to 'overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts')
| -rw-r--r-- | overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts b/overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts new file mode 100644 index 0000000..28b8518 --- /dev/null +++ b/overlays/verdin-imx8mp_panel-cap-touch-10inch-lvds_overlay.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 Toradex + * + * Capacitive Touch Display 10.1" single-channel LVDS + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +#include "imx8mp-pinfunc.h" + +/ { + compatible = "toradex,verdin-imx8mp"; +}; + +&{/} { + backlight_lvds_native: backlight-lvds-native { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT as GPIO (SODIMM 46) */ + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + /* Verdin PWM_2 (SODIMM 16) */ + pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; + }; + + panel-lvds-native { + compatible = "panel-lvds"; + backlight = <&backlight_lvds_native>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + panel-timing { + clock-frequency = <68900000 71100000 73400000>; + de-active = <1>; + hactive = <1280 1280 1280>; + hback-porch = <23 60 71>; + hfront-porch = <23 60 71>; + hsync-active = <0>; + hsync-len = <15 40 47>; + pixelclk-active = <1>; /* positive edge */ + vactive = <800 800 800>; + vback-porch = <5 7 10>; + vfront-porch = <5 7 10>; + vsync-active = <0>; + vsync-len = <6 9 12>; + }; + + port { + panel_lvds_native_in: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + touch@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_in_gpio>, + <&pinctrl_i2s_2_sync_gpio>; + /* Verdin I2S_2_SYNC as GPIO (SODIMM 44) */ + interrupt-parent = <&gpio4>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + /* Verdin I2S_2_D_IN as GPIO (SODIMM 48) */ + reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + /* + * This display uses 71.1 MHz pixel clock, so IMX8MP_VIDEO_PLL1 needs + * to be 7 times 71.1MHz, or 497.7 MHz as the internal divider will + * always divide the output LVDS clock by 7. + */ + assigned-clock-rates = <0>, <497700000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_lvds_native_in>; + }; + }; + }; +}; + +/* Verdin PWM_2 */ +&pwm2 { + status = "okay"; +}; + +&iomuxc { + pinctrl_i2s_2_d_in_gpio: gpio4io30grp { + fsl,pins = <MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1c4>; /* SODIMM 48 */ + }; + + pinctrl_i2s_2_sync_gpio: gpio4io31grp { + fsl,pins = <MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x184>; /* SODIMM 44 */ + }; +}; |