diff options
| author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
|---|---|---|
| committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
| commit | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch) | |
| tree | f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/cortexm/arch/current/include | |
| parent | f157da5337118d3c5cd464266796de4262ac9dbd (diff) | |
Added the OS files
Diffstat (limited to 'ecos/packages/hal/cortexm/arch/current/include')
12 files changed, 2280 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/arch/current/include/basetype.h b/ecos/packages/hal/cortexm/arch/current/include/basetype.h new file mode 100644 index 0000000..6ed8532 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/basetype.h @@ -0,0 +1,71 @@ +#ifndef CYGONCE_HAL_BASETYPE_H +#define CYGONCE_HAL_BASETYPE_H +/*========================================================================== +// +// hal_intr.h +// +// Cortex-M standard types +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Description: Define architecture base types +// +//####DESCRIPTIONEND#### +// +//======================================================================== +*/ + +#define CYG_BYTEORDER CYG_LSBFIRST // Little endian +#define CYG_DOUBLE_BYTEORDER CYG_LSBFIRST + +//----------------------------------------------------------------------------- +// Cortex-M does not usually use labels with underscores. + +#define CYG_LABEL_NAME(_name_) _name_ +#define CYG_LABEL_DEFN(_name_) _name_ + +//----------------------------------------------------------------------------- +// Define the standard variable sizes + +// The ARM architecture uses the default definitions of the base +// types, so we do not need to define any here. + + +//========================================================================== +#endif // CYGONCE_HAL_BASETYPE_H +// End of basetype.h diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_core.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_core.h new file mode 100644 index 0000000..cf64721 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_core.h @@ -0,0 +1,77 @@ +#ifndef CYGONCE_CORTEXM_CORE_H +#define CYGONCE_CORTEXM_CORE_H +//========================================================================== +// +// cortexm_core.h +// +// Cortex-M some core registers +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2012-06-26 +// Description: Some Cortex-M core register definitions +// +//####DESCRIPTIONEND#### +// +//======================================================================== + + +// Coprocessor Access Control Register +#define CYGARC_REG_FPU_CPACR 0xE000ED88 + +#define CYGARC_REG_FPU_CPACR_ACCESS_DENIED 0 +#define CYGARC_REG_FPU_CPACR_ACCESS_PRIVILEGED 1 +#define CYGARC_REG_FPU_CPACR_ACCESS_RESERVED 2 +#define CYGARC_REG_FPU_CPACR_ACCESS_FULL (CYGARC_REG_FPU_CPACR_ACCESS_PRIVILEGED | \ + CYGARC_REG_FPU_CPACR_ACCESS_RESERVED) + +#define CYGARC_REG_FPU_CPACR_CP10(_access) ((_access) << 20) +#define CYGARC_REG_FPU_CPACR_CP11(_access) ((_access) << 22) + +#define CYGARC_REG_FPU_CPACR_ENABLE \ + (CYGARC_REG_FPU_CPACR_CP10(CYGARC_REG_FPU_CPACR_ACCESS_FULL) | \ + CYGARC_REG_FPU_CPACR_CP11(CYGARC_REG_FPU_CPACR_ACCESS_FULL)) + +// CONTROL register +// The CONTROL register is not memory mapped. Use CYGARC_MSR() and CYGARC_MRS(). +#define CYGARC_REG_CONTROL_PRIV_M 0x1 +#define CYGARC_REG_CONTROL_SPSEL_M 0x2 +#define CYGARC_REG_CONTROL_FPCA_M 0x4 + +//========================================================================== +#endif //CYGONCE_CORTEXM_CORE_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_endian.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_endian.h new file mode 100644 index 0000000..67b3801 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_endian.h @@ -0,0 +1,77 @@ +#ifndef CYGONCE_CORTEXM_ENDIAN_H +#define CYGONCE_CORTEXM_ENDIAN_H +//========================================================================== +// +// cortexm_endian.h +// +// Cortex-M architecture endian conversion macros/functions. +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Sergei Gavrikov +// Date: 2011-08-20 +// Description: Endian conversion macros/functions optimized for Cortex-M +// Usage: #include <cyg/hal/cortexm_endian.h> +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/cortexm_regs.h> + +//=========================================================================== +// Endian operations optimized for Cortex-M architecture. + +static __inline__ cyg_uint32 cyg_hal_swap32(cyg_uint32 original) +{ + cyg_uint32 swapped; + CYGARC_REV(swapped, original); + return swapped; +} + +static __inline__ cyg_uint16 cyg_hal_swap16(cyg_uint16 original) +{ + cyg_uint16 swapped; + CYGARC_REV16(swapped, original); + return swapped; +} + +#define CYG_SWAP32(__val) cyg_hal_swap32(__val) +#define CYG_SWAP16(__val) cyg_hal_swap16(__val) + +//========================================================================== +#endif //CYGONCE_CORTEXM_ENDIAN_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_fpu.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_fpu.h new file mode 100644 index 0000000..ccc1687 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_fpu.h @@ -0,0 +1,98 @@ +#ifndef CYGONCE_CORTEXM_FPU_H +#define CYGONCE_CORTEXM_FPU_H +//========================================================================== +// +// cortexm_fpu.h +// +// Cortex-M General Floating Point Unit definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2012-04-25 +// Description: Cortex-M4F General Floating Point Unit definitions and macros +// Usage: include <cyg/hal/cortexm_fpu.h> +// +//####DESCRIPTIONEND#### +// +//======================================================================== + + +//=========================================================================== +// Floating Point Unit +// +// FPU is optional unit of Cortex-M4 + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <cyg/hal/cortexm_core.h> + +#ifdef CYGHWR_HAL_CORTEXM_FPU + +# if defined CYGSEM_HAL_ROM_MONITOR || defined CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +# define CYGSEM_HAL_DEBUG_FPU +# endif + +# ifdef CYGINT_HAL_FPV4_SP_D16 +# include <cyg/hal/fpv4_sp_d16.h> +# else +# error "Unknown FPU unit!" +# endif + +#else // CYGHWR_HAL_CORTEXM_FPU + +# define CYGARC_CORTEXM_GDB_REG_FPA + +# define GDB_STUB_SAVEDREG_FRAME_TYPE(__type) (__type->u.type) + +# define HAL_SAVEDREG_AUTO_FRAME_SIZE (8*4) + +# define HAL_SAVEDREG_FPU_THREAD_S +# define HAL_SAVEDREG_MAN_FPU_EXCEPTION_S +# define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S +# define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT + +# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT +# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT +# define GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT +# define GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT + +#endif// CYGHWR_HAL_CORTEXM_FPU + + +//========================================================================== +#endif //CYGONCE_CORTEXM_FPU_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_regs.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_regs.h new file mode 100644 index 0000000..4bb4c86 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_regs.h @@ -0,0 +1,118 @@ +#ifndef CYGONCE_CORTEXM_REGS_H +#define CYGONCE_CORTEXM_REGS_H +//========================================================================== +// +// cortexm_regs.h +// +// Cortex-M architecture, special machine instruction wrappers +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Sergei Gavrikov +// Date: 2011-06-18 +// Description: C wrappers for some special architecture instructions. +// +//####DESCRIPTIONEND#### +// +//========================================================================= + +#ifndef __ASSEMBLER__ + +//-------------------------------------------------------------------------- +// No operation +#define CYGARC_NOP() { __asm__ volatile( "nop" ); } + + +//--------------------------------------------------------------------------- +// Change processor state instructions + +// Disable / enable interrupts +#define CYGARC_CPSID( _flags_ ) __asm__ volatile ("cpsid " #_flags_ "\n") + +// Enable interrupts and fault handlers (clear FAULTMASK) +#define CYGARC_CPSIE( _flags_ ) __asm__ volatile ("cpsie " #_flags_ "\n") + +//--------------------------------------------------------------------------- +// Byte swapping instructions + +// Reverse word +#define CYGARC_REV( _swapped_, _origin_ ) \ + __asm__ volatile ("rev %0, %1\n" : "=r"(_swapped_) : "r"(_origin_)) + +// Reverse halfwords +#define CYGARC_REV16( _swapped_, _origin_ ) \ + __asm__ volatile ("rev16 %0, %1\n" : "=r"(_swapped_) : "r"(_origin_)) + +// Reverse signed halfword +#define CYGARC_REVSH( _swapped_, _origin_ ) \ + __asm__ volatile ("revsh %0, %1\n" : "=r"(_swapped_) : "r"(_origin_)) + +//------------------------------------------------------------------------ +// Barrier instructions +// Data Synchronization Barrier +#define CYGARC_DSB() __asm__ volatile( "dsb" ) +// Instruction Synchronization Barrier +#define CYGARC_ISB() __asm__ volatile( "isb" ) + +#define HAL_MEMORY_BARRIER() \ +CYG_MACRO_START \ + CYGARC_DSB(); \ + CYGARC_ISB(); \ +CYG_MACRO_END + +//---------------------------------------------------------------------------- +// MSR instuctions +// Special register instructions +#define CYGARC_MSR(_reg_, _val_) \ + __asm__ volatile ("msr " #_reg_", %0\n" : : "r"(_val_)) + +#define CYGARC_MRS(_val_, _reg_) \ + __asm__ volatile ("mrs %0," #_reg_ "\n" : "=r"(_val_) : ) + +//---------------------------------------------------------------------------- +// VFP instuctions +// Special floating point unit register instructions +#define CYGARC_VMSR(_reg_, _val_) \ + __asm__ volatile ("vmsr " #_reg_", %0\n" : : "r"(_val_)) + +#define CYGARC_VMRS(_val_, _reg_) \ + __asm__ volatile ("vmrs %0," #_reg_ "\n" : "=r"(_val_) : ) + +#endif // __ASSEMBLER__ + +//========================================================================== +#endif // CYGONCE_CORTEXM_REGS_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/cortexm_stub.h b/ecos/packages/hal/cortexm/arch/current/include/cortexm_stub.h new file mode 100644 index 0000000..9ec3b6a --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/cortexm_stub.h @@ -0,0 +1,161 @@ +#ifndef CYGONCE_HAL_CORTEXM_STUB_H +#define CYGONCE_HAL_CORTEXM_STUB_H +/*========================================================================== +// +// cortexm_stub.h +// +// Cortex-M GDB stub support +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributor(s): ilijak +// Date: 2008-07-30 +// +//####DESCRIPTIONEND#### +// +//======================================================================== +*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGHWR_HAL_CORTEXM_FPU +#include <cyg/hal/cortexm_fpu.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif +#ifndef CYGHWR_HAL_CORTEXM_FPU +// The ARM has float (and possibly other coprocessor) registers that are +// larger than it can hold in a target_register_t. +# define TARGET_HAS_LARGE_REGISTERS + +// ARM stub has special needs for register handling (not all regs are the +// the same size), so special put_register and get_register are provided. +# define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1 + +# define NUMREGS (16+8+2) // 16 GPR, 8 FPR (unused), 2 PS + +# define REGSIZE( _x_ ) (((_x_) < F0 || (_x_) >= FPS) ? 4 : 12) + +# ifndef TARGET_REGISTER_T_DEFINED +# define TARGET_REGISTER_T_DEFINED +typedef unsigned long target_register_t; +# endif + +enum regnames { + R0, R1, R2, R3, R4, R5, R6, R7, + R8, R9, R10, FP, IP, SP, LR, PC, + F0, F1, F2, F3, F4, F5, F6, F7, + FPS, PS +}; + +#endif // CYGHWR_HAL_CORTEXM_FPU + +# define HAL_STUB_REGISTERS_SIZE \ + ((sizeof(HAL_CORTEXM_GDB_Registers) + sizeof(target_register_t) - 1) / sizeof(target_register_t)) + +# define PS_N 0x80000000 +# define PS_Z 0x40000000 +# define PS_C 0x20000000 +# define PS_V 0x10000000 + +typedef enum regnames regnames_t; + +//------------------------------------------------------------------------ + +/* Given a trap value TRAP, return the corresponding signal. */ +extern int __computeSignal (unsigned int trap_number); + +/* Return the trap number corresponding to the last-taken trap. */ +extern int __get_trap_number (void); + +/* Return the currently-saved value corresponding to register REG. */ +extern target_register_t get_register (regnames_t reg); + +/* Store VALUE in the register corresponding to WHICH. */ +extern void put_register (regnames_t which, target_register_t value); + +/* Set the currently-saved pc register value to PC. This also updates NPC + as needed. */ +extern void set_pc (target_register_t pc); + +/* Set things up so that the next user resume will execute one instruction. + This may be done by setting breakpoints or setting a single step flag + in the saved user registers, for example. */ +void __single_step (void); + +/* Clear the single-step state. */ +void __clear_single_step (void); + +/* If the breakpoint we hit is in the breakpoint() instruction, return a + non-zero value. */ +extern int __is_breakpoint_function (void); + +/* Skip the current instruction. */ +extern void __skipinst (void); + +extern void __install_breakpoints (void); + +extern void __clear_breakpoints (void); + +extern int __is_bsp_syscall(void); + +//------------------------------------------------------------------------ +// Special definition of CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +// we can only do this at all if break support is enabled: + +// If this macro is used from Thumb code, we need to pass this information +// along to the place_break function so it can do the right thing. +#define CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION( _old_ ) \ +do { \ + HAL_DISABLE_INTERRUPTS(_old_); \ + cyg_hal_gdb_place_break((target_register_t)((unsigned long)&&cyg_hal_gdb_break_place));\ +} while ( 0 ) + +#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +//========================================================================== +#endif // ifndef CYGONCE_HAL_CORTEXM_STUB_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h b/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h new file mode 100644 index 0000000..d11cf07 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16.h @@ -0,0 +1,285 @@ +#ifndef CYGONCE_FPV4_SP_D16_H +#define CYGONCE_FPV4_SP_D16_H +//========================================================================== +// +// fpv4_sp_d16.h +// +// FPv4spD16 Floating Point Unit definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2012-04-25 +// Description: FPv4spD16 Floating Point Unit definitions and macros +// Usage: include <cyg/hal/fpv4_sp_d16.h> +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL +#define CYGARC_CORTEXM_FPU_EXC_AUTOSAVE +#endif + +//=========================================================================== +// Floating-point Context Control Register +#define CYGARC_REG_FPU_FPCCR 0xE000EF34 + +#define CYGARC_REG_FPU_FPCCR_LSPACT 0x1 +#define CYGARC_REG_FPU_FPCCR_USER 0x2 +#define CYGARC_REG_FPU_FPCCR_THREAD 0x8 +#define CYGARC_REG_FPU_FPCCR_HFRDY 0x10 +#define CYGARC_REG_FPU_FPCCR_MMRDY 0x20 +#define CYGARC_REG_FPU_FPCCR_BFRDY 0x40 +#define CYGARC_REG_FPU_FPCCR_MONRDY 0x100 +#define CYGARC_REG_FPU_FPCCR_LSPEN 0x40000000 +#define CYGARC_REG_FPU_FPCCR_ASPEN 0x80000000 + +#define HAL_CORTEXM_FPU_ENABLE() \ +CYG_MACRO_START \ + cyg_uint32 regval; \ + HAL_READ_UINT32(CYGARC_REG_FPU_CPACR, regval); \ + regval |= CYGARC_REG_FPU_CPACR_ENABLE; \ + HAL_WRITE_UINT32(CYGARC_REG_FPU_CPACR, regval); \ + HAL_MEMORY_BARRIER(); \ +CYG_MACRO_END + +#define HAL_CORTEXM_FPU_DISABLE() \ +CYG_MACRO_START \ + cyg_uint32 regval; \ + HAL_READ_UINT32(CYGARC_REG_FPU_CPACR, regval); \ + regval &= ~CYGARC_REG_FPU_CPACR_ENABLE; \ + HAL_WRITE_UINT32(CYGARC_REG_FPU_CPACR, regval); \ + HAL_MEMORY_BARRIER(); \ +CYG_MACRO_END + +#ifndef __ASSEMBLER__ +__externC void hal_init_fpu(void); +#endif + +// Floating-point Context Address Register +#define CYGARC_REG_FPU_FPCAR 0xE000EF38 + +// Floating-point Default Status Control Register +#define CYGARC_REG_FPU_FPDSCR 0xE000EF3C + +#define CYGARC_REG_FPU_FPDSCR_FZ BIT_(24) +#define CYGARC_REG_FPU_FPDSCR_DN BIT_(25) +#define CYGARC_REG_FPU_FPDSCR_AHP BIT_(26) + +#define CYGARC_REG_FPU_FPDSCR_ROUND(__mode) VALUE_(22, (__mode)) +// where __mode is: +#define CYGARC_REG_FPU_FPDSCR_ROUND_RN 0 +#define CYGARC_REG_FPU_FPDSCR_ROUND_RP 1 +#define CYGARC_REG_FPU_FPDSCR_ROUND_RM 2 +#define CYGARC_REG_FPU_FPDSCR_ROUND_RZ 3 + +//========================================================================== +// FPU Context +#define HAL_SAVEDREGISTERS_WITH_FPU 0x80 + +#define HAL_SAVEDREGISTERS_THREAD_FPU (HAL_SAVEDREGISTERS_THREAD | \ + HAL_SAVEDREGISTERS_WITH_FPU) + +#define HAL_SAVEDREGISTERS_EXCEPTION_FPU (HAL_SAVEDREGISTERS_EXCEPTION | \ + HAL_SAVEDREGISTERS_WITH_FPU) + +#ifndef CYGARC_CORTEXM_FPU_EXC_AUTOSAVE + +// Without automatic contex saving during exception or interrupt +# define HAL_SAVEDREGISTERS_FPU_THREAD_CONTEXT_SIZE (HAL_SAVEDREG_THREAD_FPU_N*4+4) +# define HAL_SAVEDREG_AUTO_FRAME_SIZE (8*4) + +# define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S + +#else // !CYGARC_CORTEXM_FPU_EXC_AUTOSAVE + +// With automatic contex saving during exception or interrupt enabled +# if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL + +# define HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N 16 +# define HAL_SAVEDREG_AUTO_FRAME_SIZE (8*4 + 16*4 + 4 + 4) + +// HAL_SavedRegisters entries for floating point registers +// see hal_arch.h for HAL_SavedRegisters definition. + +# define HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S \ + cyg_uint32 s_auto[HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N]; \ + cyg_uint32 fpscr_auto; \ + cyg_uint32 aligner + +# else // defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL +# error "Automatic FPU context saving is not supported in LAZY and NONE modes." +# endif // defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL +#endif // !CYGARC_CORTEXM_FPU_EXC_AUTOSAVE + +// Common for AUTOSAVE and non AUTOSAVE +#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY + +// HAL_SavedRegisters entries for floating point registers +// see hal_arch.h for HAL_SavedRegisters definition. + +# define HAL_SAVEDREG_THREAD_FPU_N 32 +# define HAL_SAVEDREG_EXCEPTION_FPU_N 32 + +# define HAL_SAVEDREG_FPU_THREAD_S \ + cyg_uint32 fpscr; \ + cyg_uint32 s[HAL_SAVEDREG_THREAD_FPU_N] + +# define HAL_SAVEDREG_FPU_EXCEPTION_S \ + cyg_uint32 s[HAL_SAVEDREG_EXCEPTION_FPU_N]; \ + cyg_uint32 fpscr; \ + cyg_uint32 cpacr + +// Thread FP context initialization +# define HAL_THREAD_INIT_FPU_REGS(__regs_p) \ +CYG_MACRO_START \ + int __reg_i; \ + for(__reg_i = 0; __reg_i < HAL_SAVEDREG_THREAD_FPU_N; __reg_i++) \ + (__regs_p)->u.thread.s[__reg_i] = 0; \ +CYG_MACRO_END + +# define HAL_THREAD_INIT_FPU_CONTEXT(__regs_p) \ +CYG_MACRO_START \ + HAL_THREAD_INIT_FPU_REGS(__regs_p); \ + (__regs_p)->u.thread.fpscr = 0; \ +CYG_MACRO_END +#else //defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY + +# define HAL_SAVEDREG_FPU_THREAD_S +# define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT + +#endif //defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY +//========================================================================== +// hal_arch.h GDB stub support + +// Register layout expected by GDB VFP +#ifndef __ASSEMBLER__ +typedef struct { + cyg_uint32 gpr[16]; + cyg_uint32 xpsr; + cyg_uint32 s[32]; + cyg_uint32 fpscr; +} HAL_CORTEXM_GDB_Registers; +#endif + +#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY + +# define GDB_STUB_SAVEDREG_FRAME_TYPE(__regs) \ + ((__regs)->u.type & ~HAL_SAVEDREGISTERS_WITH_FPU) + +# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs) \ +CYG_MACRO_START \ + cyg_uint32 reg_i; \ + for( reg_i = 0; reg_i < HAL_SAVEDREG_THREAD_FPU_N; reg_i++ ) \ + (__gdbreg)->s[reg_i] = (__regs)->u.thread.s[reg_i]; \ + (__gdbreg)->fpscr = (__regs)->u.thread.fpscr; \ +CYG_MACRO_END + +# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs) \ +CYG_MACRO_START \ + cyg_uint32 reg_i; \ + for( reg_i = 0; reg_i < HAL_SAVEDREG_THREAD_FPU_N; reg_i++ ) \ + (__regs)->u.thread.s[reg_i] = (__gdbreg)->s[reg_i]; \ + (__regs)->u.thread.fpscr = (__gdbreg)->fpscr; \ +CYG_MACRO_END + +#else // defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY + +# define GDB_STUB_SAVEDREG_FRAME_TYPE(__regs) ((__regs)->u.type) +# define GDB_STUB_SAVEDREG_FPU_THREAD_GET(__gdbreg,__regs) CYG_EMPTY_STATEMENT +# define GDB_STUB_SAVEDREG_FPU_THREAD_SET(__gdbreg,__regs) CYG_EMPTY_STATEMENT + +#endif // defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY + +#define GDB_STUB_SAVEDREG_FPU_EXCEPTION_GET(__gdbreg,__regs) \ +CYG_MACRO_START \ + cyg_uint32 reg_i; \ + for( reg_i = 0; reg_i < HAL_SAVEDREG_EXCEPTION_FPU_N; reg_i++ ) \ + (__gdbreg)->s[reg_i] = (__regs)->u.exception.s[reg_i]; \ + (__gdbreg)->fpscr = (__regs)->u.exception.fpscr; \ +CYG_MACRO_END + +#define GDB_STUB_SAVEDREG_FPU_EXCEPTION_SET(__gdbreg,__regs) \ +CYG_MACRO_START \ + cyg_uint32 reg_i; \ + for( reg_i = 0; reg_i < HAL_SAVEDREG_EXCEPTION_FPU_N; reg_i++ ) \ + (__regs)->u.exception.s[reg_i] = (__gdbreg)->s[reg_i]; \ + (__regs)->u.exception.fpscr = (__gdbreg)->fpscr; \ + if(*(cyg_uint32 *)CYGARC_REG_FPU_FPCCR & CYGARC_REG_FPU_FPCCR_ASPEN) { \ + for( reg_i = 0; reg_i < HAL_SAVEDREG_AUTO_EXCEPTION_FPU_N; reg_i++ ) \ + (__regs)->u.exception.s_auto[reg_i] = (__regs)->u.exception.s[reg_i]; \ + (__regs)->u.exception.fpscr_auto = (__regs)->u.exception.fpscr; \ + } \ +CYG_MACRO_END + +//========================================================================== +// hal_arch.h Minimal and sensible stack sizes: +// Override value in hal_arch.h +#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * (20+32+4+4)) + +// GDB stub ================================================================== +// cortexm_stub.h definitions for FPV4-SP-D16 + +// The Cortex-M4F double registers are larger then target_register_t. +#define TARGET_HAS_LARGE_REGISTERS + +// Cortex-M4F stub register handling macros +#define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1 +#define NUMREGS (FPSCR+1) // 16 GPR, XPSR, 10 non existent, 16 VFP, FPSCR +#define REGSIZE( _x_ ) (_x_ <= PC ? 4 : \ + (_x_ < XPSR ? 0 : \ + (_x_ == XPSR ? 4 : \ + (((_x_ >= VD0) && (_x_ <= VD15)) ? 8 : \ + (_x_ == FPSCR ? 4 : 0 ))))) +#ifndef __ASSEMBLER__ +# ifndef TARGET_REGISTER_T_DEFINED +# define TARGET_REGISTER_T_DEFINED +typedef unsigned long target_register_t; +# endif + +enum regnames { + R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, SP, LR, PC, + XPSR = 25, + VD0 = 26, VD1, VD2, VD3, VD4, VD5, VD6, VD7, + VD8, VD9, VD10, VD11, VD12, VD13, VD14, VD15, + FPSCR +}; +#endif // __ASSEMBLER__ + +//========================================================================== +#endif //CYGONCE_FPV4_SP_D16_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h b/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h new file mode 100644 index 0000000..57e70b8 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/fpv4_sp_d16_libm.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_FPV4_SP_D16_LIBM_H +#define CYGONCE_FPV4_SP_D16_LIBM_H +//========================================================================== +// +// fpv4_sp_d16_libm.h +// +// FPv4spD16 Floating Point Unit mathematical functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2013-06-10 +// Description: FPv4spD16 Floating Point Unit builtin mathematical functions. +// Usage: include <cyg/hal/fpv4_sp_d16_libm.h> +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#ifdef CYGSEM_LIBM_IEEE_API_INLINE + +// Builtin mathematical functions +#define __ieee754_sqrtf(__x) __builtin_sqrtf(__x) + +#endif // CYGSEM_LIBM_IEEE_API_INLINE + +//========================================================================== +#endif //CYGONCE_FPV4_SP_D16_LIBM_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/hal_arch.h b/ecos/packages/hal/cortexm/arch/current/include/hal_arch.h new file mode 100644 index 0000000..f8e73e3 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/hal_arch.h @@ -0,0 +1,390 @@ +#ifndef CYGONCE_HAL_ARCH_H +#define CYGONCE_HAL_ARCH_H +/*========================================================================== +// +// hal_arch.h +// +// Cortex-M architecture abstractions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributor(s): ilijak +// Date: 2008-07-30 +// Description: Define architecture abstractions +// +//####DESCRIPTIONEND#### +// +//======================================================================== +*/ + +#ifndef __ASSEMBLER__ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/var_arch.h> +#include <cyg/hal/cortexm_regs.h> + +#include <cyg/hal/cortexm_fpu.h> + +#endif //__ASSEMBLER__ + +//========================================================================== +// CPU save state +// +// This is a discriminated union of different save states for threads, +// exceptions and interrupts. State is saved in the most efficient way +// for each context. This makes the GDB state get/put slightly more +// complex, but that is a suitable compromise. + +#define HAL_SAVEDREGISTERS_EXCEPTION 1 +#define HAL_SAVEDREGISTERS_THREAD 2 +#define HAL_SAVEDREGISTERS_INTERRUPT 3 + +#ifndef __ASSEMBLER__ + +typedef struct +{ + union + { + cyg_uint32 type; // State type + + // Thread + struct + { + cyg_uint32 type; // State type + cyg_uint32 basepri; // BASEPRI + cyg_uint32 sp; // SP (R13) + + HAL_SAVEDREG_FPU_THREAD_S; // Floating Point Unit context + + cyg_uint32 r[13]; // R0..R12 + cyg_uint32 pc; // PC/LR + } thread; + + // Exception + struct + { + cyg_uint32 type; // State type + cyg_uint32 vector; // Exception vector number + cyg_uint32 basepri; // BASEPRI + + cyg_uint32 r4_11[8]; // Remaining CPU registers + cyg_uint32 xlr; // Exception return LR +#ifdef CYGSEM_HAL_DEBUG_FPU + HAL_SAVEDREG_FPU_EXCEPTION_S; // Floating Point Unit context +#endif + // The following are saved and restored automatically by the CPU + // for exceptions or interrupts. + + cyg_uint32 r0; + cyg_uint32 r1; + cyg_uint32 r2; + cyg_uint32 r3; + cyg_uint32 r12; + cyg_uint32 lr; + cyg_uint32 pc; + cyg_uint32 psr; + + HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S; // Floating Point Unit context + } exception; + + // Interrupt + struct + { + cyg_uint32 type; // State type + + // The following are saved and restored automatically by the CPU + // for exceptions or interrupts. + + cyg_uint32 r0; + cyg_uint32 r1; + cyg_uint32 r2; + cyg_uint32 r3; + cyg_uint32 r12; + cyg_uint32 lr; + cyg_uint32 pc; + cyg_uint32 psr; + + HAL_SAVEDREG_AUTO_FPU_EXCEPTION_S; // Floating Point Unit context + } interrupt; + } u; + +} HAL_SavedRegisters; + +//========================================================================== +// Thread context initialization + +#ifndef HAL_THREAD_INIT_FPU_CONTEXT +#define HAL_THREAD_INIT_FPU_CONTEXT(__regs) CYG_EMPTY_STATEMENT +#endif + +#define HAL_THREAD_INIT_CONTEXT( __sparg, __thread, __entry, __id ) \ +CYG_MACRO_START \ + register CYG_WORD __sp = ((CYG_WORD)__sparg) & ~7; \ + register CYG_WORD *__ep = (CYG_WORD *)(__sp -= sizeof(CYG_WORD)); \ + register HAL_SavedRegisters *__regs; \ + int __i; \ + __sp = ((CYG_WORD)__sp) &~15; \ + __regs = (HAL_SavedRegisters *)((__sp) - sizeof(__regs->u.thread)); \ + __regs->u.type = HAL_SAVEDREGISTERS_THREAD; \ + for( __i = 1; __i < 13; __i++ ) \ + __regs->u.thread.r[__i] = 0; \ + HAL_THREAD_INIT_FPU_CONTEXT(__regs); \ + *__ep = (CYG_WORD)(__entry); \ + __regs->u.thread.sp = (CYG_WORD)(__sp); \ + __regs->u.thread.r[0] = (CYG_WORD)(__thread); \ + __regs->u.thread.r[1] = (CYG_WORD)(__id); \ + __regs->u.thread.r[11] = (CYG_WORD)(__ep); \ + __regs->u.thread.pc = (CYG_WORD)__entry; \ + __regs->u.thread.basepri = 0; \ + __sparg = (CYG_ADDRESS)__regs; \ +CYG_MACRO_END + +//========================================================================== +// Context switch macros. +// The arguments are pointers to locations where the stack pointer +// of the current thread is to be stored, and from where the SP of the +// next thread is to be fetched. + +__externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); +__externC void hal_thread_load_context( CYG_ADDRESS to ) __attribute__ ((noreturn)); + +#define HAL_THREAD_SWITCH_CONTEXT(__fspptr,__tspptr) \ + hal_thread_switch_context((CYG_ADDRESS)__tspptr, \ + (CYG_ADDRESS)__fspptr); + +#define HAL_THREAD_LOAD_CONTEXT(__tspptr) \ + hal_thread_load_context( (CYG_ADDRESS)__tspptr ); + + +//========================================================================== +// Fetch PC from saved state +#if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || \ + defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY +#define CYGARC_HAL_GET_PC_REG(__regs,__val) \ +{ \ + switch(GDB_STUB_SAVEDREG_FRAME_TYPE(__regs)) \ + { \ + case HAL_SAVEDREGISTERS_THREAD: (__val) = (__regs)->u.thread.pc; break; \ + case HAL_SAVEDREGISTERS_EXCEPTION: (__val) = (__regs)->u.exception.pc; break; \ + case HAL_SAVEDREGISTERS_INTERRUPT: (__val) = (__regs)->u.interrupt.pc; break; \ + default: (__val) = 0; \ + } \ +} +#else +#define CYGARC_HAL_GET_PC_REG(__regs,__val) \ +{ \ + switch( (__regs)->u.type ) \ + { \ + case HAL_SAVEDREGISTERS_THREAD : (__val) = (__regs)->u.thread.pc; break; \ + case HAL_SAVEDREGISTERS_EXCEPTION: (__val) = (__regs)->u.exception.pc; break; \ + case HAL_SAVEDREGISTERS_INTERRUPT: (__val) = (__regs)->u.interrupt.pc; break; \ + default: (__val) = 0; \ + } \ +} +#endif +//========================================================================== +// Exception handling function +// This function is defined by the kernel according to this prototype. It is +// invoked from the HAL to deal with any CPU exceptions that the HAL does +// not want to deal with itself. It usually invokes the kernel's exception +// delivery mechanism. + +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); + +//========================================================================== +// Bit manipulation macros + +#define HAL_LSBIT_INDEX(__index, __mask) \ +{ \ + register cyg_uint32 __bit = (__mask); \ + register int __count; \ + __bit = __bit & -__bit; \ + __asm__ volatile ("clz %0,%1" : "=r"(__count) : "r"(__bit) ); \ + (__index) = 31-__count; \ +} + +#define HAL_MSBIT_INDEX(__index, __mask) \ +{ \ + register cyg_uint32 __bit = (__mask); \ + register int __count; \ + __asm__ volatile ("clz %0,%1" : "=r"(__count) : "r"(__bit) ); \ + (__index) = 31-__count; \ +} + +//========================================================================== +// Execution reorder barrier. +// When optimizing the compiler can reorder code. In multithreaded systems +// where the order of actions is vital, this can sometimes cause problems. +// This macro may be inserted into places where reordering should not happen. + +#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) + +//========================================================================== +// Breakpoint support +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen +// if executed. +// HAL_BREAKINST is the value of the breakpoint instruction and +// HAL_BREAKINST_SIZE is its size in bytes. + +#define HAL_BREAKINST 0xbebe // BKPT + +# define HAL_BREAKINST_SIZE 2 +# define HAL_BREAKINST_TYPE cyg_uint16 + +#define _stringify1(__arg) #__arg +#define _stringify(__arg) _stringify1(__arg) + +# define HAL_BREAKPOINT(_label_) \ +__asm__ volatile (" .globl " #_label_ ";" \ + #_label_":" \ + " .short " _stringify(HAL_BREAKINST) \ + ); + +//========================================================================== +// GDB support + +#ifdef CYGARC_CORTEXM_GDB_REG_FPA +// Register layout expected by GDB FPA +typedef struct +{ + cyg_uint32 gpr[16]; + cyg_uint32 f0[3]; + cyg_uint32 f1[3]; + cyg_uint32 f2[3]; + cyg_uint32 f3[3]; + cyg_uint32 f4[3]; + cyg_uint32 f5[3]; + cyg_uint32 f6[3]; + cyg_uint32 f7[3]; + cyg_uint32 fps; + cyg_uint32 xpsr; +} HAL_CORTEXM_GDB_Registers; +#endif + +// Translate a stack pointer as saved by the thread context macros +// into a pointer to a HAL_SavedRegisters structure. On the Cortex-M +// these are equivalent. + +#define HAL_THREAD_GET_SAVED_REGISTERS(__stack, __regs) \ + CYG_MACRO_START \ + (__regs) = (HAL_SavedRegisters*)(__stack); \ + CYG_MACRO_END + + +__externC void hal_get_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs ); +__externC void hal_set_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs ); + +#define HAL_GET_GDB_REGISTERS(__regval, __regs) hal_get_gdb_registers( (HAL_CORTEXM_GDB_Registers *)(__regval), (HAL_SavedRegisters *)(__regs) ) +#define HAL_SET_GDB_REGISTERS(__regs, __regval) hal_set_gdb_registers( (HAL_CORTEXM_GDB_Registers *)(__regval), (HAL_SavedRegisters *)(__regs) ) + +//========================================================================== +// HAL setjmp + +#define CYGARC_JMP_BUF_SIZE 16 + +typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; + +__externC int hal_setjmp(hal_jmp_buf env); +__externC void hal_longjmp(hal_jmp_buf env, int val); + + +//========================================================================== +// Idle thread code. +// +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. Here we only supply a default fallback if the variant/platform +// doesn't define anything. + +#ifndef HAL_IDLE_THREAD_ACTION +#define HAL_IDLE_THREAD_ACTION(__count) __asm__ volatile ( "wfi\n" ) +#endif + +//========================================================================== +// Minimal and sensible stack sizes: the intention is that applications +// will use these to provide a stack size in the first instance prior to +// proper analysis. Idle thread stack should be this big. + +// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. +// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. +// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! + +// This is not a config option because it should not be adjusted except +// under "enough rope" sort of disclaimers. + +// A minimal, optimized stack frame - space for return link plus four +// arguments or local variables. +#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 20) + +// Stack needed for a context switch +#if !defined CYGNUM_HAL_STACK_CONTEXT_SIZE +#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 20) +#endif + +// Interrupt + call to ISR, interrupt_end() and the DSR +#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ + (CYGNUM_HAL_STACK_CONTEXT_SIZE + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) + +// Space for the maximum number of nested interrupts, plus room to call functions +#define CYGNUM_HAL_MAX_INTERRUPT_NESTING 4 + +// Minimum stack size. Space for the given number of nested +// interrupts, plus a thread context switch plus a couple of function +// calls. +#define CYGNUM_HAL_STACK_SIZE_MINIMUM \ + ((CYGNUM_HAL_MAX_INTERRUPT_NESTING+1) * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \ + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) + +// Typical stack size -- used mainly for test programs. The minimum +// stack size plus enough space for some function calls. +#define CYGNUM_HAL_STACK_SIZE_TYPICAL \ + (CYGNUM_HAL_STACK_SIZE_MINIMUM + 32 * CYGNUM_HAL_STACK_FRAME_SIZE) + +//========================================================================== +// Macros for switching context between two eCos instances (jump from +// code in ROM to code in RAM or vice versa). + +#define CYGARC_HAL_SAVE_GP() +#define CYGARC_HAL_RESTORE_GP() + +#endif // __ASSEMBLER__ + +//========================================================================== +#endif //CYGONCE_HAL_ARCH_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/hal_arch.inc b/ecos/packages/hal/cortexm/arch/current/include/hal_arch.inc new file mode 100644 index 0000000..bef2e52 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/hal_arch.inc @@ -0,0 +1,115 @@ +/*========================================================================== +// +// hal_arch.inc +// +// Cortex-M exception vector macros +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributors(s): +// Date: 2012-07-08 +// Description: This file defines some GAS macros exception VSRs. +// +//####DESCRIPTIONEND#### +// +//======================================================================== +*/ + +#ifdef CYGHWR_HAL_CORTEXM_FPU + +# ifdef CYGINT_HAL_FPV4_SP_D16 + +//============================================================================ +// LAZY context switching scheme keeps FPU disabled for the threads that +// don't use floating point. We need to enable it before we save FPU context +// in order to avoid Usage Fault exception. + + .macro hal_fpu_enable + ldr r1,=CYGARC_REG_FPU_CPACR + ldr r2,[r1] + stmdb r0!,{r2} // Save thread's CPACR state + orr r2,#CYGARC_REG_FPU_CPACR_ENABLE + str r2,[r1] + .endm + +//============================================================================ +// Restore thread's FPU usage state. +// undo hal_fpu_enable + + .macro hal_fpu_undo_enable + ldmia r0!,{r2} // Retrieve previous thread's CPACR state + ldr r1,=CYGARC_REG_FPU_CPACR + str r2,[r1] + .endm + +//============================================================================ +// Store FPU context during exception if FPU was disabled then enamble it. + + .macro hal_fpu_exc_push + hal_fpu_enable + vmrs r1,fpscr + stmdb r0!,{r1} + vstmdb.f64 r0!,{d0-d15} + .endm + +//============================================================================ +// Restore FPU context during exception and undo FPU enable. + + .macro hal_fpu_exc_pop + vldmia.f64 r0!,{d0-d15} + ldmia r0!,{r1} + vmsr fpscr,r1 + hal_fpu_undo_enable + .endm + +//============================================================================ +// Make fake fpu frame for hal_pendable_svc_vsr + + .macro hal_fpu_isr_fake_frame_push + sub r12,#4 + vmrs r1,fpscr + stmdb r12!,{r1} + vstmdb.f32 r12!,{s0-s15} + .endm + +# else // CYGINT_HAL_FPV4_SP_D16 +# error Unknown Floating Point Unit! +# endif // CYGINT_HAL_FPV4_SP_D16 + +#endif //CYGHWR_HAL_CORTEXM_FPU + +// end of hal_arch.inc diff --git a/ecos/packages/hal/cortexm/arch/current/include/hal_intr.h b/ecos/packages/hal/cortexm/arch/current/include/hal_intr.h new file mode 100644 index 0000000..21745bd --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/hal_intr.h @@ -0,0 +1,409 @@ +#ifndef CYGONCE_HAL_INTR_H +#define CYGONCE_HAL_INTR_H +/*========================================================================== +// +// hal_intr.h +// +// Cortex-M interrupt and clock abstractions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Description: Define interrupt and clock abstractions +// +//####DESCRIPTIONEND#### +// +//======================================================================== +*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_io.h> + +//========================================================================== +// Exception vectors +// +// These are the common vectors defined by all Cortex-M CPUs. The +// exact number of vectors is variant specific, so the limits will be +// defined in var_intr.h. + + +#define CYGNUM_HAL_VECTOR_STACK 0 // Reset stack pointer +#define CYGNUM_HAL_VECTOR_RESET 1 // Reset entry point +#define CYGNUM_HAL_VECTOR_NMI 2 // Non-Maskable Interrupt +#define CYGNUM_HAL_VECTOR_HARD_FAULT 3 // Hard fault +#define CYGNUM_HAL_VECTOR_MEMORY_MAN 4 // Memory management (M3) +#define CYGNUM_HAL_VECTOR_BUS_FAULT 5 // Bus Fault +#define CYGNUM_HAL_VECTOR_USAGE_FAULT 6 // Usage Fault +#define CYGNUM_HAL_VECTOR_RESERVED_07 7 +#define CYGNUM_HAL_VECTOR_RESERVED_08 8 +#define CYGNUM_HAL_VECTOR_RESERVED_09 9 +#define CYGNUM_HAL_VECTOR_RESERVED_10 10 +#define CYGNUM_HAL_VECTOR_SERVICE 11 // System service call +#define CYGNUM_HAL_VECTOR_DEBUG 12 // Debug monitor (M3) +#define CYGNUM_HAL_VECTOR_RESERVED_13 13 +#define CYGNUM_HAL_VECTOR_PENDSV 14 // Pendable svc request +#define CYGNUM_HAL_VECTOR_SYS_TICK 15 // System timer tick +#define CYGNUM_HAL_VECTOR_EXTERNAL 16 // Base of external interrupts + + +//========================================================================== +// Interrupt vectors +// +// The system tick interrupt is mapped to vector 0 and all external +// interrupts are mapped from vector 1 up. + +#define CYGNUM_HAL_INTERRUPT_SYS_TICK 0 +#define CYGNUM_HAL_INTERRUPT_EXTERNAL 1 + + +//========================================================================== +// Include variant definitions here. + +#include <cyg/hal/var_intr.h> + +// Variant or platform allowed to override these definitions to use +// a different RTC +#ifndef CYGNUM_HAL_INTERRUPT_RTC +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_SYS_TICK +#endif + +//========================================================================== +// Exception vectors. +// +// These are the values used when passed out to an external exception +// handler using cyg_hal_deliver_exception() + +#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_MEMORY_MAN +#define CYGNUM_HAL_EXCEPTION_CODE_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_MEMORY_MAN +#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_BUS_FAULT +#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_BUS_FAULT +#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION CYGNUM_HAL_VECTOR_USAGE_FAULT +#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS CYGNUM_HAL_VECTOR_USAGE_FAULT +#define CYGNUM_HAL_EXCEPTION_INTERRUPT CYGNUM_HAL_VECTOR_SERVICE + + +#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_INTERRUPT +#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \ + CYGNUM_HAL_EXCEPTION_MIN + 1) + + +//========================================================================== +// VSR handling + +__externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; + +#ifndef HAL_VSR_GET +#define HAL_VSR_GET( __vector, __pvsr ) \ + *(CYG_ADDRESS *)(__pvsr) = hal_vsr_table[__vector]; +#endif + +#ifndef HAL_VSR_SET +#define HAL_VSR_SET( __vector, __vsr, __poldvsr ) \ +CYG_MACRO_START \ + if( __poldvsr != NULL ) \ + *(CYG_ADDRESS *)__poldvsr = hal_vsr_table[__vector]; \ + hal_vsr_table[__vector] = (CYG_ADDRESS)__vsr; \ +CYG_MACRO_END +#endif + +#ifndef HAL_VSR_SET_TO_ECOS_HANDLER +__externC void hal_default_interrupt_vsr( void ); +__externC void hal_default_exception_vsr( void ); +# define HAL_VSR_SET_TO_ECOS_HANDLER( __vector, __poldvsr ) \ +CYG_MACRO_START \ + cyg_uint32 __vector2 = (cyg_uint32) (__vector); \ + CYG_ADDRESS* __poldvsr2 = (CYG_ADDRESS*)(__poldvsr); \ + if( __vector2 < CYGNUM_HAL_VECTOR_SYS_TICK ) \ + HAL_VSR_SET(__vector2, &hal_default_exception_vsr, __poldvsr2); \ + else \ + HAL_VSR_SET(__vector2, &hal_default_interrupt_vsr, __poldvsr2); \ +CYG_MACRO_END +#endif + +// Default definition of HAL_TRANSLATE_VECTOR(), a no-op +#ifndef HAL_TRANSLATE_VECTOR +# define HAL_TRANSLATE_VECTOR(__vector, __index) ((__index) = (__vector)) +#endif + +//========================================================================== +// ISR handling +// +// Interrupt handler/data/object tables plus functions and macros to +// manipulate them. + +__externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +__externC volatile CYG_ADDRWORD hal_interrupt_data [CYGNUM_HAL_ISR_COUNT]; +__externC volatile CYG_ADDRESS hal_interrupt_objects [CYGNUM_HAL_ISR_COUNT]; + +//-------------------------------------------------------------------------- +// Interrupt delivery +// +// This function is used by the HAL to deliver an interrupt, and post +// a DSR if required. It may also be used to deliver secondary +// interrupts from springboard ISRs. + +__externC void hal_deliver_interrupt( cyg_uint32 vector ); + +//-------------------------------------------------------------------------- +// Default ISR The #define is used to test whether this routine +// exists, and to allow code outside the HAL to call it. + +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); +#define HAL_DEFAULT_ISR hal_default_isr + +//-------------------------------------------------------------------------- + +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ +{ \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ +} + +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ +{ \ + if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \ + { \ + hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \ + hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \ + hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \ + } \ +} + +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ +{ \ + if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \ + { \ + hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \ + hal_interrupt_data[_vector_] = 0; \ + hal_interrupt_objects[_vector_] = 0; \ + } \ +} + +//-------------------------------------------------------------------------- +// CPU interrupt control. +// +// We use the BASEPRI register to control delivery of interrupts. The +// register is set to the second highest implemented priority for this +// Cortex-M implementation to mask interrupts. It is set to zero to +// enable interrupts, which will disable the BASEPRI mechanism. + +#ifndef __ASSEMBLER__ +typedef cyg_uint32 CYG_INTERRUPT_STATE; +#endif + +#ifndef HAL_DISABLE_INTERRUPTS +# define HAL_DISABLE_INTERRUPTS(__old) \ + __asm__ volatile ( \ + "mrs %0, basepri \n" \ + "mov r1,%1 \n" \ + "msr basepri,r1 \n" \ + : "=&r" (__old) \ + : "r" (CYGNUM_HAL_CORTEXM_PRIORITY_MAX)\ + : "r1" \ + ); +#endif + +#ifndef HAL_RESTORE_INTERRUPTS +# define HAL_RESTORE_INTERRUPTS(__old) \ + __asm__ volatile ( \ + "msr basepri, %0 \n" \ + : \ + : "r" (__old) \ + ); +#endif + +#ifndef HAL_ENABLE_INTERRUPTS +# define HAL_ENABLE_INTERRUPTS() \ + __asm__ volatile ( \ + "mov r1,#0 \n" \ + "msr basepri,r1 \n" \ + : \ + : \ + : "r1" \ + ); +#endif + +#ifndef HAL_QUERY_INTERRUPTS +#define HAL_QUERY_INTERRUPTS(__state) \ + __asm__ volatile ( \ + "mrs %0, basepri \n" \ + : "=r" (__state) \ + ); +#endif + +//-------------------------------------------------------------------------- +// Interrupt masking and unmasking +// +// This is mostly done via the architecture defined NVIC. The +// HAL_VAR_*() macros allow the variant HAL to provide extended +// support for additional interrupt sources supported by supplementary +// interrupt controllers. + +__externC void hal_interrupt_mask( cyg_uint32 vector ); +__externC void hal_interrupt_unmask( cyg_uint32 vector ); +__externC void hal_interrupt_set_level( cyg_uint32 vector, cyg_uint32 level ); +__externC void hal_interrupt_acknowledge( cyg_uint32 vector ); +__externC void hal_interrupt_configure( cyg_uint32 vector, cyg_uint32 level, cyg_uint32 up ); + + +#define HAL_INTERRUPT_MASK( __vector ) hal_interrupt_mask( __vector ) +#define HAL_INTERRUPT_UNMASK( __vector ) hal_interrupt_unmask( __vector ) +#define HAL_INTERRUPT_SET_LEVEL( __vector, __level ) hal_interrupt_set_level( __vector, __level ) +#define HAL_INTERRUPT_ACKNOWLEDGE( __vector ) hal_interrupt_acknowledge( __vector ) +#define HAL_INTERRUPT_CONFIGURE( __vector, __level, __up ) hal_interrupt_configure( __vector, __level, __up ) + +//-------------------------------------------------------------------------- +// Routine to execute DSRs using separate interrupt stack + +__externC void hal_call_dsrs_vsr(void); +#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ +{ \ + __asm__ volatile ( \ + "ldr r3,=hal_call_dsrs_vsr \n" \ + "swi 0 \n" \ + : \ + : \ + : "r3" \ + ); \ +} + +//-------------------------------------------------------------------------- + +#if 0 +// these are offered solely for stack usage testing +// if they are not defined, then there is no interrupt stack. +#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base +#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack +// use them to declare these extern however you want: +// extern char HAL_INTERRUPT_STACK_BASE[]; +// extern char HAL_INTERRUPT_STACK_TOP[]; +// is recommended +#endif + +//========================================================================== +// Clock control +// +// This uses the CPU SysTick timer. Variant or platform allowed to override +// these definitions + +#ifndef CYGHWR_HAL_CLOCK_DEFINED + +__externC cyg_uint32 hal_cortexm_systick_clock; + +// Select the clock source of the system tick timer +#ifdef CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_EXTERNAL + #define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_EXT +#elif defined(CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_INTERNAL) + #define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_INT +#endif + +#define HAL_CLOCK_INITIALIZE( __period ) \ +{ \ + cyg_uint32 __p = __period; \ + __p = hal_cortexm_systick_clock / ( 1000000 / __p ) - 1; \ + HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_RELOAD, \ + __p ); \ + HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, \ + CYGARC_REG_SYSTICK_CSR_ENABLE | \ + CYGARC_REG_SYSTICK_CSR_CLK_SRC ); \ +} + +#define HAL_CLOCK_RESET( __vector, __period ) \ +{ \ + cyg_uint32 __csr CYGBLD_ATTRIB_UNUSED; \ + HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, __csr ); \ +} + +#define HAL_CLOCK_READ( __pvalue ) \ +{ \ + cyg_uint32 __period, __value; \ + HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_RELOAD, __period ); \ + HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_VALUE, __value ); \ + __value = ( __period + 1 ) - __value; \ + __value /= (hal_cortexm_systick_clock / 1000000 ); \ + *(__pvalue) = __value; \ +} + +#define HAL_CLOCK_READ_NS( __pvalue ) \ +CYG_MACRO_START \ + cyg_uint32 __period, __value; \ + HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_RELOAD, __period ); \ + HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_VALUE, __value ); \ + __value = (( __period + 1 ) - __value) * 1000; \ + __value /= (hal_cortexm_systick_clock / 1000000 ); \ + *(__pvalue) = __value; \ +CYG_MACRO_END + +#define HAL_CLOCK_LATENCY( __pvalue ) HAL_CLOCK_READ( __pvalue ) + +#endif // CYGHWR_HAL_CLOCK_DEFINED + +//========================================================================== +// HAL_DELAY_US(). +// + +__externC void hal_delay_us( cyg_int32 us ); +#define HAL_DELAY_US( __us ) hal_delay_us( __us ) + +//========================================================================== +// Reset. +// +// This uses the SYSRESETREQ bit in the Cortex-M3 NVIC. + +#define HAL_PLATFORM_RESET() \ +{ \ + HAL_WRITE_UINT32(CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_AIRCR, \ + CYGARC_REG_NVIC_AIRCR_KEY| \ + CYGARC_REG_NVIC_AIRCR_SYSRESETREQ ); \ + for(;;); \ +} + +__externC void hal_reset_vsr( void ); +#define HAL_PLATFORM_RESET_ENTRY &hal_reset_vsr + +//========================================================================== +#endif //CYGONCE_HAL_INTR_H diff --git a/ecos/packages/hal/cortexm/arch/current/include/hal_io.h b/ecos/packages/hal/cortexm/arch/current/include/hal_io.h new file mode 100644 index 0000000..c5df099 --- /dev/null +++ b/ecos/packages/hal/cortexm/arch/current/include/hal_io.h @@ -0,0 +1,417 @@ +#ifndef CYGONCE_HAL_IO_H +#define CYGONCE_HAL_IO_H +/*========================================================================== +// +// hal_io.h +// +// Cortex-M architecture IO register definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Description: Define IO registers +// +//####DESCRIPTIONEND#### +// +//======================================================================== +*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/var_io.h> + +//========================================================================== +// Handy macros for defining register bits and fields: +// + +#define BIT_(__n) (1<<(__n)) +#define MASK_(__n,__s) (((1<<(__s))-1)<<(__n)) +#define VALUE_(__n,__v) ((__v)<<(__n)) + +//========================================================================== +// SysTick timer +// +// This is really part of the NVIC, but we break it out into a +// separate definition for convenience. + +#define CYGARC_REG_SYSTICK_BASE 0xE000E010 + +#define CYGARC_REG_SYSTICK_CSR 0 +#define CYGARC_REG_SYSTICK_RELOAD 4 +#define CYGARC_REG_SYSTICK_VALUE 8 +#define CYGARC_REG_SYSTICK_CAL 12 + +#define CYGARC_REG_SYSTICK_CSR_COUNTFLAG BIT_(16) +#define CYGARC_REG_SYSTICK_CSR_CLK_EXT VALUE_(2,0) +#define CYGARC_REG_SYSTICK_CSR_CLK_INT VALUE_(2,1) +#define CYGARC_REG_SYSTICK_CSR_TICKINT BIT_(1) +#define CYGARC_REG_SYSTICK_CSR_ENABLE BIT_(0) + +#define CYGARC_REG_SYSTICK_CAL_NOREF BIT_(31) +#define CYGARC_REG_SYSTICK_CAL_SKEW BIT_(30) +#define CYGARC_REG_SYSTICK_CAL_TENMS MASK_(0,23) + +//========================================================================== +// NVIC registers + +#define CYGARC_REG_NVIC_BASE 0xE000E000 + +#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4) +#define CYGARC_REG_NVIC_TYPE 0x004 +#endif + +#define CYGARC_REG_NVIC_SER0 0x100 +#define CYGARC_REG_NVIC_CER0 0x180 +#define CYGARC_REG_NVIC_SPR0 0x200 +#define CYGARC_REG_NVIC_CPR0 0x280 +#define CYGARC_REG_NVIC_ABR0 0x300 +#define CYGARC_REG_NVIC_PR0 0x400 + +// Generate address of 32 bit control register for interrupt +#define CYGARC_REG_NVIC_SER(__intr) (CYGARC_REG_NVIC_SER0+4*((__intr)>>5)) +#define CYGARC_REG_NVIC_CER(__intr) (CYGARC_REG_NVIC_CER0+4*((__intr)>>5)) +#define CYGARC_REG_NVIC_SPR(__intr) (CYGARC_REG_NVIC_SPR0+4*((__intr)>>5)) +#define CYGARC_REG_NVIC_CPR(__intr) (CYGARC_REG_NVIC_CPR0+4*((__intr)>>5)) +#define CYGARC_REG_NVIC_ABR(__intr) (CYGARC_REG_NVIC_ABR0+4*((__intr)>>5)) + +// Generate bit in register for interrupt +#define CYGARC_REG_NVIC_IBIT(__intr) BIT_((__intr)&0x1F) + +// Generate byte address of interrupt's priority register. +#define CYGARC_REG_NVIC_PR(__intr) (CYGARC_REG_NVIC_PR0+(__intr)) + + +#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4) + +#define CYGARC_REG_NVIC_CPUID 0xD00 +#define CYGARC_REG_NVIC_ICSR 0xD04 +#define CYGARC_REG_NVIC_VTOR 0xD08 +#define CYGARC_REG_NVIC_AIRCR 0xD0C +#define CYGARC_REG_NVIC_SCR 0xD10 +#define CYGARC_REG_NVIC_CCR 0xD14 +#define CYGARC_REG_NVIC_SHPR0 0xD18 +#define CYGARC_REG_NVIC_SHPR1 0xD1C +#define CYGARC_REG_NVIC_SHPR2 0xD20 +#define CYGARC_REG_NVIC_SHCSR 0xD24 +#define CYGARC_REG_NVIC_CFSR 0xD28 +#define CYGARC_REG_NVIC_HFSR 0xD2C +#define CYGARC_REG_NVIC_DFSR 0xD30 +#define CYGARC_REG_NVIC_MMAR 0xD34 +#define CYGARC_REG_NVIC_BFAR 0xD38 +#define CYGARC_REG_NVIC_AFSR 0xD3C +#define CYGARC_REG_NVIC_PFR0 0xD40 +#define CYGARC_REG_NVIC_PFR1 0xD44 +#define CYGARC_REG_NVIC_DFR0 0xD48 +#define CYGARC_REG_NVIC_AFR0 0xD4C +#define CYGARC_REG_NVIC_MMFR0 0xD50 +#define CYGARC_REG_NVIC_MMFR1 0xD54 +#define CYGARC_REG_NVIC_MMFR2 0xD58 +#define CYGARC_REG_NVIC_MMFR3 0xD5C +#define CYGARC_REG_NVIC_ISAR0 0xD60 +#define CYGARC_REG_NVIC_ISAR1 0xD64 +#define CYGARC_REG_NVIC_ISAR2 0xD68 +#define CYGARC_REG_NVIC_ISAR3 0xD6C +#define CYGARC_REG_NVIC_ISAR4 0xD70 +#define CYGARC_REG_NVIC_STIR 0xF00 +#define CYGARC_REG_NVIC_PID4 0xFD0 +#define CYGARC_REG_NVIC_PID5 0xFD4 +#define CYGARC_REG_NVIC_PID6 0xFD8 +#define CYGARC_REG_NVIC_PID7 0xFDC +#define CYGARC_REG_NVIC_PID0 0xFE0 +#define CYGARC_REG_NVIC_PID1 0xFE4 +#define CYGARC_REG_NVIC_PID2 0xFE8 +#define CYGARC_REG_NVIC_PID3 0xFEC +#define CYGARC_REG_NVIC_CID0 0xFF0 +#define CYGARC_REG_NVIC_CID1 0xFF4 +#define CYGARC_REG_NVIC_CID2 0xFF8 +#define CYGARC_REG_NVIC_CID3 0xFFC + +// ICSR + +#define CYGARC_REG_NVIC_ICSR_NMIPENDSET BIT_(31) +#define CYGARC_REG_NVIC_ICSR_PENDSVSET BIT_(28) +#define CYGARC_REG_NVIC_ICSR_PENDSVCLR BIT_(27) +#define CYGARC_REG_NVIC_ICSR_PENDSTSET BIT_(26) +#define CYGARC_REG_NVIC_ICSR_PENDSTCLR BIT_(25) +#define CYGARC_REG_NVIC_ICSR_ISRPREEMPT BIT_(23) +#define CYGARC_REG_NVIC_ICSR_ISRPENDING BIT_(22) +#define CYGARC_REG_NVIC_ICSR_VECTPENDING MASK_(12,9) +#define CYGARC_REG_NVIC_ICSR_RETTOBASE BIT_(11) +#define CYGARC_REG_NVIC_ICSR_VECTACTIVE MASK_(0,9) + +// VTOR + +#define CYGARC_REG_NVIC_VTOR_TBLOFF(__o) VALUE_(7,__o) +#define CYGARC_REG_NVIC_VTOR_TBLBASE_CODE 0 +#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM +#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM BIT_(29) +#endif + +// AI/RCR + +#define CYGARC_REG_NVIC_AIRCR_KEY VALUE_(16,0x5FA) +#define CYGARC_REG_NVIC_AIRCR_BIGENDIAN BIT_(15) +#define CYGARC_REG_NVIC_AIRCR_PRIGROUP(__p) VALUE_(8,__p) +#define CYGARC_REG_NVIC_AIRCR_SYSRESETREQ BIT_(2) +#define CYGARC_REG_NVIC_AIRCR_VECTCLRACTIVE BIT_(1) +#define CYGARC_REG_NVIC_AIRCR_VECTRESET BIT_(0) + +// SCR + +#define CYGARC_REG_NVIC_SCR_SLEEPONEXIT BIT_(1) +#define CYGARC_REG_NVIC_SCR_DEEPSLEEP BIT_(2) +#define CYGARC_REG_NVIC_SCR_SEVONPEND BIT_(4) + +// SHCSR + +#define CYGARC_REG_NVIC_SHCSR_USGFAULTENA BIT_(18) +#define CYGARC_REG_NVIC_SHCSR_BUSFAULTENA BIT_(17) +#define CYGARC_REG_NVIC_SHCSR_MEMFAULTENA BIT_(16) +#define CYGARC_REG_NVIC_SHCSR_SVCALLPENDED BIT_(15) +#define CYGARC_REG_NVIC_SHCSR_BUSFAULTPENDED BIT_(14) +#define CYGARC_REG_NVIC_SHCSR_MEMFAULTPENDED BIT_(13) +#define CYGARC_REG_NVIC_SHCSR_USGFAULTPENDED BIT_(12) +#define CYGARC_REG_NVIC_SHCSR_SYSTICKACT BIT_(11) +#define CYGARC_REG_NVIC_SHCSR_PENDSVACT BIT_(10) +#define CYGARC_REG_NVIC_SHCSR_MONITORACT BIT_(8) +#define CYGARC_REG_NVIC_SHCSR_SVCALLACT BIT_(7) +#define CYGARC_REG_NVIC_SHCSR_USGFAULTACT BIT_(3) +#define CYGARC_REG_NVIC_SHCSR_BUSFAULTACT BIT_(1) +#define CYGARC_REG_NVIC_SHCSR_MEMFAULTACT BIT_(0) + +// Usage Fault register + +#define CYGARC_REG_UFSR 0xE000ED2A +#define CYGARC_REG_UFSR_DIVBYZERO BIT_(9) +#define CYGARC_REG_UFSR_UNALIGNED BIT_(8) +#define CYGARC_REG_UFSR_NOCP BIT_(3) +#define CYGARC_REG_UFSR_INVPC BIT_(2) +#define CYGARC_REG_UFSR_INVSTATE BIT_(1) +#define CYGARC_REG_UFSR_UNDEFINSTR BIT_(0) + +#endif + +//========================================================================== +// Debug registers + +#if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4) + +#define CYGARC_REG_DEBUG_BASE 0xE000EDF0 + +#define CYGARC_REG_DEBUG_DHSR 0x00 +#define CYGARC_REG_DEBUG_DCRSR 0x04 +#define CYGARC_REG_DEBUG_DCRDR 0x08 +#define CYGARC_REG_DEBUG_DEMCR 0x0C + + +#define CYGARC_REG_DEBUG_DHSR_DBGKEY VALUE_(16,0xA05F) +#define CYGARC_REG_DEBUG_DHSR_S_RESET BIT_(25) +#define CYGARC_REG_DEBUG_DHSR_S_RETIRE BIT_(24) +#define CYGARC_REG_DEBUG_DHSR_S_LOCKUP BIT_(19) +#define CYGARC_REG_DEBUG_DHSR_S_SLEEP BIT_(18) +#define CYGARC_REG_DEBUG_DHSR_S_HALT BIT_(17) +#define CYGARC_REG_DEBUG_DHSR_S_REGRDY BIT_(16) +#define CYGARC_REG_DEBUG_DHSR_C_SNAPSTALL BIT_(5) +#define CYGARC_REG_DEBUG_DHSR_C_MASKINTS BIT_(3) +#define CYGARC_REG_DEBUG_DHSR_C_STEP BIT_(2) +#define CYGARC_REG_DEBUG_DHSR_C_HALT BIT_(1) +#define CYGARC_REG_DEBUG_DHSR_C_DEBUGEN BIT_(0) + + +#define CYGARC_REG_DEBUG_DCRSR_REG_WRITE BIT_(16) +#define CYGARC_REG_DEBUG_DCRSR_REG_READ 0 +#define CYGARC_REG_DEBUG_DCRSR_REG(__x) VALUE_(0,__x) + + +#define CYGARC_REG_DEBUG_DEMCR_TRCENA BIT_(24) +#define CYGARC_REG_DEBUG_DEMCR_MON_REQ BIT_(19) +#define CYGARC_REG_DEBUG_DEMCR_MON_STEP BIT_(18) +#define CYGARC_REG_DEBUG_DEMCR_MON_PEND BIT_(17) +#define CYGARC_REG_DEBUG_DEMCR_MON_EN BIT_(16) +#define CYGARC_REG_DEBUG_DEMCR_VC_HARDERR BIT_(10) +#define CYGARC_REG_DEBUG_DEMCR_VC_INTERR BIT_(9) +#define CYGARC_REG_DEBUG_DEMCR_VC_BUSERR BIT_(8) +#define CYGARC_REG_DEBUG_DEMCR_VC_STATERR BIT_(7) +#define CYGARC_REG_DEBUG_DEMCR_VC_CHKERR BIT_(6) +#define CYGARC_REG_DEBUG_DEMCR_VC_NOCPERR BIT_(5) +#define CYGARC_REG_DEBUG_DEMCR_VC_MMERR BIT_(4) +#define CYGARC_REG_DEBUG_DEMCR_VC_CORERESET BIT_(0) + +#endif + +//========================================================================== +// IO Register address. +// This type is for recording the address of an IO register. + +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; + +//----------------------------------------------------------------------------- +// HAL IO macros. + +#ifndef HAL_IO_MACROS_DEFINED + +//----------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + + +#define HAL_READ_UINT8( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_BYTE *)(_register_))) + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + (*((volatile CYG_BYTE *)(_register_)) = (_value_)) + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_i_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + ((volatile CYG_BYTE *)(_register_)) = (_buf_)[_i_]; \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + + +#define HAL_READ_UINT16( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD16 *)(_register_))) + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + (*((volatile CYG_WORD16 *)(_register_)) = (_value_)) + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_i_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + ((volatile CYG_WORD16 *)(_register_))[_i_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD32 *)(_register_))) + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + (*((volatile CYG_WORD32 *)(_register_)) = (_value_)) + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#define HAL_READ_UINT32_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_i_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + ((volatile CYG_WORD32 *)(_register_))[_i_] = (_buf_)[_i_]; \ + CYG_MACRO_END + + +#define HAL_IO_MACROS_DEFINED + +#endif // !HAL_IO_MACROS_DEFINED + +// Enforce a flow "barrier" to prevent optimizing compiler from reordering +// operations. +#define HAL_IO_BARRIER() + + +//========================================================================== +#endif //CYGONCE_HAL_IO_H |